1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2010 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \160..\163 - this instruction uses DREX rather than REX, with the
70 * OC0 field set to 0, and the dest field taken from
72 * \164..\167 - this instruction uses DREX rather than REX, with the
73 * OC0 field set to 1, and the dest field taken from
75 * \171 - placement of DREX suffix in the absence of an EA
76 * \172\ab - the register number from operand a in bits 7..4, with
77 * the 4-bit immediate from operand b in bits 3..0.
78 * \173\xab - the register number from operand a in bits 7..4, with
79 * the value b in bits 3..0.
80 * \174\a - the register number from operand a in bits 7..4, and
81 * an arbitrary value in bits 3..0 (assembled as zero.)
82 * \2ab - a ModRM, calculated on EA in operand a, with the spare
83 * field equal to digit b.
84 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
85 * is not equal to the truncated and sign-extended 32-bit
86 * operand; used for 32-bit immediates in 64-bit mode.
87 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
88 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
89 * V field taken from operand 0..3.
90 * \270 - this instruction uses VEX/XOP rather than REX, with the
91 * V field set to 1111b.
93 * VEX/XOP prefixes are followed by the sequence:
94 * \tmm\wlp where mm is the M field; and wlp is:
96 * [w0] ww = 0 for W = 0
97 * [w1] ww = 1 for W = 1
98 * [wx] ww = 2 for W don't care (always assembled as 0)
99 * [ww] ww = 3 for W used as REX.W
101 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
103 * \274..\277 - a signed byte immediate operand, from operand 0..3,
104 * which is to be extended to the operand size.
105 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
106 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
107 * \312 - (disassembler only) invalid with non-default address size.
108 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
109 * \314 - (disassembler only) invalid with REX.B
110 * \315 - (disassembler only) invalid with REX.X
111 * \316 - (disassembler only) invalid with REX.R
112 * \317 - (disassembler only) invalid with REX.W
113 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
114 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
115 * \322 - indicates that this instruction is only valid when the
116 * operand size is the default (instruction to disassembler,
117 * generates no code in the assembler)
118 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
119 * \324 - indicates 64-bit operand size requiring REX prefix.
120 * \325 - instruction which always uses spl/bpl/sil/dil
121 * \330 - a literal byte follows in the code stream, to be added
122 * to the condition code value of the instruction.
123 * \331 - instruction not valid with REP prefix. Hint for
124 * disassembler only; for SSE instructions.
125 * \332 - REP prefix (0xF2 byte) used as opcode extension.
126 * \333 - REP prefix (0xF3 byte) used as opcode extension.
127 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
128 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
129 * \336 - force a REP(E) prefix (0xF2) even if not specified.
130 * \337 - force a REPNE prefix (0xF3) even if not specified.
131 * \336-\337 are still listed as prefixes in the disassembler.
132 * \340 - reserve <operand 0> bytes of uninitialized storage.
133 * Operand 0 had better be a segmentless constant.
134 * \341 - this instruction needs a WAIT "prefix"
135 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
136 * (POP is never used for CS) depending on operand 0
137 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
139 * \360 - no SSE prefix (== \364\331)
140 * \361 - 66 SSE prefix (== \366\331)
141 * \362 - F2 SSE prefix (== \364\332)
142 * \363 - F3 SSE prefix (== \364\333)
143 * \364 - operand-size prefix (0x66) not permitted
144 * \365 - address-size prefix (0x67) not permitted
145 * \366 - operand-size prefix (0x66) used as opcode extension
146 * \367 - address-size prefix (0x67) used as opcode extension
147 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
148 * 370 is used for Jcc, 371 is used for JMP.
149 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
150 * used for conditional jump over longer jump
153 #include "compiler.h"
157 #include <inttypes.h>
161 #include "assemble.h"
167 * Matching errors. These should be sorted so that more specific
168 * errors come later in the sequence.
176 * Matching success; the conditional ones first
178 MOK_JUMP
, /* Matching OK but needs jmp_match() */
179 MOK_GOOD
/* Matching unconditionally OK */
183 int sib_present
; /* is a SIB byte necessary? */
184 int bytes
; /* # of bytes of offset needed */
185 int size
; /* lazy - this is sib+bytes+1 */
186 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
189 static uint32_t cpu
; /* cpu level received from nasm.c */
190 static efunc errfunc
;
191 static struct ofmt
*outfmt
;
192 static ListGen
*list
;
194 static int64_t calcsize(int32_t, int64_t, int, insn
*, const uint8_t *);
195 static void gencode(int32_t segment
, int64_t offset
, int bits
,
196 insn
* ins
, const struct itemplate
*temp
,
198 static enum match_result
find_match(const struct itemplate
**tempp
,
200 int32_t segment
, int64_t offset
, int bits
);
201 static enum match_result
matches(const struct itemplate
*, insn
*, int bits
);
202 static opflags_t
regflag(const operand
*);
203 static int32_t regval(const operand
*);
204 static int rexflags(int, opflags_t
, int);
205 static int op_rexflags(const operand
*, int);
206 static ea
*process_ea(operand
*, ea
*, int, int, int, opflags_t
);
207 static void add_asp(insn
*, int);
209 static int has_prefix(insn
* ins
, enum prefix_pos pos
, enum prefixes prefix
)
211 return ins
->prefixes
[pos
] == prefix
;
214 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
216 if (ins
->prefixes
[pos
])
217 errfunc(ERR_NONFATAL
, "invalid %s prefix",
218 prefix_name(ins
->prefixes
[pos
]));
221 static const char *size_name(int size
)
243 static void warn_overflow(int pass
, int size
)
245 errfunc(ERR_WARNING
| pass
| ERR_WARN_NOV
,
246 "%s data exceeds bounds", size_name(size
));
249 static void warn_overflow_const(int64_t data
, int size
)
251 if (overflow_general(data
, size
))
252 warn_overflow(ERR_PASS1
, size
);
255 static void warn_overflow_opd(const struct operand
*o
, int size
)
257 if (o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
) {
258 if (overflow_general(o
->offset
, size
))
259 warn_overflow(ERR_PASS2
, size
);
264 * This routine wrappers the real output format's output routine,
265 * in order to pass a copy of the data off to the listing file
266 * generator at the same time.
268 static void out(int64_t offset
, int32_t segto
, const void *data
,
269 enum out_type type
, uint64_t size
,
270 int32_t segment
, int32_t wrt
)
272 static int32_t lineno
= 0; /* static!!! */
273 static char *lnfname
= NULL
;
276 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
278 * This is a non-relocated address, and we're going to
279 * convert it into RAWDATA format.
284 errfunc(ERR_PANIC
, "OUT_ADDRESS with size > 8");
288 WRITEADDR(q
, *(int64_t *)data
, size
);
293 list
->output(offset
, data
, type
, size
);
296 * this call to src_get determines when we call the
297 * debug-format-specific "linenum" function
298 * it updates lineno and lnfname to the current values
299 * returning 0 if "same as last time", -2 if lnfname
300 * changed, and the amount by which lineno changed,
301 * if it did. thus, these variables must be static
304 if (src_get(&lineno
, &lnfname
)) {
305 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
308 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
311 static bool jmp_match(int32_t segment
, int64_t offset
, int bits
,
312 insn
* ins
, const uint8_t *code
)
317 if ((c
!= 0370 && c
!= 0371) || (ins
->oprs
[0].type
& STRICT
))
321 if (optimizing
< 0 && c
== 0371)
324 isize
= calcsize(segment
, offset
, bits
, ins
, code
);
326 if (ins
->oprs
[0].opflags
& OPFLAG_UNKNOWN
)
327 /* Be optimistic in pass 1 */
330 if (ins
->oprs
[0].segment
!= segment
)
333 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is delta */
334 return (isize
>= -128 && isize
<= 127); /* is it byte size? */
337 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
338 insn
* instruction
, struct ofmt
*output
, efunc error
,
341 const struct itemplate
*temp
;
346 int64_t start
= offset
;
347 int64_t wsize
; /* size for DB etc. */
349 errfunc
= error
; /* to pass to other functions */
351 outfmt
= output
; /* likewise */
352 list
= listgen
; /* and again */
354 wsize
= idata_bytes(instruction
->opcode
);
360 int32_t t
= instruction
->times
;
363 "instruction->times < 0 (%ld) in assemble()", t
);
365 while (t
--) { /* repeat TIMES times */
366 list_for_each(e
, instruction
->eops
) {
367 if (e
->type
== EOT_DB_NUMBER
) {
369 errfunc(ERR_NONFATAL
,
370 "integer supplied to a DT, DO or DY"
373 out(offset
, segment
, &e
->offset
,
374 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
377 } else if (e
->type
== EOT_DB_STRING
||
378 e
->type
== EOT_DB_STRING_FREE
) {
381 out(offset
, segment
, e
->stringval
,
382 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
383 align
= e
->stringlen
% wsize
;
386 align
= wsize
- align
;
387 out(offset
, segment
, zero_buffer
,
388 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
390 offset
+= e
->stringlen
+ align
;
393 if (t
> 0 && t
== instruction
->times
- 1) {
395 * Dummy call to list->output to give the offset to the
398 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
399 list
->uplevel(LIST_TIMES
);
402 if (instruction
->times
> 1)
403 list
->downlevel(LIST_TIMES
);
404 return offset
- start
;
407 if (instruction
->opcode
== I_INCBIN
) {
408 const char *fname
= instruction
->eops
->stringval
;
411 fp
= fopen(fname
, "rb");
413 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
415 } else if (fseek(fp
, 0L, SEEK_END
) < 0) {
416 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
419 static char buf
[4096];
420 size_t t
= instruction
->times
;
425 if (instruction
->eops
->next
) {
426 base
= instruction
->eops
->next
->offset
;
428 if (instruction
->eops
->next
->next
&&
429 len
> (size_t)instruction
->eops
->next
->next
->offset
)
430 len
= (size_t)instruction
->eops
->next
->next
->offset
;
433 * Dummy call to list->output to give the offset to the
436 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
437 list
->uplevel(LIST_INCBIN
);
441 fseek(fp
, base
, SEEK_SET
);
445 m
= fread(buf
, 1, l
> sizeof(buf
) ? sizeof(buf
) : l
, fp
);
448 * This shouldn't happen unless the file
449 * actually changes while we are reading
453 "`incbin': unexpected EOF while"
454 " reading file `%s'", fname
);
455 t
= 0; /* Try to exit cleanly */
458 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
463 list
->downlevel(LIST_INCBIN
);
464 if (instruction
->times
> 1) {
466 * Dummy call to list->output to give the offset to the
469 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
470 list
->uplevel(LIST_TIMES
);
471 list
->downlevel(LIST_TIMES
);
474 return instruction
->times
* len
;
476 return 0; /* if we're here, there's an error */
479 /* Check to see if we need an address-size prefix */
480 add_asp(instruction
, bits
);
482 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
486 int64_t insn_size
= calcsize(segment
, offset
, bits
,
487 instruction
, temp
->code
);
488 itimes
= instruction
->times
;
489 if (insn_size
< 0) /* shouldn't be, on pass two */
490 error(ERR_PANIC
, "errors made it through from pass one");
493 for (j
= 0; j
< MAXPREFIX
; j
++) {
495 switch (instruction
->prefixes
[j
]) {
513 error(ERR_WARNING
| ERR_PASS2
,
514 "cs segment base generated, but will be ignored in 64-bit mode");
520 error(ERR_WARNING
| ERR_PASS2
,
521 "ds segment base generated, but will be ignored in 64-bit mode");
527 error(ERR_WARNING
| ERR_PASS2
,
528 "es segment base generated, but will be ignored in 64-bit mode");
540 error(ERR_WARNING
| ERR_PASS2
,
541 "ss segment base generated, but will be ignored in 64-bit mode");
548 "segr6 and segr7 cannot be used as prefixes");
553 "16-bit addressing is not supported "
555 } else if (bits
!= 16)
565 "64-bit addressing is only supported "
589 error(ERR_PANIC
, "invalid instruction prefix");
592 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
597 insn_end
= offset
+ insn_size
;
598 gencode(segment
, offset
, bits
, instruction
,
601 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
603 * Dummy call to list->output to give the offset to the
606 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
607 list
->uplevel(LIST_TIMES
);
610 if (instruction
->times
> 1)
611 list
->downlevel(LIST_TIMES
);
612 return offset
- start
;
616 case MERR_OPSIZEMISSING
:
617 error(ERR_NONFATAL
, "operation size not specified");
619 case MERR_OPSIZEMISMATCH
:
620 error(ERR_NONFATAL
, "mismatch in operand sizes");
623 error(ERR_NONFATAL
, "no instruction for this cpu level");
626 error(ERR_NONFATAL
, "instruction not supported in %d-bit mode",
631 "invalid combination of opcode and operands");
638 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
639 insn
* instruction
, efunc error
)
641 const struct itemplate
*temp
;
644 errfunc
= error
; /* to pass to other functions */
647 if (instruction
->opcode
== I_none
)
650 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
651 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
652 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
||
653 instruction
->opcode
== I_DY
) {
655 int32_t isize
, osize
, wsize
;
658 wsize
= idata_bytes(instruction
->opcode
);
660 list_for_each(e
, instruction
->eops
) {
664 if (e
->type
== EOT_DB_NUMBER
) {
666 warn_overflow_const(e
->offset
, wsize
);
667 } else if (e
->type
== EOT_DB_STRING
||
668 e
->type
== EOT_DB_STRING_FREE
)
669 osize
= e
->stringlen
;
671 align
= (-osize
) % wsize
;
674 isize
+= osize
+ align
;
676 return isize
* instruction
->times
;
679 if (instruction
->opcode
== I_INCBIN
) {
680 const char *fname
= instruction
->eops
->stringval
;
685 fp
= fopen(fname
, "rb");
687 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
689 else if (fseek(fp
, 0L, SEEK_END
) < 0)
690 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
694 if (instruction
->eops
->next
) {
695 len
-= instruction
->eops
->next
->offset
;
696 if (instruction
->eops
->next
->next
&&
697 len
> (size_t)instruction
->eops
->next
->next
->offset
) {
698 len
= (size_t)instruction
->eops
->next
->next
->offset
;
701 val
= instruction
->times
* len
;
708 /* Check to see if we need an address-size prefix */
709 add_asp(instruction
, bits
);
711 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
713 /* we've matched an instruction. */
715 const uint8_t *codes
= temp
->code
;
718 isize
= calcsize(segment
, offset
, bits
, instruction
, codes
);
721 for (j
= 0; j
< MAXPREFIX
; j
++) {
722 switch (instruction
->prefixes
[j
]) {
748 return isize
* instruction
->times
;
750 return -1; /* didn't match any instruction */
754 static bool possible_sbyte(operand
*o
, int min_optimizing
)
756 return o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
&&
757 !(o
->opflags
& OPFLAG_UNKNOWN
) &&
758 optimizing
>= min_optimizing
&& !(o
->type
& STRICT
);
761 /* check that opn[op] is a signed byte of size 16 or 32 */
762 static bool is_sbyte16(operand
*o
, int min_optimizing
)
766 if (!possible_sbyte(o
, min_optimizing
))
770 return v
>= -128 && v
<= 127;
773 static bool is_sbyte32(operand
*o
, int min_optimizing
)
777 if (!possible_sbyte(o
, min_optimizing
))
781 return v
>= -128 && v
<= 127;
784 /* Check if o is zero of size 16 or 32 */
785 static bool is_zero16(operand
*o
, int min_optimizing
)
789 if (!possible_sbyte(o
, min_optimizing
))
796 static bool is_zero32(operand
*o
, int min_optimizing
)
800 if (!possible_sbyte(o
, min_optimizing
))
807 /* Common construct */
808 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
810 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
811 insn
* ins
, const uint8_t *codes
)
820 ins
->rex
= 0; /* Ensure REX is reset */
822 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
825 (void)segment
; /* Don't warn that this parameter is unused */
826 (void)offset
; /* Don't warn that this parameter is unused */
830 op1
= (c
& 3) + ((opex
& 1) << 2);
831 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
832 opx
= &ins
->oprs
[op1
];
833 opex
= 0; /* For the next iteration */
840 codes
+= c
, length
+= c
;
851 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
866 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
867 length
+= (opx
->type
& BITS16
) ? 2 : 4;
869 length
+= (bits
== 16) ? 2 : 4;
877 length
+= ins
->addr_size
>> 3;
885 length
+= 8; /* MOV reg64/imm */
893 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
894 length
+= (opx
->type
& BITS16
) ? 2 : 4;
896 length
+= (bits
== 16) ? 2 : 4;
908 length
+= is_sbyte16(opx
, 0) ? 1 : 2;
917 length
+= is_sbyte32(opx
, 0) ? 1 : 4;
928 ins
->drexdst
= regval(opx
);
933 ins
->rex
|= REX_D
|REX_OC
;
934 ins
->drexdst
= regval(opx
);
948 length
+= is_sbyte32(opx
, 0) ? 1 : 4;
957 ins
->drexdst
= regval(opx
);
958 ins
->vex_cm
= *codes
++;
959 ins
->vex_wlp
= *codes
++;
965 ins
->vex_cm
= *codes
++;
966 ins
->vex_wlp
= *codes
++;
979 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
983 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
990 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
991 has_prefix(ins
, PPS_ASIZE
, P_A32
))
999 length
+= (bits
!= 16);
1003 length
+= (bits
== 16);
1041 if (!ins
->prefixes
[PPS_LREP
])
1042 ins
->prefixes
[PPS_LREP
] = P_REP
;
1046 if (!ins
->prefixes
[PPS_LREP
])
1047 ins
->prefixes
[PPS_LREP
] = P_REPNE
;
1051 if (ins
->oprs
[0].segment
!= NO_SEG
)
1052 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1053 " quantity of BSS space");
1055 length
+= ins
->oprs
[0].offset
;
1059 if (!ins
->prefixes
[PPS_WAIT
])
1060 ins
->prefixes
[PPS_WAIT
] = P_WAIT
;
1110 struct operand
*opy
= &ins
->oprs
[op2
];
1112 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1115 /* pick rfield from operand b (opx) */
1116 rflags
= regflag(opx
);
1117 rfield
= nasm_regvals
[opx
->basereg
];
1122 if (!process_ea(opy
, &ea_data
, bits
,
1123 ins
->addr_size
, rfield
, rflags
)) {
1124 errfunc(ERR_NONFATAL
, "invalid effective address");
1127 ins
->rex
|= ea_data
.rex
;
1128 length
+= ea_data
.size
;
1134 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1135 ": instruction code \\%o (0x%02X) given", c
, c
);
1140 ins
->rex
&= rex_mask
;
1142 if (ins
->rex
& REX_NH
) {
1143 if (ins
->rex
& REX_H
) {
1144 errfunc(ERR_NONFATAL
, "instruction cannot use high registers");
1147 ins
->rex
&= ~REX_P
; /* Don't force REX prefix due to high reg */
1150 if (ins
->rex
& REX_V
) {
1151 int bad32
= REX_R
|REX_W
|REX_X
|REX_B
;
1153 if (ins
->rex
& REX_H
) {
1154 errfunc(ERR_NONFATAL
, "cannot use high register in vex instruction");
1157 switch (ins
->vex_wlp
& 030) {
1171 if (bits
!= 64 && ((ins
->rex
& bad32
) || ins
->drexdst
> 7)) {
1172 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1175 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_R
|REX_B
)))
1179 } else if (ins
->rex
& REX_D
) {
1180 if (ins
->rex
& REX_H
) {
1181 errfunc(ERR_NONFATAL
, "cannot use high register in drex instruction");
1184 if (bits
!= 64 && ((ins
->rex
& (REX_R
|REX_W
|REX_X
|REX_B
)) ||
1185 ins
->drexdst
> 7)) {
1186 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1190 } else if (ins
->rex
& REX_REAL
) {
1191 if (ins
->rex
& REX_H
) {
1192 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1194 } else if (bits
== 64) {
1196 } else if ((ins
->rex
& REX_L
) &&
1197 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1200 assert_no_prefix(ins
, PPS_LREP
);
1203 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1211 #define EMIT_REX() \
1212 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1213 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1214 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1219 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1220 insn
* ins
, const struct itemplate
*temp
,
1223 static char condval
[] = { /* conditional opcodes */
1224 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1225 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1226 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1233 struct operand
*opx
;
1234 const uint8_t *codes
= temp
->code
;
1239 op1
= (c
& 3) + ((opex
& 1) << 2);
1240 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
1241 opx
= &ins
->oprs
[op1
];
1242 opex
= 0; /* For the next iteration */
1250 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1263 bytes
[0] = *codes
++ + (regval(opx
) & 7);
1264 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1269 /* The test for BITS8 and SBYTE here is intended to avoid
1270 warning on optimizer actions due to SBYTE, while still
1271 warn on explicit BYTE directives. Also warn, obviously,
1272 if the optimizer isn't enabled. */
1273 if (((opx
->type
& BITS8
) ||
1274 !(opx
->type
& temp
->opd
[op1
] & BYTENESS
)) &&
1275 (opx
->offset
< -128 || opx
->offset
> 127)) {
1276 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1277 "signed byte value exceeds bounds");
1279 if (opx
->segment
!= NO_SEG
) {
1281 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1282 opx
->segment
, opx
->wrt
);
1284 bytes
[0] = opx
->offset
;
1285 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1292 if (opx
->offset
< -256 || opx
->offset
> 255) {
1293 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1294 "byte value exceeds bounds");
1296 if (opx
->segment
!= NO_SEG
) {
1298 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1299 opx
->segment
, opx
->wrt
);
1301 bytes
[0] = opx
->offset
;
1302 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1309 if (opx
->offset
< 0 || opx
->offset
> 255)
1310 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1311 "unsigned byte value exceeds bounds");
1312 if (opx
->segment
!= NO_SEG
) {
1314 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1315 opx
->segment
, opx
->wrt
);
1317 bytes
[0] = opx
->offset
;
1318 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1325 warn_overflow_opd(opx
, 2);
1327 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1328 opx
->segment
, opx
->wrt
);
1333 if (opx
->type
& (BITS16
| BITS32
))
1334 size
= (opx
->type
& BITS16
) ? 2 : 4;
1336 size
= (bits
== 16) ? 2 : 4;
1337 warn_overflow_opd(opx
, size
);
1339 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1340 opx
->segment
, opx
->wrt
);
1345 warn_overflow_opd(opx
, 4);
1347 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1348 opx
->segment
, opx
->wrt
);
1354 size
= ins
->addr_size
>> 3;
1355 warn_overflow_opd(opx
, size
);
1356 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1357 opx
->segment
, opx
->wrt
);
1362 if (opx
->segment
!= segment
) {
1364 out(offset
, segment
, &data
,
1365 OUT_REL1ADR
, insn_end
- offset
,
1366 opx
->segment
, opx
->wrt
);
1368 data
= opx
->offset
- insn_end
;
1369 if (data
> 127 || data
< -128)
1370 errfunc(ERR_NONFATAL
, "short jump is out of range");
1371 out(offset
, segment
, &data
,
1372 OUT_ADDRESS
, 1, NO_SEG
, NO_SEG
);
1378 data
= (int64_t)opx
->offset
;
1379 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1380 opx
->segment
, opx
->wrt
);
1385 if (opx
->segment
!= segment
) {
1387 out(offset
, segment
, &data
,
1388 OUT_REL2ADR
, insn_end
- offset
,
1389 opx
->segment
, opx
->wrt
);
1391 data
= opx
->offset
- insn_end
;
1392 out(offset
, segment
, &data
,
1393 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1399 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1400 size
= (opx
->type
& BITS16
) ? 2 : 4;
1402 size
= (bits
== 16) ? 2 : 4;
1403 if (opx
->segment
!= segment
) {
1405 out(offset
, segment
, &data
,
1406 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1407 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1409 data
= opx
->offset
- insn_end
;
1410 out(offset
, segment
, &data
,
1411 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1417 if (opx
->segment
!= segment
) {
1419 out(offset
, segment
, &data
,
1420 OUT_REL4ADR
, insn_end
- offset
,
1421 opx
->segment
, opx
->wrt
);
1423 data
= opx
->offset
- insn_end
;
1424 out(offset
, segment
, &data
,
1425 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1431 if (opx
->segment
== NO_SEG
)
1432 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1435 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1436 outfmt
->segbase(1 + opx
->segment
),
1443 warn_overflow_opd(opx
, 2);
1444 if (is_sbyte16(opx
, 0)) {
1446 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1450 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1451 opx
->segment
, opx
->wrt
);
1458 bytes
[0] = *codes
++;
1459 if (is_sbyte16(opx
, 0))
1460 bytes
[0] |= 2; /* s-bit */
1461 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1467 warn_overflow_opd(opx
, 4);
1468 if (is_sbyte32(opx
, 0)) {
1470 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1474 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1475 opx
->segment
, opx
->wrt
);
1482 bytes
[0] = *codes
++;
1483 if (is_sbyte32(opx
, 0))
1484 bytes
[0] |= 2; /* s-bit */
1485 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1495 (ins
->drexdst
<< 4) |
1496 (ins
->rex
& REX_OC
? 0x08 : 0) |
1497 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1499 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1505 opx
= &ins
->oprs
[c
>> 3];
1506 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1507 opx
= &ins
->oprs
[c
& 7];
1508 if (opx
->segment
!= NO_SEG
|| opx
->wrt
!= NO_SEG
) {
1509 errfunc(ERR_NONFATAL
,
1510 "non-absolute expression not permitted as argument %d",
1513 if (opx
->offset
& ~15) {
1514 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1515 "four-bit argument exceeds bounds");
1517 bytes
[0] |= opx
->offset
& 15;
1519 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1525 opx
= &ins
->oprs
[c
>> 4];
1526 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1528 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1534 opx
= &ins
->oprs
[c
];
1535 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1536 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1542 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1543 (int32_t)data
!= (int64_t)data
) {
1544 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1545 "signed dword immediate exceeds bounds");
1547 if (is_sbyte32(opx
, 0)) {
1549 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1553 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1554 opx
->segment
, opx
->wrt
);
1561 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1562 (int32_t)data
!= (int64_t)data
) {
1563 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1564 "signed dword immediate exceeds bounds");
1566 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1567 opx
->segment
, opx
->wrt
);
1574 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
))) {
1575 bytes
[0] = (ins
->vex_cm
>> 6) ? 0x8f : 0xc4;
1576 bytes
[1] = (ins
->vex_cm
& 31) | ((~ins
->rex
& 7) << 5);
1577 bytes
[2] = ((ins
->rex
& REX_W
) << (7-3)) |
1578 ((~ins
->drexdst
& 15)<< 3) | (ins
->vex_wlp
& 07);
1579 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 3, NO_SEG
, NO_SEG
);
1583 bytes
[1] = ((~ins
->rex
& REX_R
) << (7-2)) |
1584 ((~ins
->drexdst
& 15) << 3) | (ins
->vex_wlp
& 07);
1585 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 2, NO_SEG
, NO_SEG
);
1595 if (ins
->rex
& REX_W
)
1597 else if (ins
->prefixes
[PPS_OSIZE
] == P_O16
)
1599 else if (ins
->prefixes
[PPS_OSIZE
] == P_O32
)
1604 um
= (uint64_t)2 << (s
-1);
1607 if (uv
> 127 && uv
< (uint64_t)-128 &&
1608 (uv
< um
-128 || uv
> um
-1)) {
1609 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1610 "signed byte value exceeds bounds");
1612 if (opx
->segment
!= NO_SEG
) {
1614 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1615 opx
->segment
, opx
->wrt
);
1618 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1629 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1631 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1638 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1640 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1659 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1668 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1686 *bytes
= *codes
++ ^ condval
[ins
->condition
];
1687 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1696 *bytes
= c
- 0332 + 0xF2;
1697 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1702 if (ins
->rex
& REX_R
) {
1704 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1707 ins
->rex
&= ~(REX_L
|REX_R
);
1718 if (ins
->oprs
[0].segment
!= NO_SEG
)
1719 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1721 int64_t size
= ins
->oprs
[0].offset
;
1723 out(offset
, segment
, NULL
,
1724 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1735 switch (ins
->oprs
[0].basereg
) {
1750 "bizarre 8086 segment register received");
1752 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1759 switch (ins
->oprs
[0].basereg
) {
1768 "bizarre 386 segment register received");
1770 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1779 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1785 bytes
[0] = c
- 0362 + 0xf2;
1786 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1796 *bytes
= c
- 0366 + 0x66;
1797 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1807 *bytes
= bits
== 16 ? 3 : 5;
1808 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1831 struct operand
*opy
= &ins
->oprs
[op2
];
1834 /* pick rfield from operand b (opx) */
1835 rflags
= regflag(opx
);
1836 rfield
= nasm_regvals
[opx
->basereg
];
1838 /* rfield is constant */
1843 if (!process_ea(opy
, &ea_data
, bits
, ins
->addr_size
,
1845 errfunc(ERR_NONFATAL
, "invalid effective address");
1850 *p
++ = ea_data
.modrm
;
1851 if (ea_data
.sib_present
)
1854 /* DREX suffixes come between the SIB and the displacement */
1855 if (ins
->rex
& REX_D
) {
1856 *p
++ = (ins
->drexdst
<< 4) |
1857 (ins
->rex
& REX_OC
? 0x08 : 0) |
1858 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1863 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1866 * Make sure the address gets the right offset in case
1867 * the line breaks in the .lst file (BR 1197827)
1872 switch (ea_data
.bytes
) {
1882 if (opy
->segment
== segment
) {
1884 if (overflow_signed(data
, ea_data
.bytes
))
1885 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1886 out(offset
, segment
, &data
, OUT_ADDRESS
,
1887 ea_data
.bytes
, NO_SEG
, NO_SEG
);
1889 /* overflow check in output/linker? */
1890 out(offset
, segment
, &data
, OUT_REL4ADR
,
1891 insn_end
- offset
, opy
->segment
, opy
->wrt
);
1894 if (overflow_general(opy
->offset
, ins
->addr_size
>> 3) ||
1895 signed_bits(opy
->offset
, ins
->addr_size
) !=
1896 signed_bits(opy
->offset
, ea_data
.bytes
* 8))
1897 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1900 out(offset
, segment
, &data
, OUT_ADDRESS
,
1901 ea_data
.bytes
, opy
->segment
, opy
->wrt
);
1907 "Invalid amount of bytes (%d) for offset?!",
1916 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1917 ": instruction code \\%o (0x%02X) given", c
, c
);
1923 static opflags_t
regflag(const operand
* o
)
1925 if (!is_register(o
->basereg
))
1926 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1927 return nasm_reg_flags
[o
->basereg
];
1930 static int32_t regval(const operand
* o
)
1932 if (!is_register(o
->basereg
))
1933 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1934 return nasm_regvals
[o
->basereg
];
1937 static int op_rexflags(const operand
* o
, int mask
)
1942 if (!is_register(o
->basereg
))
1943 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1945 flags
= nasm_reg_flags
[o
->basereg
];
1946 val
= nasm_regvals
[o
->basereg
];
1948 return rexflags(val
, flags
, mask
);
1951 static int rexflags(int val
, opflags_t flags
, int mask
)
1956 rex
|= REX_B
|REX_X
|REX_R
;
1959 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1961 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1967 static enum match_result
find_match(const struct itemplate
**tempp
,
1969 int32_t segment
, int64_t offset
, int bits
)
1971 const struct itemplate
*temp
;
1972 enum match_result m
, merr
;
1973 opflags_t xsizeflags
[MAX_OPERANDS
];
1974 bool opsizemissing
= false;
1977 for (i
= 0; i
< instruction
->operands
; i
++)
1978 xsizeflags
[i
] = instruction
->oprs
[i
].type
& SIZE_MASK
;
1980 merr
= MERR_INVALOP
;
1982 for (temp
= nasm_instructions
[instruction
->opcode
];
1983 temp
->opcode
!= I_none
; temp
++) {
1984 m
= matches(temp
, instruction
, bits
);
1985 if (m
== MOK_JUMP
) {
1986 if (jmp_match(segment
, offset
, bits
, instruction
, temp
->code
))
1990 } else if (m
== MERR_OPSIZEMISSING
&&
1991 (temp
->flags
& IF_SMASK
) != IF_SX
) {
1993 * Missing operand size and a candidate for fuzzy matching...
1995 for (i
= 0; i
< temp
->operands
; i
++) {
1996 if ((temp
->opd
[i
] & SAME_AS
) == 0)
1997 xsizeflags
[i
] |= temp
->opd
[i
] & SIZE_MASK
;
1999 opsizemissing
= true;
2003 if (merr
== MOK_GOOD
)
2007 /* No match, but see if we can get a fuzzy operand size match... */
2011 for (i
= 0; i
< instruction
->operands
; i
++) {
2013 * We ignore extrinsic operand sizes on registers, so we should
2014 * never try to fuzzy-match on them. This also resolves the case
2015 * when we have e.g. "xmmrm128" in two different positions.
2017 if (is_class(REGISTER
, instruction
->oprs
[i
].type
))
2020 /* This tests if xsizeflags[i] has more than one bit set */
2021 if ((xsizeflags
[i
] & (xsizeflags
[i
]-1)))
2022 goto done
; /* No luck */
2024 instruction
->oprs
[i
].type
|= xsizeflags
[i
]; /* Set the size */
2027 /* Try matching again... */
2028 for (temp
= nasm_instructions
[instruction
->opcode
];
2029 temp
->opcode
!= I_none
; temp
++) {
2030 m
= matches(temp
, instruction
, bits
);
2031 if (m
== MOK_JUMP
) {
2032 if (jmp_match(segment
, offset
, bits
, instruction
, temp
->code
))
2039 if (merr
== MOK_GOOD
)
2048 static enum match_result
matches(const struct itemplate
*itemp
,
2049 insn
*instruction
, int bits
)
2051 int i
, size
[MAX_OPERANDS
], asize
, oprs
;
2052 bool opsizemissing
= false;
2057 if (itemp
->opcode
!= instruction
->opcode
)
2058 return MERR_INVALOP
;
2061 * Count the operands
2063 if (itemp
->operands
!= instruction
->operands
)
2064 return MERR_INVALOP
;
2067 * Check that no spurious colons or TOs are present
2069 for (i
= 0; i
< itemp
->operands
; i
++)
2070 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
2071 return MERR_INVALOP
;
2074 * Process size flags
2076 switch (itemp
->flags
& IF_SMASK
) {
2116 if (itemp
->flags
& IF_ARMASK
) {
2117 /* S- flags only apply to a specific operand */
2118 i
= ((itemp
->flags
& IF_ARMASK
) >> IF_ARSHFT
) - 1;
2119 memset(size
, 0, sizeof size
);
2122 /* S- flags apply to all operands */
2123 for (i
= 0; i
< MAX_OPERANDS
; i
++)
2128 * Check that the operand flags all match up,
2129 * it's a bit tricky so lets be verbose:
2131 * 1) Find out the size of operand. If instruction
2132 * doesn't have one specified -- we're trying to
2133 * guess it either from template (IF_S* flag) or
2136 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2137 * (ie the same operand as was specified somewhere in template, and
2138 * this referred operand index is being achieved via ~SAME_AS)
2139 * we are to be sure that both registers (in template and instruction)
2142 * 3) If template operand do not match the instruction OR
2143 * template has an operand size specified AND this size differ
2144 * from which instruction has (perhaps we got it from code bits)
2146 * a) Check that only size of instruction and operand is differ
2147 * other characteristics do match
2148 * b) Perhaps it's a register specified in instruction so
2149 * for such a case we just mark that operand as "size
2150 * missing" and this will turn on fuzzy operand size
2151 * logic facility (handled by a caller)
2153 for (i
= 0; i
< itemp
->operands
; i
++) {
2154 opflags_t type
= instruction
->oprs
[i
].type
;
2155 if (!(type
& SIZE_MASK
))
2158 if (itemp
->opd
[i
] & SAME_AS
) {
2159 int j
= itemp
->opd
[i
] & ~SAME_AS
;
2160 if (type
!= instruction
->oprs
[j
].type
||
2161 instruction
->oprs
[i
].basereg
!= instruction
->oprs
[j
].basereg
)
2162 return MERR_INVALOP
;
2163 } else if (itemp
->opd
[i
] & ~type
||
2164 ((itemp
->opd
[i
] & SIZE_MASK
) &&
2165 ((itemp
->opd
[i
] ^ type
) & SIZE_MASK
))) {
2166 if ((itemp
->opd
[i
] & ~type
& ~SIZE_MASK
) || (type
& SIZE_MASK
)) {
2167 return MERR_INVALOP
;
2168 } else if (!is_class(REGISTER
, type
)) {
2170 * Note: we don't honor extrinsic operand sizes for registers,
2171 * so "missing operand size" for a register should be
2172 * considered a wildcard match rather than an error.
2174 opsizemissing
= true;
2180 return MERR_OPSIZEMISSING
;
2183 * Check operand sizes
2185 if (itemp
->flags
& (IF_SM
| IF_SM2
)) {
2186 oprs
= (itemp
->flags
& IF_SM2
? 2 : itemp
->operands
);
2187 for (i
= 0; i
< oprs
; i
++) {
2188 asize
= itemp
->opd
[i
] & SIZE_MASK
;
2190 for (i
= 0; i
< oprs
; i
++)
2196 oprs
= itemp
->operands
;
2199 for (i
= 0; i
< itemp
->operands
; i
++) {
2200 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
2201 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
2202 return MERR_OPSIZEMISMATCH
;
2206 * Check template is okay at the set cpu level
2208 if (((itemp
->flags
& IF_PLEVEL
) > cpu
))
2212 * Verify the appropriate long mode flag.
2214 if ((itemp
->flags
& (bits
== 64 ? IF_NOLONG
: IF_LONG
)))
2215 return MERR_BADMODE
;
2218 * Check if special handling needed for Jumps
2220 if ((itemp
->code
[0] & 0374) == 0370)
2226 static ea
*process_ea(operand
* input
, ea
* output
, int bits
,
2227 int addrbits
, int rfield
, opflags_t rflags
)
2229 bool byte_offs
= !!(input
->eaflags
& EAF_BYTEOFFS
);
2230 bool word_offs
= !!(input
->eaflags
& EAF_WORDOFFS
);
2231 bool no_offs
= !!(input
->eaflags
& EAF_NO_OFFS
);
2233 output
->rip
= false;
2235 /* REX flags for the rfield operand */
2236 output
->rex
|= rexflags(rfield
, rflags
, REX_R
|REX_P
|REX_W
|REX_H
);
2238 if (is_class(REGISTER
, input
->type
)) { /* register direct */
2242 if (!is_register(input
->basereg
))
2245 i
= nasm_regvals
[input
->basereg
];
2248 return NULL
; /* Invalid EA register */
2250 output
->rex
|= op_rexflags(input
, REX_B
|REX_P
|REX_W
|REX_H
);
2252 output
->sib_present
= false; /* no SIB necessary */
2253 output
->bytes
= 0; /* no offset necessary either */
2254 output
->modrm
= 0xC0 | ((rfield
& 7) << 3) | (i
& 7);
2255 } else { /* it's a memory reference */
2256 if (input
->basereg
== -1
2257 && (input
->indexreg
== -1 || input
->scale
== 0)) {
2258 /* it's a pure offset */
2260 if (bits
== 64 && ((input
->type
& IP_REL
) == IP_REL
) &&
2261 input
->segment
== NO_SEG
) {
2262 nasm_error(ERR_WARNING
| ERR_PASS1
, "absolute address can not be RIP-relative");
2263 input
->type
&= ~IP_REL
;
2264 input
->type
|= MEMORY
;
2267 if (input
->eaflags
& EAF_BYTEOFFS
||
2268 (input
->eaflags
& EAF_WORDOFFS
&&
2269 input
->disp_size
!= (addrbits
!= 16 ? 32 : 16))) {
2270 nasm_error(ERR_WARNING
| ERR_PASS1
, "displacement size ignored on absolute address");
2273 if (bits
== 64 && (~input
->type
& IP_REL
)) {
2274 int scale
, index
, base
;
2275 output
->sib_present
= true;
2279 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2281 output
->modrm
= 4 | ((rfield
& 7) << 3);
2282 output
->rip
= false;
2284 output
->sib_present
= false;
2285 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
2286 output
->modrm
= (addrbits
!= 16 ? 5 : 6) | ((rfield
& 7) << 3);
2287 output
->rip
= bits
== 64;
2289 } else { /* it's an indirection */
2290 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
2291 int hb
= input
->hintbase
, ht
= input
->hinttype
;
2292 int t
, it
, bt
; /* register numbers */
2293 opflags_t x
, ix
, bx
; /* register flags */
2296 i
= -1; /* make this easy, at least */
2298 if (is_register(i
)) {
2299 it
= nasm_regvals
[i
];
2300 ix
= nasm_reg_flags
[i
];
2306 if (is_register(b
)) {
2307 bt
= nasm_regvals
[b
];
2308 bx
= nasm_reg_flags
[b
];
2314 /* check for a 32/64-bit memory reference... */
2315 if ((ix
|bx
) & (BITS32
|BITS64
)) {
2316 /* it must be a 32/64-bit memory reference. Firstly we have
2317 * to check that all registers involved are type E/Rxx. */
2318 int32_t sok
= BITS32
|BITS64
;
2321 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
2329 return NULL
; /* Invalid register */
2330 if (~sok
& bx
& SIZE_MASK
)
2331 return NULL
; /* Invalid size */
2335 /* While we're here, ensure the user didn't specify
2337 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2340 if (addrbits
== 16 ||
2341 (addrbits
== 32 && !(sok
& BITS32
)) ||
2342 (addrbits
== 64 && !(sok
& BITS64
)))
2345 /* now reorganize base/index */
2346 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
2347 ((hb
== b
&& ht
== EAH_NOTBASE
)
2348 || (hb
== i
&& ht
== EAH_MAKEBASE
))) {
2349 /* swap if hints say so */
2350 t
= bt
, bt
= it
, it
= t
;
2351 x
= bx
, bx
= ix
, ix
= x
;
2353 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
2354 bt
= -1, bx
= 0, s
++;
2355 if (bt
== -1 && s
== 1 && !(hb
== it
&& ht
== EAH_NOTBASE
)) {
2356 /* make single reg base, unless hint */
2357 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2359 if (((s
== 2 && it
!= REG_NUM_ESP
2360 && !(input
->eaflags
& EAF_TIMESTWO
)) || s
== 3
2361 || s
== 5 || s
== 9) && bt
== -1)
2362 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2363 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
2364 && (input
->eaflags
& EAF_TIMESTWO
))
2365 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2366 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2367 if (s
== 1 && it
== REG_NUM_ESP
) {
2368 /* swap ESP into base if scale is 1 */
2369 t
= it
, it
= bt
, bt
= t
;
2370 x
= ix
, ix
= bx
, bx
= x
;
2372 if (it
== REG_NUM_ESP
2373 || (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2374 return NULL
; /* wrong, for various reasons */
2376 output
->rex
|= rexflags(it
, ix
, REX_X
);
2377 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2379 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2388 if (rm
!= REG_NUM_EBP
&&
2389 (no_offs
|| is_zero32(input
, -1)) &&
2390 !(byte_offs
|| word_offs
))
2392 else if (byte_offs
||
2393 (! word_offs
&& is_sbyte32(input
, -1)) ||
2394 (rm
== REG_NUM_EBP
&& no_offs
))
2400 output
->sib_present
= false;
2401 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2402 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2405 int mod
, scale
, index
, base
;
2425 default: /* then what the smeg is it? */
2426 return NULL
; /* panic */
2434 if (base
!= REG_NUM_EBP
&&
2435 (no_offs
|| is_zero32(input
, -1)) &&
2436 !(byte_offs
|| word_offs
))
2438 else if (byte_offs
||
2439 (! word_offs
&& is_sbyte32(input
, -1)) ||
2440 (base
== REG_NUM_EBP
&& no_offs
))
2446 output
->sib_present
= true;
2447 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2448 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | 4;
2449 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2451 } else { /* it's 16-bit */
2454 /* check for 64-bit long mode */
2458 /* check all registers are BX, BP, SI or DI */
2459 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
2460 && b
!= R_DI
) || (i
!= -1 && i
!= R_BP
&& i
!= R_BX
2461 && i
!= R_SI
&& i
!= R_DI
))
2464 /* ensure the user didn't specify DWORD/QWORD */
2465 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2468 if (s
!= 1 && i
!= -1)
2469 return NULL
; /* no can do, in 16-bit EA */
2470 if (b
== -1 && i
!= -1) {
2475 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2480 /* have BX/BP as base, SI/DI index */
2482 return NULL
; /* shouldn't ever happen, in theory */
2483 if (i
!= -1 && b
!= -1 &&
2484 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2485 return NULL
; /* invalid combinations */
2486 if (b
== -1) /* pure offset: handled above */
2487 return NULL
; /* so if it gets to here, panic! */
2491 switch (i
* 256 + b
) {
2492 case R_SI
* 256 + R_BX
:
2495 case R_DI
* 256 + R_BX
:
2498 case R_SI
* 256 + R_BP
:
2501 case R_DI
* 256 + R_BP
:
2519 if (rm
== -1) /* can't happen, in theory */
2520 return NULL
; /* so panic if it does */
2523 (no_offs
|| is_zero16(input
, -1)) &&
2524 !(byte_offs
|| word_offs
))
2526 else if (byte_offs
||
2527 (! word_offs
&& is_sbyte16(input
, -1)) ||
2528 (rm
== 6 && no_offs
))
2533 output
->sib_present
= false; /* no SIB - it's 16-bit */
2534 output
->bytes
= mod
; /* bytes of offset needed */
2535 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2540 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2544 static void add_asp(insn
*ins
, int addrbits
)
2549 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2551 switch (ins
->prefixes
[PPS_ASIZE
]) {
2562 valid
&= (addrbits
== 32) ? 16 : 32;
2568 for (j
= 0; j
< ins
->operands
; j
++) {
2569 if (is_class(MEMORY
, ins
->oprs
[j
].type
)) {
2572 /* Verify as Register */
2573 if (!is_register(ins
->oprs
[j
].indexreg
))
2576 i
= nasm_reg_flags
[ins
->oprs
[j
].indexreg
];
2578 /* Verify as Register */
2579 if (!is_register(ins
->oprs
[j
].basereg
))
2582 b
= nasm_reg_flags
[ins
->oprs
[j
].basereg
];
2584 if (ins
->oprs
[j
].scale
== 0)
2588 int ds
= ins
->oprs
[j
].disp_size
;
2589 if ((addrbits
!= 64 && ds
> 8) ||
2590 (addrbits
== 64 && ds
== 16))
2610 if (valid
& addrbits
) {
2611 ins
->addr_size
= addrbits
;
2612 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2613 /* Add an address size prefix */
2614 enum prefixes pref
= (addrbits
== 32) ? P_A16
: P_A32
;
2615 ins
->prefixes
[PPS_ASIZE
] = pref
;
2616 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2619 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2620 ins
->addr_size
= addrbits
; /* Error recovery */
2623 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2625 for (j
= 0; j
< ins
->operands
; j
++) {
2626 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2627 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
)
2628 != ins
->addr_size
) {
2629 /* mem_offs sizes must match the address size; if not,
2630 strip the MEM_OFFS bit and match only EA instructions */
2631 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);