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test/ppindirect.asm: test token pasting inside %[...]
[nasm.git] / disasm.c
blob4efcdc80100c66163c14f0427bdadfc9265f41a8
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(XMM0 & ~regflags))
118 return R_XMM0;
119 if (!(YMM0 & ~regflags))
120 return R_YMM0;
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
130
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
133 return 0;
134
135 if (!(REG8 & ~regflags)) {
136 if (rex & REX_P)
137 return nasm_rd_reg8_rex[regval];
138 else
139 return nasm_rd_reg8[regval];
140 }
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
154 if (rex & REX_P)
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
157 }
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
166
167 return 0;
168 }
169
170 /*
171 * Process a DREX suffix
172 */
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
174 {
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
177
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
181
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
184 return data;
185 }
186
187
188 /*
189 * Process an effective address (ModRM) specification.
190 */
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
193 {
194 int mod, rm, scale, index, base;
195 int rex;
196 uint8_t sib = 0;
197
198 mod = (modrm >> 6) & 03;
199 rm = modrm & 07;
200
201 if (mod != 3 && rm == 4 && asize != 16)
202 sib = *data++;
203
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
206 if (!data)
207 return NULL;
208 }
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
229 switch (rm) {
230 case 0:
231 op->basereg = R_BX;
232 op->indexreg = R_SI;
233 break;
234 case 1:
235 op->basereg = R_BX;
236 op->indexreg = R_DI;
237 break;
238 case 2:
239 op->basereg = R_BP;
240 op->indexreg = R_SI;
241 break;
242 case 3:
243 op->basereg = R_BP;
244 op->indexreg = R_DI;
245 break;
246 case 4:
247 op->basereg = R_SI;
248 break;
249 case 5:
250 op->basereg = R_DI;
251 break;
252 case 6:
253 op->basereg = R_BP;
254 break;
255 case 7:
256 op->basereg = R_BX;
257 break;
258 }
259 if (rm == 6 && mod == 0) { /* special case */
260 op->basereg = -1;
261 if (segsize != 16)
262 op->disp_size = 16;
263 mod = 2; /* fake disp16 */
264 }
265 switch (mod) {
266 case 0:
267 op->segment |= SEG_NODISP;
268 break;
269 case 1:
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
272 break;
273 case 2:
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
277 break;
278 }
279 return data;
280 } else {
281 /*
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
287 *
288 * However, rm=4
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
291 */
292 int a64 = asize == 64;
293
294 op->indexreg = -1;
295
296 if (a64)
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
298 else
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
300
301 if (rm == 5 && mod == 0) {
302 if (segsize == 64) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
306 }
307
308 if (asize != 64)
309 op->disp_size = asize;
310
311 op->basereg = -1;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
318 base = sib & 07;
319
320 op->scale = 1 << scale;
321
322 if (index == 4 && !(rex & REX_X))
323 op->indexreg = -1; /* ESP/RSP cannot be an index */
324 else if (a64)
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
326 else
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
328
329 if (base == 5 && mod == 0) {
330 op->basereg = -1;
331 mod = 2; /* Fake disp32 */
332 } else if (a64)
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
334 else
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
336
337 if (segsize == 16)
338 op->disp_size = 32;
339 }
340
341 switch (mod) {
342 case 0:
343 op->segment |= SEG_NODISP;
344 break;
345 case 1:
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
348 data++;
349 break;
350 case 2:
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
353 data += 4;
354 break;
355 }
356 return data;
357 }
358 }
359
360 /*
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
363 */
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
365
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
368 {
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
376 int i, c;
377 struct operand *opx;
378 int s_field_for = -1; /* No 144/154 series code encountered */
379 bool vex_ok = false;
380 int regmask = (segsize == 64) ? 15 : 7;
381
382 for (i = 0; i < MAX_OPERANDS; i++) {
383 ins->oprs[i].segment = ins->oprs[i].disp_size =
384 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
385 }
386 ins->condition = -1;
387 ins->rex = prefix->rex;
388 memset(ins->prefixes, 0, sizeof ins->prefixes);
389
390 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
391 return false;
392
393 if (prefix->rep == 0xF2)
394 drep = P_REPNE;
395 else if (prefix->rep == 0xF3)
396 drep = P_REP;
397
398 while ((c = *r++) != 0) {
399 opx = &ins->oprs[c & 3];
400
401 switch (c) {
402 case 01:
403 case 02:
404 case 03:
405 while (c--)
406 if (*r++ != *data++)
407 return false;
408 break;
409
410 case4(010):
411 {
412 int t = *r++, d = *data++;
413 if (d < t || d > t + 7)
414 return false;
415 else {
416 opx->basereg = (d-t)+
417 (ins->rex & REX_B ? 8 : 0);
418 opx->segment |= SEG_RMREG;
419 }
420 break;
421 }
422
423 case4(014):
424 case4(0274):
425 opx->offset = (int8_t)*data++;
426 opx->segment |= SEG_SIGNED;
427 break;
428
429 case4(020):
430 opx->offset = *data++;
431 break;
432
433 case4(024):
434 opx->offset = *data++;
435 break;
436
437 case4(030):
438 opx->offset = getu16(data);
439 data += 2;
440 break;
441
442 case4(034):
443 if (osize == 32) {
444 opx->offset = getu32(data);
445 data += 4;
446 } else {
447 opx->offset = getu16(data);
448 data += 2;
449 }
450 if (segsize != asize)
451 opx->disp_size = asize;
452 break;
453
454 case4(040):
455 case4(0254):
456 opx->offset = getu32(data);
457 data += 4;
458 break;
459
460 case4(044):
461 switch (asize) {
462 case 16:
463 opx->offset = getu16(data);
464 data += 2;
465 if (segsize != 16)
466 opx->disp_size = 16;
467 break;
468 case 32:
469 opx->offset = getu32(data);
470 data += 4;
471 if (segsize == 16)
472 opx->disp_size = 32;
473 break;
474 case 64:
475 opx->offset = getu64(data);
476 opx->disp_size = 64;
477 data += 8;
478 break;
479 }
480 break;
481
482 case4(050):
483 opx->offset = gets8(data++);
484 opx->segment |= SEG_RELATIVE;
485 break;
486
487 case4(054):
488 opx->offset = getu64(data);
489 data += 8;
490 break;
491
492 case4(060):
493 opx->offset = gets16(data);
494 data += 2;
495 opx->segment |= SEG_RELATIVE;
496 opx->segment &= ~SEG_32BIT;
497 break;
498
499 case4(064):
500 opx->segment |= SEG_RELATIVE;
501 if (osize == 16) {
502 opx->offset = gets16(data);
503 data += 2;
504 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
505 } else if (osize == 32) {
506 opx->offset = gets32(data);
507 data += 4;
508 opx->segment &= ~SEG_64BIT;
509 opx->segment |= SEG_32BIT;
510 }
511 if (segsize != osize) {
512 opx->type =
513 (opx->type & ~SIZE_MASK)
514 | ((osize == 16) ? BITS16 : BITS32);
515 }
516 break;
517
518 case4(070):
519 opx->offset = gets32(data);
520 data += 4;
521 opx->segment |= SEG_32BIT | SEG_RELATIVE;
522 break;
523
524 case4(0100):
525 case4(0110):
526 case4(0120):
527 case4(0130):
528 {
529 int modrm = *data++;
530 opx->segment |= SEG_RMREG;
531 data = do_ea(data, modrm, asize, segsize,
532 &ins->oprs[(c >> 3) & 3], ins);
533 if (!data)
534 return false;
535 opx->basereg = ((modrm >> 3)&7)+
536 (ins->rex & REX_R ? 8 : 0);
537 break;
538 }
539
540 case4(0140):
541 if (s_field_for == (c & 3)) {
542 opx->offset = gets8(data);
543 data++;
544 } else {
545 opx->offset = getu16(data);
546 data += 2;
547 }
548 break;
549
550 case4(0144):
551 case4(0154):
552 s_field_for = (*data & 0x02) ? c & 3 : -1;
553 if ((*data++ & ~0x02) != *r++)
554 return false;
555 break;
556
557 case4(0150):
558 if (s_field_for == (c & 3)) {
559 opx->offset = gets8(data);
560 data++;
561 } else {
562 opx->offset = getu32(data);
563 data += 4;
564 }
565 break;
566
567 case4(0160):
568 ins->rex |= REX_D;
569 ins->drexdst = c & 3;
570 break;
571
572 case4(0164):
573 ins->rex |= REX_D|REX_OC;
574 ins->drexdst = c & 3;
575 break;
576
577 case 0171:
578 data = do_drex(data, ins);
579 if (!data)
580 return false;
581 break;
582
583 case 0172:
584 {
585 uint8_t ximm = *data++;
586 c = *r++;
587 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
588 ins->oprs[c >> 3].segment |= SEG_RMREG;
589 ins->oprs[c & 7].offset = ximm & 15;
590 }
591 break;
592
593 case 0173:
594 {
595 uint8_t ximm = *data++;
596 c = *r++;
597
598 if ((c ^ ximm) & 15)
599 return false;
600
601 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
602 ins->oprs[c >> 4].segment |= SEG_RMREG;
603 }
604 break;
605
606 case 0174:
607 {
608 uint8_t ximm = *data++;
609 c = *r++;
610
611 ins->oprs[c].basereg = (ximm >> 4) & regmask;
612 ins->oprs[c].segment |= SEG_RMREG;
613 }
614 break;
615
616 case4(0200):
617 case4(0204):
618 case4(0210):
619 case4(0214):
620 case4(0220):
621 case4(0224):
622 case4(0230):
623 case4(0234):
624 {
625 int modrm = *data++;
626 if (((modrm >> 3) & 07) != (c & 07))
627 return false; /* spare field doesn't match up */
628 data = do_ea(data, modrm, asize, segsize,
629 &ins->oprs[(c >> 3) & 07], ins);
630 if (!data)
631 return false;
632 break;
633 }
634
635 case4(0260):
636 {
637 int vexm = *r++;
638 int vexwlp = *r++;
639 ins->rex |= REX_V;
640 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
641 return false;
642
643 if ((vexm & 0x1f) != prefix->vex_m)
644 return false;
645
646 switch (vexwlp & 030) {
647 case 000:
648 if (prefix->rex & REX_W)
649 return false;
650 break;
651 case 010:
652 if (!(prefix->rex & REX_W))
653 return false;
654 ins->rex &= ~REX_W;
655 break;
656 case 020: /* VEX.W is a don't care */
657 ins->rex &= ~REX_W;
658 break;
659 case 030:
660 break;
661 }
662
663 if ((vexwlp & 007) != prefix->vex_lp)
664 return false;
665
666 opx->segment |= SEG_RMREG;
667 opx->basereg = prefix->vex_v;
668 vex_ok = true;
669 break;
670 }
671
672 case 0270:
673 {
674 int vexm = *r++;
675 int vexwlp = *r++;
676 ins->rex |= REX_V;
677 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
678 return false;
679
680 if ((vexm & 0x1f) != prefix->vex_m)
681 return false;
682
683 switch (vexwlp & 030) {
684 case 000:
685 if (ins->rex & REX_W)
686 return false;
687 break;
688 case 010:
689 if (!(ins->rex & REX_W))
690 return false;
691 break;
692 default:
693 break; /* Need to do anything special here? */
694 }
695
696 if ((vexwlp & 007) != prefix->vex_lp)
697 return false;
698
699 if (prefix->vex_v != 0)
700 return false;
701
702 vex_ok = true;
703 break;
704 }
705
706 case 0310:
707 if (asize != 16)
708 return false;
709 else
710 a_used = true;
711 break;
712
713 case 0311:
714 if (asize == 16)
715 return false;
716 else
717 a_used = true;
718 break;
719
720 case 0312:
721 if (asize != segsize)
722 return false;
723 else
724 a_used = true;
725 break;
726
727 case 0313:
728 if (asize != 64)
729 return false;
730 else
731 a_used = true;
732 break;
733
734 case 0314:
735 if (prefix->rex & REX_B)
736 return false;
737 break;
738
739 case 0315:
740 if (prefix->rex & REX_X)
741 return false;
742 break;
743
744 case 0316:
745 if (prefix->rex & REX_R)
746 return false;
747 break;
748
749 case 0317:
750 if (prefix->rex & REX_W)
751 return false;
752 break;
753
754 case 0320:
755 if (osize != 16)
756 return false;
757 else
758 o_used = true;
759 break;
760
761 case 0321:
762 if (osize != 32)
763 return false;
764 else
765 o_used = true;
766 break;
767
768 case 0322:
769 if (osize != (segsize == 16) ? 16 : 32)
770 return false;
771 else
772 o_used = true;
773 break;
774
775 case 0323:
776 ins->rex |= REX_W; /* 64-bit only instruction */
777 osize = 64;
778 o_used = true;
779 break;
780
781 case 0324:
782 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
783 return false;
784 o_used = true;
785 break;
786
787 case 0330:
788 {
789 int t = *r++, d = *data++;
790 if (d < t || d > t + 15)
791 return false;
792 else
793 ins->condition = d - t;
794 break;
795 }
796
797 case 0331:
798 if (prefix->rep)
799 return false;
800 break;
801
802 case 0332:
803 if (prefix->rep != 0xF2)
804 return false;
805 drep = 0;
806 break;
807
808 case 0333:
809 if (prefix->rep != 0xF3)
810 return false;
811 drep = 0;
812 break;
813
814 case 0334:
815 if (lock) {
816 ins->rex |= REX_R;
817 lock = 0;
818 }
819 break;
820
821 case 0335:
822 if (drep == P_REP)
823 drep = P_REPE;
824 break;
825
826 case 0336:
827 case 0337:
828 break;
829
830 case 0340:
831 return false;
832
833 case4(0344):
834 ins->oprs[0].basereg = (*data++ >> 3) & 7;
835 break;
836
837 case 0360:
838 if (prefix->osp || prefix->rep)
839 return false;
840 break;
841
842 case 0361:
843 if (!prefix->osp || prefix->rep)
844 return false;
845 o_used = true;
846 break;
847
848 case 0362:
849 if (prefix->osp || prefix->rep != 0xf2)
850 return false;
851 drep = 0;
852 break;
853
854 case 0363:
855 if (prefix->osp || prefix->rep != 0xf3)
856 return false;
857 drep = 0;
858 break;
859
860 case 0364:
861 if (prefix->osp)
862 return false;
863 break;
864
865 case 0365:
866 if (prefix->asp)
867 return false;
868 break;
869
870 case 0366:
871 if (!prefix->osp)
872 return false;
873 o_used = true;
874 break;
875
876 case 0367:
877 if (!prefix->asp)
878 return false;
879 a_used = true;
880 break;
881
882 default:
883 return false; /* Unknown code */
884 }
885 }
886
887 if (!vex_ok && (ins->rex & REX_V))
888 return false;
889
890 /* REX cannot be combined with DREX or VEX */
891 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
892 return false;
893
894 /*
895 * Check for unused rep or a/o prefixes.
896 */
897 for (i = 0; i < t->operands; i++) {
898 if (ins->oprs[i].segment != SEG_RMREG)
899 a_used = true;
900 }
901
902 if (lock) {
903 if (ins->prefixes[PPS_LREP])
904 return false;
905 ins->prefixes[PPS_LREP] = P_LOCK;
906 }
907 if (drep) {
908 if (ins->prefixes[PPS_LREP])
909 return false;
910 ins->prefixes[PPS_LREP] = drep;
911 }
912 if (!o_used) {
913 if (osize != ((segsize == 16) ? 16 : 32)) {
914 enum prefixes pfx = 0;
915
916 switch (osize) {
917 case 16:
918 pfx = P_O16;
919 break;
920 case 32:
921 pfx = P_O32;
922 break;
923 case 64:
924 pfx = P_O64;
925 break;
926 }
927
928 if (ins->prefixes[PPS_OSIZE])
929 return false;
930 ins->prefixes[PPS_OSIZE] = pfx;
931 }
932 }
933 if (!a_used && asize != segsize) {
934 if (ins->prefixes[PPS_ASIZE])
935 return false;
936 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
937 }
938
939 /* Fix: check for redundant REX prefixes */
940
941 return data - origdata;
942 }
943
944 /* Condition names for disassembly, sorted by x86 code */
945 static const char * const condition_name[16] = {
946 "o", "no", "c", "nc", "z", "nz", "na", "a",
947 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
948 };
949
950 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
951 int32_t offset, int autosync, uint32_t prefer)
952 {
953 const struct itemplate * const *p, * const *best_p;
954 const struct disasm_index *ix;
955 uint8_t *dp;
956 int length, best_length = 0;
957 char *segover;
958 int i, slen, colon, n;
959 uint8_t *origdata;
960 int works;
961 insn tmp_ins, ins;
962 uint32_t goodness, best;
963 int best_pref;
964 struct prefix_info prefix;
965 bool end_prefix;
966
967 memset(&ins, 0, sizeof ins);
968
969 /*
970 * Scan for prefixes.
971 */
972 memset(&prefix, 0, sizeof prefix);
973 prefix.asize = segsize;
974 prefix.osize = (segsize == 64) ? 32 : segsize;
975 segover = NULL;
976 origdata = data;
977
978 ix = itable;
979
980 end_prefix = false;
981 while (!end_prefix) {
982 switch (*data) {
983 case 0xF2:
984 case 0xF3:
985 prefix.rep = *data++;
986 break;
987
988 case 0xF0:
989 prefix.lock = *data++;
990 break;
991
992 case 0x2E:
993 segover = "cs", prefix.seg = *data++;
994 break;
995 case 0x36:
996 segover = "ss", prefix.seg = *data++;
997 break;
998 case 0x3E:
999 segover = "ds", prefix.seg = *data++;
1000 break;
1001 case 0x26:
1002 segover = "es", prefix.seg = *data++;
1003 break;
1004 case 0x64:
1005 segover = "fs", prefix.seg = *data++;
1006 break;
1007 case 0x65:
1008 segover = "gs", prefix.seg = *data++;
1009 break;
1010
1011 case 0x66:
1012 prefix.osize = (segsize == 16) ? 32 : 16;
1013 prefix.osp = *data++;
1014 break;
1015 case 0x67:
1016 prefix.asize = (segsize == 32) ? 16 : 32;
1017 prefix.asp = *data++;
1018 break;
1019
1020 case 0xC4:
1021 case 0xC5:
1022 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1023 prefix.vex[0] = *data++;
1024 prefix.vex[1] = *data++;
1025
1026 prefix.rex = REX_V;
1027
1028 if (prefix.vex[0] == 0xc4) {
1029 prefix.vex[2] = *data++;
1030 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1031 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1032 prefix.vex_m = prefix.vex[1] & 0x1f;
1033 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1034 prefix.vex_lp = prefix.vex[2] & 7;
1035 } else {
1036 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1037 prefix.vex_m = 1;
1038 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1039 prefix.vex_lp = prefix.vex[1] & 7;
1040 }
1041
1042 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1043 }
1044 end_prefix = true;
1045 break;
1046
1047 case REX_P + 0x0:
1048 case REX_P + 0x1:
1049 case REX_P + 0x2:
1050 case REX_P + 0x3:
1051 case REX_P + 0x4:
1052 case REX_P + 0x5:
1053 case REX_P + 0x6:
1054 case REX_P + 0x7:
1055 case REX_P + 0x8:
1056 case REX_P + 0x9:
1057 case REX_P + 0xA:
1058 case REX_P + 0xB:
1059 case REX_P + 0xC:
1060 case REX_P + 0xD:
1061 case REX_P + 0xE:
1062 case REX_P + 0xF:
1063 if (segsize == 64) {
1064 prefix.rex = *data++;
1065 if (prefix.rex & REX_W)
1066 prefix.osize = 64;
1067 }
1068 end_prefix = true;
1069 break;
1070
1071 default:
1072 end_prefix = true;
1073 break;
1074 }
1075 }
1076
1077 best = -1; /* Worst possible */
1078 best_p = NULL;
1079 best_pref = INT_MAX;
1080
1081 if (!ix)
1082 return 0; /* No instruction table at all... */
1083
1084 dp = data;
1085 ix += *dp++;
1086 while (ix->n == -1) {
1087 ix = (const struct disasm_index *)ix->p + *dp++;
1088 }
1089
1090 p = (const struct itemplate * const *)ix->p;
1091 for (n = ix->n; n; n--, p++) {
1092 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1093 works = true;
1094 /*
1095 * Final check to make sure the types of r/m match up.
1096 * XXX: Need to make sure this is actually correct.
1097 */
1098 for (i = 0; i < (*p)->operands; i++) {
1099 if (!((*p)->opd[i] & SAME_AS) &&
1100 (
1101 /* If it's a mem-only EA but we have a
1102 register, die. */
1103 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1104 !(MEMORY & ~(*p)->opd[i])) ||
1105 /* If it's a reg-only EA but we have a memory
1106 ref, die. */
1107 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1108 !(REG_EA & ~(*p)->opd[i]) &&
1109 !((*p)->opd[i] & REG_SMASK)) ||
1110 /* Register type mismatch (eg FS vs REG_DESS):
1111 die. */
1112 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1113 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1114 !whichreg((*p)->opd[i],
1115 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1116 )) {
1117 works = false;
1118 break;
1119 }
1120 }
1121
1122 /*
1123 * Note: we always prefer instructions which incorporate
1124 * prefixes in the instructions themselves. This is to allow
1125 * e.g. PAUSE to be preferred to REP NOP, and deal with
1126 * MMX/SSE instructions where prefixes are used to select
1127 * between MMX and SSE register sets or outright opcode
1128 * selection.
1129 */
1130 if (works) {
1131 int i, nprefix;
1132 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1133 nprefix = 0;
1134 for (i = 0; i < MAXPREFIX; i++)
1135 if (tmp_ins.prefixes[i])
1136 nprefix++;
1137 if (nprefix < best_pref ||
1138 (nprefix == best_pref && goodness < best)) {
1139 /* This is the best one found so far */
1140 best = goodness;
1141 best_p = p;
1142 best_pref = nprefix;
1143 best_length = length;
1144 ins = tmp_ins;
1145 }
1146 }
1147 }
1148 }
1149
1150 if (!best_p)
1151 return 0; /* no instruction was matched */
1152
1153 /* Pick the best match */
1154 p = best_p;
1155 length = best_length;
1156
1157 slen = 0;
1158
1159 /* TODO: snprintf returns the value that the string would have if
1160 * the buffer were long enough, and not the actual length of
1161 * the returned string, so each instance of using the return
1162 * value of snprintf should actually be checked to assure that
1163 * the return value is "sane." Maybe a macro wrapper could
1164 * be used for that purpose.
1165 */
1166 for (i = 0; i < MAXPREFIX; i++)
1167 switch (ins.prefixes[i]) {
1168 case P_LOCK:
1169 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1170 break;
1171 case P_REP:
1172 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1173 break;
1174 case P_REPE:
1175 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1176 break;
1177 case P_REPNE:
1178 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1179 break;
1180 case P_A16:
1181 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1182 break;
1183 case P_A32:
1184 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1185 break;
1186 case P_A64:
1187 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1188 break;
1189 case P_O16:
1190 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1191 break;
1192 case P_O32:
1193 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1194 break;
1195 case P_O64:
1196 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1197 break;
1198 default:
1199 break;
1200 }
1201
1202 i = (*p)->opcode;
1203 if (i >= FIRST_COND_OPCODE)
1204 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1205 nasm_insn_names[i], condition_name[ins.condition]);
1206 else
1207 slen += snprintf(output + slen, outbufsize - slen, "%s",
1208 nasm_insn_names[i]);
1209
1210 colon = false;
1211 length += data - origdata; /* fix up for prefixes */
1212 for (i = 0; i < (*p)->operands; i++) {
1213 opflags_t t = (*p)->opd[i];
1214 const operand *o = &ins.oprs[i];
1215 int64_t offs;
1216
1217 if (t & SAME_AS) {
1218 o = &ins.oprs[t & ~SAME_AS];
1219 t = (*p)->opd[t & ~SAME_AS];
1220 }
1221
1222 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1223
1224 offs = o->offset;
1225 if (o->segment & SEG_RELATIVE) {
1226 offs += offset + length;
1227 /*
1228 * sort out wraparound
1229 */
1230 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1231 offs &= 0xffff;
1232 else if (segsize != 64)
1233 offs &= 0xffffffff;
1234
1235 /*
1236 * add sync marker, if autosync is on
1237 */
1238 if (autosync)
1239 add_sync(offs, 0L);
1240 }
1241
1242 if (t & COLON)
1243 colon = true;
1244 else
1245 colon = false;
1246
1247 if ((t & (REGISTER | FPUREG)) ||
1248 (o->segment & SEG_RMREG)) {
1249 enum reg_enum reg;
1250 reg = whichreg(t, o->basereg, ins.rex);
1251 if (t & TO)
1252 slen += snprintf(output + slen, outbufsize - slen, "to ");
1253 slen += snprintf(output + slen, outbufsize - slen, "%s",
1254 nasm_reg_names[reg-EXPR_REG_START]);
1255 } else if (!(UNITY & ~t)) {
1256 output[slen++] = '1';
1257 } else if (t & IMMEDIATE) {
1258 if (t & BITS8) {
1259 slen +=
1260 snprintf(output + slen, outbufsize - slen, "byte ");
1261 if (o->segment & SEG_SIGNED) {
1262 if (offs < 0) {
1263 offs *= -1;
1264 output[slen++] = '-';
1265 } else
1266 output[slen++] = '+';
1267 }
1268 } else if (t & BITS16) {
1269 slen +=
1270 snprintf(output + slen, outbufsize - slen, "word ");
1271 } else if (t & BITS32) {
1272 slen +=
1273 snprintf(output + slen, outbufsize - slen, "dword ");
1274 } else if (t & BITS64) {
1275 slen +=
1276 snprintf(output + slen, outbufsize - slen, "qword ");
1277 } else if (t & NEAR) {
1278 slen +=
1279 snprintf(output + slen, outbufsize - slen, "near ");
1280 } else if (t & SHORT) {
1281 slen +=
1282 snprintf(output + slen, outbufsize - slen, "short ");
1283 }
1284 slen +=
1285 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1286 offs);
1287 } else if (!(MEM_OFFS & ~t)) {
1288 slen +=
1289 snprintf(output + slen, outbufsize - slen,
1290 "[%s%s%s0x%"PRIx64"]",
1291 (segover ? segover : ""),
1292 (segover ? ":" : ""),
1293 (o->disp_size == 64 ? "qword " :
1294 o->disp_size == 32 ? "dword " :
1295 o->disp_size == 16 ? "word " : ""), offs);
1296 segover = NULL;
1297 } else if (!(REGMEM & ~t)) {
1298 int started = false;
1299 if (t & BITS8)
1300 slen +=
1301 snprintf(output + slen, outbufsize - slen, "byte ");
1302 if (t & BITS16)
1303 slen +=
1304 snprintf(output + slen, outbufsize - slen, "word ");
1305 if (t & BITS32)
1306 slen +=
1307 snprintf(output + slen, outbufsize - slen, "dword ");
1308 if (t & BITS64)
1309 slen +=
1310 snprintf(output + slen, outbufsize - slen, "qword ");
1311 if (t & BITS80)
1312 slen +=
1313 snprintf(output + slen, outbufsize - slen, "tword ");
1314 if (t & BITS128)
1315 slen +=
1316 snprintf(output + slen, outbufsize - slen, "oword ");
1317 if (t & BITS256)
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "yword ");
1320 if (t & FAR)
1321 slen += snprintf(output + slen, outbufsize - slen, "far ");
1322 if (t & NEAR)
1323 slen +=
1324 snprintf(output + slen, outbufsize - slen, "near ");
1325 output[slen++] = '[';
1326 if (o->disp_size)
1327 slen += snprintf(output + slen, outbufsize - slen, "%s",
1328 (o->disp_size == 64 ? "qword " :
1329 o->disp_size == 32 ? "dword " :
1330 o->disp_size == 16 ? "word " :
1331 ""));
1332 if (o->eaflags & EAF_REL)
1333 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1334 if (segover) {
1335 slen +=
1336 snprintf(output + slen, outbufsize - slen, "%s:",
1337 segover);
1338 segover = NULL;
1339 }
1340 if (o->basereg != -1) {
1341 slen += snprintf(output + slen, outbufsize - slen, "%s",
1342 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1343 started = true;
1344 }
1345 if (o->indexreg != -1) {
1346 if (started)
1347 output[slen++] = '+';
1348 slen += snprintf(output + slen, outbufsize - slen, "%s",
1349 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1350 if (o->scale > 1)
1351 slen +=
1352 snprintf(output + slen, outbufsize - slen, "*%d",
1353 o->scale);
1354 started = true;
1355 }
1356
1357
1358 if (o->segment & SEG_DISP8) {
1359 const char *prefix;
1360 uint8_t offset = offs;
1361 if ((int8_t)offset < 0) {
1362 prefix = "-";
1363 offset = -offset;
1364 } else {
1365 prefix = "+";
1366 }
1367 slen +=
1368 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1369 prefix, offset);
1370 } else if (o->segment & SEG_DISP16) {
1371 const char *prefix;
1372 uint16_t offset = offs;
1373 if ((int16_t)offset < 0 && started) {
1374 offset = -offset;
1375 prefix = "-";
1376 } else {
1377 prefix = started ? "+" : "";
1378 }
1379 slen +=
1380 snprintf(output + slen, outbufsize - slen,
1381 "%s0x%"PRIx16"", prefix, offset);
1382 } else if (o->segment & SEG_DISP32) {
1383 if (prefix.asize == 64) {
1384 const char *prefix;
1385 uint64_t offset = (int64_t)(int32_t)offs;
1386 if ((int32_t)offs < 0 && started) {
1387 offset = -offset;
1388 prefix = "-";
1389 } else {
1390 prefix = started ? "+" : "";
1391 }
1392 slen +=
1393 snprintf(output + slen, outbufsize - slen,
1394 "%s0x%"PRIx64"", prefix, offset);
1395 } else {
1396 const char *prefix;
1397 uint32_t offset = offs;
1398 if ((int32_t) offset < 0 && started) {
1399 offset = -offset;
1400 prefix = "-";
1401 } else {
1402 prefix = started ? "+" : "";
1403 }
1404 slen +=
1405 snprintf(output + slen, outbufsize - slen,
1406 "%s0x%"PRIx32"", prefix, offset);
1407 }
1408 }
1409 output[slen++] = ']';
1410 } else {
1411 slen +=
1412 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1413 i);
1414 }
1415 }
1416 output[slen] = '\0';
1417 if (segover) { /* unused segment override */
1418 char *p = output;
1419 int count = slen + 1;
1420 while (count--)
1421 p[count + 3] = p[count];
1422 strncpy(output, segover, 2);
1423 output[2] = ' ';
1424 }
1425 return length;
1426 }
1427
1428 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1429 {
1430 snprintf(output, outbufsize, "db 0x%02X", *data);
1431 return 1;
1432 }
The Netwide Assembler