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Run make alldeps
[nasm.git] / asm / assemble.c
blob78dbb60932dd89bf1b8f171f64e6edfbbe7b719a
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2016 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 00m mmm
85 * c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183
184 #include "nasm.h"
185 #include "nasmlib.h"
186 #include "assemble.h"
187 #include "insns.h"
188 #include "tables.h"
189 #include "disp8.h"
190 #include "listing.h"
191
192 enum match_result {
193 /*
194 * Matching errors. These should be sorted so that more specific
195 * errors come later in the sequence.
196 */
197 MERR_INVALOP,
198 MERR_OPSIZEMISSING,
199 MERR_OPSIZEMISMATCH,
200 MERR_BRNUMMISMATCH,
201 MERR_BADCPU,
202 MERR_BADMODE,
203 MERR_BADHLE,
204 MERR_ENCMISMATCH,
205 MERR_BADBND,
206 MERR_BADREPNE,
207 /*
208 * Matching success; the conditional ones first
209 */
210 MOK_JUMP, /* Matching OK but needs jmp_match() */
211 MOK_GOOD /* Matching unconditionally OK */
212 };
213
214 typedef struct {
215 enum ea_type type; /* what kind of EA is this? */
216 int sib_present; /* is a SIB byte necessary? */
217 int bytes; /* # of bytes of offset needed */
218 int size; /* lazy - this is sib+bytes+1 */
219 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
220 int8_t disp8; /* compressed displacement for EVEX */
221 } ea;
222
223 #define GEN_SIB(scale, index, base) \
224 (((scale) << 6) | ((index) << 3) | ((base)))
225
226 #define GEN_MODRM(mod, reg, rm) \
227 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
228
229 static iflag_t cpu; /* cpu level received from nasm.c */
230
231 static int64_t calcsize(int32_t, int64_t, int, insn *,
232 const struct itemplate *);
233 static int emit_prefix(struct out_data *data, const int bits, insn *ins);
234 static void gencode(struct out_data *data, insn *ins);
235 static enum match_result find_match(const struct itemplate **tempp,
236 insn *instruction,
237 int32_t segment, int64_t offset, int bits);
238 static enum match_result matches(const struct itemplate *, insn *, int bits);
239 static opflags_t regflag(const operand *);
240 static int32_t regval(const operand *);
241 static int rexflags(int, opflags_t, int);
242 static int op_rexflags(const operand *, int);
243 static int op_evexflags(const operand *, int, uint8_t);
244 static void add_asp(insn *, int);
245
246 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
247
248 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
249 {
250 return ins->prefixes[pos] == prefix;
251 }
252
253 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
254 {
255 if (ins->prefixes[pos])
256 nasm_error(ERR_NONFATAL, "invalid %s prefix",
257 prefix_name(ins->prefixes[pos]));
258 }
259
260 static const char *size_name(int size)
261 {
262 switch (size) {
263 case 1:
264 return "byte";
265 case 2:
266 return "word";
267 case 4:
268 return "dword";
269 case 8:
270 return "qword";
271 case 10:
272 return "tword";
273 case 16:
274 return "oword";
275 case 32:
276 return "yword";
277 case 64:
278 return "zword";
279 default:
280 return "???";
281 }
282 }
283
284 static void warn_overflow(int pass, int size)
285 {
286 nasm_error(ERR_WARNING | pass | ERR_WARN_NOV,
287 "%s data exceeds bounds", size_name(size));
288 }
289
290 static void warn_overflow_const(int64_t data, int size)
291 {
292 if (overflow_general(data, size))
293 warn_overflow(ERR_PASS1, size);
294 }
295
296 static void warn_overflow_opd(const struct operand *o, int size)
297 {
298 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
299 if (overflow_general(o->offset, size))
300 warn_overflow(ERR_PASS2, size);
301 }
302 }
303
304 /*
305 * This routine wrappers the real output format's output routine,
306 * in order to pass a copy of the data off to the listing file
307 * generator at the same time, flatten unnecessary relocations,
308 * and verify backend compatibility.
309 */
310 static void out(struct out_data *data)
311 {
312 static int32_t lineno = 0; /* static!!! */
313 static const char *lnfname = NULL;
314 int asize;
315 const int amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
316 union {
317 uint8_t b[8];
318 uint64_t q;
319 } xdata;
320 uint64_t size = data->size;
321
322 if (!data->size)
323 return; /* Nothing to do */
324
325 switch (data->type) {
326 case OUT_ADDRESS:
327 asize = data->size;
328 nasm_assert(asize <= 8);
329 if (data->tsegment == NO_SEG && data->twrt == NO_SEG) {
330 /* Convert to RAWDATA */
331 /* XXX: check for overflow */
332 uint8_t *q = xdata.b;
333
334 WRITEADDR(q, data->toffset, asize);
335 data->data = xdata.b;
336 data->type = OUT_RAWDATA;
337 asize = 0; /* No longer an address */
338 }
339 break;
340
341 case OUT_RELADDR:
342 asize = data->size;
343 nasm_assert(asize <= 8);
344 if (data->tsegment == data->segment && data->twrt == NO_SEG) {
345 /* Convert to RAWDATA */
346 uint8_t *q = xdata.b;
347 int64_t delta = data->toffset - data->offset
348 - (data->inslen - data->insoffs);
349
350 if (overflow_signed(delta, asize))
351 warn_overflow(ERR_PASS2, asize);
352
353 WRITEADDR(q, delta, asize);
354 data->data = xdata.b;
355 data->type = OUT_RAWDATA;
356 asize = 0; /* No longer an address */
357 }
358 break;
359
360 default:
361 asize = 0; /* Not an address */
362 break;
363 }
364
365 lfmt->output(data);
366
367 /*
368 * this call to src_get determines when we call the
369 * debug-format-specific "linenum" function
370 * it updates lineno and lnfname to the current values
371 * returning 0 if "same as last time", -2 if lnfname
372 * changed, and the amount by which lineno changed,
373 * if it did. thus, these variables must be static
374 */
375
376 if (src_get(&lineno, &lnfname))
377 dfmt->linenum(lnfname, lineno, data->segment);
378
379 if (asize && asize > amax) {
380 if (data->type != OUT_ADDRESS || data->sign == OUT_SIGNED) {
381 nasm_error(ERR_NONFATAL,
382 "%d-bit signed relocation unsupported by output format %s\n",
383 asize << 3, ofmt->shortname);
384 } else {
385 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
386 "%d-bit unsigned relocation zero-extended from %d bits\n",
387 asize << 3, ofmt->maxbits);
388 data->size = amax;
389 ofmt->output(data);
390 data->insoffs += amax;
391 data->offset += amax;
392 data->size = size = asize - amax;
393 }
394 data->data = zero_buffer;
395 data->type = OUT_RAWDATA;
396 }
397
398 ofmt->output(data);
399 data->offset += size;
400 data->insoffs += size;
401 }
402
403 static inline void out_rawdata(struct out_data *data, const void *rawdata,
404 size_t size)
405 {
406 data->type = OUT_RAWDATA;
407 data->data = rawdata;
408 data->size = size;
409 out(data);
410 }
411
412 static void out_rawbyte(struct out_data *data, uint8_t byte)
413 {
414 data->type = OUT_RAWDATA;
415 data->data = &byte;
416 data->size = 1;
417 out(data);
418 }
419
420 static inline void out_reserve(struct out_data *data, uint64_t size)
421 {
422 data->type = OUT_RESERVE;
423 data->size = size;
424 out(data);
425 }
426
427 static inline void out_imm(struct out_data *data, struct operand *opx,
428 int size, enum out_sign sign)
429 {
430 data->type = OUT_ADDRESS;
431 data->sign = sign;
432 data->size = size;
433 data->toffset = opx->offset;
434 data->tsegment = opx->segment;
435 data->twrt = opx->wrt;
436 out(data);
437 }
438
439 static inline void out_reladdr(struct out_data *data, struct operand *opx,
440 int size)
441 {
442 data->type = OUT_RELADDR;
443 data->sign = OUT_SIGNED;
444 data->size = size;
445 data->toffset = opx->offset;
446 data->tsegment = opx->segment;
447 data->twrt = opx->wrt;
448 out(data);
449 }
450
451 static inline void out_segment(struct out_data *data, struct operand *opx)
452 {
453 data->type = OUT_SEGMENT;
454 data->sign = OUT_UNSIGNED;
455 data->size = 2;
456 data->toffset = opx->offset;
457 data->tsegment = ofmt->segbase(opx->segment + 1);
458 data->twrt = opx->wrt;
459 out(data);
460 }
461
462 static bool jmp_match(int32_t segment, int64_t offset, int bits,
463 insn * ins, const struct itemplate *temp)
464 {
465 int64_t isize;
466 const uint8_t *code = temp->code;
467 uint8_t c = code[0];
468 bool is_byte;
469
470 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
471 return false;
472 if (!optimizing)
473 return false;
474 if (optimizing < 0 && c == 0371)
475 return false;
476
477 isize = calcsize(segment, offset, bits, ins, temp);
478
479 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
480 /* Be optimistic in pass 1 */
481 return true;
482
483 if (ins->oprs[0].segment != segment)
484 return false;
485
486 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
487 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
488
489 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
490 /* jmp short (opcode eb) cannot be used with bnd prefix. */
491 ins->prefixes[PPS_REP] = P_none;
492 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
493 "jmp short does not init bnd regs - bnd prefix dropped.");
494 }
495
496 return is_byte;
497 }
498
499 /* This is totally just a wild guess what is reasonable... */
500 #define INCBIN_MAX_BUF (ZERO_BUF_SIZE * 16)
501
502 int64_t assemble(int32_t segment, int64_t start, int bits, iflag_t cp,
503 insn * instruction)
504 {
505 struct out_data data;
506 const struct itemplate *temp;
507 enum match_result m;
508 int32_t itimes;
509 int64_t wsize; /* size for DB etc. */
510
511 cpu = cp;
512
513 data.offset = start;
514 data.segment = segment;
515 data.itemp = NULL;
516 data.sign = OUT_WRAP;
517 data.bits = bits;
518
519 wsize = idata_bytes(instruction->opcode);
520 if (wsize == -1)
521 return 0;
522
523 if (wsize) {
524 extop *e;
525 int32_t t = instruction->times;
526 if (t < 0)
527 nasm_panic(0, "instruction->times < 0 (%"PRId32") in assemble()", t);
528
529 while (t--) { /* repeat TIMES times */
530 list_for_each(e, instruction->eops) {
531 if (e->type == EOT_DB_NUMBER) {
532 if (wsize > 8) {
533 nasm_error(ERR_NONFATAL,
534 "integer supplied to a DT, DO or DY"
535 " instruction");
536 } else {
537 data.insoffs = 0;
538 data.type = OUT_ADDRESS;
539 data.inslen = data.size = wsize;
540 data.toffset = e->offset;
541 data.tsegment = e->segment;
542 data.twrt = e->wrt;
543 out(&data);
544 }
545 } else if (e->type == EOT_DB_STRING ||
546 e->type == EOT_DB_STRING_FREE) {
547 int align = e->stringlen % wsize;
548 if (align)
549 align = wsize - align;
550
551 data.insoffs = 0;
552 data.inslen = e->stringlen + align;
553
554 out_rawdata(&data, e->stringval, e->stringlen);
555 out_rawdata(&data, zero_buffer, align);
556 }
557 }
558 if (t > 0 && t == instruction->times - 1) {
559 lfmt->set_offset(data.offset);
560 lfmt->uplevel(LIST_TIMES);
561 }
562 }
563 if (instruction->times > 1)
564 lfmt->downlevel(LIST_TIMES);
565 } else if (instruction->opcode == I_INCBIN) {
566 const char *fname = instruction->eops->stringval;
567 FILE *fp;
568 size_t t = instruction->times;
569 off_t base = 0;
570 off_t len;
571 const void *map = NULL;
572 char *buf = NULL;
573 size_t blk = 0; /* Buffered I/O block size */
574 size_t m = 0; /* Bytes last read */
575
576 fp = nasm_open_read(fname, NF_BINARY|NF_FORMAP);
577 if (!fp) {
578 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
579 fname);
580 goto done;
581 }
582
583 len = nasm_file_size(fp);
584
585 if (len == (off_t)-1) {
586 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
587 fname);
588 goto close_done;
589 }
590
591 if (instruction->eops->next) {
592 base = instruction->eops->next->offset;
593 if (base >= len) {
594 len = 0;
595 } else {
596 len -= base;
597 if (instruction->eops->next->next &&
598 len > (off_t)instruction->eops->next->next->offset)
599 len = (off_t)instruction->eops->next->next->offset;
600 }
601 }
602
603 lfmt->set_offset(data.offset);
604 lfmt->uplevel(LIST_INCBIN);
605
606 if (!len)
607 goto end_incbin;
608
609 /* Try to map file data */
610 map = nasm_map_file(fp, base, len);
611 if (!map) {
612 blk = len < (off_t)INCBIN_MAX_BUF ? (size_t)len : INCBIN_MAX_BUF;
613 buf = nasm_malloc(blk);
614 }
615
616 while (t--) {
617 /*
618 * Consider these irrelevant for INCBIN, since it is fully
619 * possible that these might be (way) bigger than an int
620 * can hold; there is, however, no reason to widen these
621 * types just for INCBIN. data.inslen == 0 signals to the
622 * backend that these fields are meaningless, if at all
623 * needed.
624 */
625 data.insoffs = 0;
626 data.inslen = 0;
627
628 if (map) {
629 out_rawdata(&data, map, len);
630 } else if ((off_t)m == len) {
631 out_rawdata(&data, buf, len);
632 } else {
633 off_t l = len;
634
635 if (fseeko(fp, base, SEEK_SET) < 0 || ferror(fp)) {
636 nasm_error(ERR_NONFATAL,
637 "`incbin': unable to seek on file `%s'",
638 fname);
639 goto end_incbin;
640 }
641 while (l > 0) {
642 m = fread(buf, 1, l < (off_t)blk ? (size_t)l : blk, fp);
643 if (!m || feof(fp)) {
644 /*
645 * This shouldn't happen unless the file
646 * actually changes while we are reading
647 * it.
648 */
649 nasm_error(ERR_NONFATAL,
650 "`incbin': unexpected EOF while"
651 " reading file `%s'", fname);
652 goto end_incbin;
653 }
654 out_rawdata(&data, buf, m);
655 l -= m;
656 }
657 }
658 }
659 end_incbin:
660 lfmt->downlevel(LIST_INCBIN);
661 if (instruction->times > 1) {
662 lfmt->set_offset(data.offset);
663 lfmt->uplevel(LIST_TIMES);
664 lfmt->downlevel(LIST_TIMES);
665 }
666 if (ferror(fp)) {
667 nasm_error(ERR_NONFATAL,
668 "`incbin': error while"
669 " reading file `%s'", fname);
670 }
671 close_done:
672 if (buf)
673 nasm_free(buf);
674 if (map)
675 nasm_unmap_file(map, len);
676 fclose(fp);
677 done:
678 ;
679 } else {
680 /* "Real" instruction */
681
682 /* Check to see if we need an address-size prefix */
683 add_asp(instruction, bits);
684
685 m = find_match(&temp, instruction, data.segment, data.offset, bits);
686
687 if (m == MOK_GOOD) {
688 /* Matches! */
689 int64_t insn_size = calcsize(data.segment, data.offset,
690 bits, instruction, temp);
691 itimes = instruction->times;
692 if (insn_size < 0) /* shouldn't be, on pass two */
693 nasm_panic(0, "errors made it through from pass one");
694
695 data.itemp = temp;
696 data.bits = bits;
697
698 while (itimes--) {
699 data.insoffs = 0;
700 data.inslen = insn_size;
701
702 gencode(&data, instruction);
703 nasm_assert(data.insoffs == insn_size);
704
705 if (itimes > 0 && itimes == instruction->times - 1) {
706 lfmt->set_offset(data.offset);
707 lfmt->uplevel(LIST_TIMES);
708 }
709 }
710 if (instruction->times > 1)
711 lfmt->downlevel(LIST_TIMES);
712 } else {
713 /* No match */
714 switch (m) {
715 case MERR_OPSIZEMISSING:
716 nasm_error(ERR_NONFATAL, "operation size not specified");
717 break;
718 case MERR_OPSIZEMISMATCH:
719 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
720 break;
721 case MERR_BRNUMMISMATCH:
722 nasm_error(ERR_NONFATAL,
723 "mismatch in the number of broadcasting elements");
724 break;
725 case MERR_BADCPU:
726 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
727 break;
728 case MERR_BADMODE:
729 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
730 bits);
731 break;
732 case MERR_ENCMISMATCH:
733 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
734 break;
735 case MERR_BADBND:
736 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
737 break;
738 case MERR_BADREPNE:
739 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
740 (has_prefix(instruction, PPS_REP, P_REPNE) ?
741 "repne" : "repnz"));
742 break;
743 default:
744 nasm_error(ERR_NONFATAL,
745 "invalid combination of opcode and operands");
746 break;
747 }
748 }
749 }
750 return data.offset - start;
751 }
752
753 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
754 insn * instruction)
755 {
756 const struct itemplate *temp;
757 enum match_result m;
758
759 cpu = cp;
760
761 if (instruction->opcode == I_none)
762 return 0;
763
764 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
765 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
766 instruction->opcode == I_DT || instruction->opcode == I_DO ||
767 instruction->opcode == I_DY) {
768 extop *e;
769 int32_t isize, osize, wsize;
770
771 isize = 0;
772 wsize = idata_bytes(instruction->opcode);
773
774 list_for_each(e, instruction->eops) {
775 int32_t align;
776
777 osize = 0;
778 if (e->type == EOT_DB_NUMBER) {
779 osize = 1;
780 warn_overflow_const(e->offset, wsize);
781 } else if (e->type == EOT_DB_STRING ||
782 e->type == EOT_DB_STRING_FREE)
783 osize = e->stringlen;
784
785 align = (-osize) % wsize;
786 if (align < 0)
787 align += wsize;
788 isize += osize + align;
789 }
790 return isize;
791 }
792
793 if (instruction->opcode == I_INCBIN) {
794 const char *fname = instruction->eops->stringval;
795 off_t len;
796
797 len = nasm_file_size_by_path(fname);
798 if (len == (off_t)-1) {
799 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
800 fname);
801 return 0;
802 }
803
804 if (instruction->eops->next) {
805 if (len <= (off_t)instruction->eops->next->offset) {
806 len = 0;
807 } else {
808 len -= instruction->eops->next->offset;
809 if (instruction->eops->next->next &&
810 len > (off_t)instruction->eops->next->next->offset) {
811 len = (off_t)instruction->eops->next->next->offset;
812 }
813 }
814 }
815
816 return len;
817 }
818
819 /* Check to see if we need an address-size prefix */
820 add_asp(instruction, bits);
821
822 m = find_match(&temp, instruction, segment, offset, bits);
823 if (m == MOK_GOOD) {
824 /* we've matched an instruction. */
825 return calcsize(segment, offset, bits, instruction, temp);
826 } else {
827 return -1; /* didn't match any instruction */
828 }
829 }
830
831 static void bad_hle_warn(const insn * ins, uint8_t hleok)
832 {
833 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
834 enum whatwarn { w_none, w_lock, w_inval } ww;
835 static const enum whatwarn warn[2][4] =
836 {
837 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
838 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
839 };
840 unsigned int n;
841
842 n = (unsigned int)rep_pfx - P_XACQUIRE;
843 if (n > 1)
844 return; /* Not XACQUIRE/XRELEASE */
845
846 ww = warn[n][hleok];
847 if (!is_class(MEMORY, ins->oprs[0].type))
848 ww = w_inval; /* HLE requires operand 0 to be memory */
849
850 switch (ww) {
851 case w_none:
852 break;
853
854 case w_lock:
855 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
856 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
857 "%s with this instruction requires lock",
858 prefix_name(rep_pfx));
859 }
860 break;
861
862 case w_inval:
863 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
864 "%s invalid with this instruction",
865 prefix_name(rep_pfx));
866 break;
867 }
868 }
869
870 /* Common construct */
871 #define case3(x) case (x): case (x)+1: case (x)+2
872 #define case4(x) case3(x): case (x)+3
873
874 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
875 insn * ins, const struct itemplate *temp)
876 {
877 const uint8_t *codes = temp->code;
878 int64_t length = 0;
879 uint8_t c;
880 int rex_mask = ~0;
881 int op1, op2;
882 struct operand *opx;
883 uint8_t opex = 0;
884 enum ea_type eat;
885 uint8_t hleok = 0;
886 bool lockcheck = true;
887 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
888
889 ins->rex = 0; /* Ensure REX is reset */
890 eat = EA_SCALAR; /* Expect a scalar EA */
891 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
892
893 if (ins->prefixes[PPS_OSIZE] == P_O64)
894 ins->rex |= REX_W;
895
896 (void)segment; /* Don't warn that this parameter is unused */
897 (void)offset; /* Don't warn that this parameter is unused */
898
899 while (*codes) {
900 c = *codes++;
901 op1 = (c & 3) + ((opex & 1) << 2);
902 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
903 opx = &ins->oprs[op1];
904 opex = 0; /* For the next iteration */
905
906 switch (c) {
907 case4(01):
908 codes += c, length += c;
909 break;
910
911 case3(05):
912 opex = c;
913 break;
914
915 case4(010):
916 ins->rex |=
917 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
918 codes++, length++;
919 break;
920
921 case4(014):
922 /* this is an index reg of MIB operand */
923 mib_index = opx->basereg;
924 break;
925
926 case4(020):
927 case4(024):
928 length++;
929 break;
930
931 case4(030):
932 length += 2;
933 break;
934
935 case4(034):
936 if (opx->type & (BITS16 | BITS32 | BITS64))
937 length += (opx->type & BITS16) ? 2 : 4;
938 else
939 length += (bits == 16) ? 2 : 4;
940 break;
941
942 case4(040):
943 length += 4;
944 break;
945
946 case4(044):
947 length += ins->addr_size >> 3;
948 break;
949
950 case4(050):
951 length++;
952 break;
953
954 case4(054):
955 length += 8; /* MOV reg64/imm */
956 break;
957
958 case4(060):
959 length += 2;
960 break;
961
962 case4(064):
963 if (opx->type & (BITS16 | BITS32 | BITS64))
964 length += (opx->type & BITS16) ? 2 : 4;
965 else
966 length += (bits == 16) ? 2 : 4;
967 break;
968
969 case4(070):
970 length += 4;
971 break;
972
973 case4(074):
974 length += 2;
975 break;
976
977 case 0172:
978 case 0173:
979 codes++;
980 length++;
981 break;
982
983 case4(0174):
984 length++;
985 break;
986
987 case4(0240):
988 ins->rex |= REX_EV;
989 ins->vexreg = regval(opx);
990 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
991 ins->vex_cm = *codes++;
992 ins->vex_wlp = *codes++;
993 ins->evex_tuple = (*codes++ - 0300);
994 break;
995
996 case 0250:
997 ins->rex |= REX_EV;
998 ins->vexreg = 0;
999 ins->vex_cm = *codes++;
1000 ins->vex_wlp = *codes++;
1001 ins->evex_tuple = (*codes++ - 0300);
1002 break;
1003
1004 case4(0254):
1005 length += 4;
1006 break;
1007
1008 case4(0260):
1009 ins->rex |= REX_V;
1010 ins->vexreg = regval(opx);
1011 ins->vex_cm = *codes++;
1012 ins->vex_wlp = *codes++;
1013 break;
1014
1015 case 0270:
1016 ins->rex |= REX_V;
1017 ins->vexreg = 0;
1018 ins->vex_cm = *codes++;
1019 ins->vex_wlp = *codes++;
1020 break;
1021
1022 case3(0271):
1023 hleok = c & 3;
1024 break;
1025
1026 case4(0274):
1027 length++;
1028 break;
1029
1030 case4(0300):
1031 break;
1032
1033 case 0310:
1034 if (bits == 64)
1035 return -1;
1036 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1037 break;
1038
1039 case 0311:
1040 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1041 break;
1042
1043 case 0312:
1044 break;
1045
1046 case 0313:
1047 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1048 has_prefix(ins, PPS_ASIZE, P_A32))
1049 return -1;
1050 break;
1051
1052 case4(0314):
1053 break;
1054
1055 case 0320:
1056 {
1057 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1058 if (pfx == P_O16)
1059 break;
1060 if (pfx != P_none)
1061 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1062 else
1063 ins->prefixes[PPS_OSIZE] = P_O16;
1064 break;
1065 }
1066
1067 case 0321:
1068 {
1069 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1070 if (pfx == P_O32)
1071 break;
1072 if (pfx != P_none)
1073 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1074 else
1075 ins->prefixes[PPS_OSIZE] = P_O32;
1076 break;
1077 }
1078
1079 case 0322:
1080 break;
1081
1082 case 0323:
1083 rex_mask &= ~REX_W;
1084 break;
1085
1086 case 0324:
1087 ins->rex |= REX_W;
1088 break;
1089
1090 case 0325:
1091 ins->rex |= REX_NH;
1092 break;
1093
1094 case 0326:
1095 break;
1096
1097 case 0330:
1098 codes++, length++;
1099 break;
1100
1101 case 0331:
1102 break;
1103
1104 case 0332:
1105 case 0333:
1106 length++;
1107 break;
1108
1109 case 0334:
1110 ins->rex |= REX_L;
1111 break;
1112
1113 case 0335:
1114 break;
1115
1116 case 0336:
1117 if (!ins->prefixes[PPS_REP])
1118 ins->prefixes[PPS_REP] = P_REP;
1119 break;
1120
1121 case 0337:
1122 if (!ins->prefixes[PPS_REP])
1123 ins->prefixes[PPS_REP] = P_REPNE;
1124 break;
1125
1126 case 0340:
1127 if (ins->oprs[0].segment != NO_SEG)
1128 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1129 " quantity of BSS space");
1130 else if (ins->oprs[0].opflags & OPFLAG_FORWARD)
1131 nasm_error(ERR_WARNING | ERR_PASS1,
1132 "forward reference in RESx can have unpredictable results");
1133 else
1134 length += ins->oprs[0].offset;
1135 break;
1136
1137 case 0341:
1138 if (!ins->prefixes[PPS_WAIT])
1139 ins->prefixes[PPS_WAIT] = P_WAIT;
1140 break;
1141
1142 case 0360:
1143 break;
1144
1145 case 0361:
1146 length++;
1147 break;
1148
1149 case 0364:
1150 case 0365:
1151 break;
1152
1153 case 0366:
1154 case 0367:
1155 length++;
1156 break;
1157
1158 case 0370:
1159 case 0371:
1160 break;
1161
1162 case 0373:
1163 length++;
1164 break;
1165
1166 case 0374:
1167 eat = EA_XMMVSIB;
1168 break;
1169
1170 case 0375:
1171 eat = EA_YMMVSIB;
1172 break;
1173
1174 case 0376:
1175 eat = EA_ZMMVSIB;
1176 break;
1177
1178 case4(0100):
1179 case4(0110):
1180 case4(0120):
1181 case4(0130):
1182 case4(0200):
1183 case4(0204):
1184 case4(0210):
1185 case4(0214):
1186 case4(0220):
1187 case4(0224):
1188 case4(0230):
1189 case4(0234):
1190 {
1191 ea ea_data;
1192 int rfield;
1193 opflags_t rflags;
1194 struct operand *opy = &ins->oprs[op2];
1195 struct operand *op_er_sae;
1196
1197 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1198
1199 if (c <= 0177) {
1200 /* pick rfield from operand b (opx) */
1201 rflags = regflag(opx);
1202 rfield = nasm_regvals[opx->basereg];
1203 } else {
1204 rflags = 0;
1205 rfield = c & 7;
1206 }
1207
1208 /* EVEX.b1 : evex_brerop contains the operand position */
1209 op_er_sae = (ins->evex_brerop >= 0 ?
1210 &ins->oprs[ins->evex_brerop] : NULL);
1211
1212 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1213 /* set EVEX.b */
1214 ins->evex_p[2] |= EVEX_P2B;
1215 if (op_er_sae->decoflags & ER) {
1216 /* set EVEX.RC (rounding control) */
1217 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1218 & EVEX_P2RC;
1219 }
1220 } else {
1221 /* set EVEX.L'L (vector length) */
1222 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1223 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1224 if (opy->decoflags & BRDCAST_MASK) {
1225 /* set EVEX.b */
1226 ins->evex_p[2] |= EVEX_P2B;
1227 }
1228 }
1229
1230 if (itemp_has(temp, IF_MIB)) {
1231 opy->eaflags |= EAF_MIB;
1232 /*
1233 * if a separate form of MIB (ICC style) is used,
1234 * the index reg info is merged into mem operand
1235 */
1236 if (mib_index != R_none) {
1237 opy->indexreg = mib_index;
1238 opy->scale = 1;
1239 opy->hintbase = mib_index;
1240 opy->hinttype = EAH_NOTBASE;
1241 }
1242 }
1243
1244 if (process_ea(opy, &ea_data, bits,
1245 rfield, rflags, ins) != eat) {
1246 nasm_error(ERR_NONFATAL, "invalid effective address");
1247 return -1;
1248 } else {
1249 ins->rex |= ea_data.rex;
1250 length += ea_data.size;
1251 }
1252 }
1253 break;
1254
1255 default:
1256 nasm_panic(0, "internal instruction table corrupt"
1257 ": instruction code \\%o (0x%02X) given", c, c);
1258 break;
1259 }
1260 }
1261
1262 ins->rex &= rex_mask;
1263
1264 if (ins->rex & REX_NH) {
1265 if (ins->rex & REX_H) {
1266 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1267 return -1;
1268 }
1269 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1270 }
1271
1272 switch (ins->prefixes[PPS_VEX]) {
1273 case P_EVEX:
1274 if (!(ins->rex & REX_EV))
1275 return -1;
1276 break;
1277 case P_VEX3:
1278 case P_VEX2:
1279 if (!(ins->rex & REX_V))
1280 return -1;
1281 break;
1282 default:
1283 break;
1284 }
1285
1286 if (ins->rex & (REX_V | REX_EV)) {
1287 int bad32 = REX_R|REX_W|REX_X|REX_B;
1288
1289 if (ins->rex & REX_H) {
1290 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1291 return -1;
1292 }
1293 switch (ins->vex_wlp & 060) {
1294 case 000:
1295 case 040:
1296 ins->rex &= ~REX_W;
1297 break;
1298 case 020:
1299 ins->rex |= REX_W;
1300 bad32 &= ~REX_W;
1301 break;
1302 case 060:
1303 /* Follow REX_W */
1304 break;
1305 }
1306
1307 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1308 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1309 return -1;
1310 } else if (!(ins->rex & REX_EV) &&
1311 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1312 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1313 return -1;
1314 }
1315 if (ins->rex & REX_EV)
1316 length += 4;
1317 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1318 ins->prefixes[PPS_VEX] == P_VEX3)
1319 length += 3;
1320 else
1321 length += 2;
1322 } else if (ins->rex & REX_MASK) {
1323 if (ins->rex & REX_H) {
1324 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1325 return -1;
1326 } else if (bits == 64) {
1327 length++;
1328 } else if ((ins->rex & REX_L) &&
1329 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1330 iflag_ffs(&cpu) >= IF_X86_64) {
1331 /* LOCK-as-REX.R */
1332 assert_no_prefix(ins, PPS_LOCK);
1333 lockcheck = false; /* Already errored, no need for warning */
1334 length++;
1335 } else {
1336 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1337 return -1;
1338 }
1339 }
1340
1341 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1342 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1343 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1344 "instruction is not lockable");
1345 }
1346
1347 bad_hle_warn(ins, hleok);
1348
1349 /*
1350 * when BND prefix is set by DEFAULT directive,
1351 * BND prefix is added to every appropriate instruction line
1352 * unless it is overridden by NOBND prefix.
1353 */
1354 if (globalbnd &&
1355 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1356 ins->prefixes[PPS_REP] = P_BND;
1357
1358 /*
1359 * Add length of legacy prefixes
1360 */
1361 length += emit_prefix(NULL, bits, ins);
1362
1363 return length;
1364 }
1365
1366 static inline void emit_rex(struct out_data *data, insn *ins)
1367 {
1368 if (data->bits == 64) {
1369 if ((ins->rex & REX_MASK) &&
1370 !(ins->rex & (REX_V | REX_EV)) &&
1371 !ins->rex_done) {
1372 uint8_t rex = (ins->rex & REX_MASK) | REX_P;
1373 out_rawbyte(data, rex);
1374 ins->rex_done = true;
1375 }
1376 }
1377 }
1378
1379 static int emit_prefix(struct out_data *data, const int bits, insn *ins)
1380 {
1381 int bytes = 0;
1382 int j;
1383
1384 for (j = 0; j < MAXPREFIX; j++) {
1385 uint8_t c = 0;
1386 switch (ins->prefixes[j]) {
1387 case P_WAIT:
1388 c = 0x9B;
1389 break;
1390 case P_LOCK:
1391 c = 0xF0;
1392 break;
1393 case P_REPNE:
1394 case P_REPNZ:
1395 case P_XACQUIRE:
1396 case P_BND:
1397 c = 0xF2;
1398 break;
1399 case P_REPE:
1400 case P_REPZ:
1401 case P_REP:
1402 case P_XRELEASE:
1403 c = 0xF3;
1404 break;
1405 case R_CS:
1406 if (bits == 64) {
1407 nasm_error(ERR_WARNING | ERR_PASS2,
1408 "cs segment base generated, but will be ignored in 64-bit mode");
1409 }
1410 c = 0x2E;
1411 break;
1412 case R_DS:
1413 if (bits == 64) {
1414 nasm_error(ERR_WARNING | ERR_PASS2,
1415 "ds segment base generated, but will be ignored in 64-bit mode");
1416 }
1417 c = 0x3E;
1418 break;
1419 case R_ES:
1420 if (bits == 64) {
1421 nasm_error(ERR_WARNING | ERR_PASS2,
1422 "es segment base generated, but will be ignored in 64-bit mode");
1423 }
1424 c = 0x26;
1425 break;
1426 case R_FS:
1427 c = 0x64;
1428 break;
1429 case R_GS:
1430 c = 0x65;
1431 break;
1432 case R_SS:
1433 if (bits == 64) {
1434 nasm_error(ERR_WARNING | ERR_PASS2,
1435 "ss segment base generated, but will be ignored in 64-bit mode");
1436 }
1437 c = 0x36;
1438 break;
1439 case R_SEGR6:
1440 case R_SEGR7:
1441 nasm_error(ERR_NONFATAL,
1442 "segr6 and segr7 cannot be used as prefixes");
1443 break;
1444 case P_A16:
1445 if (bits == 64) {
1446 nasm_error(ERR_NONFATAL,
1447 "16-bit addressing is not supported "
1448 "in 64-bit mode");
1449 } else if (bits != 16)
1450 c = 0x67;
1451 break;
1452 case P_A32:
1453 if (bits != 32)
1454 c = 0x67;
1455 break;
1456 case P_A64:
1457 if (bits != 64) {
1458 nasm_error(ERR_NONFATAL,
1459 "64-bit addressing is only supported "
1460 "in 64-bit mode");
1461 }
1462 break;
1463 case P_ASP:
1464 c = 0x67;
1465 break;
1466 case P_O16:
1467 if (bits != 16)
1468 c = 0x66;
1469 break;
1470 case P_O32:
1471 if (bits == 16)
1472 c = 0x66;
1473 break;
1474 case P_O64:
1475 /* REX.W */
1476 break;
1477 case P_OSP:
1478 c = 0x66;
1479 break;
1480 case P_EVEX:
1481 case P_VEX3:
1482 case P_VEX2:
1483 case P_NOBND:
1484 case P_none:
1485 break;
1486 default:
1487 nasm_panic(0, "invalid instruction prefix");
1488 }
1489 if (c) {
1490 if (data)
1491 out_rawbyte(data, c);
1492 bytes++;
1493 }
1494 }
1495 return bytes;
1496 }
1497
1498 static void gencode(struct out_data *data, insn *ins)
1499 {
1500 uint8_t c;
1501 uint8_t bytes[4];
1502 int64_t size;
1503 int op1, op2;
1504 struct operand *opx;
1505 const uint8_t *codes = data->itemp->code;
1506 uint8_t opex = 0;
1507 enum ea_type eat = EA_SCALAR;
1508 int r;
1509 const int bits = data->bits;
1510
1511 ins->rex_done = false;
1512
1513 emit_prefix(data, bits, ins);
1514
1515 while (*codes) {
1516 c = *codes++;
1517 op1 = (c & 3) + ((opex & 1) << 2);
1518 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1519 opx = &ins->oprs[op1];
1520 opex = 0; /* For the next iteration */
1521
1522
1523 switch (c) {
1524 case 01:
1525 case 02:
1526 case 03:
1527 case 04:
1528 emit_rex(data, ins);
1529 out_rawdata(data, codes, c);
1530 codes += c;
1531 break;
1532
1533 case 05:
1534 case 06:
1535 case 07:
1536 opex = c;
1537 break;
1538
1539 case4(010):
1540 emit_rex(data, ins);
1541 out_rawbyte(data, *codes++ + (regval(opx) & 7));
1542 break;
1543
1544 case4(014):
1545 break;
1546
1547 case4(020):
1548 if (opx->offset < -256 || opx->offset > 255)
1549 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1550 "byte value exceeds bounds");
1551 out_imm(data, opx, 1, OUT_WRAP);
1552 break;
1553
1554 case4(024):
1555 if (opx->offset < 0 || opx->offset > 255)
1556 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1557 "unsigned byte value exceeds bounds");
1558 out_imm(data, opx, 1, OUT_UNSIGNED);
1559 break;
1560
1561 case4(030):
1562 warn_overflow_opd(opx, 2);
1563 out_imm(data, opx, 2, OUT_WRAP);
1564 break;
1565
1566 case4(034):
1567 if (opx->type & (BITS16 | BITS32))
1568 size = (opx->type & BITS16) ? 2 : 4;
1569 else
1570 size = (bits == 16) ? 2 : 4;
1571 warn_overflow_opd(opx, size);
1572 out_imm(data, opx, size, OUT_WRAP);
1573 break;
1574
1575 case4(040):
1576 warn_overflow_opd(opx, 4);
1577 out_imm(data, opx, 4, OUT_WRAP);
1578 break;
1579
1580 case4(044):
1581 size = ins->addr_size >> 3;
1582 warn_overflow_opd(opx, size);
1583 out_imm(data, opx, size, OUT_WRAP);
1584 break;
1585
1586 case4(050):
1587 if (opx->segment == data->segment) {
1588 int64_t delta = opx->offset - data->offset
1589 - (data->inslen - data->insoffs);
1590 if (delta > 127 || delta < -128)
1591 nasm_error(ERR_NONFATAL, "short jump is out of range");
1592 }
1593 out_reladdr(data, opx, 1);
1594 break;
1595
1596 case4(054):
1597 out_imm(data, opx, 8, OUT_WRAP);
1598 break;
1599
1600 case4(060):
1601 out_reladdr(data, opx, 2);
1602 break;
1603
1604 case4(064):
1605 if (opx->type & (BITS16 | BITS32 | BITS64))
1606 size = (opx->type & BITS16) ? 2 : 4;
1607 else
1608 size = (bits == 16) ? 2 : 4;
1609
1610 out_reladdr(data, opx, size);
1611 break;
1612
1613 case4(070):
1614 out_reladdr(data, opx, 4);
1615 break;
1616
1617 case4(074):
1618 if (opx->segment == NO_SEG)
1619 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1620 " relocatable");
1621 out_segment(data, opx);
1622 break;
1623
1624 case 0172:
1625 {
1626 int mask = ins->prefixes[PPS_VEX] == P_EVEX ? 7 : 15;
1627 const struct operand *opy;
1628
1629 c = *codes++;
1630 opx = &ins->oprs[c >> 3];
1631 opy = &ins->oprs[c & 7];
1632 if (opy->segment != NO_SEG || opy->wrt != NO_SEG) {
1633 nasm_error(ERR_NONFATAL,
1634 "non-absolute expression not permitted as argument %d",
1635 c & 7);
1636 } else if (opy->offset & ~mask) {
1637 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1638 "is4 argument exceeds bounds");
1639 }
1640 c = opy->offset & mask;
1641 goto emit_is4;
1642 }
1643
1644 case 0173:
1645 c = *codes++;
1646 opx = &ins->oprs[c >> 4];
1647 c &= 15;
1648 goto emit_is4;
1649
1650 case4(0174):
1651 c = 0;
1652 emit_is4:
1653 r = nasm_regvals[opx->basereg];
1654 out_rawbyte(data, (r << 4) | ((r & 0x10) >> 1) | c);
1655 break;
1656
1657 case4(0254):
1658 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1659 (int32_t)opx->offset != (int64_t)opx->offset) {
1660 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1661 "signed dword immediate exceeds bounds");
1662 }
1663 out_imm(data, opx, 4, OUT_SIGNED);
1664 break;
1665
1666 case4(0240):
1667 case 0250:
1668 codes += 3;
1669 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1670 EVEX_P2Z | EVEX_P2AAA, 2);
1671 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1672 bytes[0] = 0x62;
1673 /* EVEX.X can be set by either REX or EVEX for different reasons */
1674 bytes[1] = ((((ins->rex & 7) << 5) |
1675 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1676 (ins->vex_cm & EVEX_P0MM);
1677 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1678 ((~ins->vexreg & 15) << 3) |
1679 (1 << 2) | (ins->vex_wlp & 3);
1680 bytes[3] = ins->evex_p[2];
1681 out_rawdata(data, bytes, 4);
1682 break;
1683
1684 case4(0260):
1685 case 0270:
1686 codes += 2;
1687 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1688 ins->prefixes[PPS_VEX] == P_VEX3) {
1689 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1690 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1691 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1692 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1693 out_rawdata(data, bytes, 3);
1694 } else {
1695 bytes[0] = 0xc5;
1696 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1697 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1698 out_rawdata(data, bytes, 2);
1699 }
1700 break;
1701
1702 case 0271:
1703 case 0272:
1704 case 0273:
1705 break;
1706
1707 case4(0274):
1708 {
1709 uint64_t uv, um;
1710 int s;
1711
1712 if (ins->rex & REX_W)
1713 s = 64;
1714 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1715 s = 16;
1716 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1717 s = 32;
1718 else
1719 s = bits;
1720
1721 um = (uint64_t)2 << (s-1);
1722 uv = opx->offset;
1723
1724 if (uv > 127 && uv < (uint64_t)-128 &&
1725 (uv < um-128 || uv > um-1)) {
1726 /* If this wasn't explicitly byte-sized, warn as though we
1727 * had fallen through to the imm16/32/64 case.
1728 */
1729 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1730 "%s value exceeds bounds",
1731 (opx->type & BITS8) ? "signed byte" :
1732 s == 16 ? "word" :
1733 s == 32 ? "dword" :
1734 "signed dword");
1735 }
1736 out_imm(data, opx, 1, OUT_WRAP); /* XXX: OUT_SIGNED? */
1737 break;
1738 }
1739
1740 case4(0300):
1741 break;
1742
1743 case 0310:
1744 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16))
1745 out_rawbyte(data, 0x67);
1746 break;
1747
1748 case 0311:
1749 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32))
1750 out_rawbyte(data, 0x67);
1751 break;
1752
1753 case 0312:
1754 break;
1755
1756 case 0313:
1757 ins->rex = 0;
1758 break;
1759
1760 case4(0314):
1761 break;
1762
1763 case 0320:
1764 case 0321:
1765 break;
1766
1767 case 0322:
1768 case 0323:
1769 break;
1770
1771 case 0324:
1772 ins->rex |= REX_W;
1773 break;
1774
1775 case 0325:
1776 break;
1777
1778 case 0326:
1779 break;
1780
1781 case 0330:
1782 out_rawbyte(data, *codes++ ^ get_cond_opcode(ins->condition));
1783 break;
1784
1785 case 0331:
1786 break;
1787
1788 case 0332:
1789 case 0333:
1790 out_rawbyte(data, c - 0332 + 0xF2);
1791 break;
1792
1793 case 0334:
1794 if (ins->rex & REX_R)
1795 out_rawbyte(data, 0xF0);
1796 ins->rex &= ~(REX_L|REX_R);
1797 break;
1798
1799 case 0335:
1800 break;
1801
1802 case 0336:
1803 case 0337:
1804 break;
1805
1806 case 0340:
1807 if (ins->oprs[0].segment != NO_SEG)
1808 nasm_panic(0, "non-constant BSS size in pass two");
1809
1810 out_reserve(data, ins->oprs[0].offset);
1811 break;
1812
1813 case 0341:
1814 break;
1815
1816 case 0360:
1817 break;
1818
1819 case 0361:
1820 out_rawbyte(data, 0x66);
1821 break;
1822
1823 case 0364:
1824 case 0365:
1825 break;
1826
1827 case 0366:
1828 case 0367:
1829 out_rawbyte(data, c - 0366 + 0x66);
1830 break;
1831
1832 case3(0370):
1833 break;
1834
1835 case 0373:
1836 out_rawbyte(data, bits == 16 ? 3 : 5);
1837 break;
1838
1839 case 0374:
1840 eat = EA_XMMVSIB;
1841 break;
1842
1843 case 0375:
1844 eat = EA_YMMVSIB;
1845 break;
1846
1847 case 0376:
1848 eat = EA_ZMMVSIB;
1849 break;
1850
1851 case4(0100):
1852 case4(0110):
1853 case4(0120):
1854 case4(0130):
1855 case4(0200):
1856 case4(0204):
1857 case4(0210):
1858 case4(0214):
1859 case4(0220):
1860 case4(0224):
1861 case4(0230):
1862 case4(0234):
1863 {
1864 ea ea_data;
1865 int rfield;
1866 opflags_t rflags;
1867 uint8_t *p;
1868 struct operand *opy = &ins->oprs[op2];
1869
1870 if (c <= 0177) {
1871 /* pick rfield from operand b (opx) */
1872 rflags = regflag(opx);
1873 rfield = nasm_regvals[opx->basereg];
1874 } else {
1875 /* rfield is constant */
1876 rflags = 0;
1877 rfield = c & 7;
1878 }
1879
1880 if (process_ea(opy, &ea_data, bits,
1881 rfield, rflags, ins) != eat)
1882 nasm_error(ERR_NONFATAL, "invalid effective address");
1883
1884 p = bytes;
1885 *p++ = ea_data.modrm;
1886 if (ea_data.sib_present)
1887 *p++ = ea_data.sib;
1888 out_rawdata(data, bytes, p - bytes);
1889
1890 /*
1891 * Make sure the address gets the right offset in case
1892 * the line breaks in the .lst file (BR 1197827)
1893 */
1894
1895 if (ea_data.bytes) {
1896 /* use compressed displacement, if available */
1897 if (ea_data.disp8) {
1898 out_rawbyte(data, ea_data.disp8);
1899 } else if (ea_data.rip) {
1900 out_reladdr(data, opy, ea_data.bytes);
1901 } else {
1902 int asize = ins->addr_size >> 3;
1903
1904 if (overflow_general(opy->offset, asize) ||
1905 signed_bits(opy->offset, ins->addr_size) !=
1906 signed_bits(opy->offset, ea_data.bytes << 3))
1907 warn_overflow(ERR_PASS2, ea_data.bytes);
1908
1909 out_imm(data, opy, ea_data.bytes,
1910 (asize > ea_data.bytes) ? OUT_SIGNED : OUT_UNSIGNED);
1911 }
1912 }
1913 }
1914 break;
1915
1916 default:
1917 nasm_panic(0, "internal instruction table corrupt"
1918 ": instruction code \\%o (0x%02X) given", c, c);
1919 break;
1920 }
1921 }
1922 }
1923
1924 static opflags_t regflag(const operand * o)
1925 {
1926 if (!is_register(o->basereg))
1927 nasm_panic(0, "invalid operand passed to regflag()");
1928 return nasm_reg_flags[o->basereg];
1929 }
1930
1931 static int32_t regval(const operand * o)
1932 {
1933 if (!is_register(o->basereg))
1934 nasm_panic(0, "invalid operand passed to regval()");
1935 return nasm_regvals[o->basereg];
1936 }
1937
1938 static int op_rexflags(const operand * o, int mask)
1939 {
1940 opflags_t flags;
1941 int val;
1942
1943 if (!is_register(o->basereg))
1944 nasm_panic(0, "invalid operand passed to op_rexflags()");
1945
1946 flags = nasm_reg_flags[o->basereg];
1947 val = nasm_regvals[o->basereg];
1948
1949 return rexflags(val, flags, mask);
1950 }
1951
1952 static int rexflags(int val, opflags_t flags, int mask)
1953 {
1954 int rex = 0;
1955
1956 if (val >= 0 && (val & 8))
1957 rex |= REX_B|REX_X|REX_R;
1958 if (flags & BITS64)
1959 rex |= REX_W;
1960 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1961 rex |= REX_H;
1962 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1963 rex |= REX_P;
1964
1965 return rex & mask;
1966 }
1967
1968 static int evexflags(int val, decoflags_t deco,
1969 int mask, uint8_t byte)
1970 {
1971 int evex = 0;
1972
1973 switch (byte) {
1974 case 0:
1975 if (val >= 0 && (val & 16))
1976 evex |= (EVEX_P0RP | EVEX_P0X);
1977 break;
1978 case 2:
1979 if (val >= 0 && (val & 16))
1980 evex |= EVEX_P2VP;
1981 if (deco & Z)
1982 evex |= EVEX_P2Z;
1983 if (deco & OPMASK_MASK)
1984 evex |= deco & EVEX_P2AAA;
1985 break;
1986 }
1987 return evex & mask;
1988 }
1989
1990 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1991 {
1992 int val;
1993
1994 val = nasm_regvals[o->basereg];
1995
1996 return evexflags(val, o->decoflags, mask, byte);
1997 }
1998
1999 static enum match_result find_match(const struct itemplate **tempp,
2000 insn *instruction,
2001 int32_t segment, int64_t offset, int bits)
2002 {
2003 const struct itemplate *temp;
2004 enum match_result m, merr;
2005 opflags_t xsizeflags[MAX_OPERANDS];
2006 bool opsizemissing = false;
2007 int8_t broadcast = instruction->evex_brerop;
2008 int i;
2009
2010 /* broadcasting uses a different data element size */
2011 for (i = 0; i < instruction->operands; i++)
2012 if (i == broadcast)
2013 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2014 else
2015 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2016
2017 merr = MERR_INVALOP;
2018
2019 for (temp = nasm_instructions[instruction->opcode];
2020 temp->opcode != I_none; temp++) {
2021 m = matches(temp, instruction, bits);
2022 if (m == MOK_JUMP) {
2023 if (jmp_match(segment, offset, bits, instruction, temp))
2024 m = MOK_GOOD;
2025 else
2026 m = MERR_INVALOP;
2027 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2028 /*
2029 * Missing operand size and a candidate for fuzzy matching...
2030 */
2031 for (i = 0; i < temp->operands; i++)
2032 if (i == broadcast)
2033 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2034 else
2035 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2036 opsizemissing = true;
2037 }
2038 if (m > merr)
2039 merr = m;
2040 if (merr == MOK_GOOD)
2041 goto done;
2042 }
2043
2044 /* No match, but see if we can get a fuzzy operand size match... */
2045 if (!opsizemissing)
2046 goto done;
2047
2048 for (i = 0; i < instruction->operands; i++) {
2049 /*
2050 * We ignore extrinsic operand sizes on registers, so we should
2051 * never try to fuzzy-match on them. This also resolves the case
2052 * when we have e.g. "xmmrm128" in two different positions.
2053 */
2054 if (is_class(REGISTER, instruction->oprs[i].type))
2055 continue;
2056
2057 /* This tests if xsizeflags[i] has more than one bit set */
2058 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2059 goto done; /* No luck */
2060
2061 if (i == broadcast) {
2062 instruction->oprs[i].decoflags |= xsizeflags[i];
2063 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2064 BITS32 : BITS64);
2065 } else {
2066 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2067 }
2068 }
2069
2070 /* Try matching again... */
2071 for (temp = nasm_instructions[instruction->opcode];
2072 temp->opcode != I_none; temp++) {
2073 m = matches(temp, instruction, bits);
2074 if (m == MOK_JUMP) {
2075 if (jmp_match(segment, offset, bits, instruction, temp))
2076 m = MOK_GOOD;
2077 else
2078 m = MERR_INVALOP;
2079 }
2080 if (m > merr)
2081 merr = m;
2082 if (merr == MOK_GOOD)
2083 goto done;
2084 }
2085
2086 done:
2087 *tempp = temp;
2088 return merr;
2089 }
2090
2091 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2092 {
2093 opflags_t opsize = opflags & SIZE_MASK;
2094 uint8_t brcast_num;
2095
2096 /*
2097 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2098 * this cannot be a simple arithmetic calculation.
2099 */
2100 if (brsize > BITS64)
2101 nasm_error(ERR_FATAL,
2102 "size of broadcasting element is greater than 64 bits");
2103
2104 switch (opsize) {
2105 case BITS64:
2106 brcast_num = BITS64 / brsize;
2107 break;
2108 default:
2109 brcast_num = (opsize / BITS128) * (BITS64 / brsize) * 2;
2110 break;
2111 }
2112
2113 return brcast_num;
2114 }
2115
2116 static enum match_result matches(const struct itemplate *itemp,
2117 insn *instruction, int bits)
2118 {
2119 opflags_t size[MAX_OPERANDS], asize;
2120 bool opsizemissing = false;
2121 int i, oprs;
2122
2123 /*
2124 * Check the opcode
2125 */
2126 if (itemp->opcode != instruction->opcode)
2127 return MERR_INVALOP;
2128
2129 /*
2130 * Count the operands
2131 */
2132 if (itemp->operands != instruction->operands)
2133 return MERR_INVALOP;
2134
2135 /*
2136 * Is it legal?
2137 */
2138 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2139 return MERR_INVALOP;
2140
2141 /*
2142 * {evex} available?
2143 */
2144 switch (instruction->prefixes[PPS_VEX]) {
2145 case P_EVEX:
2146 if (!itemp_has(itemp, IF_EVEX))
2147 return MERR_ENCMISMATCH;
2148 break;
2149 case P_VEX3:
2150 case P_VEX2:
2151 if (!itemp_has(itemp, IF_VEX))
2152 return MERR_ENCMISMATCH;
2153 break;
2154 default:
2155 break;
2156 }
2157
2158 /*
2159 * Check that no spurious colons or TOs are present
2160 */
2161 for (i = 0; i < itemp->operands; i++)
2162 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2163 return MERR_INVALOP;
2164
2165 /*
2166 * Process size flags
2167 */
2168 switch (itemp_smask(itemp)) {
2169 case IF_GENBIT(IF_SB):
2170 asize = BITS8;
2171 break;
2172 case IF_GENBIT(IF_SW):
2173 asize = BITS16;
2174 break;
2175 case IF_GENBIT(IF_SD):
2176 asize = BITS32;
2177 break;
2178 case IF_GENBIT(IF_SQ):
2179 asize = BITS64;
2180 break;
2181 case IF_GENBIT(IF_SO):
2182 asize = BITS128;
2183 break;
2184 case IF_GENBIT(IF_SY):
2185 asize = BITS256;
2186 break;
2187 case IF_GENBIT(IF_SZ):
2188 asize = BITS512;
2189 break;
2190 case IF_GENBIT(IF_SIZE):
2191 switch (bits) {
2192 case 16:
2193 asize = BITS16;
2194 break;
2195 case 32:
2196 asize = BITS32;
2197 break;
2198 case 64:
2199 asize = BITS64;
2200 break;
2201 default:
2202 asize = 0;
2203 break;
2204 }
2205 break;
2206 default:
2207 asize = 0;
2208 break;
2209 }
2210
2211 if (itemp_armask(itemp)) {
2212 /* S- flags only apply to a specific operand */
2213 i = itemp_arg(itemp);
2214 memset(size, 0, sizeof size);
2215 size[i] = asize;
2216 } else {
2217 /* S- flags apply to all operands */
2218 for (i = 0; i < MAX_OPERANDS; i++)
2219 size[i] = asize;
2220 }
2221
2222 /*
2223 * Check that the operand flags all match up,
2224 * it's a bit tricky so lets be verbose:
2225 *
2226 * 1) Find out the size of operand. If instruction
2227 * doesn't have one specified -- we're trying to
2228 * guess it either from template (IF_S* flag) or
2229 * from code bits.
2230 *
2231 * 2) If template operand do not match the instruction OR
2232 * template has an operand size specified AND this size differ
2233 * from which instruction has (perhaps we got it from code bits)
2234 * we are:
2235 * a) Check that only size of instruction and operand is differ
2236 * other characteristics do match
2237 * b) Perhaps it's a register specified in instruction so
2238 * for such a case we just mark that operand as "size
2239 * missing" and this will turn on fuzzy operand size
2240 * logic facility (handled by a caller)
2241 */
2242 for (i = 0; i < itemp->operands; i++) {
2243 opflags_t type = instruction->oprs[i].type;
2244 decoflags_t deco = instruction->oprs[i].decoflags;
2245 bool is_broadcast = deco & BRDCAST_MASK;
2246 uint8_t brcast_num = 0;
2247 opflags_t template_opsize, insn_opsize;
2248
2249 if (!(type & SIZE_MASK))
2250 type |= size[i];
2251
2252 insn_opsize = type & SIZE_MASK;
2253 if (!is_broadcast) {
2254 template_opsize = itemp->opd[i] & SIZE_MASK;
2255 } else {
2256 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2257 /*
2258 * when broadcasting, the element size depends on
2259 * the instruction type. decorator flag should match.
2260 */
2261
2262 if (deco_brsize) {
2263 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2264 /* calculate the proper number : {1to<brcast_num>} */
2265 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2266 } else {
2267 template_opsize = 0;
2268 }
2269 }
2270
2271 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2272 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2273 return MERR_INVALOP;
2274 } else if (template_opsize) {
2275 if (template_opsize != insn_opsize) {
2276 if (insn_opsize) {
2277 return MERR_INVALOP;
2278 } else if (!is_class(REGISTER, type)) {
2279 /*
2280 * Note: we don't honor extrinsic operand sizes for registers,
2281 * so "missing operand size" for a register should be
2282 * considered a wildcard match rather than an error.
2283 */
2284 opsizemissing = true;
2285 }
2286 } else if (is_broadcast &&
2287 (brcast_num !=
2288 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2289 /*
2290 * broadcasting opsize matches but the number of repeated memory
2291 * element does not match.
2292 * if 64b double precision float is broadcasted to ymm (256b),
2293 * broadcasting decorator must be {1to4}.
2294 */
2295 return MERR_BRNUMMISMATCH;
2296 }
2297 }
2298 }
2299
2300 if (opsizemissing)
2301 return MERR_OPSIZEMISSING;
2302
2303 /*
2304 * Check operand sizes
2305 */
2306 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2307 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2308 for (i = 0; i < oprs; i++) {
2309 asize = itemp->opd[i] & SIZE_MASK;
2310 if (asize) {
2311 for (i = 0; i < oprs; i++)
2312 size[i] = asize;
2313 break;
2314 }
2315 }
2316 } else {
2317 oprs = itemp->operands;
2318 }
2319
2320 for (i = 0; i < itemp->operands; i++) {
2321 if (!(itemp->opd[i] & SIZE_MASK) &&
2322 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2323 return MERR_OPSIZEMISMATCH;
2324 }
2325
2326 /*
2327 * Check template is okay at the set cpu level
2328 */
2329 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2330 return MERR_BADCPU;
2331
2332 /*
2333 * Verify the appropriate long mode flag.
2334 */
2335 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2336 return MERR_BADMODE;
2337
2338 /*
2339 * If we have a HLE prefix, look for the NOHLE flag
2340 */
2341 if (itemp_has(itemp, IF_NOHLE) &&
2342 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2343 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2344 return MERR_BADHLE;
2345
2346 /*
2347 * Check if special handling needed for Jumps
2348 */
2349 if ((itemp->code[0] & ~1) == 0370)
2350 return MOK_JUMP;
2351
2352 /*
2353 * Check if BND prefix is allowed.
2354 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2355 */
2356 if (!itemp_has(itemp, IF_BND) &&
2357 (has_prefix(instruction, PPS_REP, P_BND) ||
2358 has_prefix(instruction, PPS_REP, P_NOBND)))
2359 return MERR_BADBND;
2360 else if (itemp_has(itemp, IF_BND) &&
2361 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2362 has_prefix(instruction, PPS_REP, P_REPNZ)))
2363 return MERR_BADREPNE;
2364
2365 return MOK_GOOD;
2366 }
2367
2368 /*
2369 * Check if ModR/M.mod should/can be 01.
2370 * - EAF_BYTEOFFS is set
2371 * - offset can fit in a byte when EVEX is not used
2372 * - offset can be compressed when EVEX is used
2373 */
2374 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2375 (o >= -128 && o <= 127 && \
2376 seg == NO_SEG && !forw_ref && \
2377 !(input->eaflags & EAF_WORDOFFS) && \
2378 !(ins->rex & REX_EV)) || \
2379 (ins->rex & REX_EV && \
2380 is_disp8n(input, ins, &output->disp8)))
2381
2382 static enum ea_type process_ea(operand *input, ea *output, int bits,
2383 int rfield, opflags_t rflags, insn *ins)
2384 {
2385 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2386 int addrbits = ins->addr_size;
2387 int eaflags = input->eaflags;
2388
2389 output->type = EA_SCALAR;
2390 output->rip = false;
2391 output->disp8 = 0;
2392
2393 /* REX flags for the rfield operand */
2394 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2395 /* EVEX.R' flag for the REG operand */
2396 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2397
2398 if (is_class(REGISTER, input->type)) {
2399 /*
2400 * It's a direct register.
2401 */
2402 if (!is_register(input->basereg))
2403 goto err;
2404
2405 if (!is_reg_class(REG_EA, input->basereg))
2406 goto err;
2407
2408 /* broadcasting is not available with a direct register operand. */
2409 if (input->decoflags & BRDCAST_MASK) {
2410 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2411 goto err;
2412 }
2413
2414 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2415 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2416 output->sib_present = false; /* no SIB necessary */
2417 output->bytes = 0; /* no offset necessary either */
2418 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2419 } else {
2420 /*
2421 * It's a memory reference.
2422 */
2423
2424 /* Embedded rounding or SAE is not available with a mem ref operand. */
2425 if (input->decoflags & (ER | SAE)) {
2426 nasm_error(ERR_NONFATAL,
2427 "Embedded rounding is available only with reg-reg op.");
2428 return -1;
2429 }
2430
2431 if (input->basereg == -1 &&
2432 (input->indexreg == -1 || input->scale == 0)) {
2433 /*
2434 * It's a pure offset.
2435 */
2436 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2437 input->segment == NO_SEG) {
2438 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2439 input->type &= ~IP_REL;
2440 input->type |= MEMORY;
2441 }
2442
2443 if (bits == 64 &&
2444 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2445 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2446 return -1;
2447 }
2448
2449 if (eaflags & EAF_BYTEOFFS ||
2450 (eaflags & EAF_WORDOFFS &&
2451 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2452 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2453 }
2454
2455 if (bits == 64 && (~input->type & IP_REL)) {
2456 output->sib_present = true;
2457 output->sib = GEN_SIB(0, 4, 5);
2458 output->bytes = 4;
2459 output->modrm = GEN_MODRM(0, rfield, 4);
2460 output->rip = false;
2461 } else {
2462 output->sib_present = false;
2463 output->bytes = (addrbits != 16 ? 4 : 2);
2464 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2465 output->rip = bits == 64;
2466 }
2467 } else {
2468 /*
2469 * It's an indirection.
2470 */
2471 int i = input->indexreg, b = input->basereg, s = input->scale;
2472 int32_t seg = input->segment;
2473 int hb = input->hintbase, ht = input->hinttype;
2474 int t, it, bt; /* register numbers */
2475 opflags_t x, ix, bx; /* register flags */
2476
2477 if (s == 0)
2478 i = -1; /* make this easy, at least */
2479
2480 if (is_register(i)) {
2481 it = nasm_regvals[i];
2482 ix = nasm_reg_flags[i];
2483 } else {
2484 it = -1;
2485 ix = 0;
2486 }
2487
2488 if (is_register(b)) {
2489 bt = nasm_regvals[b];
2490 bx = nasm_reg_flags[b];
2491 } else {
2492 bt = -1;
2493 bx = 0;
2494 }
2495
2496 /* if either one are a vector register... */
2497 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2498 opflags_t sok = BITS32 | BITS64;
2499 int32_t o = input->offset;
2500 int mod, scale, index, base;
2501
2502 /*
2503 * For a vector SIB, one has to be a vector and the other,
2504 * if present, a GPR. The vector must be the index operand.
2505 */
2506 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2507 if (s == 0)
2508 s = 1;
2509 else if (s != 1)
2510 goto err;
2511
2512 t = bt, bt = it, it = t;
2513 x = bx, bx = ix, ix = x;
2514 }
2515
2516 if (bt != -1) {
2517 if (REG_GPR & ~bx)
2518 goto err;
2519 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2520 sok &= bx;
2521 else
2522 goto err;
2523 }
2524
2525 /*
2526 * While we're here, ensure the user didn't specify
2527 * WORD or QWORD
2528 */
2529 if (input->disp_size == 16 || input->disp_size == 64)
2530 goto err;
2531
2532 if (addrbits == 16 ||
2533 (addrbits == 32 && !(sok & BITS32)) ||
2534 (addrbits == 64 && !(sok & BITS64)))
2535 goto err;
2536
2537 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2538 : ((ix & YMMREG & ~REG_EA)
2539 ? EA_YMMVSIB : EA_XMMVSIB));
2540
2541 output->rex |= rexflags(it, ix, REX_X);
2542 output->rex |= rexflags(bt, bx, REX_B);
2543 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2544
2545 index = it & 7; /* it is known to be != -1 */
2546
2547 switch (s) {
2548 case 1:
2549 scale = 0;
2550 break;
2551 case 2:
2552 scale = 1;
2553 break;
2554 case 4:
2555 scale = 2;
2556 break;
2557 case 8:
2558 scale = 3;
2559 break;
2560 default: /* then what the smeg is it? */
2561 goto err; /* panic */
2562 }
2563
2564 if (bt == -1) {
2565 base = 5;
2566 mod = 0;
2567 } else {
2568 base = (bt & 7);
2569 if (base != REG_NUM_EBP && o == 0 &&
2570 seg == NO_SEG && !forw_ref &&
2571 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2572 mod = 0;
2573 else if (IS_MOD_01())
2574 mod = 1;
2575 else
2576 mod = 2;
2577 }
2578
2579 output->sib_present = true;
2580 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2581 output->modrm = GEN_MODRM(mod, rfield, 4);
2582 output->sib = GEN_SIB(scale, index, base);
2583 } else if ((ix|bx) & (BITS32|BITS64)) {
2584 /*
2585 * it must be a 32/64-bit memory reference. Firstly we have
2586 * to check that all registers involved are type E/Rxx.
2587 */
2588 opflags_t sok = BITS32 | BITS64;
2589 int32_t o = input->offset;
2590
2591 if (it != -1) {
2592 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2593 sok &= ix;
2594 else
2595 goto err;
2596 }
2597
2598 if (bt != -1) {
2599 if (REG_GPR & ~bx)
2600 goto err; /* Invalid register */
2601 if (~sok & bx & SIZE_MASK)
2602 goto err; /* Invalid size */
2603 sok &= bx;
2604 }
2605
2606 /*
2607 * While we're here, ensure the user didn't specify
2608 * WORD or QWORD
2609 */
2610 if (input->disp_size == 16 || input->disp_size == 64)
2611 goto err;
2612
2613 if (addrbits == 16 ||
2614 (addrbits == 32 && !(sok & BITS32)) ||
2615 (addrbits == 64 && !(sok & BITS64)))
2616 goto err;
2617
2618 /* now reorganize base/index */
2619 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2620 ((hb == b && ht == EAH_NOTBASE) ||
2621 (hb == i && ht == EAH_MAKEBASE))) {
2622 /* swap if hints say so */
2623 t = bt, bt = it, it = t;
2624 x = bx, bx = ix, ix = x;
2625 }
2626
2627 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2628 /* make single reg base, unless hint */
2629 bt = it, bx = ix, it = -1, ix = 0;
2630 }
2631 if (eaflags & EAF_MIB) {
2632 /* only for mib operands */
2633 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2634 /*
2635 * make a single reg index [reg*1].
2636 * gas uses this form for an explicit index register.
2637 */
2638 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2639 }
2640 if ((ht == EAH_SUMMED) && bt == -1) {
2641 /* separate once summed index into [base, index] */
2642 bt = it, bx = ix, s--;
2643 }
2644 } else {
2645 if (((s == 2 && it != REG_NUM_ESP &&
2646 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2647 s == 3 || s == 5 || s == 9) && bt == -1) {
2648 /* convert 3*EAX to EAX+2*EAX */
2649 bt = it, bx = ix, s--;
2650 }
2651 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2652 (eaflags & EAF_TIMESTWO) &&
2653 (hb == b && ht == EAH_NOTBASE)) {
2654 /*
2655 * convert [NOSPLIT EAX*1]
2656 * to sib format with 0x0 displacement - [EAX*1+0].
2657 */
2658 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2659 }
2660 }
2661 if (s == 1 && it == REG_NUM_ESP) {
2662 /* swap ESP into base if scale is 1 */
2663 t = it, it = bt, bt = t;
2664 x = ix, ix = bx, bx = x;
2665 }
2666 if (it == REG_NUM_ESP ||
2667 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2668 goto err; /* wrong, for various reasons */
2669
2670 output->rex |= rexflags(it, ix, REX_X);
2671 output->rex |= rexflags(bt, bx, REX_B);
2672
2673 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2674 /* no SIB needed */
2675 int mod, rm;
2676
2677 if (bt == -1) {
2678 rm = 5;
2679 mod = 0;
2680 } else {
2681 rm = (bt & 7);
2682 if (rm != REG_NUM_EBP && o == 0 &&
2683 seg == NO_SEG && !forw_ref &&
2684 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2685 mod = 0;
2686 else if (IS_MOD_01())
2687 mod = 1;
2688 else
2689 mod = 2;
2690 }
2691
2692 output->sib_present = false;
2693 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2694 output->modrm = GEN_MODRM(mod, rfield, rm);
2695 } else {
2696 /* we need a SIB */
2697 int mod, scale, index, base;
2698
2699 if (it == -1)
2700 index = 4, s = 1;
2701 else
2702 index = (it & 7);
2703
2704 switch (s) {
2705 case 1:
2706 scale = 0;
2707 break;
2708 case 2:
2709 scale = 1;
2710 break;
2711 case 4:
2712 scale = 2;
2713 break;
2714 case 8:
2715 scale = 3;
2716 break;
2717 default: /* then what the smeg is it? */
2718 goto err; /* panic */
2719 }
2720
2721 if (bt == -1) {
2722 base = 5;
2723 mod = 0;
2724 } else {
2725 base = (bt & 7);
2726 if (base != REG_NUM_EBP && o == 0 &&
2727 seg == NO_SEG && !forw_ref &&
2728 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2729 mod = 0;
2730 else if (IS_MOD_01())
2731 mod = 1;
2732 else
2733 mod = 2;
2734 }
2735
2736 output->sib_present = true;
2737 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2738 output->modrm = GEN_MODRM(mod, rfield, 4);
2739 output->sib = GEN_SIB(scale, index, base);
2740 }
2741 } else { /* it's 16-bit */
2742 int mod, rm;
2743 int16_t o = input->offset;
2744
2745 /* check for 64-bit long mode */
2746 if (addrbits == 64)
2747 goto err;
2748
2749 /* check all registers are BX, BP, SI or DI */
2750 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2751 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2752 goto err;
2753
2754 /* ensure the user didn't specify DWORD/QWORD */
2755 if (input->disp_size == 32 || input->disp_size == 64)
2756 goto err;
2757
2758 if (s != 1 && i != -1)
2759 goto err; /* no can do, in 16-bit EA */
2760 if (b == -1 && i != -1) {
2761 int tmp = b;
2762 b = i;
2763 i = tmp;
2764 } /* swap */
2765 if ((b == R_SI || b == R_DI) && i != -1) {
2766 int tmp = b;
2767 b = i;
2768 i = tmp;
2769 }
2770 /* have BX/BP as base, SI/DI index */
2771 if (b == i)
2772 goto err; /* shouldn't ever happen, in theory */
2773 if (i != -1 && b != -1 &&
2774 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2775 goto err; /* invalid combinations */
2776 if (b == -1) /* pure offset: handled above */
2777 goto err; /* so if it gets to here, panic! */
2778
2779 rm = -1;
2780 if (i != -1)
2781 switch (i * 256 + b) {
2782 case R_SI * 256 + R_BX:
2783 rm = 0;
2784 break;
2785 case R_DI * 256 + R_BX:
2786 rm = 1;
2787 break;
2788 case R_SI * 256 + R_BP:
2789 rm = 2;
2790 break;
2791 case R_DI * 256 + R_BP:
2792 rm = 3;
2793 break;
2794 } else
2795 switch (b) {
2796 case R_SI:
2797 rm = 4;
2798 break;
2799 case R_DI:
2800 rm = 5;
2801 break;
2802 case R_BP:
2803 rm = 6;
2804 break;
2805 case R_BX:
2806 rm = 7;
2807 break;
2808 }
2809 if (rm == -1) /* can't happen, in theory */
2810 goto err; /* so panic if it does */
2811
2812 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2813 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2814 mod = 0;
2815 else if (IS_MOD_01())
2816 mod = 1;
2817 else
2818 mod = 2;
2819
2820 output->sib_present = false; /* no SIB - it's 16-bit */
2821 output->bytes = mod; /* bytes of offset needed */
2822 output->modrm = GEN_MODRM(mod, rfield, rm);
2823 }
2824 }
2825 }
2826
2827 output->size = 1 + output->sib_present + output->bytes;
2828 return output->type;
2829
2830 err:
2831 return output->type = EA_INVALID;
2832 }
2833
2834 static void add_asp(insn *ins, int addrbits)
2835 {
2836 int j, valid;
2837 int defdisp;
2838
2839 valid = (addrbits == 64) ? 64|32 : 32|16;
2840
2841 switch (ins->prefixes[PPS_ASIZE]) {
2842 case P_A16:
2843 valid &= 16;
2844 break;
2845 case P_A32:
2846 valid &= 32;
2847 break;
2848 case P_A64:
2849 valid &= 64;
2850 break;
2851 case P_ASP:
2852 valid &= (addrbits == 32) ? 16 : 32;
2853 break;
2854 default:
2855 break;
2856 }
2857
2858 for (j = 0; j < ins->operands; j++) {
2859 if (is_class(MEMORY, ins->oprs[j].type)) {
2860 opflags_t i, b;
2861
2862 /* Verify as Register */
2863 if (!is_register(ins->oprs[j].indexreg))
2864 i = 0;
2865 else
2866 i = nasm_reg_flags[ins->oprs[j].indexreg];
2867
2868 /* Verify as Register */
2869 if (!is_register(ins->oprs[j].basereg))
2870 b = 0;
2871 else
2872 b = nasm_reg_flags[ins->oprs[j].basereg];
2873
2874 if (ins->oprs[j].scale == 0)
2875 i = 0;
2876
2877 if (!i && !b) {
2878 int ds = ins->oprs[j].disp_size;
2879 if ((addrbits != 64 && ds > 8) ||
2880 (addrbits == 64 && ds == 16))
2881 valid &= ds;
2882 } else {
2883 if (!(REG16 & ~b))
2884 valid &= 16;
2885 if (!(REG32 & ~b))
2886 valid &= 32;
2887 if (!(REG64 & ~b))
2888 valid &= 64;
2889
2890 if (!(REG16 & ~i))
2891 valid &= 16;
2892 if (!(REG32 & ~i))
2893 valid &= 32;
2894 if (!(REG64 & ~i))
2895 valid &= 64;
2896 }
2897 }
2898 }
2899
2900 if (valid & addrbits) {
2901 ins->addr_size = addrbits;
2902 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2903 /* Add an address size prefix */
2904 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2905 ins->addr_size = (addrbits == 32) ? 16 : 32;
2906 } else {
2907 /* Impossible... */
2908 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2909 ins->addr_size = addrbits; /* Error recovery */
2910 }
2911
2912 defdisp = ins->addr_size == 16 ? 16 : 32;
2913
2914 for (j = 0; j < ins->operands; j++) {
2915 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2916 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2917 /*
2918 * mem_offs sizes must match the address size; if not,
2919 * strip the MEM_OFFS bit and match only EA instructions
2920 */
2921 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2922 }
2923 }
2924 }
The Netwide Assembler