1 /* assemble.c code generation for the Netwide Assembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into next opcode byte if operand 0..3
37 * is a signed byte rather than a word.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into next opcode byte if operand 0..3
40 * is a signed byte rather than a dword.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
58 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
59 * \322 - indicates that this instruction is only valid when the
60 * operand size is the default (instruction to disassembler,
61 * generates no code in the assembler)
62 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
63 * \324 - indicates 64-bit operand size requiring REX prefix.
64 * \330 - a literal byte follows in the code stream, to be added
65 * to the condition code value of the instruction.
66 * \331 - instruction not valid with REP prefix. Hint for
67 * disassembler only; for SSE instructions.
68 * \332 - REP prefix (0xF2 byte) used as opcode extension.
69 * \333 - REP prefix (0xF3 byte) used as opcode extension.
70 * \334 - LOCK prefix used instead of REX.R
71 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
72 * \340 - reserve <operand 0> bytes of uninitialized storage.
73 * Operand 0 had better be a segmentless constant.
74 * \364 - operand-size prefix (0x66) not permitted
75 * \365 - address-size prefix (0x67) not permitted
76 * \366 - operand-size prefix (0x66) used as opcode extension
77 * \367 - address-size prefix (0x67) used as opcode extension
78 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
79 * 370 is used for Jcc, 371 is used for JMP.
80 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
81 * used for conditional jump over longer jump
99 int sib_present
; /* is a SIB byte necessary? */
100 int bytes
; /* # of bytes of offset needed */
101 int size
; /* lazy - this is sib+bytes+1 */
102 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
105 static uint32_t cpu
; /* cpu level received from nasm.c */
106 static efunc errfunc
;
107 static struct ofmt
*outfmt
;
108 static ListGen
*list
;
110 static int32_t calcsize(int32_t, int32_t, int, insn
*, const char *);
111 static void gencode(int32_t, int32_t, int, insn
*, const char *, int32_t);
112 static int matches(const struct itemplate
*, insn
*, int bits
);
113 static int32_t regflag(const operand
*);
114 static int32_t regval(const operand
*);
115 static int rexflags(int, int32_t, int);
116 static int op_rexflags(const operand
*, int);
117 static ea
*process_ea(operand
*, ea
*, int, int, int, int32_t, int);
118 static void add_asp(insn
*, int);
120 static int has_prefix(insn
* ins
, enum prefix_pos pos
, enum prefixes prefix
)
122 return ins
->prefixes
[pos
] == prefix
;
125 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
127 if (ins
->prefixes
[pos
])
128 errfunc(ERR_NONFATAL
, "invalid %s prefix",
129 prefix_name(ins
->prefixes
[pos
]));
132 static const char *size_name(int size
)
152 static void warn_overflow(int size
, int64_t data
)
155 int64_t lim
= (1 << (size
*8))-1;
157 if (data
< ~lim
|| data
> lim
)
158 errfunc(ERR_WARNING
, "%s data exceeds bounds", size_name(size
));
162 * This routine wrappers the real output format's output routine,
163 * in order to pass a copy of the data off to the listing file
164 * generator at the same time.
166 static void out(int32_t offset
, int32_t segto
, const void *data
,
167 uint32_t type
, int32_t segment
, int32_t wrt
)
169 static int32_t lineno
= 0; /* static!!! */
170 static char *lnfname
= NULL
;
172 if ((type
& OUT_TYPMASK
) == OUT_ADDRESS
) {
173 if (segment
!= NO_SEG
|| wrt
!= NO_SEG
) {
175 * This address is relocated. We must write it as
176 * OUT_ADDRESS, so there's no work to be done here.
178 list
->output(offset
, data
, type
);
180 uint8_t p
[8], *q
= p
;
182 * This is a non-relocated address, and we're going to
183 * convert it into RAWDATA format.
185 if ((type
& OUT_SIZMASK
) == 4) {
186 WRITELONG(q
, *(int32_t *)data
);
187 list
->output(offset
, p
, OUT_RAWDATA
+ 4);
188 } else if ((type
& OUT_SIZMASK
) == 8) {
189 WRITEDLONG(q
, *(int64_t *)data
);
190 list
->output(offset
, p
, OUT_RAWDATA
+ 8);
192 WRITESHORT(q
, *(int32_t *)data
);
193 list
->output(offset
, p
, OUT_RAWDATA
+ 2);
196 } else if ((type
& OUT_TYPMASK
) == OUT_RAWDATA
) {
197 list
->output(offset
, data
, type
);
198 } else if ((type
& OUT_TYPMASK
) == OUT_RESERVE
) {
199 list
->output(offset
, NULL
, type
);
200 } else if ((type
& OUT_TYPMASK
) == OUT_REL2ADR
||
201 (type
& OUT_TYPMASK
) == OUT_REL4ADR
) {
202 list
->output(offset
, data
, type
);
206 * this call to src_get determines when we call the
207 * debug-format-specific "linenum" function
208 * it updates lineno and lnfname to the current values
209 * returning 0 if "same as last time", -2 if lnfname
210 * changed, and the amount by which lineno changed,
211 * if it did. thus, these variables must be static
214 if (src_get(&lineno
, &lnfname
)) {
215 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
218 outfmt
->output(segto
, data
, type
, segment
, wrt
);
221 static int jmp_match(int32_t segment
, int32_t offset
, int bits
,
222 insn
* ins
, const char *code
)
227 if (c
!= 0370 && c
!= 0371)
229 if (ins
->oprs
[0].opflags
& OPFLAG_FORWARD
) {
230 if ((optimizing
< 0 || (ins
->oprs
[0].type
& STRICT
))
234 return (pass0
== 0); /* match a forward reference */
236 isize
= calcsize(segment
, offset
, bits
, ins
, code
);
237 if (ins
->oprs
[0].segment
!= segment
)
239 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is now the delta */
240 if (isize
>= -128L && isize
<= 127L)
241 return 1; /* it is byte size */
246 int32_t assemble(int32_t segment
, int32_t offset
, int bits
, uint32_t cp
,
247 insn
* instruction
, struct ofmt
*output
, efunc error
,
250 const struct itemplate
*temp
;
255 int32_t start
= offset
;
256 int32_t wsize
= 0; /* size for DB etc. */
258 errfunc
= error
; /* to pass to other functions */
260 outfmt
= output
; /* likewise */
261 list
= listgen
; /* and again */
263 switch (instruction
->opcode
) {
290 int32_t t
= instruction
->times
;
293 "instruction->times < 0 (%ld) in assemble()", t
);
295 while (t
--) { /* repeat TIMES times */
296 for (e
= instruction
->eops
; e
; e
= e
->next
) {
297 if (e
->type
== EOT_DB_NUMBER
) {
299 if (e
->segment
!= NO_SEG
)
300 errfunc(ERR_NONFATAL
,
301 "one-byte relocation attempted");
303 uint8_t out_byte
= e
->offset
;
304 out(offset
, segment
, &out_byte
,
305 OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
307 } else if (wsize
> 8) {
308 errfunc(ERR_NONFATAL
, "integer supplied to a DT or DO"
311 out(offset
, segment
, &e
->offset
,
312 OUT_ADDRESS
+ wsize
, e
->segment
, e
->wrt
);
314 } else if (e
->type
== EOT_DB_STRING
) {
317 out(offset
, segment
, e
->stringval
,
318 OUT_RAWDATA
+ e
->stringlen
, NO_SEG
, NO_SEG
);
319 align
= e
->stringlen
% wsize
;
322 align
= wsize
- align
;
323 out(offset
, segment
, "\0\0\0\0\0\0\0\0",
324 OUT_RAWDATA
+ align
, NO_SEG
, NO_SEG
);
326 offset
+= e
->stringlen
+ align
;
329 if (t
> 0 && t
== instruction
->times
- 1) {
331 * Dummy call to list->output to give the offset to the
334 list
->output(offset
, NULL
, OUT_RAWDATA
);
335 list
->uplevel(LIST_TIMES
);
338 if (instruction
->times
> 1)
339 list
->downlevel(LIST_TIMES
);
340 return offset
- start
;
343 if (instruction
->opcode
== I_INCBIN
) {
344 static char fname
[FILENAME_MAX
];
347 char *prefix
= "", *combine
;
348 char **pPrevPath
= NULL
;
350 len
= FILENAME_MAX
- 1;
351 if (len
> instruction
->eops
->stringlen
)
352 len
= instruction
->eops
->stringlen
;
353 strncpy(fname
, instruction
->eops
->stringval
, len
);
356 while (1) { /* added by alexfru: 'incbin' uses include paths */
357 combine
= nasm_malloc(strlen(prefix
) + len
+ 1);
358 strcpy(combine
, prefix
);
359 strcat(combine
, fname
);
361 if ((fp
= fopen(combine
, "rb")) != NULL
) {
367 pPrevPath
= pp_get_include_path_ptr(pPrevPath
);
368 if (pPrevPath
== NULL
)
374 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
376 else if (fseek(fp
, 0L, SEEK_END
) < 0)
377 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
380 static char buf
[2048];
381 int32_t t
= instruction
->times
;
385 if (instruction
->eops
->next
) {
386 base
= instruction
->eops
->next
->offset
;
388 if (instruction
->eops
->next
->next
&&
389 len
> instruction
->eops
->next
->next
->offset
)
390 len
= instruction
->eops
->next
->next
->offset
;
393 * Dummy call to list->output to give the offset to the
396 list
->output(offset
, NULL
, OUT_RAWDATA
);
397 list
->uplevel(LIST_INCBIN
);
401 fseek(fp
, base
, SEEK_SET
);
405 fread(buf
, 1, (l
> (int32_t) sizeof(buf
) ? (int32_t) sizeof(buf
) : l
),
409 * This shouldn't happen unless the file
410 * actually changes while we are reading
414 "`incbin': unexpected EOF while"
415 " reading file `%s'", fname
);
416 t
= 0; /* Try to exit cleanly */
419 out(offset
, segment
, buf
, OUT_RAWDATA
+ m
,
424 list
->downlevel(LIST_INCBIN
);
425 if (instruction
->times
> 1) {
427 * Dummy call to list->output to give the offset to the
430 list
->output(offset
, NULL
, OUT_RAWDATA
);
431 list
->uplevel(LIST_TIMES
);
432 list
->downlevel(LIST_TIMES
);
435 return instruction
->times
* len
;
437 return 0; /* if we're here, there's an error */
440 /* Check to see if we need an address-size prefix */
441 add_asp(instruction
, bits
);
445 for (temp
= nasm_instructions
[instruction
->opcode
]; temp
->opcode
!= -1; temp
++){
446 int m
= matches(temp
, instruction
, bits
);
449 m
+= jmp_match(segment
, offset
, bits
, instruction
, temp
->code
);
451 if (m
== 100) { /* matches! */
452 const char *codes
= temp
->code
;
453 int32_t insn_size
= calcsize(segment
, offset
, bits
,
455 itimes
= instruction
->times
;
456 if (insn_size
< 0) /* shouldn't be, on pass two */
457 error(ERR_PANIC
, "errors made it through from pass one");
460 for (j
= 0; j
< MAXPREFIX
; j
++) {
462 switch (instruction
->prefixes
[j
]) {
478 "cs segment base ignored in 64-bit mode");
485 "ds segment base ignored in 64-bit mode");
492 "es segment base ignored in 64-bit mode");
505 "ss segment base ignored in 64-bit mode");
512 "segr6 and segr7 cannot be used as prefixes");
517 "16-bit addressing is not supported "
519 } else if (bits
!= 16)
529 "64-bit addressing is only supported "
553 error(ERR_PANIC
, "invalid instruction prefix");
556 out(offset
, segment
, &c
, OUT_RAWDATA
+ 1,
561 insn_end
= offset
+ insn_size
;
562 gencode(segment
, offset
, bits
, instruction
, codes
,
565 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
567 * Dummy call to list->output to give the offset to the
570 list
->output(offset
, NULL
, OUT_RAWDATA
);
571 list
->uplevel(LIST_TIMES
);
574 if (instruction
->times
> 1)
575 list
->downlevel(LIST_TIMES
);
576 return offset
- start
;
577 } else if (m
> 0 && m
> size_prob
) {
583 if (temp
->opcode
== -1) { /* didn't match any instruction */
586 error(ERR_NONFATAL
, "operation size not specified");
589 error(ERR_NONFATAL
, "mismatch in operand sizes");
592 error(ERR_NONFATAL
, "no instruction for this cpu level");
595 error(ERR_NONFATAL
, "instruction not supported in 64-bit mode");
599 "invalid combination of opcode and operands");
606 int32_t insn_size(int32_t segment
, int32_t offset
, int bits
, uint32_t cp
,
607 insn
* instruction
, efunc error
)
609 const struct itemplate
*temp
;
611 errfunc
= error
; /* to pass to other functions */
614 if (instruction
->opcode
== -1)
617 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
618 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
619 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
) {
621 int32_t isize
, osize
, wsize
= 0; /* placate gcc */
624 switch (instruction
->opcode
) {
647 for (e
= instruction
->eops
; e
; e
= e
->next
) {
651 if (e
->type
== EOT_DB_NUMBER
)
653 else if (e
->type
== EOT_DB_STRING
)
654 osize
= e
->stringlen
;
656 align
= (-osize
) % wsize
;
659 isize
+= osize
+ align
;
661 return isize
* instruction
->times
;
664 if (instruction
->opcode
== I_INCBIN
) {
665 char fname
[FILENAME_MAX
];
668 char *prefix
= "", *combine
;
669 char **pPrevPath
= NULL
;
671 len
= FILENAME_MAX
- 1;
672 if (len
> instruction
->eops
->stringlen
)
673 len
= instruction
->eops
->stringlen
;
674 strncpy(fname
, instruction
->eops
->stringval
, len
);
677 /* added by alexfru: 'incbin' uses include paths */
679 combine
= nasm_malloc(strlen(prefix
) + len
+ 1);
680 strcpy(combine
, prefix
);
681 strcat(combine
, fname
);
683 if ((fp
= fopen(combine
, "rb")) != NULL
) {
689 pPrevPath
= pp_get_include_path_ptr(pPrevPath
);
690 if (pPrevPath
== NULL
)
696 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
698 else if (fseek(fp
, 0L, SEEK_END
) < 0)
699 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
704 if (instruction
->eops
->next
) {
705 len
-= instruction
->eops
->next
->offset
;
706 if (instruction
->eops
->next
->next
&&
707 len
> instruction
->eops
->next
->next
->offset
) {
708 len
= instruction
->eops
->next
->next
->offset
;
711 return instruction
->times
* len
;
713 return 0; /* if we're here, there's an error */
716 /* Check to see if we need an address-size prefix */
717 add_asp(instruction
, bits
);
719 for (temp
= nasm_instructions
[instruction
->opcode
]; temp
->opcode
!= -1; temp
++) {
720 int m
= matches(temp
, instruction
, bits
);
722 m
+= jmp_match(segment
, offset
, bits
, instruction
, temp
->code
);
725 /* we've matched an instruction. */
727 const char *codes
= temp
->code
;
730 isize
= calcsize(segment
, offset
, bits
, instruction
, codes
);
733 for (j
= 0; j
< MAXPREFIX
; j
++) {
734 switch (instruction
->prefixes
[j
]) {
760 return isize
* instruction
->times
;
763 return -1; /* didn't match any instruction */
766 /* check that opn[op] is a signed byte of size 16 or 32,
767 and return the signed value*/
768 static int is_sbyte(insn
* ins
, int op
, int size
)
773 ret
= !(ins
->forw_ref
&& ins
->oprs
[op
].opflags
) && /* dead in the water on forward reference or External */
775 !(ins
->oprs
[op
].type
& STRICT
) &&
776 ins
->oprs
[op
].wrt
== NO_SEG
&& ins
->oprs
[op
].segment
== NO_SEG
;
778 v
= ins
->oprs
[op
].offset
;
780 v
= (int16_t)v
; /* sign extend if 16 bits */
782 return ret
&& v
>= -128L && v
<= 127L;
785 static int32_t calcsize(int32_t segment
, int32_t offset
, int bits
,
786 insn
* ins
, const char *codes
)
791 ins
->rex
= 0; /* Ensure REX is reset */
794 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
797 (void)segment
; /* Don't warn that this parameter is unused */
798 (void)offset
; /* Don't warn that this parameter is unused */
802 opx
= &ins
->oprs
[c
& 3];
807 codes
+= c
, length
+= c
;
820 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
851 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
852 length
+= (opx
->type
& BITS16
) ? 2 : 4;
854 length
+= (bits
== 16) ? 2 : 4;
866 length
+= ins
->addr_size
>> 3;
878 length
+= 8; /* MOV reg64/imm */
890 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
891 length
+= (opx
->type
& BITS16
) ? 2 : 4;
893 length
+= (bits
== 16) ? 2 : 4;
911 length
+= is_sbyte(ins
, c
& 3, 16) ? 1 : 2;
924 length
+= is_sbyte(ins
, c
& 3, 32) ? 1 : 4;
939 ins
->drexdst
= regval(&ins
->oprs
[c
& 3]);
946 ins
->rex
|= REX_D
|REX_OC
;
947 ins
->drexdst
= regval(&ins
->oprs
[c
& 3]);
962 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
965 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
970 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
971 has_prefix(ins
, PPS_ASIZE
, P_A32
))
975 length
+= (bits
!= 16);
978 length
+= (bits
== 16);
1005 if (ins
->oprs
[0].segment
!= NO_SEG
)
1006 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1007 " quantity of BSS space");
1009 length
+= ins
->oprs
[0].offset
<< (c
& 3);
1025 default: /* can't do it by 'case' statements */
1026 if (c
>= 0100 && c
<= 0277) { /* it's an EA */
1030 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1033 /* pick rfield from operand b */
1034 rflags
= regflag(&ins
->oprs
[c
& 7]);
1035 rfield
= regvals
[ins
->oprs
[c
& 7].basereg
];
1042 (&ins
->oprs
[(c
>> 3) & 7], &ea_data
, bits
,
1043 ins
->addr_size
, rfield
, rflags
, ins
->forw_ref
)) {
1044 errfunc(ERR_NONFATAL
, "invalid effective address");
1047 ins
->rex
|= ea_data
.rex
;
1048 length
+= ea_data
.size
;
1051 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1052 ": instruction code 0x%02X given", c
);
1057 ins
->rex
&= rex_mask
;
1059 if (ins
->rex
& REX_D
) {
1060 if (ins
->rex
& REX_H
) {
1061 errfunc(ERR_NONFATAL
, "cannot use high register in drex instruction");
1064 if (bits
!= 64 && ((ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1065 ins
->drexdst
> 7)) {
1066 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1070 } else if (ins
->rex
& REX_REAL
) {
1071 if (ins
->rex
& REX_H
) {
1072 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1074 } else if (bits
== 64) {
1076 } else if ((ins
->rex
& REX_L
) &&
1077 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1080 assert_no_prefix(ins
, PPS_LREP
);
1083 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1091 #define EMIT_REX() \
1092 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1093 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1094 out(offset, segment, &ins->rex, OUT_RAWDATA+1, NO_SEG, NO_SEG); \
1099 static void gencode(int32_t segment
, int32_t offset
, int bits
,
1100 insn
* ins
, const char *codes
, int32_t insn_end
)
1102 static char condval
[] = { /* conditional opcodes */
1103 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1104 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1105 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1111 struct operand
*opx
;
1115 opx
= &ins
->oprs
[c
& 3];
1121 out(offset
, segment
, codes
, OUT_RAWDATA
+ c
, NO_SEG
, NO_SEG
);
1128 switch (ins
->oprs
[0].basereg
) {
1130 bytes
[0] = 0x0E + (c
== 0x04 ? 1 : 0);
1133 bytes
[0] = 0x1E + (c
== 0x04 ? 1 : 0);
1136 bytes
[0] = 0x06 + (c
== 0x04 ? 1 : 0);
1139 bytes
[0] = 0x16 + (c
== 0x04 ? 1 : 0);
1143 "bizarre 8086 segment register received");
1145 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1151 switch (ins
->oprs
[0].basereg
) {
1153 bytes
[0] = 0xA0 + (c
== 0x05 ? 1 : 0);
1156 bytes
[0] = 0xA8 + (c
== 0x05 ? 1 : 0);
1160 "bizarre 386 segment register received");
1162 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1171 bytes
[0] = *codes
++ + ((regval(opx
)) & 7);
1172 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1180 if (opx
->offset
< -128 || opx
->offset
> 127) {
1181 errfunc(ERR_WARNING
, "signed byte value exceeds bounds");
1184 if (opx
->segment
!= NO_SEG
) {
1186 out(offset
, segment
, &data
, OUT_ADDRESS
+ 1,
1187 opx
->segment
, opx
->wrt
);
1189 bytes
[0] = opx
->offset
;
1190 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
,
1200 if (opx
->offset
< -256 || opx
->offset
> 255) {
1201 errfunc(ERR_WARNING
, "byte value exceeds bounds");
1203 if (opx
->segment
!= NO_SEG
) {
1205 out(offset
, segment
, &data
, OUT_ADDRESS
+ 1,
1206 opx
->segment
, opx
->wrt
);
1208 bytes
[0] = opx
->offset
;
1209 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
,
1219 if (opx
->offset
< 0 || opx
->offset
> 255)
1220 errfunc(ERR_WARNING
, "unsigned byte value exceeds bounds");
1221 if (opx
->segment
!= NO_SEG
) {
1223 out(offset
, segment
, &data
, OUT_ADDRESS
+ 1,
1224 opx
->segment
, opx
->wrt
);
1226 bytes
[0] = opx
->offset
;
1227 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
,
1238 if (opx
->segment
== NO_SEG
&& opx
->wrt
== NO_SEG
)
1239 warn_overflow(2, data
);
1240 out(offset
, segment
, &data
, OUT_ADDRESS
+ 2,
1241 opx
->segment
, opx
->wrt
);
1249 if (opx
->type
& (BITS16
| BITS32
))
1250 size
= (opx
->type
& BITS16
) ? 2 : 4;
1252 size
= (bits
== 16) ? 2 : 4;
1254 if (opx
->segment
== NO_SEG
&& opx
->wrt
== NO_SEG
)
1255 warn_overflow(size
, data
);
1256 out(offset
, segment
, &data
, OUT_ADDRESS
+ size
,
1257 opx
->segment
, opx
->wrt
);
1266 out(offset
, segment
, &data
, OUT_ADDRESS
+ 4,
1267 opx
->segment
, opx
->wrt
);
1276 size
= ins
->addr_size
>> 3;
1277 if (opx
->segment
== NO_SEG
&&
1279 warn_overflow(size
, data
);
1280 out(offset
, segment
, &data
, OUT_ADDRESS
+ size
,
1281 opx
->segment
, opx
->wrt
);
1289 if (opx
->segment
!= segment
)
1290 errfunc(ERR_NONFATAL
,
1291 "short relative jump outside segment");
1292 data
= opx
->offset
- insn_end
;
1293 if (data
> 127 || data
< -128)
1294 errfunc(ERR_NONFATAL
, "short jump is out of range");
1296 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1304 data
= (int64_t)opx
->offset
;
1305 out(offset
, segment
, &data
, OUT_ADDRESS
+ 8,
1306 opx
->segment
, opx
->wrt
);
1314 if (opx
->segment
!= segment
) {
1316 out(offset
, segment
, &data
,
1317 OUT_REL2ADR
+ insn_end
- offset
,
1318 opx
->segment
, opx
->wrt
);
1320 data
= opx
->offset
- insn_end
;
1321 out(offset
, segment
, &data
,
1322 OUT_ADDRESS
+ 2, NO_SEG
, NO_SEG
);
1331 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1332 size
= (opx
->type
& BITS16
) ? 2 : 4;
1334 size
= (bits
== 16) ? 2 : 4;
1335 if (opx
->segment
!= segment
) {
1336 int32_t reltype
= (size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
);
1338 out(offset
, segment
, &data
, reltype
+ insn_end
- offset
,
1339 opx
->segment
, opx
->wrt
);
1341 data
= opx
->offset
- insn_end
;
1342 out(offset
, segment
, &data
,
1343 OUT_ADDRESS
+ size
, NO_SEG
, NO_SEG
);
1352 if (opx
->segment
!= segment
) {
1354 out(offset
, segment
, &data
,
1355 OUT_REL4ADR
+ insn_end
- offset
,
1356 opx
->segment
, opx
->wrt
);
1358 data
= opx
->offset
- insn_end
;
1359 out(offset
, segment
, &data
,
1360 OUT_ADDRESS
+ 4, NO_SEG
, NO_SEG
);
1369 if (opx
->segment
== NO_SEG
)
1370 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1373 out(offset
, segment
, &data
, OUT_ADDRESS
+ 2,
1374 outfmt
->segbase(1 + opx
->segment
),
1384 if (is_sbyte(ins
, c
& 3, 16)) {
1386 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
,
1390 if (opx
->segment
== NO_SEG
&&
1392 warn_overflow(2, data
);
1393 out(offset
, segment
, &data
, OUT_ADDRESS
+ 2,
1394 opx
->segment
, opx
->wrt
);
1405 bytes
[0] = *codes
++;
1406 if (is_sbyte(ins
, c
& 3, 16))
1407 bytes
[0] |= 2; /* s-bit */
1408 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1417 if (is_sbyte(ins
, c
& 3, 32)) {
1419 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
,
1423 out(offset
, segment
, &data
, OUT_ADDRESS
+ 4,
1424 opx
->segment
, opx
->wrt
);
1435 bytes
[0] = *codes
++;
1436 if (is_sbyte(ins
, c
& 3, 32))
1437 bytes
[0] |= 2; /* s-bit */
1438 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1455 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1461 (ins
->drexdst
<< 4) |
1462 (ins
->rex
& REX_OC
? 0x08 : 0) |
1463 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1465 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1476 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1478 out(offset
, segment
, bytes
,
1479 OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1486 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1488 out(offset
, segment
, bytes
,
1489 OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1505 out(offset
, segment
, bytes
,
1506 OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1515 out(offset
, segment
, bytes
,
1516 OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1531 *bytes
= *codes
++ ^ condval
[ins
->condition
];
1532 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1541 *bytes
= c
- 0332 + 0xF2;
1542 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1547 if (ins
->rex
& REX_R
) {
1549 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1552 ins
->rex
&= ~(REX_L
|REX_R
);
1561 if (ins
->oprs
[0].segment
!= NO_SEG
)
1562 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1564 int32_t size
= ins
->oprs
[0].offset
<< (c
& 3);
1566 out(offset
, segment
, NULL
,
1567 OUT_RESERVE
+ size
, NO_SEG
, NO_SEG
);
1578 *bytes
= c
- 0366 + 0x66;
1579 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1589 *bytes
= bits
== 16 ? 3 : 5;
1590 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1, NO_SEG
, NO_SEG
);
1594 default: /* can't do it by 'case' statements */
1595 if (c
>= 0100 && c
<= 0277) { /* it's an EA */
1603 /* pick rfield from operand b */
1604 rflags
= regflag(&ins
->oprs
[c
& 7]);
1605 rfield
= regvals
[ins
->oprs
[c
& 7].basereg
];
1607 /* rfield is constant */
1613 (&ins
->oprs
[(c
>> 3) & 7], &ea_data
, bits
,
1614 ins
->addr_size
, rfield
, rflags
, ins
->forw_ref
)) {
1615 errfunc(ERR_NONFATAL
, "invalid effective address");
1619 *p
++ = ea_data
.modrm
;
1620 if (ea_data
.sib_present
)
1623 /* DREX suffixes come between the SIB and the displacement */
1624 if (ins
->rex
& REX_D
) {
1626 (ins
->drexdst
<< 4) |
1627 (ins
->rex
& REX_OC
? 0x08 : 0) |
1628 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1633 out(offset
, segment
, bytes
, OUT_RAWDATA
+ s
,
1636 switch (ea_data
.bytes
) {
1640 if (ins
->oprs
[(c
>> 3) & 7].segment
!= NO_SEG
) {
1641 data
= ins
->oprs
[(c
>> 3) & 7].offset
;
1642 out(offset
, segment
, &data
, OUT_ADDRESS
+ 1,
1643 ins
->oprs
[(c
>> 3) & 7].segment
,
1644 ins
->oprs
[(c
>> 3) & 7].wrt
);
1646 *bytes
= ins
->oprs
[(c
>> 3) & 7].offset
;
1647 out(offset
, segment
, bytes
, OUT_RAWDATA
+ 1,
1655 data
= ins
->oprs
[(c
>> 3) & 7].offset
;
1656 out(offset
, segment
, &data
,
1657 (ea_data
.rip
? OUT_REL4ADR
: OUT_ADDRESS
)
1659 ins
->oprs
[(c
>> 3) & 7].segment
,
1660 ins
->oprs
[(c
>> 3) & 7].wrt
);
1666 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1667 ": instruction code 0x%02X given", c
);
1673 static int32_t regflag(const operand
* o
)
1675 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1676 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1678 return reg_flags
[o
->basereg
];
1681 static int32_t regval(const operand
* o
)
1683 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1684 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1686 return regvals
[o
->basereg
];
1689 static int op_rexflags(const operand
* o
, int mask
)
1694 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1695 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1698 flags
= reg_flags
[o
->basereg
];
1699 val
= regvals
[o
->basereg
];
1701 return rexflags(val
, flags
, mask
);
1704 static int rexflags(int val
, int32_t flags
, int mask
)
1709 rex
|= REX_B
|REX_X
|REX_R
;
1712 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1714 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1720 static int matches(const struct itemplate
*itemp
, insn
* instruction
, int bits
)
1722 int i
, size
[MAX_OPERANDS
], asize
, oprs
, ret
;
1729 if (itemp
->opcode
!= instruction
->opcode
)
1733 * Count the operands
1735 if (itemp
->operands
!= instruction
->operands
)
1739 * Check that no spurious colons or TOs are present
1741 for (i
= 0; i
< itemp
->operands
; i
++)
1742 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
1746 * Check that the operand flags all match up
1748 for (i
= 0; i
< itemp
->operands
; i
++) {
1749 if (itemp
->opd
[i
] & SAME_AS
) {
1750 int j
= itemp
->opd
[i
] & ~SAME_AS
;
1751 if (instruction
->oprs
[i
].type
!= instruction
->oprs
[j
].type
||
1752 instruction
->oprs
[i
].basereg
!= instruction
->oprs
[j
].basereg
)
1754 } else if (itemp
->opd
[i
] & ~instruction
->oprs
[i
].type
||
1755 ((itemp
->opd
[i
] & SIZE_MASK
) &&
1756 ((itemp
->opd
[i
] ^ instruction
->oprs
[i
].type
) & SIZE_MASK
))) {
1757 if ((itemp
->opd
[i
] & ~instruction
->oprs
[i
].type
& ~SIZE_MASK
) ||
1758 (instruction
->oprs
[i
].type
& SIZE_MASK
))
1766 * Check operand sizes
1768 if (itemp
->flags
& IF_ARMASK
) {
1769 memset(size
, 0, sizeof size
);
1771 switch (itemp
->flags
& IF_ARMASK
) {
1785 break; /* Shouldn't happen */
1787 switch (itemp
->flags
& IF_SMASK
) {
1808 switch (itemp
->flags
& IF_SMASK
) {
1811 oprs
= itemp
->operands
;
1815 oprs
= itemp
->operands
;
1819 oprs
= itemp
->operands
;
1823 oprs
= itemp
->operands
;
1827 oprs
= itemp
->operands
;
1832 for (i
= 0; i
< MAX_OPERANDS
; i
++)
1836 if (itemp
->flags
& (IF_SM
| IF_SM2
)) {
1837 oprs
= (itemp
->flags
& IF_SM2
? 2 : itemp
->operands
);
1839 for (i
= 0; i
< oprs
; i
++) {
1840 if ((asize
= itemp
->opd
[i
] & SIZE_MASK
) != 0) {
1842 for (j
= 0; j
< oprs
; j
++)
1848 oprs
= itemp
->operands
;
1851 for (i
= 0; i
< itemp
->operands
; i
++) {
1852 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
1853 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
1858 * Check template is okay at the set cpu level
1860 if (((itemp
->flags
& IF_PLEVEL
) > cpu
))
1864 * Check if instruction is available in long mode
1866 if ((itemp
->flags
& IF_NOLONG
) && (bits
== 64))
1870 * Check if special handling needed for Jumps
1872 if ((uint8_t)(itemp
->code
[0]) >= 0370)
1878 static ea
*process_ea(operand
* input
, ea
* output
, int bits
,
1879 int addrbits
, int rfield
, int32_t rflags
, int forw_ref
)
1881 output
->rip
= false;
1883 /* REX flags for the rfield operand */
1884 output
->rex
|= rexflags(rfield
, rflags
, REX_R
|REX_P
|REX_W
|REX_H
);
1886 if (!(REGISTER
& ~input
->type
)) { /* register direct */
1890 if (input
->basereg
< EXPR_REG_START
/* Verify as Register */
1891 || input
->basereg
>= REG_ENUM_LIMIT
)
1894 i
= regvals
[input
->basereg
];
1897 return NULL
; /* Invalid EA register */
1899 output
->rex
|= op_rexflags(input
, REX_B
|REX_P
|REX_W
|REX_H
);
1901 output
->sib_present
= false; /* no SIB necessary */
1902 output
->bytes
= 0; /* no offset necessary either */
1903 output
->modrm
= 0xC0 | ((rfield
& 7) << 3) | (i
& 7);
1904 } else { /* it's a memory reference */
1905 if (input
->basereg
== -1
1906 && (input
->indexreg
== -1 || input
->scale
== 0)) {
1907 /* it's a pure offset */
1908 if (bits
== 64 && (~input
->type
& IP_REL
)) {
1909 int scale
, index
, base
;
1910 output
->sib_present
= true;
1914 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
1916 output
->modrm
= 4 | ((rfield
& 7) << 3);
1917 output
->rip
= false;
1919 output
->sib_present
= false;
1920 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
1921 output
->modrm
= (addrbits
!= 16 ? 5 : 6) | ((rfield
& 7) << 3);
1922 output
->rip
= bits
== 64;
1924 } else { /* it's an indirection */
1925 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
1926 int32_t o
= input
->offset
, seg
= input
->segment
;
1927 int hb
= input
->hintbase
, ht
= input
->hinttype
;
1930 int32_t ix
, bx
; /* register flags */
1933 i
= -1; /* make this easy, at least */
1935 if (i
>= EXPR_REG_START
&& i
< REG_ENUM_LIMIT
) {
1943 if (b
>= EXPR_REG_START
&& b
< REG_ENUM_LIMIT
) {
1951 /* check for a 32/64-bit memory reference... */
1952 if ((ix
|bx
) & (BITS32
|BITS64
)) {
1953 /* it must be a 32/64-bit memory reference. Firstly we have
1954 * to check that all registers involved are type E/Rxx. */
1955 int32_t sok
= BITS32
|BITS64
;
1958 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
1966 return NULL
; /* Invalid register */
1967 if (~sok
& bx
& SIZE_MASK
)
1968 return NULL
; /* Invalid size */
1972 /* While we're here, ensure the user didn't specify
1974 if (input
->disp_size
== 16 || input
->disp_size
== 64)
1977 if (addrbits
== 16 ||
1978 (addrbits
== 32 && !(sok
& BITS32
)) ||
1979 (addrbits
== 64 && !(sok
& BITS64
)))
1982 /* now reorganize base/index */
1983 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
1984 ((hb
== b
&& ht
== EAH_NOTBASE
)
1985 || (hb
== i
&& ht
== EAH_MAKEBASE
))) {
1986 /* swap if hints say so */
1987 t
= bt
, bt
= it
, it
= t
;
1988 t
= bx
, bx
= ix
, ix
= t
;
1990 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
1991 bt
= -1, bx
= 0, s
++;
1992 if (bt
== -1 && s
== 1 && !(hb
== it
&& ht
== EAH_NOTBASE
)) {
1993 /* make single reg base, unless hint */
1994 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
1996 if (((s
== 2 && it
!= REG_NUM_ESP
1997 && !(input
->eaflags
& EAF_TIMESTWO
)) || s
== 3
1998 || s
== 5 || s
== 9) && bt
== -1)
1999 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2000 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
2001 && (input
->eaflags
& EAF_TIMESTWO
))
2002 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2003 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2004 if (s
== 1 && it
== REG_NUM_ESP
) {
2005 /* swap ESP into base if scale is 1 */
2006 t
= it
, it
= bt
, bt
= t
;
2007 t
= ix
, ix
= bx
, bx
= t
;
2009 if (it
== REG_NUM_ESP
2010 || (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2011 return NULL
; /* wrong, for various reasons */
2013 output
->rex
|= rexflags(it
, ix
, REX_X
);
2014 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2016 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2025 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2026 seg
== NO_SEG
&& !forw_ref
&&
2028 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2030 else if (input
->eaflags
& EAF_BYTEOFFS
||
2031 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2033 && !(input
->eaflags
& EAF_WORDOFFS
)))
2039 output
->sib_present
= false;
2040 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2041 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2044 int mod
, scale
, index
, base
;
2064 default: /* then what the smeg is it? */
2065 return NULL
; /* panic */
2073 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2074 seg
== NO_SEG
&& !forw_ref
&&
2076 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2078 else if (input
->eaflags
& EAF_BYTEOFFS
||
2079 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2081 && !(input
->eaflags
& EAF_WORDOFFS
)))
2087 output
->sib_present
= true;
2088 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2089 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | 4;
2090 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2092 } else { /* it's 16-bit */
2095 /* check for 64-bit long mode */
2099 /* check all registers are BX, BP, SI or DI */
2100 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
2101 && b
!= R_DI
) || (i
!= -1 && i
!= R_BP
&& i
!= R_BX
2102 && i
!= R_SI
&& i
!= R_DI
))
2105 /* ensure the user didn't specify DWORD/QWORD */
2106 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2109 if (s
!= 1 && i
!= -1)
2110 return NULL
; /* no can do, in 16-bit EA */
2111 if (b
== -1 && i
!= -1) {
2116 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2121 /* have BX/BP as base, SI/DI index */
2123 return NULL
; /* shouldn't ever happen, in theory */
2124 if (i
!= -1 && b
!= -1 &&
2125 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2126 return NULL
; /* invalid combinations */
2127 if (b
== -1) /* pure offset: handled above */
2128 return NULL
; /* so if it gets to here, panic! */
2132 switch (i
* 256 + b
) {
2133 case R_SI
* 256 + R_BX
:
2136 case R_DI
* 256 + R_BX
:
2139 case R_SI
* 256 + R_BP
:
2142 case R_DI
* 256 + R_BP
:
2160 if (rm
== -1) /* can't happen, in theory */
2161 return NULL
; /* so panic if it does */
2163 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2164 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2166 else if (input
->eaflags
& EAF_BYTEOFFS
||
2167 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2169 && !(input
->eaflags
& EAF_WORDOFFS
)))
2174 output
->sib_present
= false; /* no SIB - it's 16-bit */
2175 output
->bytes
= mod
; /* bytes of offset needed */
2176 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2181 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2185 static void add_asp(insn
*ins
, int addrbits
)
2190 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2192 switch (ins
->prefixes
[PPS_ASIZE
]) {
2203 valid
&= (addrbits
== 32) ? 16 : 32;
2209 for (j
= 0; j
< ins
->operands
; j
++) {
2210 if (!(MEMORY
& ~ins
->oprs
[j
].type
)) {
2213 /* Verify as Register */
2214 if (ins
->oprs
[j
].indexreg
< EXPR_REG_START
2215 || ins
->oprs
[j
].indexreg
>= REG_ENUM_LIMIT
)
2218 i
= reg_flags
[ins
->oprs
[j
].indexreg
];
2220 /* Verify as Register */
2221 if (ins
->oprs
[j
].basereg
< EXPR_REG_START
2222 || ins
->oprs
[j
].basereg
>= REG_ENUM_LIMIT
)
2225 b
= reg_flags
[ins
->oprs
[j
].basereg
];
2227 if (ins
->oprs
[j
].scale
== 0)
2231 int ds
= ins
->oprs
[j
].disp_size
;
2232 if ((addrbits
!= 64 && ds
> 8) ||
2233 (addrbits
== 64 && ds
== 16))
2253 if (valid
& addrbits
) {
2254 ins
->addr_size
= addrbits
;
2255 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2256 /* Add an address size prefix */
2257 enum prefixes pref
= (addrbits
== 32) ? P_A16
: P_A32
;
2258 ins
->prefixes
[PPS_ASIZE
] = pref
;
2259 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2262 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2263 ins
->addr_size
= addrbits
; /* Error recovery */
2266 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2268 for (j
= 0; j
< ins
->operands
; j
++) {
2269 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2270 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
)
2271 != ins
->addr_size
) {
2272 /* mem_offs sizes must match the address size; if not,
2273 strip the MEM_OFFS bit and match only EA instructions */
2274 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);