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BR 2067837: remove double add of VEX instruction length
[nasm.git] / assemble.c
blob9345fd8a24b37f9fc13b7c41826abb4aa0920279
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a dword. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \171 - placement of DREX suffix in the absence of an EA
48 * \172\ab - the register number from operand a in bits 7..4, with
49 * the 4-bit immediate from operand b in bits 3..0.
50 * \173\xab - the register number from operand a in bits 7..4, with
51 * the value b in bits 3..0.
52 * \174\a - the register number from operand a in bits 7..4, and
53 * an arbitrary value in bits 3..0 (assembled as zero.)
54 * \2ab - a ModRM, calculated on EA in operand a, with the spare
55 * field equal to digit b.
56 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
57 * is not equal to the truncated and sign-extended 32-bit
58 * operand; used for 32-bit immediates in 64-bit mode.
59 * \260..\263 - this instruction uses VEX rather than REX, with the
60 * V field taken from operand 0..3.
61 * \270 - this instruction uses VEX rather than REX, with the
62 * V field set to 1111b.
63 *
64 * VEX prefixes are followed by the sequence:
65 * \mm\wlp where mm is the M field; and wlp is:
66 * 00 0ww lpp
67 * [w0] ww = 0 for W = 0
68 * [w1] ww = 1 for W = 1
69 * [wx] ww = 2 for W don't care (always assembled as 0)
70 * [ww] ww = 3 for W used as REX.W
71 *
72 *
73 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
74 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
75 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
76 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
77 * \314 - (disassembler only) invalid with REX.B
78 * \315 - (disassembler only) invalid with REX.X
79 * \316 - (disassembler only) invalid with REX.R
80 * \317 - (disassembler only) invalid with REX.W
81 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
82 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
83 * \322 - indicates that this instruction is only valid when the
84 * operand size is the default (instruction to disassembler,
85 * generates no code in the assembler)
86 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
87 * \324 - indicates 64-bit operand size requiring REX prefix.
88 * \330 - a literal byte follows in the code stream, to be added
89 * to the condition code value of the instruction.
90 * \331 - instruction not valid with REP prefix. Hint for
91 * disassembler only; for SSE instructions.
92 * \332 - REP prefix (0xF2 byte) used as opcode extension.
93 * \333 - REP prefix (0xF3 byte) used as opcode extension.
94 * \334 - LOCK prefix used instead of REX.R
95 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
96 * \340 - reserve <operand 0> bytes of uninitialized storage.
97 * Operand 0 had better be a segmentless constant.
98 * \360 - no SSE prefix (== \364\331)
99 * \361 - 66 SSE prefix (== \366\331)
100 * \362 - F2 SSE prefix (== \364\332)
101 * \363 - F3 SSE prefix (== \364\333)
102 * \364 - operand-size prefix (0x66) not permitted
103 * \365 - address-size prefix (0x67) not permitted
104 * \366 - operand-size prefix (0x66) used as opcode extension
105 * \367 - address-size prefix (0x67) used as opcode extension
106 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
107 * 370 is used for Jcc, 371 is used for JMP.
108 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
109 * used for conditional jump over longer jump
110 */
111
112 #include "compiler.h"
113
114 #include <stdio.h>
115 #include <string.h>
116 #include <inttypes.h>
117
118 #include "nasm.h"
119 #include "nasmlib.h"
120 #include "assemble.h"
121 #include "insns.h"
122 #include "tables.h"
123
124 /* Initialized to zero by the C standard */
125 static const uint8_t const_zero_buf[256];
126
127 typedef struct {
128 int sib_present; /* is a SIB byte necessary? */
129 int bytes; /* # of bytes of offset needed */
130 int size; /* lazy - this is sib+bytes+1 */
131 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
132 } ea;
133
134 static uint32_t cpu; /* cpu level received from nasm.c */
135 static efunc errfunc;
136 static struct ofmt *outfmt;
137 static ListGen *list;
138
139 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
140 static void gencode(int32_t, int64_t, int, insn *, const uint8_t *, int64_t);
141 static int matches(const struct itemplate *, insn *, int bits);
142 static int32_t regflag(const operand *);
143 static int32_t regval(const operand *);
144 static int rexflags(int, int32_t, int);
145 static int op_rexflags(const operand *, int);
146 static ea *process_ea(operand *, ea *, int, int, int, int32_t);
147 static void add_asp(insn *, int);
148
149 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
150 {
151 return ins->prefixes[pos] == prefix;
152 }
153
154 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
155 {
156 if (ins->prefixes[pos])
157 errfunc(ERR_NONFATAL, "invalid %s prefix",
158 prefix_name(ins->prefixes[pos]));
159 }
160
161 static const char *size_name(int size)
162 {
163 switch (size) {
164 case 1:
165 return "byte";
166 case 2:
167 return "word";
168 case 4:
169 return "dword";
170 case 8:
171 return "qword";
172 case 10:
173 return "tword";
174 case 16:
175 return "oword";
176 case 32:
177 return "yword";
178 default:
179 return "???";
180 }
181 }
182
183 static void warn_overflow(int size, int64_t data)
184 {
185 if (size < 8) {
186 int64_t lim = ((int64_t)1 << (size*8))-1;
187
188 if (data < ~lim || data > lim)
189 errfunc(ERR_WARNING | ERR_WARN_NOV,
190 "%s data exceeds bounds", size_name(size));
191 }
192 }
193 /*
194 * This routine wrappers the real output format's output routine,
195 * in order to pass a copy of the data off to the listing file
196 * generator at the same time.
197 */
198 static void out(int64_t offset, int32_t segto, const void *data,
199 enum out_type type, uint64_t size,
200 int32_t segment, int32_t wrt)
201 {
202 static int32_t lineno = 0; /* static!!! */
203 static char *lnfname = NULL;
204 uint8_t p[8];
205
206 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
207 /*
208 * This is a non-relocated address, and we're going to
209 * convert it into RAWDATA format.
210 */
211 uint8_t *q = p;
212
213 if (size > 8) {
214 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
215 return;
216 }
217
218 WRITEADDR(q, *(int64_t *)data, size);
219 data = p;
220 type = OUT_RAWDATA;
221 }
222
223 list->output(offset, data, type, size);
224
225 /*
226 * this call to src_get determines when we call the
227 * debug-format-specific "linenum" function
228 * it updates lineno and lnfname to the current values
229 * returning 0 if "same as last time", -2 if lnfname
230 * changed, and the amount by which lineno changed,
231 * if it did. thus, these variables must be static
232 */
233
234 if (src_get(&lineno, &lnfname)) {
235 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
236 }
237
238 outfmt->output(segto, data, type, size, segment, wrt);
239 }
240
241 static int jmp_match(int32_t segment, int64_t offset, int bits,
242 insn * ins, const uint8_t *code)
243 {
244 int64_t isize;
245 uint8_t c = code[0];
246
247 if (c != 0370 && c != 0371)
248 return 0;
249 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
250 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
251 && c == 0370)
252 return 1;
253 else
254 return (pass0 == 0); /* match a forward reference */
255 }
256 isize = calcsize(segment, offset, bits, ins, code);
257 if (ins->oprs[0].segment != segment)
258 return 0;
259 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
260 if (isize >= -128L && isize <= 127L)
261 return 1; /* it is byte size */
262
263 return 0;
264 }
265
266 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
267 insn * instruction, struct ofmt *output, efunc error,
268 ListGen * listgen)
269 {
270 const struct itemplate *temp;
271 int j;
272 int size_prob;
273 int64_t insn_end;
274 int32_t itimes;
275 int64_t start = offset;
276 int64_t wsize = 0; /* size for DB etc. */
277
278 errfunc = error; /* to pass to other functions */
279 cpu = cp;
280 outfmt = output; /* likewise */
281 list = listgen; /* and again */
282
283 switch (instruction->opcode) {
284 case -1:
285 return 0;
286 case I_DB:
287 wsize = 1;
288 break;
289 case I_DW:
290 wsize = 2;
291 break;
292 case I_DD:
293 wsize = 4;
294 break;
295 case I_DQ:
296 wsize = 8;
297 break;
298 case I_DT:
299 wsize = 10;
300 break;
301 case I_DO:
302 wsize = 16;
303 break;
304 case I_DY:
305 wsize = 32;
306 break;
307 default:
308 break;
309 }
310
311 if (wsize) {
312 extop *e;
313 int32_t t = instruction->times;
314 if (t < 0)
315 errfunc(ERR_PANIC,
316 "instruction->times < 0 (%ld) in assemble()", t);
317
318 while (t--) { /* repeat TIMES times */
319 for (e = instruction->eops; e; e = e->next) {
320 if (e->type == EOT_DB_NUMBER) {
321 if (wsize == 1) {
322 if (e->segment != NO_SEG)
323 errfunc(ERR_NONFATAL,
324 "one-byte relocation attempted");
325 else {
326 uint8_t out_byte = e->offset;
327 out(offset, segment, &out_byte,
328 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
329 }
330 } else if (wsize > 8) {
331 errfunc(ERR_NONFATAL,
332 "integer supplied to a DT, DO or DY"
333 " instruction");
334 } else
335 out(offset, segment, &e->offset,
336 OUT_ADDRESS, wsize, e->segment, e->wrt);
337 offset += wsize;
338 } else if (e->type == EOT_DB_STRING ||
339 e->type == EOT_DB_STRING_FREE) {
340 int align;
341
342 out(offset, segment, e->stringval,
343 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
344 align = e->stringlen % wsize;
345
346 if (align) {
347 align = wsize - align;
348 out(offset, segment, const_zero_buf,
349 OUT_RAWDATA, align, NO_SEG, NO_SEG);
350 }
351 offset += e->stringlen + align;
352 }
353 }
354 if (t > 0 && t == instruction->times - 1) {
355 /*
356 * Dummy call to list->output to give the offset to the
357 * listing module.
358 */
359 list->output(offset, NULL, OUT_RAWDATA, 0);
360 list->uplevel(LIST_TIMES);
361 }
362 }
363 if (instruction->times > 1)
364 list->downlevel(LIST_TIMES);
365 return offset - start;
366 }
367
368 if (instruction->opcode == I_INCBIN) {
369 const char *fname = instruction->eops->stringval;
370 FILE *fp;
371
372 fp = fopen(fname, "rb");
373 if (!fp) {
374 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
375 fname);
376 } else if (fseek(fp, 0L, SEEK_END) < 0) {
377 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
378 fname);
379 } else {
380 static char buf[4096];
381 size_t t = instruction->times;
382 size_t base = 0;
383 size_t len;
384
385 len = ftell(fp);
386 if (instruction->eops->next) {
387 base = instruction->eops->next->offset;
388 len -= base;
389 if (instruction->eops->next->next &&
390 len > (size_t)instruction->eops->next->next->offset)
391 len = (size_t)instruction->eops->next->next->offset;
392 }
393 /*
394 * Dummy call to list->output to give the offset to the
395 * listing module.
396 */
397 list->output(offset, NULL, OUT_RAWDATA, 0);
398 list->uplevel(LIST_INCBIN);
399 while (t--) {
400 size_t l;
401
402 fseek(fp, base, SEEK_SET);
403 l = len;
404 while (l > 0) {
405 int32_t m =
406 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
407 fp);
408 if (!m) {
409 /*
410 * This shouldn't happen unless the file
411 * actually changes while we are reading
412 * it.
413 */
414 error(ERR_NONFATAL,
415 "`incbin': unexpected EOF while"
416 " reading file `%s'", fname);
417 t = 0; /* Try to exit cleanly */
418 break;
419 }
420 out(offset, segment, buf, OUT_RAWDATA, m,
421 NO_SEG, NO_SEG);
422 l -= m;
423 }
424 }
425 list->downlevel(LIST_INCBIN);
426 if (instruction->times > 1) {
427 /*
428 * Dummy call to list->output to give the offset to the
429 * listing module.
430 */
431 list->output(offset, NULL, OUT_RAWDATA, 0);
432 list->uplevel(LIST_TIMES);
433 list->downlevel(LIST_TIMES);
434 }
435 fclose(fp);
436 return instruction->times * len;
437 }
438 return 0; /* if we're here, there's an error */
439 }
440
441 /* Check to see if we need an address-size prefix */
442 add_asp(instruction, bits);
443
444 size_prob = false;
445
446 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
447 int m = matches(temp, instruction, bits);
448
449 if (m == 99)
450 m += jmp_match(segment, offset, bits, instruction, temp->code);
451
452 if (m == 100) { /* matches! */
453 const uint8_t *codes = temp->code;
454 int64_t insn_size = calcsize(segment, offset, bits,
455 instruction, codes);
456 itimes = instruction->times;
457 if (insn_size < 0) /* shouldn't be, on pass two */
458 error(ERR_PANIC, "errors made it through from pass one");
459 else
460 while (itimes--) {
461 for (j = 0; j < MAXPREFIX; j++) {
462 uint8_t c = 0;
463 switch (instruction->prefixes[j]) {
464 case P_LOCK:
465 c = 0xF0;
466 break;
467 case P_REPNE:
468 case P_REPNZ:
469 c = 0xF2;
470 break;
471 case P_REPE:
472 case P_REPZ:
473 case P_REP:
474 c = 0xF3;
475 break;
476 case R_CS:
477 if (bits == 64) {
478 error(ERR_WARNING,
479 "cs segment base generated, but will be ignored in 64-bit mode");
480 }
481 c = 0x2E;
482 break;
483 case R_DS:
484 if (bits == 64) {
485 error(ERR_WARNING,
486 "ds segment base generated, but will be ignored in 64-bit mode");
487 }
488 c = 0x3E;
489 break;
490 case R_ES:
491 if (bits == 64) {
492 error(ERR_WARNING,
493 "es segment base generated, but will be ignored in 64-bit mode");
494 }
495 c = 0x26;
496 break;
497 case R_FS:
498 c = 0x64;
499 break;
500 case R_GS:
501 c = 0x65;
502 break;
503 case R_SS:
504 if (bits == 64) {
505 error(ERR_WARNING,
506 "ss segment base generated, but will be ignored in 64-bit mode");
507 }
508 c = 0x36;
509 break;
510 case R_SEGR6:
511 case R_SEGR7:
512 error(ERR_NONFATAL,
513 "segr6 and segr7 cannot be used as prefixes");
514 break;
515 case P_A16:
516 if (bits == 64) {
517 error(ERR_NONFATAL,
518 "16-bit addressing is not supported "
519 "in 64-bit mode");
520 } else if (bits != 16)
521 c = 0x67;
522 break;
523 case P_A32:
524 if (bits != 32)
525 c = 0x67;
526 break;
527 case P_A64:
528 if (bits != 64) {
529 error(ERR_NONFATAL,
530 "64-bit addressing is only supported "
531 "in 64-bit mode");
532 }
533 break;
534 case P_ASP:
535 c = 0x67;
536 break;
537 case P_O16:
538 if (bits != 16)
539 c = 0x66;
540 break;
541 case P_O32:
542 if (bits == 16)
543 c = 0x66;
544 break;
545 case P_O64:
546 /* REX.W */
547 break;
548 case P_OSP:
549 c = 0x66;
550 break;
551 case P_none:
552 break;
553 default:
554 error(ERR_PANIC, "invalid instruction prefix");
555 }
556 if (c != 0) {
557 out(offset, segment, &c, OUT_RAWDATA, 1,
558 NO_SEG, NO_SEG);
559 offset++;
560 }
561 }
562 insn_end = offset + insn_size;
563 gencode(segment, offset, bits, instruction, codes,
564 insn_end);
565 offset += insn_size;
566 if (itimes > 0 && itimes == instruction->times - 1) {
567 /*
568 * Dummy call to list->output to give the offset to the
569 * listing module.
570 */
571 list->output(offset, NULL, OUT_RAWDATA, 0);
572 list->uplevel(LIST_TIMES);
573 }
574 }
575 if (instruction->times > 1)
576 list->downlevel(LIST_TIMES);
577 return offset - start;
578 } else if (m > 0 && m > size_prob) {
579 size_prob = m;
580 }
581 // temp++;
582 }
583
584 if (temp->opcode == -1) { /* didn't match any instruction */
585 switch (size_prob) {
586 case 1:
587 error(ERR_NONFATAL, "operation size not specified");
588 break;
589 case 2:
590 error(ERR_NONFATAL, "mismatch in operand sizes");
591 break;
592 case 3:
593 error(ERR_NONFATAL, "no instruction for this cpu level");
594 break;
595 case 4:
596 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
597 break;
598 default:
599 error(ERR_NONFATAL,
600 "invalid combination of opcode and operands");
601 break;
602 }
603 }
604 return 0;
605 }
606
607 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
608 insn * instruction, efunc error)
609 {
610 const struct itemplate *temp;
611
612 errfunc = error; /* to pass to other functions */
613 cpu = cp;
614
615 if (instruction->opcode == -1)
616 return 0;
617
618 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
619 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
620 instruction->opcode == I_DT || instruction->opcode == I_DO ||
621 instruction->opcode == I_DY) {
622 extop *e;
623 int32_t isize, osize, wsize = 0; /* placate gcc */
624
625 isize = 0;
626 switch (instruction->opcode) {
627 case I_DB:
628 wsize = 1;
629 break;
630 case I_DW:
631 wsize = 2;
632 break;
633 case I_DD:
634 wsize = 4;
635 break;
636 case I_DQ:
637 wsize = 8;
638 break;
639 case I_DT:
640 wsize = 10;
641 break;
642 case I_DO:
643 wsize = 16;
644 break;
645 case I_DY:
646 wsize = 32;
647 break;
648 default:
649 break;
650 }
651
652 for (e = instruction->eops; e; e = e->next) {
653 int32_t align;
654
655 osize = 0;
656 if (e->type == EOT_DB_NUMBER)
657 osize = 1;
658 else if (e->type == EOT_DB_STRING ||
659 e->type == EOT_DB_STRING_FREE)
660 osize = e->stringlen;
661
662 align = (-osize) % wsize;
663 if (align < 0)
664 align += wsize;
665 isize += osize + align;
666 }
667 return isize * instruction->times;
668 }
669
670 if (instruction->opcode == I_INCBIN) {
671 const char *fname = instruction->eops->stringval;
672 FILE *fp;
673 size_t len;
674
675 fp = fopen(fname, "rb");
676 if (!fp)
677 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
678 fname);
679 else if (fseek(fp, 0L, SEEK_END) < 0)
680 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
681 fname);
682 else {
683 len = ftell(fp);
684 fclose(fp);
685 if (instruction->eops->next) {
686 len -= instruction->eops->next->offset;
687 if (instruction->eops->next->next &&
688 len > (size_t)instruction->eops->next->next->offset) {
689 len = (size_t)instruction->eops->next->next->offset;
690 }
691 }
692 return instruction->times * len;
693 }
694 return 0; /* if we're here, there's an error */
695 }
696
697 /* Check to see if we need an address-size prefix */
698 add_asp(instruction, bits);
699
700 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
701 int m = matches(temp, instruction, bits);
702 if (m == 99)
703 m += jmp_match(segment, offset, bits, instruction, temp->code);
704
705 if (m == 100) {
706 /* we've matched an instruction. */
707 int64_t isize;
708 const uint8_t *codes = temp->code;
709 int j;
710
711 isize = calcsize(segment, offset, bits, instruction, codes);
712 if (isize < 0)
713 return -1;
714 for (j = 0; j < MAXPREFIX; j++) {
715 switch (instruction->prefixes[j]) {
716 case P_A16:
717 if (bits != 16)
718 isize++;
719 break;
720 case P_A32:
721 if (bits != 32)
722 isize++;
723 break;
724 case P_O16:
725 if (bits != 16)
726 isize++;
727 break;
728 case P_O32:
729 if (bits == 16)
730 isize++;
731 break;
732 case P_A64:
733 case P_O64:
734 case P_none:
735 break;
736 default:
737 isize++;
738 break;
739 }
740 }
741 return isize * instruction->times;
742 }
743 }
744 return -1; /* didn't match any instruction */
745 }
746
747 static bool possible_sbyte(operand *o)
748 {
749 return !(o->opflags & OPFLAG_FORWARD) &&
750 optimizing >= 0 && !(o->type & STRICT) &&
751 o->wrt == NO_SEG && o->segment == NO_SEG;
752 }
753
754 /* check that opn[op] is a signed byte of size 16 or 32 */
755 static bool is_sbyte16(operand *o)
756 {
757 int16_t v;
758
759 if (!possible_sbyte(o))
760 return false;
761
762 v = o->offset;
763 return v >= -128 && v <= 127;
764 }
765
766 static bool is_sbyte32(operand *o)
767 {
768 int32_t v;
769
770 if (!possible_sbyte(o))
771 return false;
772
773 v = o->offset;
774 return v >= -128 && v <= 127;
775 }
776
777 /* check that opn[op] is a signed byte of size 32; warn if this is not
778 the original value when extended to 64 bits */
779 static bool is_sbyte64(operand *o)
780 {
781 int64_t v64;
782 int32_t v32;
783
784 /* dead in the water on forward reference or External */
785 if (!possible_sbyte(o))
786 return false;
787
788 v64 = o->offset;
789 v32 = (int32_t)v64;
790
791 warn_overflow(32, v64);
792
793 return v32 >= -128 && v32 <= 127;
794 }
795 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
796 insn * ins, const uint8_t *codes)
797 {
798 int64_t length = 0;
799 uint8_t c;
800 int rex_mask = ~0;
801 struct operand *opx;
802
803 ins->rex = 0; /* Ensure REX is reset */
804
805 if (ins->prefixes[PPS_OSIZE] == P_O64)
806 ins->rex |= REX_W;
807
808 (void)segment; /* Don't warn that this parameter is unused */
809 (void)offset; /* Don't warn that this parameter is unused */
810
811 while (*codes) {
812 c = *codes++;
813 opx = &ins->oprs[c & 3];
814 switch (c) {
815 case 01:
816 case 02:
817 case 03:
818 codes += c, length += c;
819 break;
820 case 04:
821 case 05:
822 case 06:
823 case 07:
824 length++;
825 break;
826 case 010:
827 case 011:
828 case 012:
829 case 013:
830 ins->rex |=
831 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
832 codes++, length++;
833 break;
834 case 014:
835 case 015:
836 case 016:
837 case 017:
838 length++;
839 break;
840 case 020:
841 case 021:
842 case 022:
843 case 023:
844 length++;
845 break;
846 case 024:
847 case 025:
848 case 026:
849 case 027:
850 length++;
851 break;
852 case 030:
853 case 031:
854 case 032:
855 case 033:
856 length += 2;
857 break;
858 case 034:
859 case 035:
860 case 036:
861 case 037:
862 if (opx->type & (BITS16 | BITS32 | BITS64))
863 length += (opx->type & BITS16) ? 2 : 4;
864 else
865 length += (bits == 16) ? 2 : 4;
866 break;
867 case 040:
868 case 041:
869 case 042:
870 case 043:
871 length += 4;
872 break;
873 case 044:
874 case 045:
875 case 046:
876 case 047:
877 length += ins->addr_size >> 3;
878 break;
879 case 050:
880 case 051:
881 case 052:
882 case 053:
883 length++;
884 break;
885 case 054:
886 case 055:
887 case 056:
888 case 057:
889 length += 8; /* MOV reg64/imm */
890 break;
891 case 060:
892 case 061:
893 case 062:
894 case 063:
895 length += 2;
896 break;
897 case 064:
898 case 065:
899 case 066:
900 case 067:
901 if (opx->type & (BITS16 | BITS32 | BITS64))
902 length += (opx->type & BITS16) ? 2 : 4;
903 else
904 length += (bits == 16) ? 2 : 4;
905 break;
906 case 070:
907 case 071:
908 case 072:
909 case 073:
910 length += 4;
911 break;
912 case 074:
913 case 075:
914 case 076:
915 case 077:
916 length += 2;
917 break;
918 case 0140:
919 case 0141:
920 case 0142:
921 case 0143:
922 length += is_sbyte16(opx) ? 1 : 2;
923 break;
924 case 0144:
925 case 0145:
926 case 0146:
927 case 0147:
928 codes++;
929 length++;
930 break;
931 case 0150:
932 case 0151:
933 case 0152:
934 case 0153:
935 length += is_sbyte32(opx) ? 1 : 4;
936 break;
937 case 0154:
938 case 0155:
939 case 0156:
940 case 0157:
941 codes++;
942 length++;
943 break;
944 case 0160:
945 case 0161:
946 case 0162:
947 case 0163:
948 length++;
949 ins->rex |= REX_D;
950 ins->drexdst = regval(opx);
951 break;
952 case 0164:
953 case 0165:
954 case 0166:
955 case 0167:
956 length++;
957 ins->rex |= REX_D|REX_OC;
958 ins->drexdst = regval(opx);
959 break;
960 case 0171:
961 break;
962 case 0172:
963 case 0173:
964 case 0174:
965 codes++;
966 length++;
967 break;
968 case 0250:
969 case 0251:
970 case 0252:
971 case 0253:
972 length += is_sbyte64(opx) ? 1 : 4;
973 break;
974 case 0260:
975 case 0261:
976 case 0262:
977 case 0263:
978 ins->rex |= REX_V;
979 ins->drexdst = regval(opx);
980 ins->vex_m = *codes++;
981 ins->vex_wlp = *codes++;
982 break;
983 case 0270:
984 ins->rex |= REX_V;
985 ins->drexdst = 0;
986 ins->vex_m = *codes++;
987 ins->vex_wlp = *codes++;
988 break;
989 case 0300:
990 case 0301:
991 case 0302:
992 case 0303:
993 break;
994 case 0310:
995 if (bits == 64)
996 return -1;
997 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
998 break;
999 case 0311:
1000 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1001 break;
1002 case 0312:
1003 break;
1004 case 0313:
1005 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1006 has_prefix(ins, PPS_ASIZE, P_A32))
1007 return -1;
1008 break;
1009 case 0314:
1010 case 0315:
1011 case 0316:
1012 case 0317:
1013 break;
1014 case 0320:
1015 length += (bits != 16);
1016 break;
1017 case 0321:
1018 length += (bits == 16);
1019 break;
1020 case 0322:
1021 break;
1022 case 0323:
1023 rex_mask &= ~REX_W;
1024 break;
1025 case 0324:
1026 ins->rex |= REX_W;
1027 break;
1028 case 0330:
1029 codes++, length++;
1030 break;
1031 case 0331:
1032 break;
1033 case 0332:
1034 case 0333:
1035 length++;
1036 break;
1037 case 0334:
1038 ins->rex |= REX_L;
1039 break;
1040 case 0335:
1041 break;
1042 case 0340:
1043 if (ins->oprs[0].segment != NO_SEG)
1044 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1045 " quantity of BSS space");
1046 else
1047 length += ins->oprs[0].offset;
1048 break;
1049 case 0360:
1050 break;
1051 case 0361:
1052 case 0362:
1053 case 0363:
1054 length++;
1055 break;
1056 case 0364:
1057 case 0365:
1058 break;
1059 case 0366:
1060 case 0367:
1061 length++;
1062 break;
1063 case 0370:
1064 case 0371:
1065 case 0372:
1066 break;
1067 case 0373:
1068 length++;
1069 break;
1070 default: /* can't do it by 'case' statements */
1071 if (c >= 0100 && c <= 0277) { /* it's an EA */
1072 ea ea_data;
1073 int rfield;
1074 int32_t rflags;
1075 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1076
1077 if (c <= 0177) {
1078 /* pick rfield from operand b */
1079 rflags = regflag(&ins->oprs[c & 7]);
1080 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1081 } else {
1082 rflags = 0;
1083 rfield = c & 7;
1084 }
1085
1086 if (!process_ea
1087 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1088 ins->addr_size, rfield, rflags)) {
1089 errfunc(ERR_NONFATAL, "invalid effective address");
1090 return -1;
1091 } else {
1092 ins->rex |= ea_data.rex;
1093 length += ea_data.size;
1094 }
1095 } else {
1096 errfunc(ERR_PANIC, "internal instruction table corrupt"
1097 ": instruction code 0x%02X given", c);
1098 }
1099 }
1100 }
1101
1102 ins->rex &= rex_mask;
1103
1104 if (ins->rex & REX_V) {
1105 int bad32 = REX_R|REX_W|REX_X|REX_B;
1106
1107 if (ins->rex & REX_H) {
1108 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1109 return -1;
1110 }
1111 switch (ins->vex_wlp & 030) {
1112 case 000:
1113 case 020:
1114 ins->rex &= ~REX_W;
1115 break;
1116 case 010:
1117 ins->rex |= REX_W;
1118 bad32 &= ~REX_W;
1119 break;
1120 case 030:
1121 /* Follow REX_W */
1122 break;
1123 }
1124
1125 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1126 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1127 return -1;
1128 }
1129 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1130 length += 3;
1131 else
1132 length += 2;
1133 } else if (ins->rex & REX_D) {
1134 if (ins->rex & REX_H) {
1135 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1136 return -1;
1137 }
1138 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1139 ins->drexdst > 7)) {
1140 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1141 return -1;
1142 }
1143 length++;
1144 } else if (ins->rex & REX_REAL) {
1145 if (ins->rex & REX_H) {
1146 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1147 return -1;
1148 } else if (bits == 64) {
1149 length++;
1150 } else if ((ins->rex & REX_L) &&
1151 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1152 cpu >= IF_X86_64) {
1153 /* LOCK-as-REX.R */
1154 assert_no_prefix(ins, PPS_LREP);
1155 length++;
1156 } else {
1157 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1158 return -1;
1159 }
1160 }
1161
1162 return length;
1163 }
1164
1165 #define EMIT_REX() \
1166 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1167 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1168 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1169 ins->rex = 0; \
1170 offset += 1; \
1171 }
1172
1173 static void gencode(int32_t segment, int64_t offset, int bits,
1174 insn * ins, const uint8_t *codes, int64_t insn_end)
1175 {
1176 static char condval[] = { /* conditional opcodes */
1177 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1178 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1179 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1180 };
1181 uint8_t c;
1182 uint8_t bytes[4];
1183 int64_t size;
1184 int64_t data;
1185 struct operand *opx;
1186
1187 while (*codes) {
1188 c = *codes++;
1189 opx = &ins->oprs[c & 3];
1190 switch (c) {
1191 case 01:
1192 case 02:
1193 case 03:
1194 EMIT_REX();
1195 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1196 codes += c;
1197 offset += c;
1198 break;
1199
1200 case 04:
1201 case 06:
1202 switch (ins->oprs[0].basereg) {
1203 case R_CS:
1204 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1205 break;
1206 case R_DS:
1207 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1208 break;
1209 case R_ES:
1210 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1211 break;
1212 case R_SS:
1213 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1214 break;
1215 default:
1216 errfunc(ERR_PANIC,
1217 "bizarre 8086 segment register received");
1218 }
1219 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1220 offset++;
1221 break;
1222
1223 case 05:
1224 case 07:
1225 switch (ins->oprs[0].basereg) {
1226 case R_FS:
1227 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1228 break;
1229 case R_GS:
1230 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1231 break;
1232 default:
1233 errfunc(ERR_PANIC,
1234 "bizarre 386 segment register received");
1235 }
1236 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1237 offset++;
1238 break;
1239
1240 case 010:
1241 case 011:
1242 case 012:
1243 case 013:
1244 EMIT_REX();
1245 bytes[0] = *codes++ + ((regval(opx)) & 7);
1246 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1247 offset += 1;
1248 break;
1249
1250 case 014:
1251 case 015:
1252 case 016:
1253 case 017:
1254 /* XXX: warns for legitimate optimizer actions */
1255 if (opx->offset < -128 || opx->offset > 127) {
1256 errfunc(ERR_WARNING | ERR_WARN_NOV,
1257 "signed byte value exceeds bounds");
1258 }
1259
1260 if (opx->segment != NO_SEG) {
1261 data = opx->offset;
1262 out(offset, segment, &data, OUT_ADDRESS, 1,
1263 opx->segment, opx->wrt);
1264 } else {
1265 bytes[0] = opx->offset;
1266 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1267 NO_SEG);
1268 }
1269 offset += 1;
1270 break;
1271
1272 case 020:
1273 case 021:
1274 case 022:
1275 case 023:
1276 if (opx->offset < -256 || opx->offset > 255) {
1277 errfunc(ERR_WARNING | ERR_WARN_NOV,
1278 "byte value exceeds bounds");
1279 }
1280 if (opx->segment != NO_SEG) {
1281 data = opx->offset;
1282 out(offset, segment, &data, OUT_ADDRESS, 1,
1283 opx->segment, opx->wrt);
1284 } else {
1285 bytes[0] = opx->offset;
1286 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1287 NO_SEG);
1288 }
1289 offset += 1;
1290 break;
1291
1292 case 024:
1293 case 025:
1294 case 026:
1295 case 027:
1296 if (opx->offset < 0 || opx->offset > 255)
1297 errfunc(ERR_WARNING | ERR_WARN_NOV,
1298 "unsigned byte value exceeds bounds");
1299 if (opx->segment != NO_SEG) {
1300 data = opx->offset;
1301 out(offset, segment, &data, OUT_ADDRESS, 1,
1302 opx->segment, opx->wrt);
1303 } else {
1304 bytes[0] = opx->offset;
1305 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1306 NO_SEG);
1307 }
1308 offset += 1;
1309 break;
1310
1311 case 030:
1312 case 031:
1313 case 032:
1314 case 033:
1315 data = opx->offset;
1316 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1317 warn_overflow(2, data);
1318 out(offset, segment, &data, OUT_ADDRESS, 2,
1319 opx->segment, opx->wrt);
1320 offset += 2;
1321 break;
1322
1323 case 034:
1324 case 035:
1325 case 036:
1326 case 037:
1327 if (opx->type & (BITS16 | BITS32))
1328 size = (opx->type & BITS16) ? 2 : 4;
1329 else
1330 size = (bits == 16) ? 2 : 4;
1331 data = opx->offset;
1332 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1333 warn_overflow(size, data);
1334 out(offset, segment, &data, OUT_ADDRESS, size,
1335 opx->segment, opx->wrt);
1336 offset += size;
1337 break;
1338
1339 case 040:
1340 case 041:
1341 case 042:
1342 case 043:
1343 data = opx->offset;
1344 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1345 warn_overflow(4, data);
1346 out(offset, segment, &data, OUT_ADDRESS, 4,
1347 opx->segment, opx->wrt);
1348 offset += 4;
1349 break;
1350
1351 case 044:
1352 case 045:
1353 case 046:
1354 case 047:
1355 data = opx->offset;
1356 size = ins->addr_size >> 3;
1357 if (opx->segment == NO_SEG &&
1358 opx->wrt == NO_SEG)
1359 warn_overflow(size, data);
1360 out(offset, segment, &data, OUT_ADDRESS, size,
1361 opx->segment, opx->wrt);
1362 offset += size;
1363 break;
1364
1365 case 050:
1366 case 051:
1367 case 052:
1368 case 053:
1369 if (opx->segment != segment)
1370 errfunc(ERR_NONFATAL,
1371 "short relative jump outside segment");
1372 data = opx->offset - insn_end;
1373 if (data > 127 || data < -128)
1374 errfunc(ERR_NONFATAL, "short jump is out of range");
1375 bytes[0] = data;
1376 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1377 offset += 1;
1378 break;
1379
1380 case 054:
1381 case 055:
1382 case 056:
1383 case 057:
1384 data = (int64_t)opx->offset;
1385 out(offset, segment, &data, OUT_ADDRESS, 8,
1386 opx->segment, opx->wrt);
1387 offset += 8;
1388 break;
1389
1390 case 060:
1391 case 061:
1392 case 062:
1393 case 063:
1394 if (opx->segment != segment) {
1395 data = opx->offset;
1396 out(offset, segment, &data,
1397 OUT_REL2ADR, insn_end - offset,
1398 opx->segment, opx->wrt);
1399 } else {
1400 data = opx->offset - insn_end;
1401 out(offset, segment, &data,
1402 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1403 }
1404 offset += 2;
1405 break;
1406
1407 case 064:
1408 case 065:
1409 case 066:
1410 case 067:
1411 if (opx->type & (BITS16 | BITS32 | BITS64))
1412 size = (opx->type & BITS16) ? 2 : 4;
1413 else
1414 size = (bits == 16) ? 2 : 4;
1415 if (opx->segment != segment) {
1416 data = opx->offset;
1417 out(offset, segment, &data,
1418 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1419 insn_end - offset, opx->segment, opx->wrt);
1420 } else {
1421 data = opx->offset - insn_end;
1422 out(offset, segment, &data,
1423 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1424 }
1425 offset += size;
1426 break;
1427
1428 case 070:
1429 case 071:
1430 case 072:
1431 case 073:
1432 if (opx->segment != segment) {
1433 data = opx->offset;
1434 out(offset, segment, &data,
1435 OUT_REL4ADR, insn_end - offset,
1436 opx->segment, opx->wrt);
1437 } else {
1438 data = opx->offset - insn_end;
1439 out(offset, segment, &data,
1440 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1441 }
1442 offset += 4;
1443 break;
1444
1445 case 074:
1446 case 075:
1447 case 076:
1448 case 077:
1449 if (opx->segment == NO_SEG)
1450 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1451 " relocatable");
1452 data = 0;
1453 out(offset, segment, &data, OUT_ADDRESS, 2,
1454 outfmt->segbase(1 + opx->segment),
1455 opx->wrt);
1456 offset += 2;
1457 break;
1458
1459 case 0140:
1460 case 0141:
1461 case 0142:
1462 case 0143:
1463 data = opx->offset;
1464 if (is_sbyte16(opx)) {
1465 bytes[0] = data;
1466 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1467 NO_SEG);
1468 offset++;
1469 } else {
1470 if (opx->segment == NO_SEG &&
1471 opx->wrt == NO_SEG)
1472 warn_overflow(2, data);
1473 out(offset, segment, &data, OUT_ADDRESS, 2,
1474 opx->segment, opx->wrt);
1475 offset += 2;
1476 }
1477 break;
1478
1479 case 0144:
1480 case 0145:
1481 case 0146:
1482 case 0147:
1483 EMIT_REX();
1484 bytes[0] = *codes++;
1485 if (is_sbyte16(opx))
1486 bytes[0] |= 2; /* s-bit */
1487 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1488 offset++;
1489 break;
1490
1491 case 0150:
1492 case 0151:
1493 case 0152:
1494 case 0153:
1495 data = opx->offset;
1496 if (is_sbyte32(opx)) {
1497 bytes[0] = data;
1498 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1499 NO_SEG);
1500 offset++;
1501 } else {
1502 out(offset, segment, &data, OUT_ADDRESS, 4,
1503 opx->segment, opx->wrt);
1504 offset += 4;
1505 }
1506 break;
1507
1508 case 0154:
1509 case 0155:
1510 case 0156:
1511 case 0157:
1512 EMIT_REX();
1513 bytes[0] = *codes++;
1514 if (is_sbyte32(opx))
1515 bytes[0] |= 2; /* s-bit */
1516 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1517 offset++;
1518 break;
1519
1520 case 0160:
1521 case 0161:
1522 case 0162:
1523 case 0163:
1524 case 0164:
1525 case 0165:
1526 case 0166:
1527 case 0167:
1528 break;
1529
1530 case 0171:
1531 bytes[0] =
1532 (ins->drexdst << 4) |
1533 (ins->rex & REX_OC ? 0x08 : 0) |
1534 (ins->rex & (REX_R|REX_X|REX_B));
1535 ins->rex = 0;
1536 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1537 offset++;
1538 break;
1539
1540 case 0172:
1541 c = *codes++;
1542 opx = &ins->oprs[c >> 3];
1543 bytes[0] = nasm_regvals[opx->basereg] << 4;
1544 opx = &ins->oprs[c & 7];
1545 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1546 errfunc(ERR_NONFATAL,
1547 "non-absolute expression not permitted as argument %d",
1548 c & 7);
1549 } else {
1550 if (opx->offset & ~15) {
1551 errfunc(ERR_WARNING | ERR_WARN_NOV,
1552 "four-bit argument exceeds bounds");
1553 }
1554 bytes[0] |= opx->offset & 15;
1555 }
1556 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1557 offset++;
1558 break;
1559
1560 case 0173:
1561 c = *codes++;
1562 opx = &ins->oprs[c >> 4];
1563 bytes[0] = nasm_regvals[opx->basereg] << 4;
1564 bytes[0] |= c & 15;
1565 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1566 offset++;
1567 break;
1568
1569 case 0174:
1570 c = *codes++;
1571 opx = &ins->oprs[c];
1572 bytes[0] = nasm_regvals[opx->basereg] << 4;
1573 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1574 offset++;
1575 break;
1576
1577 case 0250:
1578 case 0251:
1579 case 0252:
1580 case 0253:
1581 data = opx->offset;
1582 /* is_sbyte32() is right here, we have already warned */
1583 if (is_sbyte32(opx)) {
1584 bytes[0] = data;
1585 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1586 NO_SEG);
1587 offset++;
1588 } else {
1589 out(offset, segment, &data, OUT_ADDRESS, 4,
1590 opx->segment, opx->wrt);
1591 offset += 4;
1592 }
1593 break;
1594
1595 case 0260:
1596 case 0261:
1597 case 0262:
1598 case 0263:
1599 case 0270:
1600 codes += 2;
1601 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1602 bytes[0] = 0xc4;
1603 bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5);
1604 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1605 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1606 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1607 offset += 3;
1608 } else {
1609 bytes[0] = 0xc5;
1610 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1611 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1612 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1613 offset += 2;
1614 }
1615 break;
1616
1617 case 0300:
1618 case 0301:
1619 case 0302:
1620 case 0303:
1621 break;
1622
1623 case 0310:
1624 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1625 *bytes = 0x67;
1626 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1627 offset += 1;
1628 } else
1629 offset += 0;
1630 break;
1631
1632 case 0311:
1633 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1634 *bytes = 0x67;
1635 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1636 offset += 1;
1637 } else
1638 offset += 0;
1639 break;
1640
1641 case 0312:
1642 break;
1643
1644 case 0313:
1645 ins->rex = 0;
1646 break;
1647
1648 case 0314:
1649 case 0315:
1650 case 0316:
1651 case 0317:
1652 break;
1653
1654 case 0320:
1655 if (bits != 16) {
1656 *bytes = 0x66;
1657 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1658 offset += 1;
1659 } else
1660 offset += 0;
1661 break;
1662
1663 case 0321:
1664 if (bits == 16) {
1665 *bytes = 0x66;
1666 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1667 offset += 1;
1668 } else
1669 offset += 0;
1670 break;
1671
1672 case 0322:
1673 case 0323:
1674 break;
1675
1676 case 0324:
1677 ins->rex |= REX_W;
1678 break;
1679
1680 case 0330:
1681 *bytes = *codes++ ^ condval[ins->condition];
1682 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1683 offset += 1;
1684 break;
1685
1686 case 0331:
1687 break;
1688
1689 case 0332:
1690 case 0333:
1691 *bytes = c - 0332 + 0xF2;
1692 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1693 offset += 1;
1694 break;
1695
1696 case 0334:
1697 if (ins->rex & REX_R) {
1698 *bytes = 0xF0;
1699 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1700 offset += 1;
1701 }
1702 ins->rex &= ~(REX_L|REX_R);
1703 break;
1704
1705 case 0335:
1706 break;
1707
1708 case 0340:
1709 if (ins->oprs[0].segment != NO_SEG)
1710 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1711 else {
1712 int64_t size = ins->oprs[0].offset;
1713 if (size > 0)
1714 out(offset, segment, NULL,
1715 OUT_RESERVE, size, NO_SEG, NO_SEG);
1716 offset += size;
1717 }
1718 break;
1719
1720 case 0360:
1721 break;
1722
1723 case 0361:
1724 bytes[0] = 0x66;
1725 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1726 offset += 1;
1727 break;
1728
1729 case 0362:
1730 case 0363:
1731 bytes[0] = c - 0362 + 0xf2;
1732 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1733 offset += 1;
1734 break;
1735
1736 case 0364:
1737 case 0365:
1738 break;
1739
1740 case 0366:
1741 case 0367:
1742 *bytes = c - 0366 + 0x66;
1743 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1744 offset += 1;
1745 break;
1746
1747 case 0370:
1748 case 0371:
1749 case 0372:
1750 break;
1751
1752 case 0373:
1753 *bytes = bits == 16 ? 3 : 5;
1754 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1755 offset += 1;
1756 break;
1757
1758 default: /* can't do it by 'case' statements */
1759 if (c >= 0100 && c <= 0277) { /* it's an EA */
1760 ea ea_data;
1761 int rfield;
1762 int32_t rflags;
1763 uint8_t *p;
1764 int32_t s;
1765
1766 if (c <= 0177) {
1767 /* pick rfield from operand b */
1768 rflags = regflag(&ins->oprs[c & 7]);
1769 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1770 } else {
1771 /* rfield is constant */
1772 rflags = 0;
1773 rfield = c & 7;
1774 }
1775
1776 if (!process_ea
1777 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1778 ins->addr_size, rfield, rflags)) {
1779 errfunc(ERR_NONFATAL, "invalid effective address");
1780 }
1781
1782
1783 p = bytes;
1784 *p++ = ea_data.modrm;
1785 if (ea_data.sib_present)
1786 *p++ = ea_data.sib;
1787
1788 /* DREX suffixes come between the SIB and the displacement */
1789 if (ins->rex & REX_D) {
1790 *p++ =
1791 (ins->drexdst << 4) |
1792 (ins->rex & REX_OC ? 0x08 : 0) |
1793 (ins->rex & (REX_R|REX_X|REX_B));
1794 ins->rex = 0;
1795 }
1796
1797 s = p - bytes;
1798 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1799
1800 switch (ea_data.bytes) {
1801 case 0:
1802 break;
1803 case 1:
1804 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1805 data = ins->oprs[(c >> 3) & 7].offset;
1806 out(offset, segment, &data, OUT_ADDRESS, 1,
1807 ins->oprs[(c >> 3) & 7].segment,
1808 ins->oprs[(c >> 3) & 7].wrt);
1809 } else {
1810 *bytes = ins->oprs[(c >> 3) & 7].offset;
1811 out(offset, segment, bytes, OUT_RAWDATA, 1,
1812 NO_SEG, NO_SEG);
1813 }
1814 s++;
1815 break;
1816 case 8:
1817 case 2:
1818 case 4:
1819 data = ins->oprs[(c >> 3) & 7].offset;
1820 warn_overflow(ea_data.bytes, data);
1821 out(offset, segment, &data,
1822 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1823 ea_data.bytes,
1824 ins->oprs[(c >> 3) & 7].segment,
1825 ins->oprs[(c >> 3) & 7].wrt);
1826 s += ea_data.bytes;
1827 break;
1828 }
1829 offset += s;
1830 } else {
1831 errfunc(ERR_PANIC, "internal instruction table corrupt"
1832 ": instruction code 0x%02X given", c);
1833 }
1834 }
1835 }
1836 }
1837
1838 static int32_t regflag(const operand * o)
1839 {
1840 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1841 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1842 }
1843 return nasm_reg_flags[o->basereg];
1844 }
1845
1846 static int32_t regval(const operand * o)
1847 {
1848 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1849 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1850 }
1851 return nasm_regvals[o->basereg];
1852 }
1853
1854 static int op_rexflags(const operand * o, int mask)
1855 {
1856 int32_t flags;
1857 int val;
1858
1859 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1860 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1861 }
1862
1863 flags = nasm_reg_flags[o->basereg];
1864 val = nasm_regvals[o->basereg];
1865
1866 return rexflags(val, flags, mask);
1867 }
1868
1869 static int rexflags(int val, int32_t flags, int mask)
1870 {
1871 int rex = 0;
1872
1873 if (val >= 8)
1874 rex |= REX_B|REX_X|REX_R;
1875 if (flags & BITS64)
1876 rex |= REX_W;
1877 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1878 rex |= REX_H;
1879 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1880 rex |= REX_P;
1881
1882 return rex & mask;
1883 }
1884
1885 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1886 {
1887 int i, size[MAX_OPERANDS], asize, oprs, ret;
1888
1889 ret = 100;
1890
1891 /*
1892 * Check the opcode
1893 */
1894 if (itemp->opcode != instruction->opcode)
1895 return 0;
1896
1897 /*
1898 * Count the operands
1899 */
1900 if (itemp->operands != instruction->operands)
1901 return 0;
1902
1903 /*
1904 * Check that no spurious colons or TOs are present
1905 */
1906 for (i = 0; i < itemp->operands; i++)
1907 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1908 return 0;
1909
1910 /*
1911 * Process size flags
1912 */
1913 if (itemp->flags & IF_ARMASK) {
1914 memset(size, 0, sizeof size);
1915
1916 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1917
1918 switch (itemp->flags & IF_SMASK) {
1919 case IF_SB:
1920 size[i] = BITS8;
1921 break;
1922 case IF_SW:
1923 size[i] = BITS16;
1924 break;
1925 case IF_SD:
1926 size[i] = BITS32;
1927 break;
1928 case IF_SQ:
1929 size[i] = BITS64;
1930 break;
1931 case IF_SO:
1932 size[i] = BITS128;
1933 break;
1934 case IF_SY:
1935 size[i] = BITS256;
1936 break;
1937 case IF_SZ:
1938 switch (bits) {
1939 case 16:
1940 size[i] = BITS16;
1941 break;
1942 case 32:
1943 size[i] = BITS32;
1944 break;
1945 case 64:
1946 size[i] = BITS64;
1947 break;
1948 }
1949 break;
1950 default:
1951 break;
1952 }
1953 } else {
1954 asize = 0;
1955 switch (itemp->flags & IF_SMASK) {
1956 case IF_SB:
1957 asize = BITS8;
1958 break;
1959 case IF_SW:
1960 asize = BITS16;
1961 break;
1962 case IF_SD:
1963 asize = BITS32;
1964 break;
1965 case IF_SQ:
1966 asize = BITS64;
1967 break;
1968 case IF_SO:
1969 asize = BITS128;
1970 break;
1971 case IF_SY:
1972 asize = BITS256;
1973 break;
1974 case IF_SZ:
1975 switch (bits) {
1976 case 16:
1977 asize = BITS16;
1978 break;
1979 case 32:
1980 asize = BITS32;
1981 break;
1982 case 64:
1983 asize = BITS64;
1984 break;
1985 }
1986 break;
1987 default:
1988 break;
1989 }
1990 for (i = 0; i < MAX_OPERANDS; i++)
1991 size[i] = asize;
1992 }
1993
1994 /*
1995 * Check that the operand flags all match up
1996 */
1997 for (i = 0; i < itemp->operands; i++) {
1998 int32_t type = instruction->oprs[i].type;
1999 if (!(type & SIZE_MASK))
2000 type |= size[i];
2001
2002 if (itemp->opd[i] & SAME_AS) {
2003 int j = itemp->opd[i] & ~SAME_AS;
2004 if (type != instruction->oprs[j].type ||
2005 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2006 return 0;
2007 } else if (itemp->opd[i] & ~type ||
2008 ((itemp->opd[i] & SIZE_MASK) &&
2009 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2010 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2011 (type & SIZE_MASK))
2012 return 0;
2013 else
2014 return 1;
2015 }
2016 }
2017
2018 /*
2019 * Check operand sizes
2020 */
2021 if (itemp->flags & (IF_SM | IF_SM2)) {
2022 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2023 asize = 0;
2024 for (i = 0; i < oprs; i++) {
2025 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2026 int j;
2027 for (j = 0; j < oprs; j++)
2028 size[j] = asize;
2029 break;
2030 }
2031 }
2032 } else {
2033 oprs = itemp->operands;
2034 }
2035
2036 for (i = 0; i < itemp->operands; i++) {
2037 if (!(itemp->opd[i] & SIZE_MASK) &&
2038 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2039 return 2;
2040 }
2041
2042 /*
2043 * Check template is okay at the set cpu level
2044 */
2045 if (((itemp->flags & IF_PLEVEL) > cpu))
2046 return 3;
2047
2048 /*
2049 * Check if instruction is available in long mode
2050 */
2051 if ((itemp->flags & IF_NOLONG) && (bits == 64))
2052 return 4;
2053
2054 /*
2055 * Check if special handling needed for Jumps
2056 */
2057 if ((uint8_t)(itemp->code[0]) >= 0370)
2058 return 99;
2059
2060 return ret;
2061 }
2062
2063 static ea *process_ea(operand * input, ea * output, int bits,
2064 int addrbits, int rfield, int32_t rflags)
2065 {
2066 bool forw_ref = !!(input->opflags & OPFLAG_FORWARD);
2067
2068 output->rip = false;
2069
2070 /* REX flags for the rfield operand */
2071 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2072
2073 if (!(REGISTER & ~input->type)) { /* register direct */
2074 int i;
2075 int32_t f;
2076
2077 if (input->basereg < EXPR_REG_START /* Verify as Register */
2078 || input->basereg >= REG_ENUM_LIMIT)
2079 return NULL;
2080 f = regflag(input);
2081 i = nasm_regvals[input->basereg];
2082
2083 if (REG_EA & ~f)
2084 return NULL; /* Invalid EA register */
2085
2086 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2087
2088 output->sib_present = false; /* no SIB necessary */
2089 output->bytes = 0; /* no offset necessary either */
2090 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2091 } else { /* it's a memory reference */
2092 if (input->basereg == -1
2093 && (input->indexreg == -1 || input->scale == 0)) {
2094 /* it's a pure offset */
2095 if (bits == 64 && (~input->type & IP_REL)) {
2096 int scale, index, base;
2097 output->sib_present = true;
2098 scale = 0;
2099 index = 4;
2100 base = 5;
2101 output->sib = (scale << 6) | (index << 3) | base;
2102 output->bytes = 4;
2103 output->modrm = 4 | ((rfield & 7) << 3);
2104 output->rip = false;
2105 } else {
2106 output->sib_present = false;
2107 output->bytes = (addrbits != 16 ? 4 : 2);
2108 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2109 output->rip = bits == 64;
2110 }
2111 } else { /* it's an indirection */
2112 int i = input->indexreg, b = input->basereg, s = input->scale;
2113 int32_t o = input->offset, seg = input->segment;
2114 int hb = input->hintbase, ht = input->hinttype;
2115 int t;
2116 int it, bt;
2117 int32_t ix, bx; /* register flags */
2118
2119 if (s == 0)
2120 i = -1; /* make this easy, at least */
2121
2122 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2123 it = nasm_regvals[i];
2124 ix = nasm_reg_flags[i];
2125 } else {
2126 it = -1;
2127 ix = 0;
2128 }
2129
2130 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2131 bt = nasm_regvals[b];
2132 bx = nasm_reg_flags[b];
2133 } else {
2134 bt = -1;
2135 bx = 0;
2136 }
2137
2138 /* check for a 32/64-bit memory reference... */
2139 if ((ix|bx) & (BITS32|BITS64)) {
2140 /* it must be a 32/64-bit memory reference. Firstly we have
2141 * to check that all registers involved are type E/Rxx. */
2142 int32_t sok = BITS32|BITS64;
2143
2144 if (it != -1) {
2145 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2146 sok &= ix;
2147 else
2148 return NULL;
2149 }
2150
2151 if (bt != -1) {
2152 if (REG_GPR & ~bx)
2153 return NULL; /* Invalid register */
2154 if (~sok & bx & SIZE_MASK)
2155 return NULL; /* Invalid size */
2156 sok &= bx;
2157 }
2158
2159 /* While we're here, ensure the user didn't specify
2160 WORD or QWORD. */
2161 if (input->disp_size == 16 || input->disp_size == 64)
2162 return NULL;
2163
2164 if (addrbits == 16 ||
2165 (addrbits == 32 && !(sok & BITS32)) ||
2166 (addrbits == 64 && !(sok & BITS64)))
2167 return NULL;
2168
2169 /* now reorganize base/index */
2170 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2171 ((hb == b && ht == EAH_NOTBASE)
2172 || (hb == i && ht == EAH_MAKEBASE))) {
2173 /* swap if hints say so */
2174 t = bt, bt = it, it = t;
2175 t = bx, bx = ix, ix = t;
2176 }
2177 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2178 bt = -1, bx = 0, s++;
2179 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2180 /* make single reg base, unless hint */
2181 bt = it, bx = ix, it = -1, ix = 0;
2182 }
2183 if (((s == 2 && it != REG_NUM_ESP
2184 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2185 || s == 5 || s == 9) && bt == -1)
2186 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2187 if (it == -1 && (bt & 7) != REG_NUM_ESP
2188 && (input->eaflags & EAF_TIMESTWO))
2189 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2190 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2191 if (s == 1 && it == REG_NUM_ESP) {
2192 /* swap ESP into base if scale is 1 */
2193 t = it, it = bt, bt = t;
2194 t = ix, ix = bx, bx = t;
2195 }
2196 if (it == REG_NUM_ESP
2197 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2198 return NULL; /* wrong, for various reasons */
2199
2200 output->rex |= rexflags(it, ix, REX_X);
2201 output->rex |= rexflags(bt, bx, REX_B);
2202
2203 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2204 /* no SIB needed */
2205 int mod, rm;
2206
2207 if (bt == -1) {
2208 rm = 5;
2209 mod = 0;
2210 } else {
2211 rm = (bt & 7);
2212 if (rm != REG_NUM_EBP && o == 0 &&
2213 seg == NO_SEG && !forw_ref &&
2214 !(input->eaflags &
2215 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2216 mod = 0;
2217 else if (input->eaflags & EAF_BYTEOFFS ||
2218 (o >= -128 && o <= 127 && seg == NO_SEG
2219 && !forw_ref
2220 && !(input->eaflags & EAF_WORDOFFS)))
2221 mod = 1;
2222 else
2223 mod = 2;
2224 }
2225
2226 output->sib_present = false;
2227 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2228 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2229 } else {
2230 /* we need a SIB */
2231 int mod, scale, index, base;
2232
2233 if (it == -1)
2234 index = 4, s = 1;
2235 else
2236 index = (it & 7);
2237
2238 switch (s) {
2239 case 1:
2240 scale = 0;
2241 break;
2242 case 2:
2243 scale = 1;
2244 break;
2245 case 4:
2246 scale = 2;
2247 break;
2248 case 8:
2249 scale = 3;
2250 break;
2251 default: /* then what the smeg is it? */
2252 return NULL; /* panic */
2253 }
2254
2255 if (bt == -1) {
2256 base = 5;
2257 mod = 0;
2258 } else {
2259 base = (bt & 7);
2260 if (base != REG_NUM_EBP && o == 0 &&
2261 seg == NO_SEG && !forw_ref &&
2262 !(input->eaflags &
2263 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2264 mod = 0;
2265 else if (input->eaflags & EAF_BYTEOFFS ||
2266 (o >= -128 && o <= 127 && seg == NO_SEG
2267 && !forw_ref
2268 && !(input->eaflags & EAF_WORDOFFS)))
2269 mod = 1;
2270 else
2271 mod = 2;
2272 }
2273
2274 output->sib_present = true;
2275 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2276 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2277 output->sib = (scale << 6) | (index << 3) | base;
2278 }
2279 } else { /* it's 16-bit */
2280 int mod, rm;
2281
2282 /* check for 64-bit long mode */
2283 if (addrbits == 64)
2284 return NULL;
2285
2286 /* check all registers are BX, BP, SI or DI */
2287 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2288 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2289 && i != R_SI && i != R_DI))
2290 return NULL;
2291
2292 /* ensure the user didn't specify DWORD/QWORD */
2293 if (input->disp_size == 32 || input->disp_size == 64)
2294 return NULL;
2295
2296 if (s != 1 && i != -1)
2297 return NULL; /* no can do, in 16-bit EA */
2298 if (b == -1 && i != -1) {
2299 int tmp = b;
2300 b = i;
2301 i = tmp;
2302 } /* swap */
2303 if ((b == R_SI || b == R_DI) && i != -1) {
2304 int tmp = b;
2305 b = i;
2306 i = tmp;
2307 }
2308 /* have BX/BP as base, SI/DI index */
2309 if (b == i)
2310 return NULL; /* shouldn't ever happen, in theory */
2311 if (i != -1 && b != -1 &&
2312 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2313 return NULL; /* invalid combinations */
2314 if (b == -1) /* pure offset: handled above */
2315 return NULL; /* so if it gets to here, panic! */
2316
2317 rm = -1;
2318 if (i != -1)
2319 switch (i * 256 + b) {
2320 case R_SI * 256 + R_BX:
2321 rm = 0;
2322 break;
2323 case R_DI * 256 + R_BX:
2324 rm = 1;
2325 break;
2326 case R_SI * 256 + R_BP:
2327 rm = 2;
2328 break;
2329 case R_DI * 256 + R_BP:
2330 rm = 3;
2331 break;
2332 } else
2333 switch (b) {
2334 case R_SI:
2335 rm = 4;
2336 break;
2337 case R_DI:
2338 rm = 5;
2339 break;
2340 case R_BP:
2341 rm = 6;
2342 break;
2343 case R_BX:
2344 rm = 7;
2345 break;
2346 }
2347 if (rm == -1) /* can't happen, in theory */
2348 return NULL; /* so panic if it does */
2349
2350 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2351 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2352 mod = 0;
2353 else if (input->eaflags & EAF_BYTEOFFS ||
2354 (o >= -128 && o <= 127 && seg == NO_SEG
2355 && !forw_ref
2356 && !(input->eaflags & EAF_WORDOFFS)))
2357 mod = 1;
2358 else
2359 mod = 2;
2360
2361 output->sib_present = false; /* no SIB - it's 16-bit */
2362 output->bytes = mod; /* bytes of offset needed */
2363 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2364 }
2365 }
2366 }
2367
2368 output->size = 1 + output->sib_present + output->bytes;
2369 return output;
2370 }
2371
2372 static void add_asp(insn *ins, int addrbits)
2373 {
2374 int j, valid;
2375 int defdisp;
2376
2377 valid = (addrbits == 64) ? 64|32 : 32|16;
2378
2379 switch (ins->prefixes[PPS_ASIZE]) {
2380 case P_A16:
2381 valid &= 16;
2382 break;
2383 case P_A32:
2384 valid &= 32;
2385 break;
2386 case P_A64:
2387 valid &= 64;
2388 break;
2389 case P_ASP:
2390 valid &= (addrbits == 32) ? 16 : 32;
2391 break;
2392 default:
2393 break;
2394 }
2395
2396 for (j = 0; j < ins->operands; j++) {
2397 if (!(MEMORY & ~ins->oprs[j].type)) {
2398 int32_t i, b;
2399
2400 /* Verify as Register */
2401 if (ins->oprs[j].indexreg < EXPR_REG_START
2402 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2403 i = 0;
2404 else
2405 i = nasm_reg_flags[ins->oprs[j].indexreg];
2406
2407 /* Verify as Register */
2408 if (ins->oprs[j].basereg < EXPR_REG_START
2409 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2410 b = 0;
2411 else
2412 b = nasm_reg_flags[ins->oprs[j].basereg];
2413
2414 if (ins->oprs[j].scale == 0)
2415 i = 0;
2416
2417 if (!i && !b) {
2418 int ds = ins->oprs[j].disp_size;
2419 if ((addrbits != 64 && ds > 8) ||
2420 (addrbits == 64 && ds == 16))
2421 valid &= ds;
2422 } else {
2423 if (!(REG16 & ~b))
2424 valid &= 16;
2425 if (!(REG32 & ~b))
2426 valid &= 32;
2427 if (!(REG64 & ~b))
2428 valid &= 64;
2429
2430 if (!(REG16 & ~i))
2431 valid &= 16;
2432 if (!(REG32 & ~i))
2433 valid &= 32;
2434 if (!(REG64 & ~i))
2435 valid &= 64;
2436 }
2437 }
2438 }
2439
2440 if (valid & addrbits) {
2441 ins->addr_size = addrbits;
2442 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2443 /* Add an address size prefix */
2444 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2445 ins->prefixes[PPS_ASIZE] = pref;
2446 ins->addr_size = (addrbits == 32) ? 16 : 32;
2447 } else {
2448 /* Impossible... */
2449 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2450 ins->addr_size = addrbits; /* Error recovery */
2451 }
2452
2453 defdisp = ins->addr_size == 16 ? 16 : 32;
2454
2455 for (j = 0; j < ins->operands; j++) {
2456 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2457 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2458 != ins->addr_size) {
2459 /* mem_offs sizes must match the address size; if not,
2460 strip the MEM_OFFS bit and match only EA instructions */
2461 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2462 }
2463 }
2464 }
The Netwide Assembler