opflags.h

   1 /* ----------------------------------------------------------------------- *
   2  *
   3  *   Copyright 1996-2013 The NASM Authors - All Rights Reserved
   4  *   See the file AUTHORS included with the NASM distribution for
   5  *   the specific copyright holders.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following
   9  *   conditions are met:
  10  *
  11  *   * Redistributions of source code must retain the above copyright
  12  *     notice, this list of conditions and the following disclaimer.
  13  *   * Redistributions in binary form must reproduce the above
  14  *     copyright notice, this list of conditions and the following
  15  *     disclaimer in the documentation and/or other materials provided
  16  *     with the distribution.
  17  *
  18  *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
  19  *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  20  *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  21  *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  22  *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  23  *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  24  *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  26  *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  29  *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  30  *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * ----------------------------------------------------------------------- */
  33
  34 /*
  35  * opflags.h - operand flags
  36  */
  37
  38 #ifndef NASM_OPFLAGS_H
  39 #define NASM_OPFLAGS_H
  40
  41 #include "compiler.h"
  42 #include "tables.h"     /* for opflags_t and nasm_reg_flags[] */
  43
  44 /*
  45  * Here we define the operand types. These are implemented as bit
  46  * masks, since some are subsets of others; e.g. AX in a MOV
  47  * instruction is a special operand type, whereas AX in other
  48  * contexts is just another 16-bit register. (Also, consider CL in
  49  * shift instructions, DX in OUT, etc.)
  50  *
  51  * The basic concept here is that
  52  *    (class & ~operand) == 0
  53  *
  54  * if and only if "operand" belongs to class type "class".
  55  */
  56
  57 #define OP_GENMASK(bits, shift)         (((UINT64_C(1) << (bits)) - 1) << (shift))
  58 #define OP_GENBIT(bit, shift)           (UINT64_C(1) << ((shift) + (bit)))
  59
  60 /*
  61  * Type of operand: memory reference, register, etc.
  62  *
  63  * Bits: 0 - 3
  64  */
  65 #define OPTYPE_SHIFT            (0)
  66 #define OPTYPE_BITS             (4)
  67 #define OPTYPE_MASK             OP_GENMASK(OPTYPE_BITS, OPTYPE_SHIFT)
  68 #define GEN_OPTYPE(bit)         OP_GENBIT(bit, OPTYPE_SHIFT)
  69
  70 /*
  71  * Modifiers.
  72  *
  73  * Bits: 4 - 6
  74  */
  75 #define MODIFIER_SHIFT          (4)
  76 #define MODIFIER_BITS           (3)
  77 #define MODIFIER_MASK           OP_GENMASK(MODIFIER_BITS, MODIFIER_SHIFT)
  78 #define GEN_MODIFIER(bit)       OP_GENBIT(bit, MODIFIER_SHIFT)
  79
  80 /*
  81  * Register classes.
  82  *
  83  * Bits: 7 - 16
  84  */
  85 #define REG_CLASS_SHIFT         (7)
  86 #define REG_CLASS_BITS          (10)
  87 #define REG_CLASS_MASK          OP_GENMASK(REG_CLASS_BITS, REG_CLASS_SHIFT)
  88 #define GEN_REG_CLASS(bit)      OP_GENBIT(bit, REG_CLASS_SHIFT)
  89
  90 /*
  91  * Subclasses. Depends on type of operand.
  92  *
  93  * Bits: 17 - 24
  94  */
  95 #define SUBCLASS_SHIFT          (17)
  96 #define SUBCLASS_BITS           (8)
  97 #define SUBCLASS_MASK           OP_GENMASK(SUBCLASS_BITS, SUBCLASS_SHIFT)
  98 #define GEN_SUBCLASS(bit)       OP_GENBIT(bit, SUBCLASS_SHIFT)
  99
 100 /*
 101  * Special flags. Context dependant.
 102  *
 103  * Bits: 25 - 31
 104  */
 105 #define SPECIAL_SHIFT           (25)
 106 #define SPECIAL_BITS            (7)
 107 #define SPECIAL_MASK            OP_GENMASK(SPECIAL_BITS, SPECIAL_SHIFT)
 108 #define GEN_SPECIAL(bit)        OP_GENBIT(bit, SPECIAL_SHIFT)
 109
 110 /*
 111  * Sizes of the operands and attributes.
 112  *
 113  * Bits: 32 - 42
 114  */
 115 #define SIZE_SHIFT              (32)
 116 #define SIZE_BITS               (11)
 117 #define SIZE_MASK               OP_GENMASK(SIZE_BITS, SIZE_SHIFT)
 118 #define GEN_SIZE(bit)           OP_GENBIT(bit, SIZE_SHIFT)
 119
 120 /*
 121  * Bits distribution (counted from 0)
 122  *
 123  *    6         5         4         3         2         1
 124  * 3210987654321098765432109876543210987654321098765432109876543210
 125  *                                 |
 126  *                                 | dword bound
 127  *
 128  * ............................................................1111 optypes
 129  * .........................................................111.... modifiers
 130  * ...............................................1111111111....... register classes
 131  * .......................................11111111................. subclasses
 132  * ................................1111111......................... specials
 133  * .....................11111111111................................ sizes
 134  */
 135
 136 #define REGISTER                GEN_OPTYPE(0)                   /* register number in 'basereg' */
 137 #define IMMEDIATE               GEN_OPTYPE(1)
 138 #define REGMEM                  GEN_OPTYPE(2)                   /* for r/m, ie EA, operands */
 139 #define MEMORY                  (GEN_OPTYPE(3) | REGMEM)
 140
 141 #define BITS8                   GEN_SIZE(0)                     /*   8 bits (BYTE) */
 142 #define BITS16                  GEN_SIZE(1)                     /*  16 bits (WORD) */
 143 #define BITS32                  GEN_SIZE(2)                     /*  32 bits (DWORD) */
 144 #define BITS64                  GEN_SIZE(3)                     /*  64 bits (QWORD), x64 and FPU only */
 145 #define BITS80                  GEN_SIZE(4)                     /*  80 bits (TWORD), FPU only */
 146 #define BITS128                 GEN_SIZE(5)                     /* 128 bits (OWORD) */
 147 #define BITS256                 GEN_SIZE(6)                     /* 256 bits (YWORD) */
 148 #define BITS512                 GEN_SIZE(7)                     /* 512 bits (ZWORD) */
 149 #define FAR                     GEN_SIZE(8)                     /* grotty: this means 16:16 or 16:32, like in CALL/JMP */
 150 #define NEAR                    GEN_SIZE(9)
 151 #define SHORT                   GEN_SIZE(10)                    /* and this means what it says :) */
 152
 153 #define TO                      GEN_MODIFIER(0)                 /* reverse effect in FADD, FSUB &c */
 154 #define COLON                   GEN_MODIFIER(1)                 /* operand is followed by a colon */
 155 #define STRICT                  GEN_MODIFIER(2)                 /* do not optimize this operand */
 156
 157 #define REG_CLASS_CDT           GEN_REG_CLASS(0)
 158 #define REG_CLASS_GPR           GEN_REG_CLASS(1)
 159 #define REG_CLASS_SREG          GEN_REG_CLASS(2)
 160 #define REG_CLASS_FPUREG        GEN_REG_CLASS(3)
 161 #define REG_CLASS_RM_MMX        GEN_REG_CLASS(4)
 162 #define REG_CLASS_RM_XMM        GEN_REG_CLASS(5)
 163 #define REG_CLASS_RM_YMM        GEN_REG_CLASS(6)
 164 #define REG_CLASS_RM_ZMM        GEN_REG_CLASS(7)
 165 #define REG_CLASS_OPMASK        GEN_REG_CLASS(8)
 166 #define REG_CLASS_BND           GEN_REG_CLASS(9)
 167
 168 #define is_class(class, op)         (!((opflags_t)(class) & ~(opflags_t)(op)))
 169 #define is_reg_class(class, reg)    is_class((class), nasm_reg_flags[(reg)])
 170
 171 #define IS_SREG(reg)                is_reg_class(REG_SREG, (reg))
 172 #define IS_FSGS(reg)                is_reg_class(REG_FSGS, (reg))
 173
 174 /* Register classes */
 175 #define REG_EA                  (                                               REGMEM | REGISTER)      /* 'normal' reg, qualifies as EA */
 176 #define RM_GPR                  (                  REG_CLASS_GPR              | REGMEM)                 /* integer operand */
 177 #define REG_GPR                 (                  REG_CLASS_GPR              | REGMEM | REGISTER)      /* integer register */
 178 #define REG8                    (                  REG_CLASS_GPR    | BITS8   | REGMEM | REGISTER)      /*  8-bit GPR  */
 179 #define REG16                   (                  REG_CLASS_GPR    | BITS16  | REGMEM | REGISTER)      /* 16-bit GPR */
 180 #define REG32                   (                  REG_CLASS_GPR    | BITS32  | REGMEM | REGISTER)      /* 32-bit GPR */
 181 #define REG64                   (                  REG_CLASS_GPR    | BITS64  | REGMEM | REGISTER)      /* 64-bit GPR */
 182 #define FPUREG                  (                  REG_CLASS_FPUREG                    | REGISTER)      /* floating point stack registers */
 183 #define FPU0                    (GEN_SUBCLASS(1) | REG_CLASS_FPUREG                    | REGISTER)      /* FPU stack register zero */
 184 #define RM_MMX                  (                  REG_CLASS_RM_MMX           | REGMEM)                 /* MMX operand */
 185 #define MMXREG                  (                  REG_CLASS_RM_MMX           | REGMEM | REGISTER)      /* MMX register */
 186 #define RM_XMM                  (                  REG_CLASS_RM_XMM           | REGMEM)                 /* XMM (SSE) operand */
 187 #define XMMREG                  (                  REG_CLASS_RM_XMM           | REGMEM | REGISTER)      /* XMM (SSE) register */
 188 #define RM_YMM                  (                  REG_CLASS_RM_YMM           | REGMEM)                 /* YMM (AVX) operand */
 189 #define YMMREG                  (                  REG_CLASS_RM_YMM           | REGMEM | REGISTER)      /* YMM (AVX) register */
 190 #define RM_ZMM                  (                  REG_CLASS_RM_ZMM           | REGMEM)                 /* ZMM (AVX512) operand */
 191 #define ZMMREG                  (                  REG_CLASS_RM_ZMM           | REGMEM | REGISTER)      /* ZMM (AVX512) register */
 192 #define RM_OPMASK               (                  REG_CLASS_OPMASK           | REGMEM)                 /* Opmask operand */
 193 #define OPMASKREG               (                  REG_CLASS_OPMASK           | REGMEM | REGISTER)      /* Opmask register */
 194 #define OPMASK0                 (GEN_SUBCLASS(1) | REG_CLASS_OPMASK           | REGMEM | REGISTER)      /* Opmask register zero (k0) */
 195 #define RM_K                    RM_OPMASK
 196 #define KREG                    OPMASKREG
 197 #define RM_BND                  (                  REG_CLASS_BND              | REGMEM)                 /* Bounds operand */
 198 #define BNDREG                  (                  REG_CLASS_BND              | REGMEM | REGISTER)      /* Bounds register */
 199 #define REG_CDT                 (                  REG_CLASS_CDT    | BITS32           | REGISTER)      /* CRn, DRn and TRn */
 200 #define REG_CREG                (GEN_SUBCLASS(1) | REG_CLASS_CDT    | BITS32           | REGISTER)      /* CRn */
 201 #define REG_DREG                (GEN_SUBCLASS(2) | REG_CLASS_CDT    | BITS32           | REGISTER)      /* DRn */
 202 #define REG_TREG                (GEN_SUBCLASS(3) | REG_CLASS_CDT    | BITS32           | REGISTER)      /* TRn */
 203 #define REG_SREG                (                  REG_CLASS_SREG   | BITS16           | REGISTER)      /* any segment register */
 204
 205 /* Segment registers */
 206 #define REG_ES                  (GEN_SUBCLASS(0) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER)      /* ES */
 207 #define REG_CS                  (GEN_SUBCLASS(1) | GEN_SUBCLASS(2) | REG_CLASS_SREG | BITS16 | REGISTER)      /* CS */
 208 #define REG_SS                  (GEN_SUBCLASS(0) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER)      /* SS */
 209 #define REG_DS                  (GEN_SUBCLASS(1) | GEN_SUBCLASS(3) | REG_CLASS_SREG | BITS16 | REGISTER)      /* DS */
 210 #define REG_FS                  (GEN_SUBCLASS(0) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER)      /* FS */
 211 #define REG_GS                  (GEN_SUBCLASS(1) | GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER)      /* GS */
 212 #define REG_FSGS                (                  GEN_SUBCLASS(4) | REG_CLASS_SREG | BITS16 | REGISTER)      /* FS or GS */
 213 #define REG_SEG67               (                  GEN_SUBCLASS(5) | REG_CLASS_SREG | BITS16 | REGISTER)      /* Unimplemented segment registers */
 214
 215 /* Special GPRs */
 216 #define REG_SMASK               SUBCLASS_MASK                                                                           /* a mask for the following */
 217 #define REG_ACCUM               (GEN_SUBCLASS(1)                   | REG_CLASS_GPR           | REGMEM | REGISTER)       /* accumulator: AL, AX, EAX, RAX */
 218 #define REG_AL                  (GEN_SUBCLASS(1)                   | REG_CLASS_GPR | BITS8   | REGMEM | REGISTER)
 219 #define REG_AX                  (GEN_SUBCLASS(1)                   | REG_CLASS_GPR | BITS16  | REGMEM | REGISTER)
 220 #define REG_EAX                 (GEN_SUBCLASS(1)                   | REG_CLASS_GPR | BITS32  | REGMEM | REGISTER)
 221 #define REG_RAX                 (GEN_SUBCLASS(1)                   | REG_CLASS_GPR | BITS64  | REGMEM | REGISTER)
 222 #define REG_COUNT               (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR           | REGMEM | REGISTER)       /* counter: CL, CX, ECX, RCX */
 223 #define REG_CL                  (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS8   | REGMEM | REGISTER)
 224 #define REG_CX                  (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS16  | REGMEM | REGISTER)
 225 #define REG_ECX                 (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS32  | REGMEM | REGISTER)
 226 #define REG_RCX                 (GEN_SUBCLASS(5) | GEN_SUBCLASS(2) | REG_CLASS_GPR | BITS64  | REGMEM | REGISTER)
 227 #define REG_DL                  (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS8   | REGMEM | REGISTER)       /* data: DL, DX, EDX, RDX */
 228 #define REG_DX                  (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS16  | REGMEM | REGISTER)
 229 #define REG_EDX                 (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS32  | REGMEM | REGISTER)
 230 #define REG_RDX                 (GEN_SUBCLASS(5) | GEN_SUBCLASS(3) | REG_CLASS_GPR | BITS64  | REGMEM | REGISTER)
 231 #define REG_HIGH                (GEN_SUBCLASS(5) | GEN_SUBCLASS(4) | REG_CLASS_GPR | BITS8   | REGMEM | REGISTER)       /* high regs: AH, CH, DH, BH */
 232 #define REG_NOTACC              GEN_SUBCLASS(5)                                                                         /* non-accumulator register */
 233 #define REG8NA                  (GEN_SUBCLASS(5)                   | REG_CLASS_GPR | BITS8   | REGMEM | REGISTER)       /*  8-bit non-acc GPR  */
 234 #define REG16NA                 (GEN_SUBCLASS(5)                   | REG_CLASS_GPR | BITS16  | REGMEM | REGISTER)       /* 16-bit non-acc GPR */
 235 #define REG32NA                 (GEN_SUBCLASS(5)                   | REG_CLASS_GPR | BITS32  | REGMEM | REGISTER)       /* 32-bit non-acc GPR */
 236 #define REG64NA                 (GEN_SUBCLASS(5)                   | REG_CLASS_GPR | BITS64  | REGMEM | REGISTER)       /* 64-bit non-acc GPR */
 237
 238 /* special types of EAs */
 239 #define MEM_OFFS                (GEN_SUBCLASS(1) | MEMORY)      /* simple [address] offset - absolute! */
 240 #define IP_REL                  (GEN_SUBCLASS(2) | MEMORY)      /* IP-relative offset */
 241 #define XMEM                    (GEN_SUBCLASS(3) | MEMORY)      /* 128-bit vector SIB */
 242 #define YMEM                    (GEN_SUBCLASS(4) | MEMORY)      /* 256-bit vector SIB */
 243 #define ZMEM                    (GEN_SUBCLASS(5) | MEMORY)      /* 512-bit vector SIB */
 244
 245 /* memory which matches any type of r/m operand */
 246 #define MEMORY_ANY              (MEMORY | RM_GPR | RM_MMX | RM_XMM_L16 | RM_YMM_L16 | RM_ZMM_L16 | RM_OPMASK | RM_BND)
 247
 248 /* special immediate values */
 249 #define UNITY                   (GEN_SUBCLASS(0) | IMMEDIATE)   /* operand equals 1 */
 250 #define SBYTEWORD               (GEN_SUBCLASS(1) | IMMEDIATE)   /* operand is in the range -128..127 mod 2^16 */
 251 #define SBYTEDWORD              (GEN_SUBCLASS(2) | IMMEDIATE)   /* operand is in the range -128..127 mod 2^32 */
 252 #define SDWORD                  (GEN_SUBCLASS(3) | IMMEDIATE)   /* operand is in the range -0x80000000..0x7FFFFFFF */
 253 #define UDWORD                  (GEN_SUBCLASS(4) | IMMEDIATE)   /* operand is in the range 0..0xFFFFFFFF */
 254
 255 /*
 256  * Subset of vector registers: register 0 only and registers 0-15.
 257  * Avoid conflicts in subclass bitfield with any of special EA types!
 258  */
 259 #define RM_XMM_L16              (GEN_SUBCLASS(6) | RM_XMM)                                              /* XMM r/m operand  0 ~ 15 */
 260 #define XMM0                    (GEN_SUBCLASS(1) | GEN_SUBCLASS(6) | XMMREG)                            /* XMM register   zero  */
 261 #define XMM_L16                 (                  GEN_SUBCLASS(6) | XMMREG)                            /* XMM register  0 ~ 15 */
 262
 263 #define RM_YMM_L16              (GEN_SUBCLASS(6) | RM_YMM)                                              /* YMM r/m operand  0 ~ 15 */
 264 #define YMM0                    (GEN_SUBCLASS(1) | GEN_SUBCLASS(6) | YMMREG)                            /* YMM register   zero  */
 265 #define YMM_L16                 (                  GEN_SUBCLASS(6) | YMMREG)                            /* YMM register  0 ~ 15 */
 266
 267 #define RM_ZMM_L16              (GEN_SUBCLASS(6) | RM_ZMM)                                              /* ZMM r/m operand  0 ~ 15 */
 268 #define ZMM0                    (GEN_SUBCLASS(1) | GEN_SUBCLASS(6) | ZMMREG)                            /* ZMM register   zero  */
 269 #define ZMM_L16                 (                  GEN_SUBCLASS(6) | ZMMREG)                            /* ZMM register  0 ~ 15 */
 270
 271 #endif /* NASM_OPFLAGS_H */