x86/insns-iflags.ph

   1 #!/usr/bin/perl
   2 ## --------------------------------------------------------------------------
   3 ##
   4 ##   Copyright 1996-2018 The NASM Authors - All Rights Reserved
   5 ##   See the file AUTHORS included with the NASM distribution for
   6 ##   the specific copyright holders.
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  13 ##     notice, this list of conditions and the following disclaimer.
  14 ##   * Redistributions in binary form must reproduce the above
  15 ##     copyright notice, this list of conditions and the following
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  17 ##     with the distribution.
  18 ##
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  32 ##
  33 ## --------------------------------------------------------------------------
  34
  35 #
  36 # Instruction template flags. These specify which processor
  37 # targets the instruction is eligible for, whether it is
  38 # privileged or undocumented, and also specify extra error
  39 # checking on the matching of the instruction.
  40 #
  41 # IF_SM stands for Size Match: any operand whose size is not
  42 # explicitly specified by the template is `really' intended to be
  43 # the same size as the first size-specified operand.
  44 # Non-specification is tolerated in the input instruction, but
  45 # _wrong_ specification is not.
  46 #
  47 # IF_SM2 invokes Size Match on only the first _two_ operands, for
  48 # three-operand instructions such as SHLD: it implies that the
  49 # first two operands must match in size, but that the third is
  50 # required to be _unspecified_.
  51 #
  52 # IF_SB invokes Size Byte: operands with unspecified size in the
  53 # template are really bytes, and so no non-byte specification in
  54 # the input instruction will be tolerated. IF_SW similarly invokes
  55 # Size Word, and IF_SD invokes Size Doubleword.
  56 #
  57 # (The default state if neither IF_SM nor IF_SM2 is specified is
  58 # that any operand with unspecified size in the template is
  59 # required to have unspecified size in the instruction too...)
  60 #
  61 # iflag_t is defined to store these flags.
  62 #
  63 # The order does matter here. We use some predefined masks to quick test
  64 # for a set of flags, so be careful moving bits (and
  65 # don't forget to update C code generation then).
  66 #
  67 sub dword_align($) {
  68     my($n) = @_;
  69
  70     $$n = ($$n + 31) & ~31;
  71     return $n;
  72 }
  73
  74 my $f = 0;
  75 my %insns_flag_bit = (
  76     #
  77     # dword bound, index 0 - specific flags
  78     #
  79     "SM"                => [$f++, "Size match"],
  80     "SM2"               => [$f++, "Size match first two operands"],
  81     "SB"                => [$f++, "Unsized operands can't be non-byte"],
  82     "SW"                => [$f++, "Unsized operands can't be non-word"],
  83     "SD"                => [$f++, "Unsized operands can't be non-dword"],
  84     "SQ"                => [$f++, "Unsized operands can't be non-qword"],
  85     "SO"                => [$f++, "Unsized operands can't be non-oword"],
  86     "SY"                => [$f++, "Unsized operands can't be non-yword"],
  87     "SZ"                => [$f++, "Unsized operands can't be non-zword"],
  88     "SIZE"              => [$f++, "Unsized operands must match the bitsize"],
  89     "SX"                => [$f++, "Unsized operands not allowed"],
  90     "AR0"               => [$f++, "SB, SW, SD applies to argument 0"],
  91     "AR1"               => [$f++, "SB, SW, SD applies to argument 1"],
  92     "AR2"               => [$f++, "SB, SW, SD applies to argument 2"],
  93     "AR3"               => [$f++, "SB, SW, SD applies to argument 3"],
  94     "AR4"               => [$f++, "SB, SW, SD applies to argument 4"],
  95     "OPT"               => [$f++, "Optimizing assembly only"],
  96
  97     #
  98     # dword bound - instruction filtering flags
  99     #
 100     "PRIV"              => [${dword_align(\$f)}++, "Privileged instruction"],
 101     "SMM"               => [$f++, "Only valid in SMM"],
 102     "PROT"              => [$f++, "Protected mode only"],
 103     "LOCK"              => [$f++, "Lockable if operand 0 is memory"],
 104     "NOLONG"            => [$f++, "Not available in long mode"],
 105     "LONG"              => [$f++, "Long mode"],
 106     "NOHLE"             => [$f++, "HLE prefixes forbidden"],
 107     "MIB"               => [$f++, "disassemble with split EA"],
 108     "BND"               => [$f++, "BND (0xF2) prefix available"],
 109     "UNDOC"             => [$f++, "Undocumented"],
 110     "HLE"               => [$f++, "HLE prefixed"],
 111     "FPU"               => [$f++, "FPU"],
 112     "MMX"               => [$f++, "MMX"],
 113     "3DNOW"             => [$f++, "3DNow!"],
 114     "SSE"               => [$f++, "SSE (KNI, MMX2)"],
 115     "SSE2"              => [$f++, "SSE2"],
 116     "SSE3"              => [$f++, "SSE3 (PNI)"],
 117     "VMX"               => [$f++, "VMX"],
 118     "SSSE3"             => [$f++, "SSSE3"],
 119     "SSE4A"             => [$f++, "AMD SSE4a"],
 120     "SSE41"             => [$f++, "SSE4.1"],
 121     "SSE42"             => [$f++, "SSE4.2"],
 122     "SSE5"              => [$f++, "SSE5"],
 123     "AVX"               => [$f++, "AVX  (256-bit floating point)"],
 124     "AVX2"              => [$f++, "AVX2 (256-bit integer)"],
 125     "FMA"               => [$f++, ""],
 126     "BMI1"              => [$f++, ""],
 127     "BMI2"              => [$f++, ""],
 128     "TBM"               => [$f++, ""],
 129     "RTM"               => [$f++, ""],
 130     "INVPCID"           => [$f++, ""],
 131     "AVX512"            => [$f++, "AVX-512F (512-bit base architecture)"],
 132     "AVX512CD"          => [$f++, "AVX-512 Conflict Detection"],
 133     "AVX512ER"          => [$f++, "AVX-512 Exponential and Reciprocal"],
 134     "AVX512PF"          => [$f++, "AVX-512 Prefetch"],
 135     "MPX"               => [$f++, "MPX"],
 136     "SHA"               => [$f++, "SHA"],
 137     "PREFETCHWT1"       => [$f++, "PREFETCHWT1"],
 138     "AVX512VL"          => [$f++, "AVX-512 Vector Length Orthogonality"],
 139     "AVX512DQ"          => [$f++, "AVX-512 Dword and Qword"],
 140     "AVX512BW"          => [$f++, "AVX-512 Byte and Word"],
 141     "AVX512IFMA"        => [$f++, "AVX-512 IFMA instructions"],
 142     "AVX512VBMI"        => [$f++, "AVX-512 VBMI instructions"],
 143     "AES"               => [$f++, "AES instructions"],
 144     "VAES"              => [$f++, "AES AVX instructions"],
 145     "VPCLMULQDQ"        => [$f++, "AVX Carryless Multiplication"],
 146     "GFNI"              => [$f++, "Galois Field instructions"],
 147     "AVX512VBMI2"       => [$f++, "AVX-512 VBMI2 instructions"],
 148     "AVX512VNNI"        => [$f++, "AVX-512 VNNI instructions"],
 149     "AVX512BITALG"      => [$f++, "AVX-512 Bit Algorithm instructions"],
 150     "AVX512VPOPCNTDQ"   => [$f++, "AVX-512 VPOPCNTD/VPOPCNTQ"],
 151     "AVX5124FMAPS"      => [$f++, "AVX-512 4-iteration multiply-add"],
 152     "AVX5124VNNIW"      => [$f++, "AVX-512 4-iteration dot product"],
 153     "SGX"               => [$f++, "Intel Software Guard Extensions (SGX)"],
 154
 155     # Put these last
 156     "OBSOLETE"          => [$f++, "Instruction removed from architecture"],
 157     "VEX"               => [$f++, "VEX or XOP encoded instruction"],
 158     "EVEX"              => [$f++, "EVEX encoded instruction"],
 159
 160     #
 161     # dword bound - cpu type flags
 162     #
 163     # The CYRIX and AMD flags should have the highest bit values; the
 164     # disassembler selection algorithm depends on it.
 165     #
 166     "8086"              => [${dword_align(\$f)}++, "8086"],
 167     "186"               => [$f++, "186+"],
 168     "286"               => [$f++, "286+"],
 169     "386"               => [$f++, "386+"],
 170     "486"               => [$f++, "486+"],
 171     "PENT"              => [$f++, "Pentium"],
 172     "P6"                => [$f++, "P6"],
 173     "KATMAI"            => [$f++, "Katmai"],
 174     "WILLAMETTE"        => [$f++, "Willamette"],
 175     "PRESCOTT"          => [$f++, "Prescott"],
 176     "X86_64"            => [$f++, "x86-64 (long or legacy mode)"],
 177     "NEHALEM"           => [$f++, "Nehalem"],
 178     "WESTMERE"          => [$f++, "Westmere"],
 179     "SANDYBRIDGE"       => [$f++, "Sandy Bridge"],
 180     "FUTURE"            => [$f++, "Future processor (not yet disclosed)"],
 181     "IA64"              => [$f++, "IA64 (in x86 mode)"],
 182
 183     # Put these last
 184     "CYRIX"             => [$f++, "Cyrix-specific"],
 185     "AMD"               => [$f++, "AMD-specific"],
 186 );
 187
 188 my %insns_flag_hash = ();
 189 my @insns_flag_values = ();
 190 my $iflag_words;
 191
 192 sub get_flag_words() {
 193     my $max = -1;
 194
 195     foreach my $vp (values(%insns_flag_bit)) {
 196         if ($vp->[0] > $max) {
 197             $max = $vp->[0];
 198         }
 199     }
 200
 201     return int($max/32)+1;
 202 }
 203
 204 sub insns_flag_index(@) {
 205     return undef if $_[0] eq "ignore";
 206
 207     my @prekey = sort(@_);
 208     my $key = join("", @prekey);
 209
 210     if (not defined($insns_flag_hash{$key})) {
 211         my @newkey = (0) x $iflag_words;
 212
 213         for my $i (@prekey) {
 214             die "No key for $i\n" if not defined($insns_flag_bit{$i});
 215             $newkey[$insns_flag_bit{$i}[0]/32] |=
 216                 (1 << ($insns_flag_bit{$i}[0] % 32));
 217         }
 218
 219         my $str = join(',', map { sprintf("UINT32_C(0x%08x)",$_) } @newkey);
 220
 221         push @insns_flag_values, $str;
 222         $insns_flag_hash{$key} = $#insns_flag_values;
 223     }
 224
 225     return $insns_flag_hash{$key};
 226 }
 227
 228 sub write_iflaggen_h() {
 229     print STDERR "Writing $oname...\n";
 230
 231     open(N, '>', $oname) or die "$0: $!\n";
 232
 233     print N "/* This file is auto-generated. Don't edit. */\n";
 234     print N "#ifndef NASM_IFLAGGEN_H\n";
 235     print N "#define NASM_IFLAGGEN_H 1\n\n";
 236
 237     my @flagnames = keys(%insns_flag_bit);
 238     @flagnames = sort {
 239         $insns_flag_bit{$a}->[0] <=> $insns_flag_bit{$b}->[0]
 240     } @flagnames;
 241     my $next = 0;
 242     foreach my $key (@flagnames) {
 243         my $v = $insns_flag_bit{$key};
 244         if ($v->[0] > $next) {
 245             printf N "%-31s /* %-64s */\n", '',
 246                 ($next != $v->[0]-1) ?
 247                 sprintf("%d...%d unused", $next, $v->[0]-1) :
 248                 sprintf("%d unused", $next);
 249         }
 250         print N sprintf("#define IF_%-16s %3d /* %-64s */\n",
 251                         $key, $v->[0], $v->[1]);
 252         $next = $v->[0] + 1;
 253     }
 254
 255     print N "\n";
 256     printf N "#define IF_FIELD_COUNT %d\n", $iflag_words;
 257     print N "typedef struct {\n";
 258     print N "    uint32_t field[IF_FIELD_COUNT];\n";
 259     print N "} iflag_t;\n";
 260
 261     print N "\n";
 262     printf N "extern const iflag_t insns_flags[%d];\n\n",
 263         $#insns_flag_values + 1;
 264
 265     print N "#endif /* NASM_IFLAGGEN_H */\n";
 266     close N;
 267 }
 268
 269 sub write_iflag_c() {
 270     print STDERR "Writing $oname...\n";
 271
 272     open(N, '>', $oname) or die "$0: $!\n";
 273
 274     print N "/* This file is auto-generated. Don't edit. */\n";
 275     print N "#include \"iflag.h\"\n\n";
 276     print N "/* Global flags referenced from instruction templates */\n";
 277     printf N "const iflag_t insns_flags[%d] = {\n",
 278         $#insns_flag_values + 1;
 279     foreach my $i (0 .. $#insns_flag_values) {
 280         print N sprintf("    /* %4d */ {{ %s }},\n", $i, $insns_flag_values[$i]);
 281     }
 282     print N "};\n\n";
 283     close N;
 284 }
 285
 286 $iflag_words = get_flag_words();
 287
 288 1;