12 #if defined(ARCH_X86) || defined(ARCH_X86_64)
17 #if defined (__NetBSD__) || defined(__OpenBSD__)
18 #include <sys/param.h>
19 #include <sys/sysctl.h>
20 #include <machine/cpu.h>
23 #if defined(__FreeBSD__) || defined(__DragonFly__)
24 #include <sys/types.h>
25 #include <sys/sysctl.h>
36 //#define X86_FXSR_MAGIC
37 /* Thanks to the FreeBSD project for some of this cpuid code, and
38 * help understanding how to use it. Thanks to the Mesa
39 * team for SSE support detection and more cpu detect code.
42 /* I believe this code works. However, it has only been used on a PII and PIII */
44 static void check_os_katmai_support( void );
47 // return TRUE if cpuid supported
48 static int has_cpuid()
52 // code from libavcodec:
53 __asm__
__volatile__ (
54 /* See if CPUID instruction is supported ... */
55 /* ... Get copies of EFLAGS into eax and ecx */
60 /* ... Toggle the ID bit in one copy and store */
61 /* to the EFLAGS reg */
62 "xor $0x200000, %0\n\t"
66 /* ... Get the (hopefully modified) EFLAGS */
79 do_cpuid(unsigned int ax
, unsigned int *p
)
84 : "=a" (p
[0]), "=b" (p
[1]), "=c" (p
[2]), "=d" (p
[3])
88 // code from libavcodec:
90 ("mov %%"REG_b
", %%"REG_S
"\n\t"
92 "xchg %%"REG_b
", %%"REG_S
93 : "=a" (p
[0]), "=S" (p
[1]),
94 "=c" (p
[2]), "=d" (p
[3])
100 void GetCpuCaps( CpuCaps
*caps
)
102 unsigned int regs
[4];
103 unsigned int regs2
[4];
105 memset(caps
, 0, sizeof(*caps
));
107 caps
->cl_size
=32; /* default */
109 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"CPUID not supported!??? (maybe an old 486?)\n");
112 do_cpuid(0x00000000, regs
); // get _max_ cpuid level and vendor name
113 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
114 (char*) (regs
+1),(char*) (regs
+3),(char*) (regs
+2), regs
[0]);
115 if (regs
[0]>=0x00000001)
120 do_cpuid(0x00000001, regs2
);
122 caps
->cpuType
=(regs2
[0] >> 8)&0xf;
123 if(caps
->cpuType
==0xf){
124 // use extended family (P4, IA64)
125 caps
->cpuType
=8+((regs2
[0]>>20)&255);
127 caps
->cpuStepping
=regs2
[0] & 0xf;
129 // general feature flags:
130 caps
->hasTSC
= (regs2
[3] & (1 << 8 )) >> 8; // 0x0000010
131 caps
->hasMMX
= (regs2
[3] & (1 << 23 )) >> 23; // 0x0800000
132 caps
->hasSSE
= (regs2
[3] & (1 << 25 )) >> 25; // 0x2000000
133 caps
->hasSSE2
= (regs2
[3] & (1 << 26 )) >> 26; // 0x4000000
134 caps
->hasMMX2
= caps
->hasSSE
; // SSE cpus supports mmxext too
135 cl_size
= ((regs2
[1] >> 8) & 0xFF)*8;
136 if(cl_size
) caps
->cl_size
= cl_size
;
138 tmpstr
=GetCpuFriendlyName(regs
, regs2
);
139 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: %s ",tmpstr
);
141 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"(Family: %d, Stepping: %d)\n",
142 caps
->cpuType
, caps
->cpuStepping
);
145 do_cpuid(0x80000000, regs
);
146 if (regs
[0]>=0x80000001) {
147 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"extended cpuid-level: %d\n",regs
[0]&0x7FFFFFFF);
148 do_cpuid(0x80000001, regs2
);
149 caps
->hasMMX
|= (regs2
[3] & (1 << 23 )) >> 23; // 0x0800000
150 caps
->hasMMX2
|= (regs2
[3] & (1 << 22 )) >> 22; // 0x400000
151 caps
->has3DNow
= (regs2
[3] & (1 << 31 )) >> 31; //0x80000000
152 caps
->has3DNowExt
= (regs2
[3] & (1 << 30 )) >> 30;
154 if(regs
[0]>=0x80000006)
156 do_cpuid(0x80000006, regs2
);
157 mp_msg(MSGT_CPUDETECT
,MSGL_V
,"extended cache-info: %d\n",regs2
[2]&0x7FFFFFFF);
158 caps
->cl_size
= regs2
[2] & 0xFF;
160 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"Detected cache-line size is %u bytes\n",caps
->cl_size
);
162 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
168 gCpuCaps
.has3DNowExt
);
171 /* FIXME: Does SSE2 need more OS support, too? */
172 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__)
174 check_os_katmai_support();
182 // caps->hasMMX2 = 0;
186 if(caps
->hasMMX
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"MMX supported but disabled\n");
190 if(caps
->hasMMX2
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"MMX2 supported but disabled\n");
194 if(caps
->hasSSE
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"SSE supported but disabled\n");
198 if(caps
->hasSSE2
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"SSE2 supported but disabled\n");
202 if(caps
->has3DNow
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"3DNow supported but disabled\n");
206 if(caps
->has3DNowExt
) mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"3DNowExt supported but disabled\n");
212 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
213 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
214 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
215 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
216 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
217 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
219 char *GetCpuFriendlyName(unsigned int regs
[], unsigned int regs2
[]){
220 #include "cputable.h" /* get cpuname and cpuvendors */
225 if (NULL
==(retname
=(char*)malloc(256))) {
226 mp_msg(MSGT_CPUDETECT
,MSGL_FATAL
,"Error: GetCpuFriendlyName() not enough memory\n");
230 sprintf(vendor
,"%.4s%.4s%.4s",(char*)(regs
+1),(char*)(regs
+3),(char*)(regs
+2));
232 for(i
=0; i
<MAX_VENDORS
; i
++){
233 if(!strcmp(cpuvendors
[i
].string
,vendor
)){
234 if(cpuname
[i
][CPUID_FAMILY
][CPUID_MODEL
]){
235 snprintf(retname
,255,"%s %s",cpuvendors
[i
].name
,cpuname
[i
][CPUID_FAMILY
][CPUID_MODEL
]);
237 snprintf(retname
,255,"unknown %s %d. Generation CPU",cpuvendors
[i
].name
,CPUID_FAMILY
);
238 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"unknown %s CPU:\n",cpuvendors
[i
].name
);
239 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Vendor: %s\n",cpuvendors
[i
].string
);
240 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Type: %d\n",CPUID_TYPE
);
241 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Family: %d (ext: %d)\n",CPUID_FAMILY
,CPUID_EXTFAMILY
);
242 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Model: %d (ext: %d)\n",CPUID_MODEL
,CPUID_EXTMODEL
);
243 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Stepping: %d\n",CPUID_STEPPING
);
244 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
,"Please send the above info along with the exact CPU name"
245 "to the MPlayer-Developers, so we can add it to the list!\n");
251 //printf("Detected CPU: %s\n", retname);
255 #undef CPUID_EXTFAMILY
256 #undef CPUID_EXTMODEL
260 #undef CPUID_STEPPING
263 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
264 static void sigill_handler_sse( int signal
, struct sigcontext sc
)
266 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGILL, " );
268 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
269 * instructions are 3 bytes long. We must increment the instruction
270 * pointer manually to avoid repeated execution of the offending
273 * If the SIGILL is caused by a divide-by-zero when unmasked
274 * exceptions aren't supported, the SIMD FPU status and control
275 * word will be restored at the end of the test, so we don't need
276 * to worry about doing it here. Besides, we may not be able to...
283 static void sigfpe_handler_sse( int signal
, struct sigcontext sc
)
285 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGFPE, " );
287 if ( sc
.fpstate
->magic
!= 0xffff ) {
288 /* Our signal context has the extended FPU state, so reset the
289 * divide-by-zero exception mask and clear the divide-by-zero
292 sc
.fpstate
->mxcsr
|= 0x00000200;
293 sc
.fpstate
->mxcsr
&= 0xfffffffb;
295 /* If we ever get here, we're completely hosed.
297 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "\n\n" );
298 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SSE enabling test failed badly!" );
301 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
304 LONG CALLBACK
win32_sig_handler_sse(EXCEPTION_POINTERS
* ep
)
306 if(ep
->ExceptionRecord
->ExceptionCode
==EXCEPTION_ILLEGAL_INSTRUCTION
){
307 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "SIGILL, " );
308 ep
->ContextRecord
->Eip
+=3;
310 return EXCEPTION_CONTINUE_EXECUTION
;
312 return EXCEPTION_CONTINUE_SEARCH
;
316 /* If we're running on a processor that can do SSE, let's see if we
317 * are allowed to or not. This will catch 2.4.0 or later kernels that
318 * haven't been configured for a Pentium III but are running on one,
319 * and RedHat patched 2.2 kernels that have broken exception handling
320 * support for user space apps that do SSE.
322 static void check_os_katmai_support( void )
327 #elif defined(__FreeBSD__) || defined(__DragonFly__)
329 size_t len
=sizeof(has_sse
);
331 ret
= sysctlbyname("hw.instruction_sse", &has_sse
, &len
, NULL
, 0);
335 #elif defined(__NetBSD__) || defined (__OpenBSD__)
336 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
337 int has_sse
, has_sse2
, ret
, mib
[2];
340 mib
[0] = CTL_MACHDEP
;
342 varlen
= sizeof(has_sse
);
344 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
345 ret
= sysctl(mib
, 2, &has_sse
, &varlen
, NULL
, 0);
346 if (ret
< 0 || !has_sse
) {
348 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
351 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes!\n" );
355 varlen
= sizeof(has_sse2
);
356 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE2... " );
357 ret
= sysctl(mib
, 2, &has_sse2
, &varlen
, NULL
, 0);
358 if (ret
< 0 || !has_sse2
) {
360 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
363 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes!\n" );
367 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "No OS support for SSE, disabling to be safe.\n" );
370 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil
;
371 if ( gCpuCaps
.hasSSE
) {
372 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
373 exc_fil
= SetUnhandledExceptionFilter(win32_sig_handler_sse
);
374 __asm
__volatile ("xorps %xmm0, %xmm0");
375 SetUnhandledExceptionFilter(exc_fil
);
376 if ( gCpuCaps
.hasSSE
) mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
377 else mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
379 #elif defined(__linux__)
380 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
381 struct sigaction saved_sigill
;
382 struct sigaction saved_sigfpe
;
384 /* Save the original signal handlers.
386 sigaction( SIGILL
, NULL
, &saved_sigill
);
387 sigaction( SIGFPE
, NULL
, &saved_sigfpe
);
389 signal( SIGILL
, (void (*)(int))sigill_handler_sse
);
390 signal( SIGFPE
, (void (*)(int))sigfpe_handler_sse
);
392 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
393 * supports the extended FPU save and restore required for SSE. If
394 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
395 * doesn't support Streaming SIMD Exceptions, even if the processor
398 if ( gCpuCaps
.hasSSE
) {
399 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE... " );
401 // __asm __volatile ("xorps %%xmm0, %%xmm0");
402 __asm
__volatile ("xorps %xmm0, %xmm0");
404 if ( gCpuCaps
.hasSSE
) {
405 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
407 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
411 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
412 * it supports unmasked SIMD FPU exceptions. If we unmask the
413 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
414 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
415 * as expected, we're okay but we need to clean up after it.
417 * Are we being too stringent in our requirement that the OS support
418 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
419 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
420 * doesn't even support them. We at least know the user-space SSE
421 * support is good in kernels that do support unmasked exceptions,
422 * and therefore to be safe I'm going to leave this test in here.
424 if ( gCpuCaps
.hasSSE
) {
425 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Testing OS support for SSE unmasked exceptions... " );
427 // test_os_katmai_exception_support();
429 if ( gCpuCaps
.hasSSE
) {
430 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "yes.\n" );
432 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "no!\n" );
436 /* Restore the original signal handlers.
438 sigaction( SIGILL
, &saved_sigill
, NULL
);
439 sigaction( SIGFPE
, &saved_sigfpe
, NULL
);
441 /* If we've gotten to here and the XMM CPUID bit is still set, we're
442 * safe to go ahead and hook out the SSE code throughout Mesa.
444 if ( gCpuCaps
.hasSSE
) {
445 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Tests of OS support for SSE passed.\n" );
447 mp_msg(MSGT_CPUDETECT
,MSGL_V
, "Tests of OS support for SSE failed!\n" );
450 /* We can't use POSIX signal handling to test the availability of
451 * SSE, so we disable it by default.
453 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "Cannot test OS support for SSE, disabling to be safe.\n" );
455 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
457 /* Do nothing on other platforms for now.
459 mp_msg(MSGT_CPUDETECT
,MSGL_WARN
, "Cannot test OS support for SSE, leaving disabled.\n" );
461 #endif /* __linux__ */
463 #else /* ARCH_X86 || ARCH_X86_64 */
466 #include <sys/sysctl.h>
471 static sigjmp_buf jmpbuf
;
472 static volatile sig_atomic_t canjump
= 0;
474 static void sigill_handler (int sig
)
477 signal (sig
, SIG_DFL
);
482 siglongjmp (jmpbuf
, 1);
486 void GetCpuCaps( CpuCaps
*caps
)
497 caps
->hasAltiVec
= 0;
501 rip-off from ffmpeg altivec detection code.
502 this code also appears on Apple's AltiVec pages.
505 int sels
[2] = {CTL_HW
, HW_VECTORUNIT
};
507 size_t len
= sizeof(has_vu
);
510 err
= sysctl(sels
, 2, &has_vu
, &len
, NULL
, 0);
514 caps
->hasAltiVec
= 1;
516 #else /* SYS_DARWIN */
517 /* no Darwin, do it the brute-force way */
518 /* this is borrowed from the libmpeg2 library */
520 signal (SIGILL
, sigill_handler
);
521 if (sigsetjmp (jmpbuf
, 1)) {
522 signal (SIGILL
, SIG_DFL
);
526 asm volatile ("mtspr 256, %0\n\t"
527 "vand %%v0, %%v0, %%v0"
531 signal (SIGILL
, SIG_DFL
);
532 caps
->hasAltiVec
= 1;
535 #endif /* SYS_DARWIN */
536 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"AltiVec %sfound\n", (caps
->hasAltiVec
? "" : "not "));
537 #endif /* HAVE_ALTIVEC */
540 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: Intel Itanium\n");
544 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: Sun Sparc\n");
548 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: ARM\n");
552 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: PowerPC\n");
556 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: Digital Alpha\n");
560 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: SGI MIPS\n");
564 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: Hewlett-Packard PA-RISC\n");
568 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: IBM S/390\n");
572 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
,"CPU: IBM S/390X\n");
576 mp_msg(MSGT_CPUDETECT
,MSGL_INFO
, "CPU: Digital VAX\n" );
579 #endif /* !ARCH_X86 */