cpudetect.c

   1 /*
   2  * This file is part of MPlayer.
   3  *
   4  * MPlayer is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * MPlayer is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with MPlayer; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include "config.h"
  20 #include "cpudetect.h"
  21 #include "mp_msg.h"
  22
  23 CpuCaps gCpuCaps;
  24
  25 #include <stdlib.h>
  26
  27 #if ARCH_X86
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31
  32 #if defined (__NetBSD__) || defined(__OpenBSD__)
  33 #include <sys/param.h>
  34 #include <sys/sysctl.h>
  35 #include <machine/cpu.h>
  36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  37 #include <sys/types.h>
  38 #include <sys/sysctl.h>
  39 #elif defined(__linux__)
  40 #include <signal.h>
  41 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  42 #include <windows.h>
  43 #elif defined(__AMIGAOS4__)
  44 #include <proto/exec.h>
  45 #endif
  46
  47 /* Thanks to the FreeBSD project for some of this cpuid code, and
  48  * help understanding how to use it.  Thanks to the Mesa
  49  * team for SSE support detection and more cpu detect code.
  50  */
  51
  52 #if CONFIG_RUNTIME_CPUDETECT
  53 /* I believe this code works.  However, it has only been used on a PII and PIII */
  54
  55 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
  56 static void sigill_handler_sse( int signal, struct sigcontext sc )
  57 {
  58    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
  59
  60    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
  61     * instructions are 3 bytes long.  We must increment the instruction
  62     * pointer manually to avoid repeated execution of the offending
  63     * instruction.
  64     *
  65     * If the SIGILL is caused by a divide-by-zero when unmasked
  66     * exceptions aren't supported, the SIMD FPU status and control
  67     * word will be restored at the end of the test, so we don't need
  68     * to worry about doing it here.  Besides, we may not be able to...
  69     */
  70    sc.eip += 3;
  71
  72    gCpuCaps.hasSSE=0;
  73 }
  74 #endif /* __linux__ && _POSIX_SOURCE */
  75
  76 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
  77 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
  78 {
  79     if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
  80         mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
  81         ep->ContextRecord->Eip +=3;
  82         gCpuCaps.hasSSE=0;
  83         return EXCEPTION_CONTINUE_EXECUTION;
  84     }
  85     return EXCEPTION_CONTINUE_SEARCH;
  86 }
  87 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
  88
  89 /* If we're running on a processor that can do SSE, let's see if we
  90  * are allowed to or not.  This will catch 2.4.0 or later kernels that
  91  * haven't been configured for a Pentium III but are running on one,
  92  * and RedHat patched 2.2 kernels that have broken exception handling
  93  * support for user space apps that do SSE.
  94  */
  95
  96 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
  97 #define SSE_SYSCTL_NAME "hw.instruction_sse"
  98 #elif defined(__APPLE__)
  99 #define SSE_SYSCTL_NAME "hw.optional.sse"
 100 #endif
 101
 102 static void check_os_katmai_support( void )
 103 {
 104 #if ARCH_X86_64
 105     gCpuCaps.hasSSE=1;
 106     gCpuCaps.hasSSE2=1;
 107 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 108     int has_sse=0, ret;
 109     size_t len=sizeof(has_sse);
 110
 111     ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 112     if (ret || !has_sse)
 113         gCpuCaps.hasSSE=0;
 114
 115 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 116 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 117     int has_sse, has_sse2, ret, mib[2];
 118     size_t varlen;
 119
 120     mib[0] = CTL_MACHDEP;
 121     mib[1] = CPU_SSE;
 122     varlen = sizeof(has_sse);
 123
 124     mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 125     ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 126     gCpuCaps.hasSSE = ret >= 0 && has_sse;
 127     mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 128
 129     mib[1] = CPU_SSE2;
 130     varlen = sizeof(has_sse2);
 131     mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 132     ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 133     gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 134     mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 135 #else
 136     gCpuCaps.hasSSE = 0;
 137     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 138 #endif
 139 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 140     LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 141     if ( gCpuCaps.hasSSE ) {
 142         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 143         exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 144         __asm__ volatile ("xorps %xmm0, %xmm0");
 145         SetUnhandledExceptionFilter(exc_fil);
 146         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 147     }
 148 #elif defined(__linux__)
 149 #if defined(_POSIX_SOURCE)
 150     struct sigaction saved_sigill;
 151
 152     /* Save the original signal handlers.
 153      */
 154     sigaction( SIGILL, NULL, &saved_sigill );
 155
 156     signal( SIGILL, (void (*)(int))sigill_handler_sse );
 157
 158     /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 159      * supports the extended FPU save and restore required for SSE.  If
 160      * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 161      * doesn't support Streaming SIMD Exceptions, even if the processor
 162      * does.
 163      */
 164     if ( gCpuCaps.hasSSE ) {
 165         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 166
 167 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 168         __asm__ volatile ("xorps %xmm0, %xmm0");
 169
 170         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 171     }
 172
 173     /* Restore the original signal handlers.
 174      */
 175     sigaction( SIGILL, &saved_sigill, NULL );
 176
 177     /* If we've gotten to here and the XMM CPUID bit is still set, we're
 178      * safe to go ahead and hook out the SSE code throughout Mesa.
 179      */
 180     mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 181 #else
 182     /* We can't use POSIX signal handling to test the availability of
 183      * SSE, so we disable it by default.
 184      */
 185     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 186     gCpuCaps.hasSSE=0;
 187 #endif /* _POSIX_SOURCE */
 188 #else
 189     /* Do nothing on other platforms for now.
 190      */
 191     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 192     gCpuCaps.hasSSE=0;
 193 #endif /* __linux__ */
 194 }
 195 #endif
 196
 197
 198 // return TRUE if cpuid supported
 199 static int has_cpuid(void)
 200 {
 201 // code from libavcodec:
 202 #if ARCH_X86_64
 203    return 1;
 204 #else
 205    long a, c;
 206    __asm__ volatile (
 207        /* See if CPUID instruction is supported ... */
 208        /* ... Get copies of EFLAGS into eax and ecx */
 209        "pushfl\n\t"
 210        "pop %0\n\t"
 211        "mov %0, %1\n\t"
 212
 213        /* ... Toggle the ID bit in one copy and store */
 214        /*     to the EFLAGS reg */
 215        "xor $0x200000, %0\n\t"
 216        "push %0\n\t"
 217        "popfl\n\t"
 218
 219        /* ... Get the (hopefully modified) EFLAGS */
 220        "pushfl\n\t"
 221        "pop %0\n\t"
 222        : "=a" (a), "=c" (c)
 223        :
 224        : "cc"
 225        );
 226
 227    return a != c;
 228 #endif
 229 }
 230
 231 void
 232 do_cpuid(unsigned int ax, unsigned int *p)
 233 {
 234 // code from libavcodec:
 235     __asm__ volatile
 236         ("mov %%"REG_b", %%"REG_S"\n\t"
 237          "cpuid\n\t"
 238          "xchg %%"REG_b", %%"REG_S
 239          : "=a" (p[0]), "=S" (p[1]),
 240            "=c" (p[2]), "=d" (p[3])
 241          : "0" (ax));
 242 }
 243
 244 void GetCpuCaps( CpuCaps *caps)
 245 {
 246     unsigned int regs[4];
 247     unsigned int regs2[4];
 248
 249     memset(caps, 0, sizeof(*caps));
 250     caps->isX86=1;
 251     caps->cl_size=32; /* default */
 252     if (!has_cpuid()) {
 253         mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 254         return;
 255     }
 256     do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 257     mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 258             (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 259     if (regs[0]>=0x00000001)
 260     {
 261         char *tmpstr, *ptmpstr;
 262         unsigned cl_size;
 263
 264         do_cpuid(0x00000001, regs2);
 265
 266         caps->cpuType=(regs2[0] >> 8)&0xf;
 267         caps->cpuModel=(regs2[0] >> 4)&0xf;
 268
 269 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 270 // System Instructions, Table 3-2: Effective family computation, page 120.
 271         if(caps->cpuType==0xf){
 272             // use extended family (P4, IA64, K8)
 273             caps->cpuType=0xf+((regs2[0]>>20)&255);
 274         }
 275         if(caps->cpuType==0xf || caps->cpuType==6)
 276             caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 277
 278         caps->cpuStepping=regs2[0] & 0xf;
 279
 280         // general feature flags:
 281         caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 282         caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 283         caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 284         caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 285         caps->hasSSE3 = (regs2[2] & 1);        // 0x0000001
 286         caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 287         caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 288         cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 289         if(cl_size) caps->cl_size = cl_size;
 290
 291         ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 292         while(*ptmpstr == ' ')    // strip leading spaces
 293             ptmpstr++;
 294         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 295         free(tmpstr);
 296         mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 297                caps->cpuType, caps->cpuModel, caps->cpuStepping);
 298
 299     }
 300     do_cpuid(0x80000000, regs);
 301     if (regs[0]>=0x80000001) {
 302         mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 303         do_cpuid(0x80000001, regs2);
 304         caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 305         caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 306         caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 307         caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 308         caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 309     }
 310     if(regs[0]>=0x80000006)
 311     {
 312         do_cpuid(0x80000006, regs2);
 313         mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 314         caps->cl_size  = regs2[2] & 0xFF;
 315     }
 316     mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 317 #if 0
 318     mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 319            gCpuCaps.hasMMX,
 320            gCpuCaps.hasMMX2,
 321            gCpuCaps.hasSSE,
 322            gCpuCaps.hasSSE2,
 323            gCpuCaps.has3DNow,
 324            gCpuCaps.has3DNowExt);
 325 #endif
 326
 327 #if CONFIG_RUNTIME_CPUDETECT
 328         /* FIXME: Does SSE2 need more OS support, too? */
 329         if (caps->hasSSE)
 330             check_os_katmai_support();
 331         if (!caps->hasSSE)
 332             caps->hasSSE2 = 0;
 333 //          caps->has3DNow=1;
 334 //          caps->hasMMX2 = 0;
 335 //          caps->hasMMX = 0;
 336
 337 #else
 338 #if !HAVE_MMX
 339         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 340         caps->hasMMX=0;
 341 #endif
 342 #if !HAVE_MMX2
 343         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 344         caps->hasMMX2=0;
 345 #endif
 346 #if !HAVE_SSE
 347         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 348         caps->hasSSE=0;
 349 #endif
 350 #if !HAVE_SSE2
 351         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 352         caps->hasSSE2=0;
 353 #endif
 354 #if !HAVE_AMD3DNOW
 355         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 356         caps->has3DNow=0;
 357 #endif
 358 #if !HAVE_AMD3DNOWEXT
 359         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 360         caps->has3DNowExt=0;
 361 #endif
 362 #endif  // CONFIG_RUNTIME_CPUDETECT
 363 }
 364
 365 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 366     char vendor[13];
 367     char *retname;
 368     int i;
 369
 370     if (NULL==(retname=malloc(256))) {
 371         mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 372         exit(1);
 373     }
 374     retname[0] = '\0';
 375
 376     sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 377
 378     do_cpuid(0x80000000,regs);
 379     if (regs[0] >= 0x80000004)
 380     {
 381         // CPU has built-in namestring
 382         for (i = 0x80000002; i <= 0x80000004; i++)
 383         {
 384             do_cpuid(i, regs);
 385             strncat(retname, (char*)regs, 16);
 386         }
 387     }
 388     return retname;
 389 }
 390
 391 #else /* ARCH_X86 */
 392
 393 #ifdef __APPLE__
 394 #include <sys/sysctl.h>
 395 #elif defined(__AMIGAOS4__)
 396 /* nothing */
 397 #else
 398 #include <signal.h>
 399 #include <setjmp.h>
 400
 401 static sigjmp_buf jmpbuf;
 402 static volatile sig_atomic_t canjump = 0;
 403
 404 static void sigill_handler (int sig)
 405 {
 406     if (!canjump) {
 407         signal (sig, SIG_DFL);
 408         raise (sig);
 409     }
 410
 411     canjump = 0;
 412     siglongjmp (jmpbuf, 1);
 413 }
 414 #endif /* __APPLE__ */
 415
 416 void GetCpuCaps( CpuCaps *caps)
 417 {
 418     caps->cpuType=0;
 419     caps->cpuModel=0;
 420     caps->cpuStepping=0;
 421     caps->hasMMX=0;
 422     caps->hasMMX2=0;
 423     caps->has3DNow=0;
 424     caps->has3DNowExt=0;
 425     caps->hasSSE=0;
 426     caps->hasSSE2=0;
 427     caps->hasSSE3=0;
 428     caps->hasSSSE3=0;
 429     caps->hasSSE4a=0;
 430     caps->isX86=0;
 431     caps->hasAltiVec = 0;
 432 #if HAVE_ALTIVEC
 433 #ifdef __APPLE__
 434 /*
 435   rip-off from ffmpeg altivec detection code.
 436   this code also appears on Apple's AltiVec pages.
 437  */
 438     {
 439         int sels[2] = {CTL_HW, HW_VECTORUNIT};
 440         int has_vu = 0;
 441         size_t len = sizeof(has_vu);
 442         int err;
 443
 444         err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 445
 446         if (err == 0)
 447             if (has_vu != 0)
 448                 caps->hasAltiVec = 1;
 449     }
 450 #elif defined(__AMIGAOS4__)
 451     ULONG result = 0;
 452
 453     GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 454     if (result == VECTORTYPE_ALTIVEC)
 455         caps->hasAltiVec = 1;
 456 #else
 457 /* no Darwin, do it the brute-force way */
 458 /* this is borrowed from the libmpeg2 library */
 459     {
 460         signal (SIGILL, sigill_handler);
 461         if (sigsetjmp (jmpbuf, 1)) {
 462             signal (SIGILL, SIG_DFL);
 463         } else {
 464             canjump = 1;
 465
 466         __asm__ volatile ("mtspr 256, %0\n\t"
 467                           "vand %%v0, %%v0, %%v0"
 468                           :
 469                           : "r" (-1));
 470
 471         signal (SIGILL, SIG_DFL);
 472         caps->hasAltiVec = 1;
 473         }
 474     }
 475 #endif /* __APPLE__ */
 476     mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 477 #endif /* HAVE_ALTIVEC */
 478
 479     if (ARCH_IA64)
 480         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 481
 482     if (ARCH_SPARC)
 483         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 484
 485     if (ARCH_ARM)
 486         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 487
 488     if (ARCH_PPC)
 489         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 490
 491     if (ARCH_ALPHA)
 492         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 493
 494     if (ARCH_MIPS)
 495         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n");
 496
 497     if (ARCH_PA_RISC)
 498         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 499
 500     if (ARCH_S390)
 501         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 502
 503     if (ARCH_S390X)
 504         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 505
 506     if (ARCH_VAX)
 507         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 508
 509     if (ARCH_XTENSA)
 510         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 511 }
 512 #endif /* !ARCH_X86 */