cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #ifdef ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #ifdef WIN32
  33 #include <windows.h>
  34 #endif
  35
  36 #ifdef __AMIGAOS4__
  37 #include <proto/exec.h>
  38 #endif
  39
  40 //#define X86_FXSR_MAGIC
  41 /* Thanks to the FreeBSD project for some of this cpuid code, and
  42  * help understanding how to use it.  Thanks to the Mesa
  43  * team for SSE support detection and more cpu detect code.
  44  */
  45
  46 /* I believe this code works.  However, it has only been used on a PII and PIII */
  47
  48 static void check_os_katmai_support( void );
  49
  50 #if 1
  51 // return TRUE if cpuid supported
  52 static int has_cpuid(void)
  53 {
  54         long a, c;
  55
  56 // code from libavcodec:
  57     __asm__ __volatile__ (
  58                           /* See if CPUID instruction is supported ... */
  59                           /* ... Get copies of EFLAGS into eax and ecx */
  60                           "pushf\n\t"
  61                           "pop %0\n\t"
  62                           "mov %0, %1\n\t"
  63
  64                           /* ... Toggle the ID bit in one copy and store */
  65                           /*     to the EFLAGS reg */
  66                           "xor $0x200000, %0\n\t"
  67                           "push %0\n\t"
  68                           "popf\n\t"
  69
  70                           /* ... Get the (hopefully modified) EFLAGS */
  71                           "pushf\n\t"
  72                           "pop %0\n\t"
  73                           : "=a" (a), "=c" (c)
  74                           :
  75                           : "cc"
  76                           );
  77
  78         return (a!=c);
  79 }
  80 #endif
  81
  82 static void
  83 do_cpuid(unsigned int ax, unsigned int *p)
  84 {
  85 #if 0
  86         __asm __volatile(
  87         "cpuid;"
  88         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  89         :  "0" (ax)
  90         );
  91 #else
  92 // code from libavcodec:
  93     __asm __volatile
  94         ("mov %%"REG_b", %%"REG_S"\n\t"
  95          "cpuid\n\t"
  96          "xchg %%"REG_b", %%"REG_S
  97          : "=a" (p[0]), "=S" (p[1]),
  98            "=c" (p[2]), "=d" (p[3])
  99          : "0" (ax));
 100 #endif
 101
 102 }
 103
 104 void GetCpuCaps( CpuCaps *caps)
 105 {
 106         unsigned int regs[4];
 107         unsigned int regs2[4];
 108
 109         memset(caps, 0, sizeof(*caps));
 110         caps->isX86=1;
 111         caps->cl_size=32; /* default */
 112         if (!has_cpuid()) {
 113             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 114             return;
 115         }
 116         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 117         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 118                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 119         if (regs[0]>=0x00000001)
 120         {
 121                 char *tmpstr, *ptmpstr;
 122                 unsigned cl_size;
 123
 124                 do_cpuid(0x00000001, regs2);
 125
 126                 caps->cpuType=(regs2[0] >> 8)&0xf;
 127                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 128
 129 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 130 // System Instructions, Table 3-2: Effective family computation, page 120.
 131                 if(caps->cpuType==0xf){
 132                     // use extended family (P4, IA64, K8)
 133                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 134                 }
 135                 if(caps->cpuType==0xf || caps->cpuType==6)
 136                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 137
 138                 caps->cpuStepping=regs2[0] & 0xf;
 139
 140                 // general feature flags:
 141                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 142                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 143                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 144                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 145                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 146                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 147                 if(cl_size) caps->cl_size = cl_size;
 148
 149                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 150                 while(*ptmpstr == ' ')        // strip leading spaces
 151                     ptmpstr++;
 152                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr);
 153                 free(tmpstr);
 154                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n",
 155                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 156
 157         }
 158         do_cpuid(0x80000000, regs);
 159         if (regs[0]>=0x80000001) {
 160                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 161                 do_cpuid(0x80000001, regs2);
 162                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 163                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 164                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 165                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 166         }
 167         if(regs[0]>=0x80000006)
 168         {
 169                 do_cpuid(0x80000006, regs2);
 170                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 171                 caps->cl_size  = regs2[2] & 0xFF;
 172         }
 173         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 174 #if 0
 175         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 176                 gCpuCaps.hasMMX,
 177                 gCpuCaps.hasMMX2,
 178                 gCpuCaps.hasSSE,
 179                 gCpuCaps.hasSSE2,
 180                 gCpuCaps.has3DNow,
 181                 gCpuCaps.has3DNowExt );
 182 #endif
 183
 184                 /* FIXME: Does SSE2 need more OS support, too? */
 185 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__)
 186                 if (caps->hasSSE)
 187                         check_os_katmai_support();
 188                 if (!caps->hasSSE)
 189                         caps->hasSSE2 = 0;
 190 #else
 191                 caps->hasSSE=0;
 192                 caps->hasSSE2 = 0;
 193 #endif
 194 //              caps->has3DNow=1;
 195 //              caps->hasMMX2 = 0;
 196 //              caps->hasMMX = 0;
 197
 198 #ifndef HAVE_MMX
 199         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 200         caps->hasMMX=0;
 201 #endif
 202 #ifndef HAVE_MMX2
 203         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 204         caps->hasMMX2=0;
 205 #endif
 206 #ifndef HAVE_SSE
 207         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 208         caps->hasSSE=0;
 209 #endif
 210 #ifndef HAVE_SSE2
 211         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 212         caps->hasSSE2=0;
 213 #endif
 214 #ifndef HAVE_3DNOW
 215         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 216         caps->has3DNow=0;
 217 #endif
 218 #ifndef HAVE_3DNOWEX
 219         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 220         caps->has3DNowExt=0;
 221 #endif
 222 }
 223
 224
 225 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 226 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 227 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 228 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 229 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 230 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 231
 232 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 233 #include "cputable.h" /* get cpuname and cpuvendors */
 234         char vendor[13];
 235         char *retname;
 236         int i;
 237
 238         if (NULL==(retname=malloc(256))) {
 239                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 240                 exit(1);
 241         }
 242
 243         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 244
 245         do_cpuid(0x80000000,regs);
 246         if (regs[0] >= 0x80000004)
 247         {
 248                 // CPU has built-in namestring
 249                 retname[0] = '\0';
 250                 for (i = 0x80000002; i <= 0x80000004; i++)
 251                 {
 252                         do_cpuid(i, regs);
 253                         strncat(retname, (char*)regs, 16);
 254                 }
 255                 return retname;
 256         }
 257
 258         for(i=0; i<MAX_VENDORS; i++){
 259                 if(!strcmp(cpuvendors[i].string,vendor)){
 260                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 261                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 262                         } else {
 263                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 264                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 265                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 266                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 267                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 268                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 269                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 270                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 271                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 272                         }
 273                 }
 274         }
 275         retname[255] = 0;
 276
 277         //printf("Detected CPU: %s\n", retname);
 278         return retname;
 279 }
 280
 281 #undef CPUID_EXTFAMILY
 282 #undef CPUID_EXTMODEL
 283 #undef CPUID_TYPE
 284 #undef CPUID_FAMILY
 285 #undef CPUID_MODEL
 286 #undef CPUID_STEPPING
 287
 288
 289 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 290 static void sigill_handler_sse( int signal, struct sigcontext sc )
 291 {
 292    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 293
 294    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 295     * instructions are 3 bytes long.  We must increment the instruction
 296     * pointer manually to avoid repeated execution of the offending
 297     * instruction.
 298     *
 299     * If the SIGILL is caused by a divide-by-zero when unmasked
 300     * exceptions aren't supported, the SIMD FPU status and control
 301     * word will be restored at the end of the test, so we don't need
 302     * to worry about doing it here.  Besides, we may not be able to...
 303     */
 304    sc.eip += 3;
 305
 306    gCpuCaps.hasSSE=0;
 307 }
 308
 309 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
 310 {
 311    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
 312
 313    if ( sc.fpstate->magic != 0xffff ) {
 314       /* Our signal context has the extended FPU state, so reset the
 315        * divide-by-zero exception mask and clear the divide-by-zero
 316        * exception bit.
 317        */
 318       sc.fpstate->mxcsr |= 0x00000200;
 319       sc.fpstate->mxcsr &= 0xfffffffb;
 320    } else {
 321       /* If we ever get here, we're completely hosed.
 322        */
 323       mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
 324       mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
 325    }
 326 }
 327 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 328
 329 #ifdef WIN32
 330 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 331 {
 332    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 333       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 334       ep->ContextRecord->Eip +=3;
 335       gCpuCaps.hasSSE=0;
 336           return EXCEPTION_CONTINUE_EXECUTION;
 337    }
 338    return EXCEPTION_CONTINUE_SEARCH;
 339 }
 340 #endif /* WIN32 */
 341
 342 /* If we're running on a processor that can do SSE, let's see if we
 343  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 344  * haven't been configured for a Pentium III but are running on one,
 345  * and RedHat patched 2.2 kernels that have broken exception handling
 346  * support for user space apps that do SSE.
 347  */
 348
 349 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 350 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 351 #elif defined(__APPLE__)
 352 #define SSE_SYSCTL_NAME "hw.optional.sse"
 353 #endif
 354
 355 static void check_os_katmai_support( void )
 356 {
 357 #ifdef ARCH_X86_64
 358    gCpuCaps.hasSSE=1;
 359    gCpuCaps.hasSSE2=1;
 360 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 361    int has_sse=0, ret;
 362    size_t len=sizeof(has_sse);
 363
 364    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 365    if (ret || !has_sse)
 366       gCpuCaps.hasSSE=0;
 367
 368 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 369 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 370    int has_sse, has_sse2, ret, mib[2];
 371    size_t varlen;
 372
 373    mib[0] = CTL_MACHDEP;
 374    mib[1] = CPU_SSE;
 375    varlen = sizeof(has_sse);
 376
 377    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 378    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 379    if (ret < 0 || !has_sse) {
 380       gCpuCaps.hasSSE=0;
 381       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 382    } else {
 383       gCpuCaps.hasSSE=1;
 384       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 385    }
 386
 387    mib[1] = CPU_SSE2;
 388    varlen = sizeof(has_sse2);
 389    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 390    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 391    if (ret < 0 || !has_sse2) {
 392       gCpuCaps.hasSSE2=0;
 393       mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 394    } else {
 395       gCpuCaps.hasSSE2=1;
 396       mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
 397    }
 398 #else
 399    gCpuCaps.hasSSE = 0;
 400    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 401 #endif
 402 #elif defined(WIN32)
 403    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 404    if ( gCpuCaps.hasSSE ) {
 405       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 406       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 407       __asm __volatile ("xorps %xmm0, %xmm0");
 408       SetUnhandledExceptionFilter(exc_fil);
 409       if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 410       else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 411    }
 412 #elif defined(__linux__)
 413 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
 414    struct sigaction saved_sigill;
 415    struct sigaction saved_sigfpe;
 416
 417    /* Save the original signal handlers.
 418     */
 419    sigaction( SIGILL, NULL, &saved_sigill );
 420    sigaction( SIGFPE, NULL, &saved_sigfpe );
 421
 422    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 423    signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
 424
 425    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 426     * supports the extended FPU save and restore required for SSE.  If
 427     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 428     * doesn't support Streaming SIMD Exceptions, even if the processor
 429     * does.
 430     */
 431    if ( gCpuCaps.hasSSE ) {
 432       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 433
 434 //      __asm __volatile ("xorps %%xmm0, %%xmm0");
 435       __asm __volatile ("xorps %xmm0, %xmm0");
 436
 437       if ( gCpuCaps.hasSSE ) {
 438          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 439       } else {
 440          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 441       }
 442    }
 443
 444    /* Emulate test for OSXMMEXCPT in CR4.  The OS will set this bit if
 445     * it supports unmasked SIMD FPU exceptions.  If we unmask the
 446     * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
 447     * doesn't support unmasked SIMD FPU exceptions.  If we get a SIGFPE
 448     * as expected, we're okay but we need to clean up after it.
 449     *
 450     * Are we being too stringent in our requirement that the OS support
 451     * unmasked exceptions?  Certain RedHat 2.2 kernels enable SSE by
 452     * setting CR4.OSFXSR but don't support unmasked exceptions.  Win98
 453     * doesn't even support them.  We at least know the user-space SSE
 454     * support is good in kernels that do support unmasked exceptions,
 455     * and therefore to be safe I'm going to leave this test in here.
 456     */
 457    if ( gCpuCaps.hasSSE ) {
 458       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
 459
 460 //      test_os_katmai_exception_support();
 461
 462       if ( gCpuCaps.hasSSE ) {
 463          mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
 464       } else {
 465          mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
 466       }
 467    }
 468
 469    /* Restore the original signal handlers.
 470     */
 471    sigaction( SIGILL, &saved_sigill, NULL );
 472    sigaction( SIGFPE, &saved_sigfpe, NULL );
 473
 474    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 475     * safe to go ahead and hook out the SSE code throughout Mesa.
 476     */
 477    if ( gCpuCaps.hasSSE ) {
 478       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
 479    } else {
 480       mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
 481    }
 482 #else
 483    /* We can't use POSIX signal handling to test the availability of
 484     * SSE, so we disable it by default.
 485     */
 486    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 487    gCpuCaps.hasSSE=0;
 488 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
 489 #else
 490    /* Do nothing on other platforms for now.
 491     */
 492    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 493    gCpuCaps.hasSSE=0;
 494 #endif /* __linux__ */
 495 }
 496 #else /* ARCH_X86 */
 497
 498 #ifdef SYS_DARWIN
 499 #include <sys/sysctl.h>
 500 #else
 501 #ifndef __AMIGAOS4__
 502 #include <signal.h>
 503 #include <setjmp.h>
 504
 505 static sigjmp_buf jmpbuf;
 506 static volatile sig_atomic_t canjump = 0;
 507
 508 static void sigill_handler (int sig)
 509 {
 510     if (!canjump) {
 511         signal (sig, SIG_DFL);
 512         raise (sig);
 513     }
 514
 515     canjump = 0;
 516     siglongjmp (jmpbuf, 1);
 517 }
 518 #endif //__AMIGAOS4__
 519 #endif
 520
 521 void GetCpuCaps( CpuCaps *caps)
 522 {
 523         caps->cpuType=0;
 524         caps->cpuModel=0;
 525         caps->cpuStepping=0;
 526         caps->hasMMX=0;
 527         caps->hasMMX2=0;
 528         caps->has3DNow=0;
 529         caps->has3DNowExt=0;
 530         caps->hasSSE=0;
 531         caps->hasSSE2=0;
 532         caps->isX86=0;
 533         caps->hasAltiVec = 0;
 534 #ifdef HAVE_ALTIVEC
 535 #ifdef SYS_DARWIN
 536 /*
 537   rip-off from ffmpeg altivec detection code.
 538   this code also appears on Apple's AltiVec pages.
 539  */
 540         {
 541                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 542                 int has_vu = 0;
 543                 size_t len = sizeof(has_vu);
 544                 int err;
 545
 546                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 547
 548                 if (err == 0)
 549                         if (has_vu != 0)
 550                                 caps->hasAltiVec = 1;
 551         }
 552 #else /* SYS_DARWIN */
 553 #ifdef __AMIGAOS4__
 554         ULONG result = 0;
 555
 556         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 557         if (result == VECTORTYPE_ALTIVEC)
 558                 caps->hasAltiVec = 1;
 559 #else
 560 /* no Darwin, do it the brute-force way */
 561 /* this is borrowed from the libmpeg2 library */
 562         {
 563           signal (SIGILL, sigill_handler);
 564           if (sigsetjmp (jmpbuf, 1)) {
 565             signal (SIGILL, SIG_DFL);
 566           } else {
 567             canjump = 1;
 568
 569             asm volatile ("mtspr 256, %0\n\t"
 570                           "vand %%v0, %%v0, %%v0"
 571                           :
 572                           : "r" (-1));
 573
 574             signal (SIGILL, SIG_DFL);
 575             caps->hasAltiVec = 1;
 576           }
 577         }
 578 #endif //__AMIGAOS4__
 579 #endif /* SYS_DARWIN */
 580         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 581 #endif /* HAVE_ALTIVEC */
 582
 583 #ifdef ARCH_IA64
 584         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
 585 #endif
 586
 587 #ifdef ARCH_SPARC
 588         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
 589 #endif
 590
 591 #ifdef ARCH_ARMV4L
 592         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
 593 #endif
 594
 595 #ifdef ARCH_POWERPC
 596         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
 597 #endif
 598
 599 #ifdef ARCH_ALPHA
 600         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
 601 #endif
 602
 603 #ifdef ARCH_SGI_MIPS
 604         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
 605 #endif
 606
 607 #ifdef ARCH_PA_RISC
 608         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
 609 #endif
 610
 611 #ifdef ARCH_S390
 612         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
 613 #endif
 614
 615 #ifdef ARCH_S390X
 616         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
 617 #endif
 618
 619 #ifdef ARCH_VAX
 620         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
 621 #endif
 622 }
 623 #endif /* !ARCH_X86 */