cpudetect.c

   1 #include "config.h"
   2 #include "cpudetect.h"
   3 #include "mp_msg.h"
   4
   5 CpuCaps gCpuCaps;
   6
   7 #ifdef HAVE_MALLOC_H
   8 #include <malloc.h>
   9 #endif
  10 #include <stdlib.h>
  11
  12 #ifdef ARCH_X86
  13
  14 #include <stdio.h>
  15 #include <string.h>
  16
  17 #if defined (__NetBSD__) || defined(__OpenBSD__)
  18 #include <sys/param.h>
  19 #include <sys/sysctl.h>
  20 #include <machine/cpu.h>
  21 #endif
  22
  23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  24 #include <sys/types.h>
  25 #include <sys/sysctl.h>
  26 #endif
  27
  28 #ifdef __linux__
  29 #include <signal.h>
  30 #endif
  31
  32 #if defined(__MINGW32__) || defined(__CYGWIN__)
  33 #include <windows.h>
  34 #endif
  35
  36 #ifdef __OS2__
  37 #define INCL_DOS
  38 #include <os2.h>
  39 #endif
  40
  41 #ifdef __AMIGAOS4__
  42 #include <proto/exec.h>
  43 #endif
  44
  45 /* Thanks to the FreeBSD project for some of this cpuid code, and
  46  * help understanding how to use it.  Thanks to the Mesa
  47  * team for SSE support detection and more cpu detect code.
  48  */
  49
  50 /* I believe this code works.  However, it has only been used on a PII and PIII */
  51
  52 static void check_os_katmai_support( void );
  53
  54 // return TRUE if cpuid supported
  55 static int has_cpuid(void)
  56 {
  57         long a, c;
  58
  59 // code from libavcodec:
  60 #ifdef ARCH_X86_64
  61 #define PUSHF "pushfq\n\t"
  62 #define POPF "popfq\n\t"
  63 #else
  64 #define PUSHF "pushfl\n\t"
  65 #define POPF "popfl\n\t"
  66 #endif
  67     __asm__ volatile (
  68                           /* See if CPUID instruction is supported ... */
  69                           /* ... Get copies of EFLAGS into eax and ecx */
  70                           PUSHF
  71                           "pop %0\n\t"
  72                           "mov %0, %1\n\t"
  73
  74                           /* ... Toggle the ID bit in one copy and store */
  75                           /*     to the EFLAGS reg */
  76                           "xor $0x200000, %0\n\t"
  77                           "push %0\n\t"
  78                           POPF
  79
  80                           /* ... Get the (hopefully modified) EFLAGS */
  81                           PUSHF
  82                           "pop %0\n\t"
  83                           : "=a" (a), "=c" (c)
  84                           :
  85                           : "cc"
  86                           );
  87 #undef PUSHF
  88 #undef POPF
  89
  90         return a != c;
  91 }
  92
  93 static void
  94 do_cpuid(unsigned int ax, unsigned int *p)
  95 {
  96 #if 0
  97         __asm__ volatile(
  98         "cpuid;"
  99         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
 100         :  "0" (ax)
 101         );
 102 #else
 103 // code from libavcodec:
 104     __asm__ volatile
 105         ("mov %%"REG_b", %%"REG_S"\n\t"
 106          "cpuid\n\t"
 107          "xchg %%"REG_b", %%"REG_S
 108          : "=a" (p[0]), "=S" (p[1]),
 109            "=c" (p[2]), "=d" (p[3])
 110          : "0" (ax));
 111 #endif
 112
 113 }
 114
 115 void GetCpuCaps( CpuCaps *caps)
 116 {
 117         unsigned int regs[4];
 118         unsigned int regs2[4];
 119
 120         memset(caps, 0, sizeof(*caps));
 121         caps->isX86=1;
 122         caps->cl_size=32; /* default */
 123         if (!has_cpuid()) {
 124             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 125             return;
 126         }
 127         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 128         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 129                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 130         if (regs[0]>=0x00000001)
 131         {
 132                 char *tmpstr, *ptmpstr;
 133                 unsigned cl_size;
 134
 135                 do_cpuid(0x00000001, regs2);
 136
 137                 caps->cpuType=(regs2[0] >> 8)&0xf;
 138                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 139
 140 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 141 // System Instructions, Table 3-2: Effective family computation, page 120.
 142                 if(caps->cpuType==0xf){
 143                     // use extended family (P4, IA64, K8)
 144                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 145                 }
 146                 if(caps->cpuType==0xf || caps->cpuType==6)
 147                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 148
 149                 caps->cpuStepping=regs2[0] & 0xf;
 150
 151                 // general feature flags:
 152                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 153                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 154                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 155                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 156                 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 157                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 158                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 159                 if(cl_size) caps->cl_size = cl_size;
 160
 161                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 162                 while(*ptmpstr == ' ')        // strip leading spaces
 163                     ptmpstr++;
 164                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr);
 165                 free(tmpstr);
 166                 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n",
 167                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 168
 169         }
 170         do_cpuid(0x80000000, regs);
 171         if (regs[0]>=0x80000001) {
 172                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 173                 do_cpuid(0x80000001, regs2);
 174                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 175                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 176                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 177                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 178                 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 179         }
 180         if(regs[0]>=0x80000006)
 181         {
 182                 do_cpuid(0x80000006, regs2);
 183                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 184                 caps->cl_size  = regs2[2] & 0xFF;
 185         }
 186         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 187 #if 0
 188         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 189                 gCpuCaps.hasMMX,
 190                 gCpuCaps.hasMMX2,
 191                 gCpuCaps.hasSSE,
 192                 gCpuCaps.hasSSE2,
 193                 gCpuCaps.has3DNow,
 194                 gCpuCaps.has3DNowExt );
 195 #endif
 196
 197                 /* FIXME: Does SSE2 need more OS support, too? */
 198 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 199   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 200   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 201   || defined(__OS2__)
 202                 if (caps->hasSSE)
 203                         check_os_katmai_support();
 204                 if (!caps->hasSSE)
 205                         caps->hasSSE2 = 0;
 206 #else
 207                 caps->hasSSE=0;
 208                 caps->hasSSE2 = 0;
 209 #endif
 210 //              caps->has3DNow=1;
 211 //              caps->hasMMX2 = 0;
 212 //              caps->hasMMX = 0;
 213
 214 #ifndef RUNTIME_CPUDETECT
 215 #ifndef HAVE_MMX
 216         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 217         caps->hasMMX=0;
 218 #endif
 219 #ifndef HAVE_MMX2
 220         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 221         caps->hasMMX2=0;
 222 #endif
 223 #ifndef HAVE_SSE
 224         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 225         caps->hasSSE=0;
 226 #endif
 227 #ifndef HAVE_SSE2
 228         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 229         caps->hasSSE2=0;
 230 #endif
 231 #ifndef HAVE_3DNOW
 232         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 233         caps->has3DNow=0;
 234 #endif
 235 #ifndef HAVE_3DNOWEX
 236         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 237         caps->has3DNowExt=0;
 238 #endif
 239 #endif  // RUNTIME_CPUDETECT
 240 }
 241
 242
 243 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
 244 #define CPUID_EXTMODEL  ((regs2[0] >> 16)&0x0F) /* 19..16 */
 245 #define CPUID_TYPE              ((regs2[0] >> 12)&0x04) /* 13..12 */
 246 #define CPUID_FAMILY    ((regs2[0] >>  8)&0x0F) /* 11..08 */
 247 #define CPUID_MODEL             ((regs2[0] >>  4)&0x0F) /* 07..04 */
 248 #define CPUID_STEPPING  ((regs2[0] >>  0)&0x0F) /* 03..00 */
 249
 250 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 251 #include "cputable.h" /* get cpuname and cpuvendors */
 252         char vendor[13];
 253         char *retname;
 254         int i;
 255
 256         if (NULL==(retname=malloc(256))) {
 257                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 258                 exit(1);
 259         }
 260
 261         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 262
 263         do_cpuid(0x80000000,regs);
 264         if (regs[0] >= 0x80000004)
 265         {
 266                 // CPU has built-in namestring
 267                 retname[0] = '\0';
 268                 for (i = 0x80000002; i <= 0x80000004; i++)
 269                 {
 270                         do_cpuid(i, regs);
 271                         strncat(retname, (char*)regs, 16);
 272                 }
 273                 return retname;
 274         }
 275
 276         for(i=0; i<MAX_VENDORS; i++){
 277                 if(!strcmp(cpuvendors[i].string,vendor)){
 278                         if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
 279                                 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
 280                         } else {
 281                                 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
 282                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
 283                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor:   %s\n",cpuvendors[i].string);
 284                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type:     %d\n",CPUID_TYPE);
 285                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family:   %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
 286                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model:    %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
 287                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
 288                                 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
 289                                        "to the MPlayer-Developers, so we can add it to the list!\n");
 290                         }
 291                 }
 292         }
 293         retname[255] = 0;
 294
 295         //printf("Detected CPU: %s\n", retname);
 296         return retname;
 297 }
 298
 299 #undef CPUID_EXTFAMILY
 300 #undef CPUID_EXTMODEL
 301 #undef CPUID_TYPE
 302 #undef CPUID_FAMILY
 303 #undef CPUID_MODEL
 304 #undef CPUID_STEPPING
 305
 306
 307 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64)
 308 static void sigill_handler_sse( int signal, struct sigcontext sc )
 309 {
 310    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 311
 312    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 313     * instructions are 3 bytes long.  We must increment the instruction
 314     * pointer manually to avoid repeated execution of the offending
 315     * instruction.
 316     *
 317     * If the SIGILL is caused by a divide-by-zero when unmasked
 318     * exceptions aren't supported, the SIMD FPU status and control
 319     * word will be restored at the end of the test, so we don't need
 320     * to worry about doing it here.  Besides, we may not be able to...
 321     */
 322    sc.eip += 3;
 323
 324    gCpuCaps.hasSSE=0;
 325 }
 326 #endif /* __linux__ && _POSIX_SOURCE */
 327
 328 #if defined(__MINGW32__) || defined(__CYGWIN__)
 329 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 330 {
 331    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 332       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 333       ep->ContextRecord->Eip +=3;
 334       gCpuCaps.hasSSE=0;
 335           return EXCEPTION_CONTINUE_EXECUTION;
 336    }
 337    return EXCEPTION_CONTINUE_SEARCH;
 338 }
 339 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 340
 341 #ifdef __OS2__
 342 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 343                                    PEXCEPTIONREGISTRATIONRECORD p2,
 344                                    PCONTEXTRECORD               p3,
 345                                    PVOID                        p4 )
 346 {
 347    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 348       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 349
 350       p3->ctx_RegEip += 3;
 351       gCpuCaps.hasSSE = 0;
 352
 353       return XCPT_CONTINUE_EXECUTION;
 354    }
 355    return XCPT_CONTINUE_SEARCH;
 356 }
 357 #endif
 358
 359 /* If we're running on a processor that can do SSE, let's see if we
 360  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 361  * haven't been configured for a Pentium III but are running on one,
 362  * and RedHat patched 2.2 kernels that have broken exception handling
 363  * support for user space apps that do SSE.
 364  */
 365
 366 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 367 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 368 #elif defined(__APPLE__)
 369 #define SSE_SYSCTL_NAME "hw.optional.sse"
 370 #endif
 371
 372 static void check_os_katmai_support( void )
 373 {
 374 #ifdef ARCH_X86_64
 375    gCpuCaps.hasSSE=1;
 376    gCpuCaps.hasSSE2=1;
 377 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 378    int has_sse=0, ret;
 379    size_t len=sizeof(has_sse);
 380
 381    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 382    if (ret || !has_sse)
 383       gCpuCaps.hasSSE=0;
 384
 385 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 386 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 387    int has_sse, has_sse2, ret, mib[2];
 388    size_t varlen;
 389
 390    mib[0] = CTL_MACHDEP;
 391    mib[1] = CPU_SSE;
 392    varlen = sizeof(has_sse);
 393
 394    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 395    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 396    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 397    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 398
 399    mib[1] = CPU_SSE2;
 400    varlen = sizeof(has_sse2);
 401    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 402    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 403    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 404    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 405 #else
 406    gCpuCaps.hasSSE = 0;
 407    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 408 #endif
 409 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 410    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 411    if ( gCpuCaps.hasSSE ) {
 412       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 413       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 414       __asm__ volatile ("xorps %xmm0, %xmm0");
 415       SetUnhandledExceptionFilter(exc_fil);
 416       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 417    }
 418 #elif defined(__OS2__)
 419    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 420    if ( gCpuCaps.hasSSE ) {
 421       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 422       DosSetExceptionHandler( &RegRec );
 423       __asm__ volatile ("xorps %xmm0, %xmm0");
 424       DosUnsetExceptionHandler( &RegRec );
 425       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 426    }
 427 #elif defined(__linux__)
 428 #if defined(_POSIX_SOURCE)
 429    struct sigaction saved_sigill;
 430
 431    /* Save the original signal handlers.
 432     */
 433    sigaction( SIGILL, NULL, &saved_sigill );
 434
 435    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 436
 437    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 438     * supports the extended FPU save and restore required for SSE.  If
 439     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 440     * doesn't support Streaming SIMD Exceptions, even if the processor
 441     * does.
 442     */
 443    if ( gCpuCaps.hasSSE ) {
 444       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 445
 446 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 447       __asm__ volatile ("xorps %xmm0, %xmm0");
 448
 449       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 450    }
 451
 452    /* Restore the original signal handlers.
 453     */
 454    sigaction( SIGILL, &saved_sigill, NULL );
 455
 456    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 457     * safe to go ahead and hook out the SSE code throughout Mesa.
 458     */
 459    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 460 #else
 461    /* We can't use POSIX signal handling to test the availability of
 462     * SSE, so we disable it by default.
 463     */
 464    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 465    gCpuCaps.hasSSE=0;
 466 #endif /* _POSIX_SOURCE */
 467 #else
 468    /* Do nothing on other platforms for now.
 469     */
 470    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 471    gCpuCaps.hasSSE=0;
 472 #endif /* __linux__ */
 473 }
 474 #else /* ARCH_X86 */
 475
 476 #ifdef __APPLE__
 477 #include <sys/sysctl.h>
 478 #elif __AMIGAOS4__
 479 /* nothing */
 480 #else
 481 #include <signal.h>
 482 #include <setjmp.h>
 483
 484 static sigjmp_buf jmpbuf;
 485 static volatile sig_atomic_t canjump = 0;
 486
 487 static void sigill_handler (int sig)
 488 {
 489     if (!canjump) {
 490         signal (sig, SIG_DFL);
 491         raise (sig);
 492     }
 493
 494     canjump = 0;
 495     siglongjmp (jmpbuf, 1);
 496 }
 497 #endif /* __APPLE__ */
 498
 499 void GetCpuCaps( CpuCaps *caps)
 500 {
 501         caps->cpuType=0;
 502         caps->cpuModel=0;
 503         caps->cpuStepping=0;
 504         caps->hasMMX=0;
 505         caps->hasMMX2=0;
 506         caps->has3DNow=0;
 507         caps->has3DNowExt=0;
 508         caps->hasSSE=0;
 509         caps->hasSSE2=0;
 510         caps->hasSSSE3=0;
 511         caps->hasSSE4a=0;
 512         caps->isX86=0;
 513         caps->hasAltiVec = 0;
 514 #ifdef HAVE_ALTIVEC
 515 #ifdef __APPLE__
 516 /*
 517   rip-off from ffmpeg altivec detection code.
 518   this code also appears on Apple's AltiVec pages.
 519  */
 520         {
 521                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 522                 int has_vu = 0;
 523                 size_t len = sizeof(has_vu);
 524                 int err;
 525
 526                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 527
 528                 if (err == 0)
 529                         if (has_vu != 0)
 530                                 caps->hasAltiVec = 1;
 531         }
 532 #elif __AMIGAOS4__
 533         ULONG result = 0;
 534
 535         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 536         if (result == VECTORTYPE_ALTIVEC)
 537                 caps->hasAltiVec = 1;
 538 #else
 539 /* no Darwin, do it the brute-force way */
 540 /* this is borrowed from the libmpeg2 library */
 541         {
 542           signal (SIGILL, sigill_handler);
 543           if (sigsetjmp (jmpbuf, 1)) {
 544             signal (SIGILL, SIG_DFL);
 545           } else {
 546             canjump = 1;
 547
 548             __asm__ volatile ("mtspr 256, %0\n\t"
 549                           "vand %%v0, %%v0, %%v0"
 550                           :
 551                           : "r" (-1));
 552
 553             signal (SIGILL, SIG_DFL);
 554             caps->hasAltiVec = 1;
 555           }
 556         }
 557 #endif /* __APPLE__ */
 558         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 559 #endif /* HAVE_ALTIVEC */
 560
 561 #ifdef ARCH_IA64
 562         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n");
 563 #endif
 564
 565 #ifdef ARCH_SPARC
 566         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n");
 567 #endif
 568
 569 #ifdef ARCH_ARMV4L
 570         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n");
 571 #endif
 572
 573 #ifdef ARCH_PPC
 574         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n");
 575 #endif
 576
 577 #ifdef ARCH_ALPHA
 578         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n");
 579 #endif
 580
 581 #ifdef ARCH_SGI_MIPS
 582         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n");
 583 #endif
 584
 585 #ifdef ARCH_PA_RISC
 586         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n");
 587 #endif
 588
 589 #ifdef ARCH_S390
 590         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n");
 591 #endif
 592
 593 #ifdef ARCH_S390X
 594         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n");
 595 #endif
 596
 597 #ifdef ARCH_VAX
 598         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" );
 599 #endif
 600
 601 #ifdef ARCH_XTENSA
 602         mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" );
 603 #endif
 604 }
 605 #endif /* !ARCH_X86 */