cpudetect.c

   1 /*
   2  * This file is part of MPlayer.
   3  *
   4  * MPlayer is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * MPlayer is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with MPlayer; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include "config.h"
  20 #include "cpudetect.h"
  21 #include "mp_msg.h"
  22
  23 CpuCaps gCpuCaps;
  24
  25 #include <stdlib.h>
  26
  27 #if ARCH_X86
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31
  32 #if defined (__NetBSD__) || defined(__OpenBSD__)
  33 #include <sys/param.h>
  34 #include <sys/sysctl.h>
  35 #include <machine/cpu.h>
  36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  37 #include <sys/types.h>
  38 #include <sys/sysctl.h>
  39 #elif defined(__linux__)
  40 #include <signal.h>
  41 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  42 #include <windows.h>
  43 #elif defined(__OS2__)
  44 #define INCL_DOS
  45 #include <os2.h>
  46 #elif defined(__AMIGAOS4__)
  47 #include <proto/exec.h>
  48 #endif
  49
  50 /* Thanks to the FreeBSD project for some of this cpuid code, and
  51  * help understanding how to use it.  Thanks to the Mesa
  52  * team for SSE support detection and more cpu detect code.
  53  */
  54
  55 #if CONFIG_RUNTIME_CPUDETECT
  56 /* I believe this code works.  However, it has only been used on a PII and PIII */
  57
  58 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
  59 static void sigill_handler_sse( int signal, struct sigcontext sc )
  60 {
  61    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
  62
  63    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
  64     * instructions are 3 bytes long.  We must increment the instruction
  65     * pointer manually to avoid repeated execution of the offending
  66     * instruction.
  67     *
  68     * If the SIGILL is caused by a divide-by-zero when unmasked
  69     * exceptions aren't supported, the SIMD FPU status and control
  70     * word will be restored at the end of the test, so we don't need
  71     * to worry about doing it here.  Besides, we may not be able to...
  72     */
  73    sc.eip += 3;
  74
  75    gCpuCaps.hasSSE=0;
  76 }
  77 #endif /* __linux__ && _POSIX_SOURCE */
  78
  79 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
  80 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
  81 {
  82     if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
  83         mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
  84         ep->ContextRecord->Eip +=3;
  85         gCpuCaps.hasSSE=0;
  86         return EXCEPTION_CONTINUE_EXECUTION;
  87     }
  88     return EXCEPTION_CONTINUE_SEARCH;
  89 }
  90 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
  91
  92 #ifdef __OS2__
  93 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD       p1,
  94                                   PEXCEPTIONREGISTRATIONRECORD p2,
  95                                   PCONTEXTRECORD               p3,
  96                                   PVOID                        p4)
  97 {
  98     if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
  99         mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 100
 101         p3->ctx_RegEip += 3;
 102         gCpuCaps.hasSSE = 0;
 103
 104         return XCPT_CONTINUE_EXECUTION;
 105     }
 106     return XCPT_CONTINUE_SEARCH;
 107 }
 108 #endif
 109
 110 /* If we're running on a processor that can do SSE, let's see if we
 111  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 112  * haven't been configured for a Pentium III but are running on one,
 113  * and RedHat patched 2.2 kernels that have broken exception handling
 114  * support for user space apps that do SSE.
 115  */
 116
 117 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 118 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 119 #elif defined(__APPLE__)
 120 #define SSE_SYSCTL_NAME "hw.optional.sse"
 121 #endif
 122
 123 static void check_os_katmai_support( void )
 124 {
 125 #if ARCH_X86_64
 126     gCpuCaps.hasSSE=1;
 127     gCpuCaps.hasSSE2=1;
 128 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 129     int has_sse=0, ret;
 130     size_t len=sizeof(has_sse);
 131
 132     ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 133     if (ret || !has_sse)
 134         gCpuCaps.hasSSE=0;
 135
 136 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 137 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 138     int has_sse, has_sse2, ret, mib[2];
 139     size_t varlen;
 140
 141     mib[0] = CTL_MACHDEP;
 142     mib[1] = CPU_SSE;
 143     varlen = sizeof(has_sse);
 144
 145     mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 146     ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 147     gCpuCaps.hasSSE = ret >= 0 && has_sse;
 148     mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 149
 150     mib[1] = CPU_SSE2;
 151     varlen = sizeof(has_sse2);
 152     mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 153     ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 154     gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 155     mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 156 #else
 157     gCpuCaps.hasSSE = 0;
 158     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 159 #endif
 160 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 161     LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 162     if ( gCpuCaps.hasSSE ) {
 163         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 164         exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 165         __asm__ volatile ("xorps %xmm0, %xmm0");
 166         SetUnhandledExceptionFilter(exc_fil);
 167         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 168     }
 169 #elif defined(__OS2__)
 170     EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 171     if ( gCpuCaps.hasSSE ) {
 172         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 173         DosSetExceptionHandler( &RegRec );
 174         __asm__ volatile ("xorps %xmm0, %xmm0");
 175         DosUnsetExceptionHandler( &RegRec );
 176         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 177     }
 178 #elif defined(__linux__)
 179 #if defined(_POSIX_SOURCE)
 180     struct sigaction saved_sigill;
 181
 182     /* Save the original signal handlers.
 183      */
 184     sigaction( SIGILL, NULL, &saved_sigill );
 185
 186     signal( SIGILL, (void (*)(int))sigill_handler_sse );
 187
 188     /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 189      * supports the extended FPU save and restore required for SSE.  If
 190      * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 191      * doesn't support Streaming SIMD Exceptions, even if the processor
 192      * does.
 193      */
 194     if ( gCpuCaps.hasSSE ) {
 195         mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 196
 197 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 198         __asm__ volatile ("xorps %xmm0, %xmm0");
 199
 200         mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 201     }
 202
 203     /* Restore the original signal handlers.
 204      */
 205     sigaction( SIGILL, &saved_sigill, NULL );
 206
 207     /* If we've gotten to here and the XMM CPUID bit is still set, we're
 208      * safe to go ahead and hook out the SSE code throughout Mesa.
 209      */
 210     mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 211 #else
 212     /* We can't use POSIX signal handling to test the availability of
 213      * SSE, so we disable it by default.
 214      */
 215     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 216     gCpuCaps.hasSSE=0;
 217 #endif /* _POSIX_SOURCE */
 218 #else
 219     /* Do nothing on other platforms for now.
 220      */
 221     mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 222     gCpuCaps.hasSSE=0;
 223 #endif /* __linux__ */
 224 }
 225 #endif
 226
 227
 228 // return TRUE if cpuid supported
 229 static int has_cpuid(void)
 230 {
 231 // code from libavcodec:
 232 #if ARCH_X86_64
 233    return 1;
 234 #else
 235    long a, c;
 236    __asm__ volatile (
 237        /* See if CPUID instruction is supported ... */
 238        /* ... Get copies of EFLAGS into eax and ecx */
 239        "pushfl\n\t"
 240        "pop %0\n\t"
 241        "mov %0, %1\n\t"
 242
 243        /* ... Toggle the ID bit in one copy and store */
 244        /*     to the EFLAGS reg */
 245        "xor $0x200000, %0\n\t"
 246        "push %0\n\t"
 247        "popfl\n\t"
 248
 249        /* ... Get the (hopefully modified) EFLAGS */
 250        "pushfl\n\t"
 251        "pop %0\n\t"
 252        : "=a" (a), "=c" (c)
 253        :
 254        : "cc"
 255        );
 256
 257    return a != c;
 258 #endif
 259 }
 260
 261 void
 262 do_cpuid(unsigned int ax, unsigned int *p)
 263 {
 264 // code from libavcodec:
 265     __asm__ volatile
 266         ("mov %%"REG_b", %%"REG_S"\n\t"
 267          "cpuid\n\t"
 268          "xchg %%"REG_b", %%"REG_S
 269          : "=a" (p[0]), "=S" (p[1]),
 270            "=c" (p[2]), "=d" (p[3])
 271          : "0" (ax));
 272 }
 273
 274 void GetCpuCaps( CpuCaps *caps)
 275 {
 276     unsigned int regs[4];
 277     unsigned int regs2[4];
 278
 279     memset(caps, 0, sizeof(*caps));
 280     caps->isX86=1;
 281     caps->cl_size=32; /* default */
 282     if (!has_cpuid()) {
 283         mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 284         return;
 285     }
 286     do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 287     mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 288             (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 289     if (regs[0]>=0x00000001)
 290     {
 291         char *tmpstr, *ptmpstr;
 292         unsigned cl_size;
 293
 294         do_cpuid(0x00000001, regs2);
 295
 296         caps->cpuType=(regs2[0] >> 8)&0xf;
 297         caps->cpuModel=(regs2[0] >> 4)&0xf;
 298
 299 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 300 // System Instructions, Table 3-2: Effective family computation, page 120.
 301         if(caps->cpuType==0xf){
 302             // use extended family (P4, IA64, K8)
 303             caps->cpuType=0xf+((regs2[0]>>20)&255);
 304         }
 305         if(caps->cpuType==0xf || caps->cpuType==6)
 306             caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 307
 308         caps->cpuStepping=regs2[0] & 0xf;
 309
 310         // general feature flags:
 311         caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 312         caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 313         caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 314         caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 315         caps->hasSSE3 = (regs2[2] & 1);        // 0x0000001
 316         caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 317         caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 318         cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 319         if(cl_size) caps->cl_size = cl_size;
 320
 321         ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 322         while(*ptmpstr == ' ')    // strip leading spaces
 323             ptmpstr++;
 324         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 325         free(tmpstr);
 326         mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 327                caps->cpuType, caps->cpuModel, caps->cpuStepping);
 328
 329     }
 330     do_cpuid(0x80000000, regs);
 331     if (regs[0]>=0x80000001) {
 332         mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 333         do_cpuid(0x80000001, regs2);
 334         caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 335         caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 336         caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 337         caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 338         caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 339     }
 340     if(regs[0]>=0x80000006)
 341     {
 342         do_cpuid(0x80000006, regs2);
 343         mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 344         caps->cl_size  = regs2[2] & 0xFF;
 345     }
 346     mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 347 #if 0
 348     mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 349            gCpuCaps.hasMMX,
 350            gCpuCaps.hasMMX2,
 351            gCpuCaps.hasSSE,
 352            gCpuCaps.hasSSE2,
 353            gCpuCaps.has3DNow,
 354            gCpuCaps.has3DNowExt);
 355 #endif
 356
 357 #if CONFIG_RUNTIME_CPUDETECT
 358         /* FIXME: Does SSE2 need more OS support, too? */
 359         if (caps->hasSSE)
 360             check_os_katmai_support();
 361         if (!caps->hasSSE)
 362             caps->hasSSE2 = 0;
 363 //          caps->has3DNow=1;
 364 //          caps->hasMMX2 = 0;
 365 //          caps->hasMMX = 0;
 366
 367 #else
 368 #if !HAVE_MMX
 369         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 370         caps->hasMMX=0;
 371 #endif
 372 #if !HAVE_MMX2
 373         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 374         caps->hasMMX2=0;
 375 #endif
 376 #if !HAVE_SSE
 377         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 378         caps->hasSSE=0;
 379 #endif
 380 #if !HAVE_SSE2
 381         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 382         caps->hasSSE2=0;
 383 #endif
 384 #if !HAVE_AMD3DNOW
 385         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 386         caps->has3DNow=0;
 387 #endif
 388 #if !HAVE_AMD3DNOWEXT
 389         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 390         caps->has3DNowExt=0;
 391 #endif
 392 #endif  // CONFIG_RUNTIME_CPUDETECT
 393 }
 394
 395 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 396     char vendor[13];
 397     char *retname;
 398     int i;
 399
 400     if (NULL==(retname=malloc(256))) {
 401         mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 402         exit(1);
 403     }
 404     retname[0] = '\0';
 405
 406     sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 407
 408     do_cpuid(0x80000000,regs);
 409     if (regs[0] >= 0x80000004)
 410     {
 411         // CPU has built-in namestring
 412         for (i = 0x80000002; i <= 0x80000004; i++)
 413         {
 414             do_cpuid(i, regs);
 415             strncat(retname, (char*)regs, 16);
 416         }
 417     }
 418     return retname;
 419 }
 420
 421 #else /* ARCH_X86 */
 422
 423 #ifdef __APPLE__
 424 #include <sys/sysctl.h>
 425 #elif defined(__AMIGAOS4__)
 426 /* nothing */
 427 #else
 428 #include <signal.h>
 429 #include <setjmp.h>
 430
 431 static sigjmp_buf jmpbuf;
 432 static volatile sig_atomic_t canjump = 0;
 433
 434 static void sigill_handler (int sig)
 435 {
 436     if (!canjump) {
 437         signal (sig, SIG_DFL);
 438         raise (sig);
 439     }
 440
 441     canjump = 0;
 442     siglongjmp (jmpbuf, 1);
 443 }
 444 #endif /* __APPLE__ */
 445
 446 void GetCpuCaps( CpuCaps *caps)
 447 {
 448     caps->cpuType=0;
 449     caps->cpuModel=0;
 450     caps->cpuStepping=0;
 451     caps->hasMMX=0;
 452     caps->hasMMX2=0;
 453     caps->has3DNow=0;
 454     caps->has3DNowExt=0;
 455     caps->hasSSE=0;
 456     caps->hasSSE2=0;
 457     caps->hasSSE3=0;
 458     caps->hasSSSE3=0;
 459     caps->hasSSE4a=0;
 460     caps->isX86=0;
 461     caps->hasAltiVec = 0;
 462 #if HAVE_ALTIVEC
 463 #ifdef __APPLE__
 464 /*
 465   rip-off from ffmpeg altivec detection code.
 466   this code also appears on Apple's AltiVec pages.
 467  */
 468     {
 469         int sels[2] = {CTL_HW, HW_VECTORUNIT};
 470         int has_vu = 0;
 471         size_t len = sizeof(has_vu);
 472         int err;
 473
 474         err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 475
 476         if (err == 0)
 477             if (has_vu != 0)
 478                 caps->hasAltiVec = 1;
 479     }
 480 #elif defined(__AMIGAOS4__)
 481     ULONG result = 0;
 482
 483     GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 484     if (result == VECTORTYPE_ALTIVEC)
 485         caps->hasAltiVec = 1;
 486 #else
 487 /* no Darwin, do it the brute-force way */
 488 /* this is borrowed from the libmpeg2 library */
 489     {
 490         signal (SIGILL, sigill_handler);
 491         if (sigsetjmp (jmpbuf, 1)) {
 492             signal (SIGILL, SIG_DFL);
 493         } else {
 494             canjump = 1;
 495
 496         __asm__ volatile ("mtspr 256, %0\n\t"
 497                           "vand %%v0, %%v0, %%v0"
 498                           :
 499                           : "r" (-1));
 500
 501         signal (SIGILL, SIG_DFL);
 502         caps->hasAltiVec = 1;
 503         }
 504     }
 505 #endif /* __APPLE__ */
 506     mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 507 #endif /* HAVE_ALTIVEC */
 508
 509     if (ARCH_IA64)
 510         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 511
 512     if (ARCH_SPARC)
 513         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 514
 515     if (ARCH_ARM)
 516         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 517
 518     if (ARCH_PPC)
 519         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 520
 521     if (ARCH_ALPHA)
 522         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 523
 524     if (ARCH_MIPS)
 525         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n");
 526
 527     if (ARCH_PA_RISC)
 528         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 529
 530     if (ARCH_S390)
 531         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 532
 533     if (ARCH_S390X)
 534         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 535
 536     if (ARCH_VAX)
 537         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 538
 539     if (ARCH_XTENSA)
 540         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 541 }
 542 #endif /* !ARCH_X86 */