cpudetect.c

   1 /*
   2  * This file is part of MPlayer.
   3  *
   4  * MPlayer is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * MPlayer is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with MPlayer; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include "config.h"
  20 #include "cpudetect.h"
  21 #include "mp_msg.h"
  22
  23 CpuCaps gCpuCaps;
  24
  25 #include <stdlib.h>
  26
  27 #if ARCH_X86
  28
  29 #include <stdio.h>
  30 #include <string.h>
  31
  32 #if defined (__NetBSD__) || defined(__OpenBSD__)
  33 #include <sys/param.h>
  34 #include <sys/sysctl.h>
  35 #include <machine/cpu.h>
  36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
  37 #include <sys/types.h>
  38 #include <sys/sysctl.h>
  39 #elif defined(__linux__)
  40 #include <signal.h>
  41 #elif defined(__MINGW32__) || defined(__CYGWIN__)
  42 #include <windows.h>
  43 #elif defined(__OS2__)
  44 #define INCL_DOS
  45 #include <os2.h>
  46 #elif defined(__AMIGAOS4__)
  47 #include <proto/exec.h>
  48 #endif
  49
  50 /* Thanks to the FreeBSD project for some of this cpuid code, and
  51  * help understanding how to use it.  Thanks to the Mesa
  52  * team for SSE support detection and more cpu detect code.
  53  */
  54
  55 /* I believe this code works.  However, it has only been used on a PII and PIII */
  56
  57 static void check_os_katmai_support( void );
  58
  59 // return TRUE if cpuid supported
  60 static int has_cpuid(void)
  61 {
  62 // code from libavcodec:
  63 #if ARCH_X86_64
  64    return 1;
  65 #else
  66         long a, c;
  67     __asm__ volatile (
  68                           /* See if CPUID instruction is supported ... */
  69                           /* ... Get copies of EFLAGS into eax and ecx */
  70                           "pushfl\n\t"
  71                           "pop %0\n\t"
  72                           "mov %0, %1\n\t"
  73
  74                           /* ... Toggle the ID bit in one copy and store */
  75                           /*     to the EFLAGS reg */
  76                           "xor $0x200000, %0\n\t"
  77                           "push %0\n\t"
  78                           "popfl\n\t"
  79
  80                           /* ... Get the (hopefully modified) EFLAGS */
  81                           "pushfl\n\t"
  82                           "pop %0\n\t"
  83                           : "=a" (a), "=c" (c)
  84                           :
  85                           : "cc"
  86                           );
  87
  88         return a != c;
  89 #endif
  90 }
  91
  92 static void
  93 do_cpuid(unsigned int ax, unsigned int *p)
  94 {
  95 #if 0
  96         __asm__ volatile(
  97         "cpuid;"
  98         : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
  99         :  "0" (ax)
 100         );
 101 #else
 102 // code from libavcodec:
 103     __asm__ volatile
 104         ("mov %%"REG_b", %%"REG_S"\n\t"
 105          "cpuid\n\t"
 106          "xchg %%"REG_b", %%"REG_S
 107          : "=a" (p[0]), "=S" (p[1]),
 108            "=c" (p[2]), "=d" (p[3])
 109          : "0" (ax));
 110 #endif
 111
 112 }
 113
 114 void GetCpuCaps( CpuCaps *caps)
 115 {
 116         unsigned int regs[4];
 117         unsigned int regs2[4];
 118
 119         memset(caps, 0, sizeof(*caps));
 120         caps->isX86=1;
 121         caps->cl_size=32; /* default */
 122         if (!has_cpuid()) {
 123             mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
 124             return;
 125         }
 126         do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
 127         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s  max cpuid level: %d\n",
 128                         (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
 129         if (regs[0]>=0x00000001)
 130         {
 131                 char *tmpstr, *ptmpstr;
 132                 unsigned cl_size;
 133
 134                 do_cpuid(0x00000001, regs2);
 135
 136                 caps->cpuType=(regs2[0] >> 8)&0xf;
 137                 caps->cpuModel=(regs2[0] >> 4)&0xf;
 138
 139 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and
 140 // System Instructions, Table 3-2: Effective family computation, page 120.
 141                 if(caps->cpuType==0xf){
 142                     // use extended family (P4, IA64, K8)
 143                     caps->cpuType=0xf+((regs2[0]>>20)&255);
 144                 }
 145                 if(caps->cpuType==0xf || caps->cpuType==6)
 146                     caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4;
 147
 148                 caps->cpuStepping=regs2[0] & 0xf;
 149
 150                 // general feature flags:
 151                 caps->hasTSC  = (regs2[3] & (1 << 8  )) >>  8; // 0x0000010
 152                 caps->hasMMX  = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 153                 caps->hasSSE  = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
 154                 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
 155                 caps->hasSSE3 = (regs2[2] & 1);                // 0x0000001
 156                 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >>  9; // 0x0000200
 157                 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
 158                 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
 159                 if(cl_size) caps->cl_size = cl_size;
 160
 161                 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2);
 162                 while(*ptmpstr == ' ')        // strip leading spaces
 163                     ptmpstr++;
 164                 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr);
 165                 free(tmpstr);
 166                 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n",
 167                     caps->cpuType, caps->cpuModel, caps->cpuStepping);
 168
 169         }
 170         do_cpuid(0x80000000, regs);
 171         if (regs[0]>=0x80000001) {
 172                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
 173                 do_cpuid(0x80000001, regs2);
 174                 caps->hasMMX  |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
 175                 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
 176                 caps->has3DNow    = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
 177                 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
 178                 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >>  6; // 0x0000040
 179         }
 180         if(regs[0]>=0x80000006)
 181         {
 182                 do_cpuid(0x80000006, regs2);
 183                 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
 184                 caps->cl_size  = regs2[2] & 0xFF;
 185         }
 186         mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size);
 187 #if 0
 188         mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
 189                 gCpuCaps.hasMMX,
 190                 gCpuCaps.hasMMX2,
 191                 gCpuCaps.hasSSE,
 192                 gCpuCaps.hasSSE2,
 193                 gCpuCaps.has3DNow,
 194                 gCpuCaps.has3DNowExt );
 195 #endif
 196
 197                 /* FIXME: Does SSE2 need more OS support, too? */
 198 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \
 199   || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \
 200   || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \
 201   || defined(__OS2__)
 202                 if (caps->hasSSE)
 203                         check_os_katmai_support();
 204                 if (!caps->hasSSE)
 205                         caps->hasSSE2 = 0;
 206 #else
 207                 caps->hasSSE=0;
 208                 caps->hasSSE2 = 0;
 209 #endif
 210 //              caps->has3DNow=1;
 211 //              caps->hasMMX2 = 0;
 212 //              caps->hasMMX = 0;
 213
 214 #if !CONFIG_RUNTIME_CPUDETECT
 215 #if !HAVE_MMX
 216         if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
 217         caps->hasMMX=0;
 218 #endif
 219 #if !HAVE_MMX2
 220         if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
 221         caps->hasMMX2=0;
 222 #endif
 223 #if !HAVE_SSE
 224         if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
 225         caps->hasSSE=0;
 226 #endif
 227 #if !HAVE_SSE2
 228         if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
 229         caps->hasSSE2=0;
 230 #endif
 231 #if !HAVE_AMD3DNOW
 232         if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
 233         caps->has3DNow=0;
 234 #endif
 235 #if !HAVE_AMD3DNOWEXT
 236         if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
 237         caps->has3DNowExt=0;
 238 #endif
 239 #endif  // CONFIG_RUNTIME_CPUDETECT
 240 }
 241
 242 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
 243         char vendor[13];
 244         char *retname;
 245         int i;
 246
 247         if (NULL==(retname=malloc(256))) {
 248                 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
 249                 exit(1);
 250         }
 251         retname[0] = '\0';
 252
 253         sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
 254
 255         do_cpuid(0x80000000,regs);
 256         if (regs[0] >= 0x80000004)
 257         {
 258                 // CPU has built-in namestring
 259                 for (i = 0x80000002; i <= 0x80000004; i++)
 260                 {
 261                         do_cpuid(i, regs);
 262                         strncat(retname, (char*)regs, 16);
 263                 }
 264         }
 265         return retname;
 266 }
 267
 268 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64
 269 static void sigill_handler_sse( int signal, struct sigcontext sc )
 270 {
 271    mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 272
 273    /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
 274     * instructions are 3 bytes long.  We must increment the instruction
 275     * pointer manually to avoid repeated execution of the offending
 276     * instruction.
 277     *
 278     * If the SIGILL is caused by a divide-by-zero when unmasked
 279     * exceptions aren't supported, the SIMD FPU status and control
 280     * word will be restored at the end of the test, so we don't need
 281     * to worry about doing it here.  Besides, we may not be able to...
 282     */
 283    sc.eip += 3;
 284
 285    gCpuCaps.hasSSE=0;
 286 }
 287 #endif /* __linux__ && _POSIX_SOURCE */
 288
 289 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64
 290 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep)
 291 {
 292    if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){
 293       mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
 294       ep->ContextRecord->Eip +=3;
 295       gCpuCaps.hasSSE=0;
 296           return EXCEPTION_CONTINUE_EXECUTION;
 297    }
 298    return EXCEPTION_CONTINUE_SEARCH;
 299 }
 300 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */
 301
 302 #ifdef __OS2__
 303 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD       p1,
 304                                    PEXCEPTIONREGISTRATIONRECORD p2,
 305                                    PCONTEXTRECORD               p3,
 306                                    PVOID                        p4 )
 307 {
 308    if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){
 309       mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, ");
 310
 311       p3->ctx_RegEip += 3;
 312       gCpuCaps.hasSSE = 0;
 313
 314       return XCPT_CONTINUE_EXECUTION;
 315    }
 316    return XCPT_CONTINUE_SEARCH;
 317 }
 318 #endif
 319
 320 /* If we're running on a processor that can do SSE, let's see if we
 321  * are allowed to or not.  This will catch 2.4.0 or later kernels that
 322  * haven't been configured for a Pentium III but are running on one,
 323  * and RedHat patched 2.2 kernels that have broken exception handling
 324  * support for user space apps that do SSE.
 325  */
 326
 327 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__)
 328 #define SSE_SYSCTL_NAME "hw.instruction_sse"
 329 #elif defined(__APPLE__)
 330 #define SSE_SYSCTL_NAME "hw.optional.sse"
 331 #endif
 332
 333 static void check_os_katmai_support( void )
 334 {
 335 #if ARCH_X86_64
 336    gCpuCaps.hasSSE=1;
 337    gCpuCaps.hasSSE2=1;
 338 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__)
 339    int has_sse=0, ret;
 340    size_t len=sizeof(has_sse);
 341
 342    ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0);
 343    if (ret || !has_sse)
 344       gCpuCaps.hasSSE=0;
 345
 346 #elif defined(__NetBSD__) || defined (__OpenBSD__)
 347 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__)
 348    int has_sse, has_sse2, ret, mib[2];
 349    size_t varlen;
 350
 351    mib[0] = CTL_MACHDEP;
 352    mib[1] = CPU_SSE;
 353    varlen = sizeof(has_sse);
 354
 355    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 356    ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
 357    gCpuCaps.hasSSE = ret >= 0 && has_sse;
 358    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 359
 360    mib[1] = CPU_SSE2;
 361    varlen = sizeof(has_sse2);
 362    mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
 363    ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
 364    gCpuCaps.hasSSE2 = ret >= 0 && has_sse2;
 365    mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" );
 366 #else
 367    gCpuCaps.hasSSE = 0;
 368    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
 369 #endif
 370 #elif defined(__MINGW32__) || defined(__CYGWIN__)
 371    LPTOP_LEVEL_EXCEPTION_FILTER exc_fil;
 372    if ( gCpuCaps.hasSSE ) {
 373       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 374       exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse);
 375       __asm__ volatile ("xorps %xmm0, %xmm0");
 376       SetUnhandledExceptionFilter(exc_fil);
 377       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 378    }
 379 #elif defined(__OS2__)
 380    EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse };
 381    if ( gCpuCaps.hasSSE ) {
 382       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 383       DosSetExceptionHandler( &RegRec );
 384       __asm__ volatile ("xorps %xmm0, %xmm0");
 385       DosUnsetExceptionHandler( &RegRec );
 386       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 387    }
 388 #elif defined(__linux__)
 389 #if defined(_POSIX_SOURCE)
 390    struct sigaction saved_sigill;
 391
 392    /* Save the original signal handlers.
 393     */
 394    sigaction( SIGILL, NULL, &saved_sigill );
 395
 396    signal( SIGILL, (void (*)(int))sigill_handler_sse );
 397
 398    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
 399     * supports the extended FPU save and restore required for SSE.  If
 400     * we execute an SSE instruction on a PIII and get a SIGILL, the OS
 401     * doesn't support Streaming SIMD Exceptions, even if the processor
 402     * does.
 403     */
 404    if ( gCpuCaps.hasSSE ) {
 405       mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
 406
 407 //      __asm__ volatile ("xorps %%xmm0, %%xmm0");
 408       __asm__ volatile ("xorps %xmm0, %xmm0");
 409
 410       mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" );
 411    }
 412
 413    /* Restore the original signal handlers.
 414     */
 415    sigaction( SIGILL, &saved_sigill, NULL );
 416
 417    /* If we've gotten to here and the XMM CPUID bit is still set, we're
 418     * safe to go ahead and hook out the SSE code throughout Mesa.
 419     */
 420    mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" );
 421 #else
 422    /* We can't use POSIX signal handling to test the availability of
 423     * SSE, so we disable it by default.
 424     */
 425    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
 426    gCpuCaps.hasSSE=0;
 427 #endif /* _POSIX_SOURCE */
 428 #else
 429    /* Do nothing on other platforms for now.
 430     */
 431    mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
 432    gCpuCaps.hasSSE=0;
 433 #endif /* __linux__ */
 434 }
 435 #else /* ARCH_X86 */
 436
 437 #ifdef __APPLE__
 438 #include <sys/sysctl.h>
 439 #elif defined(__AMIGAOS4__)
 440 /* nothing */
 441 #else
 442 #include <signal.h>
 443 #include <setjmp.h>
 444
 445 static sigjmp_buf jmpbuf;
 446 static volatile sig_atomic_t canjump = 0;
 447
 448 static void sigill_handler (int sig)
 449 {
 450     if (!canjump) {
 451         signal (sig, SIG_DFL);
 452         raise (sig);
 453     }
 454
 455     canjump = 0;
 456     siglongjmp (jmpbuf, 1);
 457 }
 458 #endif /* __APPLE__ */
 459
 460 void GetCpuCaps( CpuCaps *caps)
 461 {
 462         caps->cpuType=0;
 463         caps->cpuModel=0;
 464         caps->cpuStepping=0;
 465         caps->hasMMX=0;
 466         caps->hasMMX2=0;
 467         caps->has3DNow=0;
 468         caps->has3DNowExt=0;
 469         caps->hasSSE=0;
 470         caps->hasSSE2=0;
 471         caps->hasSSE3=0;
 472         caps->hasSSSE3=0;
 473         caps->hasSSE4a=0;
 474         caps->isX86=0;
 475         caps->hasAltiVec = 0;
 476 #if HAVE_ALTIVEC
 477 #ifdef __APPLE__
 478 /*
 479   rip-off from ffmpeg altivec detection code.
 480   this code also appears on Apple's AltiVec pages.
 481  */
 482         {
 483                 int sels[2] = {CTL_HW, HW_VECTORUNIT};
 484                 int has_vu = 0;
 485                 size_t len = sizeof(has_vu);
 486                 int err;
 487
 488                 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
 489
 490                 if (err == 0)
 491                         if (has_vu != 0)
 492                                 caps->hasAltiVec = 1;
 493         }
 494 #elif defined(__AMIGAOS4__)
 495         ULONG result = 0;
 496
 497         GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE);
 498         if (result == VECTORTYPE_ALTIVEC)
 499                 caps->hasAltiVec = 1;
 500 #else
 501 /* no Darwin, do it the brute-force way */
 502 /* this is borrowed from the libmpeg2 library */
 503         {
 504           signal (SIGILL, sigill_handler);
 505           if (sigsetjmp (jmpbuf, 1)) {
 506             signal (SIGILL, SIG_DFL);
 507           } else {
 508             canjump = 1;
 509
 510             __asm__ volatile ("mtspr 256, %0\n\t"
 511                           "vand %%v0, %%v0, %%v0"
 512                           :
 513                           : "r" (-1));
 514
 515             signal (SIGILL, SIG_DFL);
 516             caps->hasAltiVec = 1;
 517           }
 518         }
 519 #endif /* __APPLE__ */
 520         mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
 521 #endif /* HAVE_ALTIVEC */
 522
 523 if (ARCH_IA64)
 524         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n");
 525
 526 if (ARCH_SPARC)
 527         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n");
 528
 529 if (ARCH_ARM)
 530         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n");
 531
 532 if (ARCH_PPC)
 533         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n");
 534
 535 if (ARCH_ALPHA)
 536         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n");
 537
 538 if (ARCH_SGI_MIPS)
 539         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: SGI MIPS\n");
 540
 541 if (ARCH_PA_RISC)
 542         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n");
 543
 544 if (ARCH_S390)
 545         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n");
 546
 547 if (ARCH_S390X)
 548         mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n");
 549
 550 if (ARCH_VAX)
 551         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" );
 552
 553 if (ARCH_XTENSA)
 554         mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" );
 555 }
 556 #endif /* !ARCH_X86 */