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AMSv2 SD: receive sd card command responses during initialisation instead of ignoring...
[maemo-rb.git] / firmware / target / arm / as3525 / sd-as3525v2.c
blob7aecf12e72c9f5d44057cdab2ea27b9fe0ee8591
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2006 Daniel Ankers
11 * Copyright © 2008-2009 Rafaël Carré
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
17 *
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
20 *
21 ****************************************************************************/
22
23 #include "config.h" /* for HAVE_MULTIVOLUME */
24 #include "fat.h"
25 #include "thread.h"
26 #include "gcc_extensions.h"
27 #include "led.h"
28 #include "sdmmc.h"
29 #include "system.h"
30 #include "kernel.h"
31 #include "cpu.h"
32 #include <stdio.h>
33 #include <stdlib.h>
34 #include <string.h>
35 #include "as3525v2.h"
36 #include "pl081.h" /* DMA controller */
37 #include "dma-target.h" /* DMA request lines */
38 #include "clock-target.h"
39 #include "panic.h"
40 #include "stdbool.h"
41 #include "ata_idle_notify.h"
42 #include "sd.h"
43 #include "usb.h"
44
45 #ifdef HAVE_HOTSWAP
46 #include "disk.h"
47 #endif
48
49 #if defined(SANSA_FUZEV2)
50 #include "backlight-target.h"
51 #endif
52
53 #include "lcd.h"
54 #include <stdarg.h>
55 #include "sysfont.h"
56
57 #define INTERNAL_AS3525 0 /* embedded SD card */
58 #define SD_SLOT_AS3525 1 /* SD slot if present */
59
60 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
61 #define AMS_OF_SIZE 0xf000
62
63 /* command flags */
64 #define MCI_NO_RESP (0<<0)
65 #define MCI_RESP (1<<0)
66 #define MCI_LONG_RESP (1<<1)
67 #define MCI_ACMD (1<<2)
68
69 /* controller registers */
70 #define SD_BASE 0xC6070000
71
72 #define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x))
73
74 #define MCI_CTRL SD_REG(0x00)
75
76 /* control bits */
77 #define CTRL_RESET (1<<0)
78 #define FIFO_RESET (1<<1)
79 #define DMA_RESET (1<<2)
80 #define INT_ENABLE (1<<4)
81 #define DMA_ENABLE (1<<5)
82 #define READ_WAIT (1<<6)
83 #define SEND_IRQ_RESP (1<<7)
84 #define ABRT_READ_DATA (1<<8)
85 #define SEND_CCSD (1<<9)
86 #define SEND_AS_CCSD (1<<10)
87 #define EN_OD_PULLUP (1<<24)
88
89
90 #define MCI_PWREN SD_REG(0x04) /* power enable */
91
92 #define PWR_CRD_0 (1<<0)
93 #define PWR_CRD_1 (1<<1)
94 #define PWR_CRD_2 (1<<2)
95 #define PWR_CRD_3 (1<<3)
96
97 #define MCI_CLKDIV SD_REG(0x08) /* clock divider */
98 /* CLK_DIV_0 : bits 7:0
99 * CLK_DIV_1 : bits 15:8
100 * CLK_DIV_2 : bits 23:16
101 * CLK_DIV_3 : bits 31:24
102 */
103
104 #define MCI_CLKSRC SD_REG(0x0C) /* clock source */
105 /* CLK_SRC_CRD0: bits 1:0
106 * CLK_SRC_CRD1: bits 3:2
107 * CLK_SRC_CRD2: bits 5:4
108 * CLK_SRC_CRD3: bits 7:6
109 */
110
111 #define MCI_CLKENA SD_REG(0x10) /* clock enable */
112
113 #define CCLK_ENA_CRD0 (1<<0)
114 #define CCLK_ENA_CRD1 (1<<1)
115 #define CCLK_ENA_CRD2 (1<<2)
116 #define CCLK_ENA_CRD3 (1<<3)
117 #define CCLK_LP_CRD0 (1<<16) /* LP --> Low Power Mode? */
118 #define CCLK_LP_CRD1 (1<<17)
119 #define CCLK_LP_CRD2 (1<<18)
120 #define CCLK_LP_CRD3 (1<<19)
121
122 #define MCI_TMOUT SD_REG(0x14) /* timeout */
123 /* response timeout bits 0:7
124 * data timeout bits 8:31
125 */
126
127 #define MCI_CTYPE SD_REG(0x18) /* card type */
128 /* 1 bit per card, set = wide bus */
129 #define WIDTH4_CRD0 (1<<0)
130 #define WIDTH4_CRD1 (1<<1)
131 #define WIDTH4_CRD2 (1<<2)
132 #define WIDTH4_CRD3 (1<<3)
133
134 #define MCI_BLKSIZ SD_REG(0x1C) /* block size bits 0:15*/
135 #define MCI_BYTCNT SD_REG(0x20) /* byte count bits 0:31*/
136 #define MCI_MASK SD_REG(0x24) /* interrupt mask */
137
138
139
140 #define MCI_ARGUMENT SD_REG(0x28)
141 #define MCI_COMMAND SD_REG(0x2C)
142
143 /* command bits (bits 5:0 are the command index) */
144 #define CMD_RESP_EXP_BIT (1<<6)
145 #define CMD_RESP_LENGTH_BIT (1<<7)
146 #define CMD_CHECK_CRC_BIT (1<<8)
147 #define CMD_DATA_EXP_BIT (1<<9)
148 #define CMD_RW_BIT (1<<10)
149 #define CMD_TRANSMODE_BIT (1<<11)
150 #define CMD_SENT_AUTO_STOP_BIT (1<<12)
151 #define CMD_WAIT_PRV_DAT_BIT (1<<13)
152 #define CMD_ABRT_CMD_BIT (1<<14)
153 #define CMD_SEND_INIT_BIT (1<<15)
154 #define CMD_CARD_NO(x) ((x)<<16) /* 5 bits wide */
155 #define CMD_SEND_CLK_ONLY (1<<21)
156 #define CMD_READ_CEATA (1<<22)
157 #define CMD_CCS_EXPECTED (1<<23)
158 #define CMD_DONE_BIT (1<<31)
159
160 #define TRANSFER_CMD (cmd == SD_READ_MULTIPLE_BLOCK || \
161 cmd == SD_WRITE_MULTIPLE_BLOCK)
162
163 #define MCI_RESP0 SD_REG(0x30)
164 #define MCI_RESP1 SD_REG(0x34)
165 #define MCI_RESP2 SD_REG(0x38)
166 #define MCI_RESP3 SD_REG(0x3C)
167
168 #define MCI_MASK_STATUS SD_REG(0x40) /* masked interrupt status */
169 #define MCI_RAW_STATUS SD_REG(0x44) /* raw interrupt status, also used as
170 * status clear */
171
172 /* interrupt bits */ /* C D E (Cmd) (Data) (End) */
173 #define MCI_INT_CRDDET (1<<0) /* card detect */
174 #define MCI_INT_RE (1<<1) /* x response error */
175 #define MCI_INT_CD (1<<2) /* x command done */
176 #define MCI_INT_DTO (1<<3) /* x data transfer over */
177 #define MCI_INT_TXDR (1<<4) /* tx fifo data request */
178 #define MCI_INT_RXDR (1<<5) /* rx fifo data request */
179 #define MCI_INT_RCRC (1<<6) /* x response crc error */
180 #define MCI_INT_DCRC (1<<7) /* x data crc error */
181 #define MCI_INT_RTO (1<<8) /* x response timeout */
182 #define MCI_INT_DRTO (1<<9) /* x data read timeout */
183 #define MCI_INT_HTO (1<<10) /* x data starv timeout */
184 #define MCI_INT_FRUN (1<<11) /* x fifo over/underrun */
185 #define MCI_INT_HLE (1<<12) /* x x hw locked while error */
186 #define MCI_INT_SBE (1<<13) /* x start bit error */
187 #define MCI_INT_ACD (1<<14) /* auto command done */
188 #define MCI_INT_EBE (1<<15) /* x end bit error */
189 #define MCI_INT_SDIO (0xf<<16)
190
191 /*
192 * STATUS register
193 * & 0xBA80 = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
194 * MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
195 * & 8 = MCI_INT_DTO
196 * & 0x428 = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
197 * & 0x418 = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
198 */
199
200 #define MCI_CMD_ERROR \
201 (MCI_INT_RE | \
202 MCI_INT_RCRC | \
203 MCI_INT_RTO | \
204 MCI_INT_HLE)
205
206 #define MCI_DATA_ERROR \
207 ( MCI_INT_DCRC | \
208 MCI_INT_DRTO | \
209 MCI_INT_HTO | \
210 MCI_INT_FRUN | \
211 MCI_INT_HLE | \
212 MCI_INT_SBE | \
213 MCI_INT_EBE)
214
215 #define MCI_STATUS SD_REG(0x48)
216
217 #define FIFO_RX_WM (1<<0)
218 #define FIFO_TX_WM (1<<1)
219 #define FIFO_EMPTY (1<<2)
220 #define FIFO_FULL (1<<3)
221 #define CMD_FSM_STATE_B0 (1<<4)
222 #define CMD_FSM_STATE_B1 (1<<5)
223 #define CMD_FSM_STATE_B2 (1<<6)
224 #define CMD_FSM_STATE_B3 (1<<7)
225 #define DATA_3_STAT (1<<8)
226 #define DATA_BUSY (1<<9)
227 #define DATA_STAT_MC_BUSY (1<<10)
228 #define RESP_IDX_B0 (1<<11)
229 #define RESP_IDX_B1 (1<<12)
230 #define RESP_IDX_B2 (1<<13)
231 #define RESP_IDX_B3 (1<<14)
232 #define RESP_IDX_B4 (1<<15)
233 #define RESP_IDX_B5 (1<<16)
234 #define FIFO_CNT_B00 (1<<17)
235 #define FIFO_CNT_B01 (1<<18)
236 #define FIFO_CNT_B02 (1<<19)
237 #define FIFO_CNT_B03 (1<<20)
238 #define FIFO_CNT_B04 (1<<21)
239 #define FIFO_CNT_B05 (1<<22)
240 #define FIFO_CNT_B06 (1<<23)
241 #define FIFO_CNT_B07 (1<<24)
242 #define FIFO_CNT_B08 (1<<25)
243 #define FIFO_CNT_B09 (1<<26)
244 #define FIFO_CNT_B10 (1<<27)
245 #define FIFO_CNT_B11 (1<<28)
246 #define FIFO_CNT_B12 (1<<29)
247 #define DMA_ACK (1<<30)
248 #define START_CMD (1<<31)
249
250 #define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */
251 /* TX watermark : bits 11:0
252 * RX watermark : bits 27:16
253 * DMA MTRANS SIZE : bits 30:28
254 * bits 31, 15:12 : unused
255 */
256 #define MCI_FIFOTH_MASK 0x8000f000
257
258 #define MCI_CDETECT SD_REG(0x50) /* card detect */
259
260 #define CDETECT_CRD_0 (1<<0)
261 #define CDETECT_CRD_1 (1<<1)
262 #define CDETECT_CRD_2 (1<<2)
263 #define CDETECT_CRD_3 (1<<3)
264
265 #define MCI_WRTPRT SD_REG(0x54) /* write protect */
266 #define MCI_GPIO SD_REG(0x58)
267 #define MCI_TCBCNT SD_REG(0x5C) /* transferred CIU byte count (card)*/
268 #define MCI_TBBCNT SD_REG(0x60) /* transferred host/DMA to/from bytes (FIFO)*/
269 #define MCI_DEBNCE SD_REG(0x64) /* card detect debounce bits 23:0*/
270 #define MCI_USRID SD_REG(0x68) /* user id */
271 #define MCI_VERID SD_REG(0x6C) /* version id */
272
273 #define MCI_HCON SD_REG(0x70) /* hardware config */
274 /* bit 0 : card type
275 * bits 5:1 : maximum card index
276 * bit 6 : BUS TYPE
277 * bits 9:7 : DATA WIDTH
278 * bits 15:10 : ADDR WIDTH
279 * bits 17:16 : DMA IF
280 * bits 20:18 : DMA WIDTH
281 * bit 21 : FIFO RAM INSIDE
282 * bit 22 : IMPL HOLD REG
283 * bit 23 : SET CLK FALSE
284 * bits 25:24 : MAX CLK DIV IDX
285 * bit 26 : AREA OPTIM
286 */
287
288 #define MCI_BMOD SD_REG(0x80) /* bus mode */
289 /* bit 0 : SWR
290 * bit 1 : FB
291 * bits 6:2 : DSL
292 * bit 7 : DE
293 * bit 10:8 : PBL
294 */
295
296 #define MCI_PLDMND SD_REG(0x84) /* poll demand */
297 #define MCI_DBADDR SD_REG(0x88) /* descriptor base address */
298 #define MCI_IDSTS SD_REG(0x8C) /* internal DMAC status */
299 /* bit 0 : TI
300 * bit 1 : RI
301 * bit 2 : FBE
302 * bit 3 : unused
303 * bit 4 : DU
304 * bit 5 : CES
305 * bits 7:6 : unused
306 * bits 8 : NIS
307 * bit 9 : AIS
308 * bits 12:10 : EB
309 * bits 16:13 : FSM
310 */
311
312 #define MCI_IDINTEN SD_REG(0x90) /* internal DMAC interrupt enable */
313 /* bit 0 : TI
314 * bit 1 : RI
315 * bit 2 : FBE
316 * bit 3 : unused
317 * bit 4 : DU
318 * bit 5 : CES
319 * bits 7:6 : unused
320 * bits 8 : NI
321 * bit 9 : AI
322 */
323 #define MCI_DSCADDR SD_REG(0x94) /* current host descriptor address */
324 #define MCI_BUFADDR SD_REG(0x98) /* current host buffer address */
325
326 #define MCI_FIFO ((unsigned long *) (SD_BASE+0x100))
327
328 #define UNALIGNED_NUM_SECTORS 10
329 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32))); /* align on cache line size */
330 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
331
332 static tCardInfo card_info[NUM_DRIVES];
333
334 /* for compatibility */
335 static long last_disk_activity = -1;
336
337 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
338 static const char sd_thread_name[] = "ata/sd";
339 static struct mutex sd_mtx SHAREDBSS_ATTR;
340 static struct event_queue sd_queue;
341 #ifndef BOOTLOADER
342 bool sd_enabled = false;
343 #endif
344
345 static struct semaphore transfer_completion_signal;
346 static struct semaphore command_completion_signal;
347 static volatile bool retry;
348 static volatile int cmd_error;
349
350 #if defined(HAVE_MULTIDRIVE)
351 #define EXT_SD_BITS (1<<2)
352 #endif
353
354 static inline void mci_delay(void) { udelay(1000); }
355
356 void INT_NAND(void)
357 {
358 MCI_CTRL &= ~INT_ENABLE;
359 /* use raw status here as we need to check some Ints that are masked */
360 const int status = MCI_RAW_STATUS;
361
362 MCI_RAW_STATUS = status; /* clear status */
363
364 if(status & MCI_DATA_ERROR)
365 retry = true;
366
367 if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
368 semaphore_release(&transfer_completion_signal);
369
370 cmd_error = status & MCI_CMD_ERROR;
371
372 if(status & MCI_INT_CD)
373 semaphore_release(&command_completion_signal);
374
375 MCI_CTRL |= INT_ENABLE;
376 }
377
378 static inline bool card_detect_target(void)
379 {
380 #if defined(HAVE_MULTIDRIVE)
381 #if defined(SANSA_FUZEV2)
382 return GPIOA_PIN(2);
383 #elif defined(SANSA_CLIPPLUS)
384 return !(GPIOA_PIN(2));
385 #else
386 #error "microSD pin not defined for your target"
387 #endif
388 #else
389 return false;
390 #endif
391 }
392
393 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
394 unsigned long *response)
395 {
396 int card_no;
397
398 if ((flags & MCI_ACMD) && /* send SD_APP_CMD first */
399 !send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, response))
400 return false;
401
402 #if defined(HAVE_MULTIDRIVE)
403 if(sd_present(SD_SLOT_AS3525))
404 GPIOB_PIN(5) = (1-drive) << 5;
405 #endif
406
407 MCI_ARGUMENT = arg;
408
409 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
410 if (amsv2_variant == 1)
411 card_no = 1 << 16;
412 else
413 #endif
414 card_no = CMD_CARD_NO(drive);
415
416 /* Construct MCI_COMMAND */
417 MCI_COMMAND =
418 /*b5:0*/ cmd
419 /*b6 */ | ((flags & MCI_RESP) ? CMD_RESP_EXP_BIT: 0)
420 /*b7 */ | ((flags & MCI_LONG_RESP) ? CMD_RESP_LENGTH_BIT: 0)
421 /*b8 | CMD_CHECK_CRC_BIT unused */
422 /*b9 */ | (TRANSFER_CMD ? CMD_DATA_EXP_BIT: 0)
423 /*b10 */ | ((cmd == SD_WRITE_MULTIPLE_BLOCK) ? CMD_RW_BIT: 0)
424 /*b11 | CMD_TRANSMODE_BIT unused */
425 /*b12 | CMD_SENT_AUTO_STOP_BIT unused */
426 /*b13 */ | ((cmd != SD_STOP_TRANSMISSION) ? CMD_WAIT_PRV_DAT_BIT: 0)
427 /*b14 | CMD_ABRT_CMD_BIT unused */
428 /*b15 | CMD_SEND_INIT_BIT unused */
429 /*b20:16 */ | card_no
430 /*b21 | CMD_SEND_CLK_ONLY unused */
431 /*b22 | CMD_READ_CEATA unused */
432 /*b23 | CMD_CCS_EXPECTED unused */
433 /*b31 */ | CMD_DONE_BIT;
434
435 #if defined(SANSA_FUZEV2)
436 if (amsv2_variant == 0)
437 {
438 extern int buttonlight_is_on;
439 if(buttonlight_is_on)
440 _buttonlight_on();
441 else
442 _buttonlight_off();
443 }
444 #endif
445 semaphore_wait(&command_completion_signal, TIMEOUT_BLOCK);
446
447 /* Handle command responses & errors */
448 if(flags & MCI_RESP)
449 {
450 if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
451 return false;
452
453 if(flags & MCI_LONG_RESP)
454 {
455 response[0] = MCI_RESP3;
456 response[1] = MCI_RESP2;
457 response[2] = MCI_RESP1;
458 response[3] = MCI_RESP0;
459 }
460 else
461 response[0] = MCI_RESP0;
462 }
463 return true;
464 }
465
466 static int sd_wait_for_tran_state(const int drive)
467 {
468 unsigned long response;
469 unsigned int timeout = current_tick + 5*HZ;
470 int cmd_retry = 10;
471
472 while (1)
473 {
474 while (!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
475 &response) && cmd_retry > 0)
476 {
477 cmd_retry--;
478 }
479
480 if (cmd_retry <= 0)
481 return -1;
482
483 if (((response >> 9) & 0xf) == SD_TRAN)
484 return 0;
485
486 if(TIME_AFTER(current_tick, timeout))
487 return -10 * ((response >> 9) & 0xf);
488
489 last_disk_activity = current_tick;
490 }
491 }
492
493
494 static int sd_init_card(const int drive)
495 {
496 unsigned long response;
497 long init_timeout;
498 bool sd_v2 = false;
499
500 card_info[drive].rca = 0;
501
502 /* assume 24 MHz clock / 60 = 400 kHz */
503 MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C; /* CLK_DIV_0 : bits 7:0 */
504
505 /* 100 - 400kHz clock required for Identification Mode */
506 /* Start of Card Identification Mode ************************************/
507
508 /* CMD0 Go Idle */
509 if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
510 return -1;
511 mci_delay();
512
513 /* CMD8 Check for v2 sd card. Must be sent before using ACMD41
514 Non v2 cards will not respond to this command*/
515 if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
516 if((response & 0xFFF) == 0x1AA)
517 sd_v2 = true;
518
519 /* timeout for initialization is 1sec, from SD Specification 2.00 */
520 init_timeout = current_tick + HZ;
521
522 do {
523 /* this timeout is the only valid error for this loop*/
524 if(TIME_AFTER(current_tick, init_timeout))
525 return -2;
526
527 /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
528 if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
529 MCI_ACMD|MCI_RESP, &card_info[drive].ocr))
530 return -3;
531 } while(!(card_info[drive].ocr & (1<<31)) );
532
533 /* CMD2 send CID */
534 if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
535 return -4;
536
537 /* CMD3 send RCA */
538 if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
539 return -5;
540
541 #ifdef HAVE_MULTIDRIVE
542 /* Make sure we have 2 unique rca numbers */
543 if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
544 if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
545 return -6;
546 #endif
547 /* End of Card Identification Mode ************************************/
548
549 if (sd_v2)
550 {
551 /* Attempt to switch cards to HS timings, non HS cards just ignore this */
552 /* CMD7 w/rca: Select card to put it in TRAN state */
553 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
554 return -7;
555
556 if(sd_wait_for_tran_state(drive))
557 return -8;
558
559 /* CMD6 */
560 if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_RESP, &response))
561 return -9;
562
563 /* This delay is a bit of a hack, but seems to fix card detection
564 problems with some SD cards (particularly 16 GB and bigger cards).
565 Preferably we should handle this properly instead of using a delay,
566 see also FS#11870. */
567 sleep(HZ/10);
568
569 /* We need to go back to STBY state now so we can read csd */
570 /* CMD7 w/rca=0: Deselect card to put it in STBY state */
571 if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
572 return -10;
573 }
574
575 /* CMD9 send CSD */
576 if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
577 MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
578 return -11;
579
580 /* Another delay hack, see FS#11798 */
581 mci_delay();
582
583 sd_parse_csd(&card_info[drive]);
584
585 if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
586 card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
587
588 /* Card back to full speed */
589 MCI_CLKDIV &= ~(0xFF); /* CLK_DIV_0 : bits 7:0 = 0x00 */
590
591 /* CMD7 w/rca: Select card to put it in TRAN state */
592 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
593 return -12;
594
595 #ifndef BOOTLOADER
596 /* Switch to to 4 bit widebus mode */
597 if(sd_wait_for_tran_state(drive) < 0)
598 return -13;
599 /* ACMD6 */
600 if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ACMD|MCI_RESP, &response))
601 return -15;
602 /* ACMD42 */
603 if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ACMD|MCI_RESP, &response))
604 return -17;
605
606 /* Now that card is widebus make controller aware */
607 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
608 if (amsv2_variant == 1)
609 MCI_CTYPE |= 1<<1;
610 else
611 #endif
612 MCI_CTYPE |= (1<<drive);
613
614 #endif /* ! BOOTLOADER */
615
616 /* Set low power mode */
617 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
618 if (amsv2_variant == 1)
619 MCI_CLKENA |= 1<<16;
620 else
621 #endif
622 MCI_CLKENA |= 1<<(drive + 16);
623
624 card_info[drive].initialized = 1;
625
626 return 0;
627 }
628
629 static void sd_thread(void) NORETURN_ATTR;
630 static void sd_thread(void)
631 {
632 struct queue_event ev;
633 bool idle_notified = false;
634
635 while (1)
636 {
637 queue_wait_w_tmo(&sd_queue, &ev, HZ);
638
639 switch ( ev.id )
640 {
641 #ifdef HAVE_HOTSWAP
642 case SYS_HOTSWAP_INSERTED:
643 case SYS_HOTSWAP_EXTRACTED:
644 {
645 int microsd_init = 1;
646 fat_lock(); /* lock-out FAT activity first -
647 prevent deadlocking via disk_mount that
648 would cause a reverse-order attempt with
649 another thread */
650 mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
651 into driver that bypass the fat cache */
652
653 /* We now have exclusive control of fat cache and ata */
654
655 disk_unmount(SD_SLOT_AS3525); /* release "by force", ensure file
656 descriptors aren't leaked and any busy
657 ones are invalid if mounting */
658 /* Force card init for new card, re-init for re-inserted one or
659 * clear if the last attempt to init failed with an error. */
660 card_info[SD_SLOT_AS3525].initialized = 0;
661
662 if (ev.id == SYS_HOTSWAP_INSERTED)
663 {
664 sd_enable(true);
665 microsd_init = sd_init_card(SD_SLOT_AS3525);
666 if (microsd_init < 0) /* initialisation failed */
667 panicf("microSD init failed : %d", microsd_init);
668
669 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
670 }
671
672 /*
673 * Mount succeeded, or this was an EXTRACTED event,
674 * in both cases notify the system about the changed filesystems
675 */
676 if (microsd_init)
677 queue_broadcast(SYS_FS_CHANGED, 0);
678
679 sd_enable(false);
680
681 /* Access is now safe */
682 mutex_unlock(&sd_mtx);
683 fat_unlock();
684 }
685 break;
686 #endif
687 case SYS_TIMEOUT:
688 if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
689 {
690 idle_notified = false;
691 }
692 else if (!idle_notified)
693 {
694 call_storage_idle_notifys(false);
695 idle_notified = true;
696 }
697 break;
698
699 case SYS_USB_CONNECTED:
700 usb_acknowledge(SYS_USB_CONNECTED_ACK);
701 /* Wait until the USB cable is extracted again */
702 usb_wait_for_disconnect(&sd_queue);
703
704 break;
705 }
706 }
707 }
708
709 static void init_controller(void)
710 {
711 int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
712 int card_mask = (1 << hcon_numcards) - 1;
713 int pwr_mask;
714
715 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
716 if (amsv2_variant == 1)
717 pwr_mask = 1 << 1;
718 else
719 #endif
720 pwr_mask = card_mask;
721
722 MCI_PWREN &= ~pwr_mask; /* power off all cards */
723 MCI_PWREN = pwr_mask; /* power up cards */
724
725 MCI_CTRL |= CTRL_RESET;
726 while(MCI_CTRL & CTRL_RESET)
727 ;
728
729 MCI_RAW_STATUS = 0xffffffff; /* Clear all MCI Interrupts */
730
731 MCI_TMOUT = 0xffffffff; /* data b31:8, response b7:0 */
732
733 MCI_CTYPE = 0x0; /* all cards 1 bit bus for now */
734
735 MCI_CLKENA = card_mask; /* Enables card clocks */
736
737 MCI_ARGUMENT = 0;
738 MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
739 while(MCI_COMMAND & CMD_DONE_BIT)
740 ;
741
742 MCI_DEBNCE = 0xfffff; /* default value */
743
744 /* Rx watermark = 63(sd reads) Tx watermark = 128 (sd writes) */
745 MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
746
747 /* RCRC & RTO interrupts should be set together with the CD interrupt but
748 * in practice sometimes incorrectly precede the CD interrupt. If we leave
749 * them masked for now we can check them in the isr by reading raw status when
750 * the CD int is triggered.
751 */
752 MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO | MCI_INT_CD);
753
754 MCI_CTRL |= INT_ENABLE | DMA_ENABLE;
755
756 MCI_BLKSIZ = SD_BLOCK_SIZE;
757 }
758
759 int sd_init(void)
760 {
761 int ret;
762
763 bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
764
765 CGU_IDE = (1<<7) /* AHB interface enable */
766 | (AS3525_IDE_DIV << 2)
767 | 1; /* clock source = PLLA */
768
769 CGU_MEMSTICK = (1<<7) /* interface enable */
770 | (AS3525_MS_DIV << 2)
771 | 1; /* clock source = PLLA */
772
773 CGU_SDSLOT = (1<<7) /* interface enable */
774 | (AS3525_SDSLOT_DIV << 2)
775 | 1; /* clock source = PLLA */
776
777 semaphore_init(&transfer_completion_signal, 1, 0);
778 semaphore_init(&command_completion_signal, 1, 0);
779
780 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
781 if (amsv2_variant == 1)
782 GPIOB_DIR |= 1 << 5;
783 #endif
784
785 #ifdef HAVE_MULTIDRIVE
786 /* clear previous irq */
787 GPIOA_IC = EXT_SD_BITS;
788 /* enable edge detecting */
789 GPIOA_IS &= ~EXT_SD_BITS;
790 /* detect both raising and falling edges */
791 GPIOA_IBE |= EXT_SD_BITS;
792 /* enable the card detect interrupt */
793 GPIOA_IE |= EXT_SD_BITS;
794 #endif /* HAVE_MULTIDRIVE */
795
796 #ifndef SANSA_CLIPV2
797 /* Configure XPD for SD-MCI interface */
798 bitset32(&CCU_IO, 1<<2);
799 #endif
800
801 VIC_INT_ENABLE = INTERRUPT_NAND;
802
803 init_controller();
804 ret = sd_init_card(INTERNAL_AS3525);
805 if(ret < 0)
806 return ret;
807
808 /* init mutex */
809 mutex_init(&sd_mtx);
810
811 queue_init(&sd_queue, true);
812 create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
813 sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
814
815 #ifndef BOOTLOADER
816 sd_enabled = true;
817 sd_enable(false);
818 #endif
819 return 0;
820 }
821
822 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
823 int count, void* buf, bool write)
824 {
825 int ret = 0;
826 #ifndef HAVE_MULTIDRIVE
827 const int drive = 0;
828 #endif
829 bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
830 int const retry_all_max = 1;
831 int retry_all = 0;
832 int const retry_data_max = 100; /* Generous, methinks */
833 int retry_data;
834
835 mutex_lock(&sd_mtx);
836 #ifndef BOOTLOADER
837 sd_enable(true);
838 led(true);
839 #endif
840
841 if(count < 0) /* XXX: why is it signed ? */
842 {
843 ret = -18;
844 goto sd_transfer_error_no_dma;
845 }
846
847 if((start+count) > card_info[drive].numblocks)
848 {
849 ret = -19;
850 goto sd_transfer_error_no_dma;
851 }
852
853 /* skip SanDisk OF */
854 if (drive == INTERNAL_AS3525)
855 start += AMS_OF_SIZE;
856
857 /* no need for complete retry on main, just SD */
858 if (drive == SD_SLOT_AS3525)
859 retry_all = retry_all_max;
860
861 sd_transfer_retry_with_reinit:
862 if (card_info[drive].initialized <= 0)
863 {
864 ret = sd_init_card(drive);
865 if (!(card_info[drive].initialized))
866 goto sd_transfer_error_no_dma;
867 }
868
869 /* CMD7 w/rca: Select card to put it in TRAN state */
870 if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
871 {
872 ret = -20;
873 goto sd_transfer_error_no_dma;
874 }
875
876 dma_retain();
877
878 if(aligned)
879 { /* direct transfer, indirect is always uncached */
880 if(write)
881 commit_dcache_range(buf, count * SECTOR_SIZE);
882 else
883 discard_dcache_range(buf, count * SECTOR_SIZE);
884 }
885
886 const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
887 retry_data = retry_data_max;
888
889 while (1)
890 {
891 void *dma_buf;
892 unsigned int transfer = count;
893
894 last_disk_activity = current_tick;
895
896 if(aligned)
897 {
898 dma_buf = AS3525_PHYSICAL_ADDR(buf);
899 }
900 else
901 {
902 dma_buf = AS3525_PHYSICAL_ADDR(&aligned_buffer[0]);
903 if(transfer > UNALIGNED_NUM_SECTORS)
904 transfer = UNALIGNED_NUM_SECTORS;
905
906 if(write)
907 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
908 }
909
910 /* Interrupt handler might set this to true during transfer */
911 retry = false;
912
913 MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
914
915 ret = sd_wait_for_tran_state(drive);
916 if (ret < 0)
917 {
918 ret -= 25;
919 goto sd_transfer_error;
920 }
921
922 int arg = start;
923 if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
924 arg *= SD_BLOCK_SIZE;
925
926 if(write)
927 dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
928 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
929 else
930 dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
931 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
932
933 unsigned long dummy; /* if we don't ask for a response, writing fails */
934 if(!send_cmd(drive, cmd, arg, MCI_RESP, &dummy))
935 {
936 ret = -21;
937 goto sd_transfer_error;
938 }
939
940 semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
941
942 last_disk_activity = current_tick;
943
944 if(write)
945 {
946 /* wait for the card to exit programming state */
947 while(MCI_STATUS & DATA_BUSY) ;
948 }
949
950 if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
951 {
952 ret = -22;
953 goto sd_transfer_error;
954 }
955
956 if(!retry)
957 {
958 if(!write && !aligned)
959 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
960 buf += transfer * SD_BLOCK_SIZE;
961 start += transfer;
962 count -= transfer;
963
964 if (count > 0)
965 continue;
966 }
967 else /* reset controller if we had an error */
968 {
969 MCI_CTRL |= (FIFO_RESET|DMA_RESET);
970 while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
971 ;
972 if (--retry_data >= 0)
973 continue;
974 }
975
976 break;
977 }
978
979 dma_release();
980
981 /* CMD lines are separate, not common, so we need to actively deselect */
982 /* CMD7 w/rca =0 : deselects card & puts it in STBY state */
983 if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
984 {
985 ret = -23;
986 goto sd_transfer_error;
987 }
988
989 while (1)
990 {
991 #ifndef BOOTLOADER
992 sd_enable(false);
993 led(false);
994 #endif
995 mutex_unlock(&sd_mtx);
996 return ret;
997
998 sd_transfer_error:
999 dma_release();
1000
1001 sd_transfer_error_no_dma:
1002 card_info[drive].initialized = 0;
1003
1004 /* .initialized might have been >= 0 but now stale if the ata sd thread
1005 * isn't handling an insert because of USB */
1006 if (--retry_all >= 0)
1007 goto sd_transfer_retry_with_reinit;
1008 }
1009 }
1010
1011 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
1012 void* buf)
1013 {
1014 return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
1015 }
1016
1017 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
1018 const void* buf)
1019 {
1020 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
1021 #ifdef HAVE_MULTIDRIVE
1022 (void) drive;
1023 #endif
1024 (void) start;
1025 (void) count;
1026 (void) buf;
1027 return -1;
1028 #else
1029 return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
1030 #endif /* defined(BOOTLOADER) */
1031 }
1032
1033 #ifndef BOOTLOADER
1034 long sd_last_disk_activity(void)
1035 {
1036 return last_disk_activity;
1037 }
1038
1039 void sd_enable(bool on)
1040 {
1041 if (on)
1042 {
1043 bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1044 CGU_IDE |= (1<<7); /* AHB interface enable */
1045 CGU_MEMSTICK |= (1<<7); /* interface enable */
1046 CGU_SDSLOT |= (1<<7); /* interface enable */
1047 }
1048 else
1049 {
1050 CGU_SDSLOT &= ~(1<<7); /* interface enable */
1051 CGU_MEMSTICK &= ~(1<<7); /* interface enable */
1052 CGU_IDE &= ~(1<<7); /* AHB interface enable */
1053 bitclr32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1054 }
1055 }
1056
1057 tCardInfo *card_get_info_target(int card_no)
1058 {
1059 return &card_info[card_no];
1060 }
1061 #endif /* BOOTLOADER */
1062
1063 #ifdef HAVE_HOTSWAP
1064 bool sd_removable(IF_MD_NONVOID(int drive))
1065 {
1066 return (drive==1);
1067 }
1068
1069 bool sd_present(IF_MD_NONVOID(int drive))
1070 {
1071 return (drive == 0) ? true : card_detect_target();
1072 }
1073
1074 static int sd1_oneshot_callback(struct timeout *tmo)
1075 {
1076 (void)tmo;
1077
1078 /* This is called only if the state was stable for 300ms - check state
1079 * and post appropriate event. */
1080 if (card_detect_target())
1081 {
1082 queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
1083 }
1084 else
1085 queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
1086
1087 return 0;
1088 }
1089
1090 void sd_gpioa_isr(void)
1091 {
1092 static struct timeout sd1_oneshot;
1093 if (GPIOA_MIS & EXT_SD_BITS)
1094 timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
1095 /* acknowledge interrupt */
1096 GPIOA_IC = EXT_SD_BITS;
1097 }
1098 #endif /* HAVE_HOTSWAP */
1099
1100 #ifdef CONFIG_STORAGE_MULTI
1101 int sd_num_drives(int first_drive)
1102 {
1103 /* We don't care which logical drive number(s) we have been assigned */
1104 (void)first_drive;
1105
1106 return NUM_DRIVES;
1107 }
1108 #endif /* CONFIG_STORAGE_MULTI */
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