firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "gcc_extensions.h"
  27 #include "led.h"
  28 #include "sdmmc.h"
  29 #include "system.h"
  30 #include "kernel.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "as3525v2.h"
  36 #include "pl081.h"  /* DMA controller */
  37 #include "dma-target.h" /* DMA request lines */
  38 #include "clock-target.h"
  39 #include "panic.h"
  40 #include "stdbool.h"
  41 #include "ata_idle_notify.h"
  42 #include "sd.h"
  43 #include "usb.h"
  44
  45 #ifdef HAVE_HOTSWAP
  46 #include "disk.h"
  47 #endif
  48
  49 #include "lcd.h"
  50 #include <stdarg.h>
  51 #include "sysfont.h"
  52
  53 #define     INTERNAL_AS3525  0   /* embedded SD card */
  54 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  55
  56 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
  57 #define AMS_OF_SIZE 0xf000
  58
  59 /* command flags */
  60 #define MCI_NO_RESP     (0<<0)
  61 #define MCI_RESP        (1<<0)
  62 #define MCI_LONG_RESP   (1<<1)
  63 #define MCI_ACMD        (1<<2)
  64
  65 /* controller registers */
  66 #define SD_BASE 0xC6070000
  67
  68 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  69
  70 #define MCI_CTRL        SD_REG(0x00)
  71
  72 /* control bits */
  73 #define CTRL_RESET      (1<<0)
  74 #define FIFO_RESET      (1<<1)
  75 #define DMA_RESET       (1<<2)
  76 #define INT_ENABLE      (1<<4)
  77 #define DMA_ENABLE      (1<<5)
  78 #define READ_WAIT       (1<<6)
  79 #define SEND_IRQ_RESP   (1<<7)
  80 #define ABRT_READ_DATA  (1<<8)
  81 #define SEND_CCSD       (1<<9)
  82 #define SEND_AS_CCSD    (1<<10)
  83 #define EN_OD_PULLUP    (1<<24)
  84
  85
  86 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  87
  88 #define PWR_CRD_0       (1<<0)
  89 #define PWR_CRD_1       (1<<1)
  90 #define PWR_CRD_2       (1<<2)
  91 #define PWR_CRD_3       (1<<3)
  92
  93 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  94 /* CLK_DIV_0 :    bits 7:0
  95  * CLK_DIV_1 :    bits 15:8
  96  * CLK_DIV_2 :    bits 23:16
  97  * CLK_DIV_3 :    bits 31:24
  98  */
  99
 100 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
 101 /* CLK_SRC_CRD0:  bits 1:0
 102  * CLK_SRC_CRD1:  bits 3:2
 103  * CLK_SRC_CRD2:  bits 5:4
 104  * CLK_SRC_CRD3:  bits 7:6
 105  */
 106
 107 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 108
 109 #define CCLK_ENA_CRD0   (1<<0)
 110 #define CCLK_ENA_CRD1   (1<<1)
 111 #define CCLK_ENA_CRD2   (1<<2)
 112 #define CCLK_ENA_CRD3   (1<<3)
 113 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 114 #define CCLK_LP_CRD1    (1<<17)
 115 #define CCLK_LP_CRD2    (1<<18)
 116 #define CCLK_LP_CRD3    (1<<19)
 117
 118 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 119 /* response timeout bits 0:7
 120  * data timeout bits     8:31
 121  */
 122
 123 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 124                                         /* 1 bit per card, set = wide bus */
 125 #define WIDTH4_CRD0     (1<<0)
 126 #define WIDTH4_CRD1     (1<<1)
 127 #define WIDTH4_CRD2     (1<<2)
 128 #define WIDTH4_CRD3     (1<<3)
 129
 130 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 131 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 132 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 133
 134
 135
 136 #define MCI_ARGUMENT    SD_REG(0x28)
 137 #define MCI_COMMAND     SD_REG(0x2C)
 138
 139 /* command bits (bits 5:0 are the command index) */
 140 #define CMD_RESP_EXP_BIT        (1<<6)
 141 #define CMD_RESP_LENGTH_BIT     (1<<7)
 142 #define CMD_CHECK_CRC_BIT       (1<<8)
 143 #define CMD_DATA_EXP_BIT        (1<<9)
 144 #define CMD_RW_BIT              (1<<10)
 145 #define CMD_TRANSMODE_BIT       (1<<11)
 146 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 147 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 148 #define CMD_ABRT_CMD_BIT        (1<<14)
 149 #define CMD_SEND_INIT_BIT       (1<<15)
 150 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 151 #define CMD_SEND_CLK_ONLY       (1<<21)
 152 #define CMD_READ_CEATA          (1<<22)
 153 #define CMD_CCS_EXPECTED        (1<<23)
 154 #define CMD_DONE_BIT            (1<<31)
 155
 156 #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
 157                        cmd == SD_WRITE_MULTIPLE_BLOCK)
 158
 159 #define MCI_RESP0       SD_REG(0x30)
 160 #define MCI_RESP1       SD_REG(0x34)
 161 #define MCI_RESP2       SD_REG(0x38)
 162 #define MCI_RESP3       SD_REG(0x3C)
 163
 164 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 165 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 166                                          * status clear */
 167
 168 /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
 169 #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
 170 #define MCI_INT_RE      (1<<1)      /* x         response error */
 171 #define MCI_INT_CD      (1<<2)      /*     x     command done */
 172 #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
 173 #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
 174 #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
 175 #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
 176 #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
 177 #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
 178 #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
 179 #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
 180 #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
 181 #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
 182 #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
 183 #define MCI_INT_ACD     (1<<14)     /*          auto command done */
 184 #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
 185 #define MCI_INT_SDIO    (0xf<<16)
 186
 187 /*
 188  *  STATUS register
 189  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 190  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 191  *  & 8         = MCI_INT_DTO
 192  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 193  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 194  */
 195
 196 #define MCI_CMD_ERROR    \
 197          (MCI_INT_RE   | \
 198           MCI_INT_RCRC | \
 199           MCI_INT_RTO  | \
 200           MCI_INT_HLE)
 201
 202 #define MCI_DATA_ERROR    \
 203         ( MCI_INT_DCRC  | \
 204           MCI_INT_DRTO  | \
 205           MCI_INT_HTO   | \
 206           MCI_INT_FRUN  | \
 207           MCI_INT_HLE   | \
 208           MCI_INT_SBE   | \
 209           MCI_INT_EBE)
 210
 211 #define MCI_STATUS      SD_REG(0x48)
 212
 213 #define FIFO_RX_WM              (1<<0)
 214 #define FIFO_TX_WM              (1<<1)
 215 #define FIFO_EMPTY              (1<<2)
 216 #define FIFO_FULL               (1<<3)
 217 #define CMD_FSM_STATE_B0        (1<<4)
 218 #define CMD_FSM_STATE_B1        (1<<5)
 219 #define CMD_FSM_STATE_B2        (1<<6)
 220 #define CMD_FSM_STATE_B3        (1<<7)
 221 #define DATA_3_STAT             (1<<8)
 222 #define DATA_BUSY               (1<<9)
 223 #define DATA_STAT_MC_BUSY       (1<<10)
 224 #define RESP_IDX_B0             (1<<11)
 225 #define RESP_IDX_B1             (1<<12)
 226 #define RESP_IDX_B2             (1<<13)
 227 #define RESP_IDX_B3             (1<<14)
 228 #define RESP_IDX_B4             (1<<15)
 229 #define RESP_IDX_B5             (1<<16)
 230 #define FIFO_CNT_B00            (1<<17)
 231 #define FIFO_CNT_B01            (1<<18)
 232 #define FIFO_CNT_B02            (1<<19)
 233 #define FIFO_CNT_B03            (1<<20)
 234 #define FIFO_CNT_B04            (1<<21)
 235 #define FIFO_CNT_B05            (1<<22)
 236 #define FIFO_CNT_B06            (1<<23)
 237 #define FIFO_CNT_B07            (1<<24)
 238 #define FIFO_CNT_B08            (1<<25)
 239 #define FIFO_CNT_B09            (1<<26)
 240 #define FIFO_CNT_B10            (1<<27)
 241 #define FIFO_CNT_B11            (1<<28)
 242 #define FIFO_CNT_B12            (1<<29)
 243 #define DMA_ACK                 (1<<30)
 244 #define START_CMD               (1<<31)
 245
 246 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 247 /* TX watermark :    bits 11:0
 248  * RX watermark :    bits 27:16
 249  * DMA MTRANS SIZE : bits 30:28
 250  * bits 31, 15:12 : unused
 251  */
 252 #define MCI_FIFOTH_MASK 0x8000f000
 253
 254 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 255
 256 #define CDETECT_CRD_0   (1<<0)
 257 #define CDETECT_CRD_1   (1<<1)
 258 #define CDETECT_CRD_2   (1<<2)
 259 #define CDETECT_CRD_3   (1<<3)
 260
 261 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 262 #define MCI_GPIO        SD_REG(0x58)
 263 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 264 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 265 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 266 #define MCI_USRID       SD_REG(0x68)    /* user id */
 267 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 268
 269 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 270 /* bit  0       : card type
 271  * bits 5:1     : maximum card index
 272  * bit  6       : BUS TYPE
 273  * bits 9:7     : DATA WIDTH
 274  * bits 15:10   : ADDR WIDTH
 275  * bits 17:16   : DMA IF
 276  * bits 20:18   : DMA WIDTH
 277  * bit  21      : FIFO RAM INSIDE
 278  * bit  22      : IMPL HOLD REG
 279  * bit  23      : SET CLK FALSE
 280  * bits 25:24   : MAX CLK DIV IDX
 281  * bit  26      : AREA OPTIM
 282  */
 283
 284 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 285 /* bit  0       : SWR
 286  * bit  1       : FB
 287  * bits 6:2     : DSL
 288  * bit  7       : DE
 289  * bit  10:8    : PBL
 290  */
 291
 292 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 293 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 294 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 295 /* bit  0       : TI
 296  * bit  1       : RI
 297  * bit  2       : FBE
 298  * bit  3       : unused
 299  * bit  4       : DU
 300  * bit  5       : CES
 301  * bits 7:6     : unused
 302  * bits 8       : NIS
 303  * bit  9       : AIS
 304  * bits 12:10   : EB
 305  * bits 16:13   : FSM
 306  */
 307
 308 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 309 /* bit  0       : TI
 310  * bit  1       : RI
 311  * bit  2       : FBE
 312  * bit  3       : unused
 313  * bit  4       : DU
 314  * bit  5       : CES
 315  * bits 7:6     : unused
 316  * bits 8       : NI
 317  * bit  9       : AI
 318  */
 319 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 320 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 321
 322 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 323
 324 #define UNALIGNED_NUM_SECTORS 10
 325 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 326 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 327
 328 static tCardInfo card_info[NUM_DRIVES];
 329
 330 /* for compatibility */
 331 static long last_disk_activity = -1;
 332
 333 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 334 static const char         sd_thread_name[] = "ata/sd";
 335 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 336 static struct event_queue sd_queue;
 337 #ifndef BOOTLOADER
 338 bool sd_enabled = false;
 339 #endif
 340
 341 static struct semaphore transfer_completion_signal;
 342 static struct semaphore command_completion_signal;
 343 static volatile bool retry;
 344 static volatile int cmd_error;
 345
 346 #if defined(HAVE_MULTIDRIVE)
 347 #define EXT_SD_BITS (1<<2)
 348 #endif
 349
 350 static inline void mci_delay(void) { udelay(1000); }
 351
 352 void INT_NAND(void)
 353 {
 354     MCI_CTRL &= ~INT_ENABLE;
 355     /* use raw status here as we need to check some Ints that are masked */
 356     const int status = MCI_RAW_STATUS;
 357
 358     MCI_RAW_STATUS = status;    /* clear status */
 359
 360     if(status & MCI_DATA_ERROR)
 361         retry = true;
 362
 363     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
 364         semaphore_release(&transfer_completion_signal);
 365
 366     cmd_error = status & MCI_CMD_ERROR;
 367
 368     if(status & MCI_INT_CD)
 369         semaphore_release(&command_completion_signal);
 370
 371     MCI_CTRL |= INT_ENABLE;
 372 }
 373
 374 static inline bool card_detect_target(void)
 375 {
 376 #if defined(HAVE_MULTIDRIVE)
 377 #if defined(SANSA_FUZEV2)
 378     return GPIOA_PIN(2);
 379 #elif defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
 380     return !(GPIOA_PIN(2));
 381 #else
 382 #error "microSD pin not defined for your target"
 383 #endif
 384 #else
 385     return false;
 386 #endif
 387 }
 388
 389 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 390         unsigned long *response)
 391 {
 392     int card_no;
 393
 394     if ((flags & MCI_ACMD) && /* send SD_APP_CMD first */
 395         !send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, response))
 396         return false;
 397
 398 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
 399     if (amsv2_variant == 1)
 400         GPIOB_PIN(5) = (drive == INTERNAL_AS3525) ? 1 << 5 : 0;
 401 #endif
 402
 403     MCI_ARGUMENT = arg;
 404
 405 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
 406     if (amsv2_variant == 1)
 407         card_no = 1 << 16;
 408     else
 409 #endif
 410         card_no = CMD_CARD_NO(drive);
 411
 412     /* Construct MCI_COMMAND  */
 413     MCI_COMMAND =
 414       /*b5:0*/    cmd
 415       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
 416       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
 417       /*b8      | CMD_CHECK_CRC_BIT       unused  */
 418       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
 419       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
 420       /*b11     | CMD_TRANSMODE_BIT       unused  */
 421       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
 422       /*b13 */  | ((cmd != SD_STOP_TRANSMISSION)     ? CMD_WAIT_PRV_DAT_BIT:  0)
 423       /*b14     | CMD_ABRT_CMD_BIT        unused  */
 424       /*b15 */  | ((cmd == SD_GO_IDLE_STATE)         ? CMD_SEND_INIT_BIT:     0)
 425    /*b20:16 */  |                                      card_no
 426       /*b21     | CMD_SEND_CLK_ONLY       unused  */
 427       /*b22     | CMD_READ_CEATA          unused  */
 428       /*b23     | CMD_CCS_EXPECTED        unused  */
 429       /*b31 */  |                                      CMD_DONE_BIT;
 430
 431     semaphore_wait(&command_completion_signal, TIMEOUT_BLOCK);
 432
 433     /*  Handle command responses & errors */
 434     if(flags & MCI_RESP)
 435     {
 436         if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
 437             return false;
 438
 439         if(flags & MCI_LONG_RESP)
 440         {
 441             response[0] = MCI_RESP3;
 442             response[1] = MCI_RESP2;
 443             response[2] = MCI_RESP1;
 444             response[3] = MCI_RESP0;
 445         }
 446         else
 447             response[0] = MCI_RESP0;
 448     }
 449     return true;
 450 }
 451
 452 static int sd_wait_for_tran_state(const int drive)
 453 {
 454     unsigned long response;
 455     unsigned int timeout = current_tick + 5*HZ;
 456     int cmd_retry = 10;
 457
 458     while (1)
 459     {
 460         while (!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
 461                          &response) && cmd_retry > 0)
 462         {
 463             cmd_retry--;
 464         }
 465
 466         if (cmd_retry <= 0)
 467             return -1;
 468
 469         if (((response >> 9) & 0xf) == SD_TRAN)
 470             return 0;
 471
 472         if(TIME_AFTER(current_tick, timeout))
 473             return -10 * ((response >> 9) & 0xf);
 474
 475         last_disk_activity = current_tick;
 476     }
 477 }
 478
 479
 480 static int sd_init_card(const int drive)
 481 {
 482     unsigned long response;
 483     long init_timeout;
 484     bool sd_v2 = false;
 485
 486     card_info[drive].rca = 0;
 487
 488     /*  assume 24 MHz clock / 60 = 400 kHz  */
 489     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 490
 491     /* 100 - 400kHz clock required for Identification Mode  */
 492     /*  Start of Card Identification Mode ************************************/
 493
 494     /* CMD0 Go Idle  */
 495     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 496         return -1;
 497     mci_delay();
 498
 499     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 500       Non v2 cards will not respond to this command*/
 501     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 502         if((response & 0xFFF) == 0x1AA)
 503             sd_v2 = true;
 504
 505     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 506     init_timeout = current_tick + HZ;
 507
 508     do {
 509         /* this timeout is the only valid error for this loop*/
 510         if(TIME_AFTER(current_tick, init_timeout))
 511             return -2;
 512
 513          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 514         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 515                         MCI_ACMD|MCI_RESP, &card_info[drive].ocr))
 516             return -3;
 517     } while(!(card_info[drive].ocr & (1<<31)) );
 518
 519     /* CMD2 send CID */
 520     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 521         return -4;
 522
 523     /* CMD3 send RCA */
 524     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 525         return -5;
 526
 527 #ifdef HAVE_MULTIDRIVE
 528     /* Make sure we have 2 unique rca numbers */
 529     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 530         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 531             return -6;
 532 #endif
 533     /*  End of Card Identification Mode   ************************************/
 534
 535     /*  Card back to full speed  */
 536     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 537
 538     /* CMD9 send CSD */
 539     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 540                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 541         return -11;
 542
 543     sd_parse_csd(&card_info[drive]);
 544
 545     if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
 546         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 547
 548 #ifndef BOOTLOADER
 549     /*  Switch to to 4 bit widebus mode  */
 550
 551     /*  CMD7 w/rca: Select card to put it in TRAN state */
 552     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 553         return -12;
 554     if(sd_wait_for_tran_state(drive) < 0)
 555         return -13;
 556
 557     /* ACMD6: set bus width to 4-bit */
 558     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ACMD|MCI_RESP, &response))
 559         return -15;
 560     /* ACMD42: disconnect the pull-up resistor on CD/DAT3 */
 561     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ACMD|MCI_RESP, &response))
 562         return -17;
 563
 564     /* Now that card is widebus make controller aware */
 565 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
 566     if (amsv2_variant == 1)
 567         MCI_CTYPE |= 1<<1;
 568     else
 569 #endif
 570         MCI_CTYPE |= (1<<drive);
 571
 572 #endif /* ! BOOTLOADER */
 573
 574     /*  Set low power mode  */
 575 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
 576     if (amsv2_variant == 1)
 577         MCI_CLKENA |= 1<<(1 + 16);
 578     else
 579 #endif
 580         MCI_CLKENA |= 1<<(drive + 16);
 581
 582     card_info[drive].initialized = 1;
 583
 584     return 0;
 585 }
 586
 587 static void sd_thread(void) NORETURN_ATTR;
 588 static void sd_thread(void)
 589 {
 590     struct queue_event ev;
 591     bool idle_notified = false;
 592
 593     while (1)
 594     {
 595         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 596
 597         switch ( ev.id )
 598         {
 599 #ifdef HAVE_HOTSWAP
 600         case SYS_HOTSWAP_INSERTED:
 601         case SYS_HOTSWAP_EXTRACTED:
 602         {
 603             int changed = 1;
 604             fat_lock();          /* lock-out FAT activity first -
 605                                     prevent deadlocking via disk_mount that
 606                                     would cause a reverse-order attempt with
 607                                     another thread */
 608             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 609                                     into driver that bypass the fat cache */
 610
 611             /* We now have exclusive control of fat cache and ata */
 612
 613             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 614                                     descriptors aren't leaked and any busy
 615                                     ones are invalid if mounting */
 616             /* Force card init for new card, re-init for re-inserted one or
 617              * clear if the last attempt to init failed with an error. */
 618             card_info[SD_SLOT_AS3525].initialized = 0;
 619
 620             if (ev.id == SYS_HOTSWAP_INSERTED)
 621             {
 622                 sd_enable(true);
 623                 changed = (sd_init_card(SD_SLOT_AS3525) == 0) && disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 624             }
 625
 626             /*
 627              * Mount succeeded, or this was an EXTRACTED event,
 628              * in both cases notify the system about the changed filesystems
 629              */
 630             if (changed)
 631                 queue_broadcast(SYS_FS_CHANGED, 0);
 632
 633             sd_enable(false);
 634
 635             /* Access is now safe */
 636             mutex_unlock(&sd_mtx);
 637             fat_unlock();
 638             }
 639             break;
 640 #endif
 641         case SYS_TIMEOUT:
 642             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 643             {
 644                 idle_notified = false;
 645             }
 646             else if (!idle_notified)
 647             {
 648                 call_storage_idle_notifys(false);
 649                 idle_notified = true;
 650             }
 651             break;
 652
 653         case SYS_USB_CONNECTED:
 654             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 655             /* Wait until the USB cable is extracted again */
 656             usb_wait_for_disconnect(&sd_queue);
 657
 658             break;
 659         }
 660     }
 661 }
 662
 663 static void init_controller(void)
 664 {
 665     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 666     int card_mask = (1 << hcon_numcards) - 1;
 667     int pwr_mask;
 668
 669 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
 670     if (amsv2_variant == 1)
 671         pwr_mask = 1 << 1;
 672     else
 673 #endif
 674         pwr_mask = card_mask;
 675
 676     MCI_PWREN &= ~pwr_mask;             /*  power off all cards  */
 677     MCI_PWREN = pwr_mask;               /*  power up cards  */
 678
 679     MCI_CTRL |= CTRL_RESET;
 680     while(MCI_CTRL & CTRL_RESET)
 681         ;
 682
 683     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
 684
 685     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 686
 687     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 688
 689     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
 690
 691     MCI_ARGUMENT = 0;
 692     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 693     while(MCI_COMMAND & CMD_DONE_BIT)
 694         ;
 695
 696     MCI_DEBNCE = 0xfffff;               /* default value */
 697
 698     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
 699     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
 700
 701 /*  RCRC & RTO interrupts should be set together with the CD interrupt but
 702  *  in practice sometimes incorrectly precede the CD interrupt.  If we leave
 703  *  them masked for now we can check them in the isr by reading raw status when
 704  *  the CD int is triggered.
 705  */
 706     MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO | MCI_INT_CD);
 707
 708     MCI_CTRL |= INT_ENABLE | DMA_ENABLE;
 709
 710     MCI_BLKSIZ = SD_BLOCK_SIZE;
 711 }
 712
 713 int sd_init(void)
 714 {
 715     int ret;
 716
 717     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 718
 719     CGU_IDE =   (1<<7)          /* AHB interface enable */
 720             |   (AS3525_IDE_DIV << 2)
 721             |   1;              /* clock source = PLLA */
 722
 723     CGU_MEMSTICK =  (1<<7)      /* interface enable */
 724                  |  (AS3525_MS_DIV << 2)
 725                  |  1;          /* clock source = PLLA */
 726
 727     CGU_SDSLOT = (1<<7)         /* interface enable */
 728                | (AS3525_SDSLOT_DIV << 2)
 729                | 1;             /* clock source = PLLA */
 730
 731     semaphore_init(&transfer_completion_signal, 1, 0);
 732     semaphore_init(&command_completion_signal, 1, 0);
 733
 734 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
 735     if (amsv2_variant == 1)
 736         GPIOB_DIR |= 1 << 5;
 737 #endif
 738
 739 #ifdef HAVE_MULTIDRIVE
 740     /* clear previous irq */
 741     GPIOA_IC = EXT_SD_BITS;
 742     /* enable edge detecting */
 743     GPIOA_IS &= ~EXT_SD_BITS;
 744     /* detect both raising and falling edges */
 745     GPIOA_IBE |= EXT_SD_BITS;
 746     /* enable the card detect interrupt */
 747     GPIOA_IE |= EXT_SD_BITS;
 748 #endif /* HAVE_MULTIDRIVE */
 749
 750 #ifndef SANSA_CLIPV2
 751     /* Configure XPD for SD-MCI interface */
 752     bitmod32(&CCU_IO, 1<<2, 3<<2);
 753 #endif
 754
 755     VIC_INT_ENABLE = INTERRUPT_NAND;
 756
 757     init_controller();
 758     ret = sd_init_card(INTERNAL_AS3525);
 759     if(ret < 0)
 760         return ret;
 761
 762     /* init mutex */
 763     mutex_init(&sd_mtx);
 764
 765     queue_init(&sd_queue, true);
 766     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 767             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 768
 769 #ifndef BOOTLOADER
 770     sd_enabled = true;
 771     sd_enable(false);
 772 #endif
 773     return 0;
 774 }
 775
 776 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 777                                 int count, void* buf, bool write)
 778 {
 779     unsigned long response;
 780     int ret = 0;
 781 #ifndef HAVE_MULTIDRIVE
 782     const int drive = 0;
 783 #endif
 784     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 785     int const retry_all_max = 1;
 786     int retry_all = 0;
 787     int const retry_data_max = 100; /* Generous, methinks */
 788     int retry_data;
 789     unsigned int real_numblocks;
 790
 791     mutex_lock(&sd_mtx);
 792 #ifndef BOOTLOADER
 793     sd_enable(true);
 794     led(true);
 795 #endif
 796
 797     if(count < 0) /* XXX: why is it signed ? */
 798     {
 799         ret = -18;
 800         goto sd_transfer_error_no_dma;
 801     }
 802
 803     /* skip SanDisk OF */
 804     if (drive == INTERNAL_AS3525)
 805         start += AMS_OF_SIZE;
 806
 807     /* no need for complete retry on main, just SD */
 808     if (drive == SD_SLOT_AS3525)
 809         retry_all = retry_all_max;
 810
 811 sd_transfer_retry_with_reinit:
 812     if (card_info[drive].initialized <= 0)
 813     {
 814         ret = sd_init_card(drive);
 815         if (!(card_info[drive].initialized))
 816             goto sd_transfer_error_no_dma;
 817     }
 818
 819     /* Check the real block size after the card has been initialized */
 820     real_numblocks = card_info[drive].numblocks;
 821     /* 'start' represents the real (physical) starting sector
 822      *  so we must compare it to the real (physical) number of sectors */
 823     if (drive == INTERNAL_AS3525)
 824         real_numblocks += AMS_OF_SIZE;
 825     if ((start+count) > real_numblocks)
 826     {
 827         ret = -19;
 828         goto sd_transfer_error_no_dma;
 829     }
 830
 831     /*  CMD7 w/rca: Select card to put it in TRAN state */
 832     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 833     {
 834         ret = -20;
 835         goto sd_transfer_error_no_dma;
 836     }
 837
 838     dma_retain();
 839
 840     if(aligned)
 841     {   /* direct transfer, indirect is always uncached */
 842         if(write)
 843             commit_dcache_range(buf, count * SECTOR_SIZE);
 844         else
 845             discard_dcache_range(buf, count * SECTOR_SIZE);
 846     }
 847
 848     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 849     retry_data = retry_data_max;
 850
 851     while (1)
 852     {
 853         void *dma_buf;
 854         unsigned int transfer = count;
 855
 856         last_disk_activity = current_tick;
 857
 858         if(aligned)
 859         {
 860             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 861         }
 862         else
 863         {
 864             dma_buf = AS3525_PHYSICAL_ADDR(&aligned_buffer[0]);
 865             if(transfer > UNALIGNED_NUM_SECTORS)
 866                 transfer = UNALIGNED_NUM_SECTORS;
 867
 868             if(write)
 869                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 870         }
 871
 872         /* Interrupt handler might set this to true during transfer */
 873         retry = false;
 874
 875         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 876
 877         ret = sd_wait_for_tran_state(drive);
 878         if (ret < 0)
 879         {
 880             ret -= 25;
 881             goto sd_transfer_error;
 882         }
 883
 884         int arg = start;
 885         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 886             arg *= SD_BLOCK_SIZE;
 887
 888         if(write)
 889             dma_enable_channel(1, dma_buf, MCI_FIFO, DMA_PERI_SD,
 890                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 891         else
 892             dma_enable_channel(1, MCI_FIFO, dma_buf, DMA_PERI_SD,
 893                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 894
 895         if(!send_cmd(drive, cmd, arg, MCI_RESP, &response))
 896         {
 897             ret = -21;
 898             goto sd_transfer_error;
 899         }
 900
 901         semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 902
 903         last_disk_activity = current_tick;
 904
 905         if(write)
 906         {
 907             /* wait for the card to exit programming state */
 908             while(MCI_STATUS & DATA_BUSY) ;
 909         }
 910
 911         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &response))
 912         {
 913             ret = -22;
 914             goto sd_transfer_error;
 915         }
 916
 917         if(!retry)
 918         {
 919             if(!write && !aligned)
 920                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 921             buf += transfer * SD_BLOCK_SIZE;
 922             start += transfer;
 923             count -= transfer;
 924
 925             if (count > 0)
 926                 continue;
 927         }
 928         else   /*  reset controller if we had an error  */
 929         {
 930             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 931             while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 932                 ;
 933             if (--retry_data >= 0)
 934                 continue;
 935         }
 936
 937         break;
 938     }
 939
 940     dma_release();
 941
 942     /* CMD lines are separate, not common, so we need to actively deselect */
 943     /*  CMD7 w/rca =0 : deselects card & puts it in STBY state */
 944     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 945     {
 946         ret = -23;
 947         goto sd_transfer_error;
 948     }
 949
 950     while (1)
 951     {
 952 #ifndef BOOTLOADER
 953         sd_enable(false);
 954         led(false);
 955 #endif
 956         mutex_unlock(&sd_mtx);
 957         return ret;
 958
 959 sd_transfer_error:
 960         dma_release();
 961
 962 sd_transfer_error_no_dma:
 963         card_info[drive].initialized = 0;
 964
 965         /* .initialized might have been >= 0 but now stale if the ata sd thread
 966          * isn't handling an insert because of USB */
 967         if (--retry_all >= 0)
 968             goto sd_transfer_retry_with_reinit;
 969     }
 970 }
 971
 972 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 973                     void* buf)
 974 {
 975     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 976 }
 977
 978 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 979                      const void* buf)
 980 {
 981     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 982 }
 983
 984 #ifndef BOOTLOADER
 985 long sd_last_disk_activity(void)
 986 {
 987     return last_disk_activity;
 988 }
 989
 990 void sd_enable(bool on)
 991 {
 992     if (on)
 993     {
 994         bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 995         CGU_IDE |= (1<<7);                  /* AHB interface enable */
 996         CGU_MEMSTICK |= (1<<7);             /* interface enable */
 997         CGU_SDSLOT |= (1<<7);               /* interface enable */
 998     }
 999     else
1000     {
1001         CGU_SDSLOT &= ~(1<<7);              /* interface enable */
1002         CGU_MEMSTICK &= ~(1<<7);            /* interface enable */
1003         CGU_IDE &= ~(1<<7);                 /* AHB interface enable */
1004         bitclr32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1005     }
1006 }
1007 #endif /* BOOTLOADER */
1008
1009 tCardInfo *card_get_info_target(int card_no)
1010 {
1011     return &card_info[card_no];
1012 }
1013
1014 #ifdef HAVE_HOTSWAP
1015 bool sd_removable(IF_MD_NONVOID(int drive))
1016 {
1017     return (drive == SD_SLOT_AS3525);
1018 }
1019
1020 bool sd_present(IF_MD_NONVOID(int drive))
1021 {
1022     return (drive == INTERNAL_AS3525) ? true : card_detect_target();
1023 }
1024
1025 static int sd1_oneshot_callback(struct timeout *tmo)
1026 {
1027     (void)tmo;
1028
1029     /* This is called only if the state was stable for 300ms - check state
1030      * and post appropriate event. */
1031     if (card_detect_target())
1032     {
1033         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
1034     }
1035     else
1036         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
1037
1038     return 0;
1039 }
1040
1041 void sd_gpioa_isr(void)
1042 {
1043     static struct timeout sd1_oneshot;
1044
1045     if (GPIOA_MIS & EXT_SD_BITS)
1046     {
1047         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
1048         GPIOA_IC = EXT_SD_BITS; /* acknowledge interrupt */
1049     }
1050 }
1051 #endif /* HAVE_HOTSWAP */
1052
1053 #ifdef CONFIG_STORAGE_MULTI
1054 int sd_num_drives(int first_drive)
1055 {
1056     /* We don't care which logical drive number(s) we have been assigned */
1057     (void)first_drive;
1058
1059     return NUM_DRIVES;
1060 }
1061 #endif /* CONFIG_STORAGE_MULTI */