firmware/target/arm/as3525/sd-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  26 #include "fat.h"
  27 #include "thread.h"
  28 #include "led.h"
  29 #include "sdmmc.h"
  30 #include "system.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "gcc_extensions.h"
  36 #include "as3525.h"
  37 #include "pl180.h"  /* SD controller */
  38 #include "pl081.h"  /* DMA controller */
  39 #include "dma-target.h" /* DMA request lines */
  40 #include "clock-target.h"
  41 #include "panic.h"
  42 #ifdef HAVE_BUTTON_LIGHT
  43 #include "backlight-target.h"
  44 #endif
  45 #include "stdbool.h"
  46 #include "ata_idle_notify.h"
  47 #include "sd.h"
  48 #include "usb.h"
  49 /*#define LOGF_ENABLE*/
  50 #include "logf.h"
  51
  52 #ifdef HAVE_HOTSWAP
  53 #include "disk.h"
  54 #endif
  55
  56 //#define VERIFY_WRITE 1
  57
  58 /* command flags */
  59 #define MCI_NO_RESP     (0<<0)
  60 #define MCI_RESP        (1<<0)
  61 #define MCI_LONG_RESP   (1<<1)
  62 #define MCI_ACMD        (1<<2)
  63 #define MCI_NOCRC       (1<<3)
  64
  65 /* ARM PL180 registers */
  66 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  67 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  68 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  69 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  70 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  71 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  72 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  73 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  74 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  75 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  76 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  77 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  78 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  79 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  80 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  81 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  82 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  83 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  84 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  85
  86 #define MCI_DATA_ERROR    \
  87     ( MCI_DATA_CRC_FAIL   \
  88     | MCI_DATA_TIMEOUT    \
  89     | MCI_TX_UNDERRUN     \
  90     | MCI_RX_OVERRUN      \
  91     | MCI_START_BIT_ERR)
  92
  93 #define MCI_RESPONSE_ERROR    \
  94     ( MCI_CMD_TIMEOUT         \
  95     | MCI_CMD_CRC_FAIL)
  96
  97 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  98 /* volumes */
  99 #define     INTERNAL_AS3525 0   /* embedded SD card */
 100 #define     SD_SLOT_AS3525   1   /* SD slot if present */
 101
 102 static const int pl180_base[NUM_DRIVES] = {
 103             NAND_FLASH_BASE
 104 #ifdef HAVE_MULTIDRIVE
 105             , SD_MCI_BASE
 106 #endif
 107 };
 108
 109 static int sd_wait_for_tran_state(const int drive);
 110 static int sd_select_bank(signed char bank);
 111 static int sd_init_card(const int drive);
 112 static void init_pl180_controller(const int drive);
 113
 114 #define BLOCKS_PER_BANK 0x7a7800u
 115
 116 static tCardInfo card_info[NUM_DRIVES];
 117
 118 /* maximum timeouts recommanded in the SD Specification v2.00 */
 119 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 120 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 121
 122 /* for compatibility */
 123 static long last_disk_activity = -1;
 124
 125 #define MIN_YIELD_PERIOD 5  /* ticks */
 126 static long next_yield = 0;
 127
 128 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 129 static const char         sd_thread_name[] = "ata/sd";
 130 static struct mutex       sd_mtx;
 131 static struct event_queue sd_queue;
 132 bool sd_enabled = false;
 133
 134 #if defined(HAVE_MULTIDRIVE)
 135 static bool hs_card = false;
 136 #define EXT_SD_BITS (1<<2)
 137 #endif
 138
 139 static struct semaphore transfer_completion_signal;
 140 static volatile unsigned int transfer_error[NUM_DRIVES];
 141 #define PL180_MAX_TRANSFER_ERRORS 10
 142
 143 #define UNALIGNED_NUM_SECTORS 10
 144 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 145 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 146
 147
 148 static inline void mci_delay(void) { udelay(1000) ; }
 149
 150
 151 static inline bool card_detect_target(void)
 152 {
 153 #if defined(HAVE_MULTIDRIVE)
 154     return !(GPIOA_PIN(2));
 155 #else
 156     return false;
 157 #endif
 158 }
 159
 160
 161 #ifdef HAVE_HOTSWAP
 162 static int sd1_oneshot_callback(struct timeout *tmo)
 163 {
 164     (void)tmo;
 165
 166     /* This is called only if the state was stable for 300ms - check state
 167      * and post appropriate event. */
 168     if (card_detect_target())
 169     {
 170         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 171     }
 172     else
 173         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 174
 175     return 0;
 176 }
 177
 178 void sd_gpioa_isr(void)
 179 {
 180     static struct timeout sd1_oneshot;
 181     if (GPIOA_MIS & EXT_SD_BITS)
 182         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 183     /* acknowledge interrupt */
 184     GPIOA_IC = EXT_SD_BITS;
 185 }
 186 #endif  /* HAVE_HOTSWAP */
 187
 188 void INT_NAND(void)
 189 {
 190     const int status = MCI_STATUS(INTERNAL_AS3525);
 191
 192     transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
 193
 194     semaphore_release(&transfer_completion_signal);
 195     MCI_CLEAR(INTERNAL_AS3525) = status;
 196 }
 197
 198 #ifdef HAVE_MULTIDRIVE
 199 void INT_MCI0(void)
 200 {
 201     const int status = MCI_STATUS(SD_SLOT_AS3525);
 202
 203     transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
 204
 205     semaphore_release(&transfer_completion_signal);
 206     MCI_CLEAR(SD_SLOT_AS3525) = status;
 207 }
 208 #endif
 209
 210 static bool send_cmd(const int drive, const int cmd, const int arg,
 211                      const int flags, long *response)
 212 {
 213     int status;
 214
 215     unsigned cmd_retries = 6;
 216     while(cmd_retries--)
 217     {
 218         if ((flags & MCI_ACMD) && /* send SD_APP_CMD before each try */
 219             !send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, response))
 220             return false;
 221
 222         /* Clear old status flags */
 223         MCI_CLEAR(drive) = 0x7ff;
 224
 225         /* Load command argument or clear if none */
 226         MCI_ARGUMENT(drive) = arg;
 227
 228         /* Construct MCI_COMMAND & enable CPSM */
 229         MCI_COMMAND(drive) =
 230            /*b0:5*/  cmd
 231            /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 232            /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 233            /* b8   | MCI_COMMAND_INTERRUPT */
 234            /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 235            /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 236
 237         /* Wait while cmd completes then disable CPSM */
 238         while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 239         MCI_COMMAND(drive) = 0;
 240
 241         status = MCI_STATUS(drive);
 242
 243         /*  Handle command responses */
 244         if(flags & MCI_RESP)                /* CMD expects response */
 245         {
 246             response[0] = MCI_RESP0(drive); /* Always prepare short response */
 247
 248             if(status & MCI_RESPONSE_ERROR) {/* timeout or crc failure */
 249                 if ((status & MCI_CMD_CRC_FAIL) &&
 250                     (flags & MCI_NOCRC))
 251                     break;
 252                 logf("sd cmd error: drive %d cmd %d arg %08x sd_status %08x resp0 %08lx",
 253                      drive, cmd, arg, status, response[0]);
 254                 continue;
 255             }
 256
 257             if((flags & MCI_RESP) &&
 258                !(flags & MCI_LONG_RESP) &&
 259                (response[0] & SD_R1_CARD_ERROR)) {
 260                 logf("sd card error: drive %d cmd %d arg %08x r1 %08lx",
 261                      drive, cmd, arg, response[0]);
 262             }
 263
 264             if(status & MCI_CMD_RESP_END)   /* Response passed CRC check */
 265             {
 266                 if(flags & MCI_LONG_RESP)
 267                 {   /* response[0] has already been read */
 268                     response[1] = MCI_RESP1(drive);
 269                     response[2] = MCI_RESP2(drive);
 270                     response[3] = MCI_RESP3(drive);
 271                 }
 272                 return true;
 273             }
 274         }
 275         else if(status & MCI_CMD_SENT)  /* CMD sent, no response required */
 276             return true;
 277     }
 278
 279     return false;
 280 }
 281
 282 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 283 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 284 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 285 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 286
 287 static int sd_init_card(const int drive)
 288 {
 289     unsigned long response;
 290     long init_timeout;
 291     bool sd_v2 = false;
 292
 293     card_info[drive].rca = 0;
 294
 295     /* MCLCK on and set to 400kHz ident frequency  */
 296     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 297
 298     /* 100 - 400kHz clock required for Identification Mode  */
 299     /*  Start of Card Identification Mode ************************************/
 300
 301     /* CMD0 Go Idle  */
 302     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 303         return -1;
 304     mci_delay();
 305
 306     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 307       Non v2 cards will not respond to this command*/
 308     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 309         if((response & 0xFFF) == 0x1AA)
 310             sd_v2 = true;
 311
 312     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 313     init_timeout = current_tick + HZ;
 314
 315     do {
 316         /* this timeout is the only valid error for this loop*/
 317         if(TIME_AFTER(current_tick, init_timeout))
 318             return -2;
 319
 320         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 321         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 322                         MCI_ACMD|MCI_NOCRC|MCI_RESP, &card_info[drive].ocr);
 323
 324     } while(!(card_info[drive].ocr & (1<<31)));
 325
 326     /* CMD2 send CID */
 327     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP,
 328                             card_info[drive].cid))
 329         return -3;
 330
 331     /* CMD3 send RCA */
 332     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP,
 333                 &card_info[drive].rca))
 334         return -4;
 335
 336     /*  End of Card Identification Mode   ************************************/
 337
 338 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 339
 340     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 341     if(sd_v2)
 342     {
 343         /*  CMD7 w/rca: Select card to put it in TRAN state */
 344         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 345             return -5;
 346
 347         if(sd_wait_for_tran_state(drive))
 348             return -6;
 349         /* CMD6 */
 350         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 351             return -7;
 352         sleep(HZ/10);
 353
 354         /*  go back to STBY state so we can read csd */
 355         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 356         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 357             return -8;
 358         mci_delay();
 359     }
 360 #endif /*  HAVE_MULTIDRIVE  */
 361
 362     /* CMD9 send CSD */
 363     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 364                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 365         return -9;
 366
 367     sd_parse_csd(&card_info[drive]);
 368
 369 #if defined(HAVE_MULTIDRIVE)
 370     hs_card = (card_info[drive].speed == 50000000);
 371 #endif
 372
 373     /* Boost MCICLK to operating speed */
 374     if(drive == INTERNAL_AS3525)
 375         MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
 376 #if defined(HAVE_MULTIDRIVE)
 377     else
 378         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
 379         MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
 380 #endif
 381
 382     /*  CMD7 w/rca: Select card to put it in TRAN state */
 383     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 384         return -10;
 385
 386 #if 0 /* FIXME : it seems that reading fails on some models */
 387     /*  Switch to to 4 bit widebus mode  */
 388     if(sd_wait_for_tran_state(drive) < 0)
 389         return -11;
 390     /* ACMD42  */
 391     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ACMD|MCI_RESP, &response))
 392         return -15;
 393     /* ACMD6  */
 394     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ACMD|MCI_RESP, &response))
 395         return -13;
 396     /* Now that card is widebus make controller aware */
 397     MCI_CLOCK(drive) |= MCI_CLOCK_WIDEBUS;
 398 #endif
 399
 400     /*
 401      * enable bank switching
 402      * without issuing this command, we only have access to 1/4 of the blocks
 403      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 404      * CSD register)
 405      */
 406     if(drive == INTERNAL_AS3525)
 407     {
 408         const int ret = sd_select_bank(-1);
 409         if(ret < 0)
 410             return ret -16;
 411
 412         /*  CMD7 w/rca = 0: Unselect card to put it in STBY state */
 413         if(!send_cmd(drive, SD_SELECT_CARD, 0, MCI_NO_RESP, NULL))
 414             return -17;
 415         mci_delay();
 416
 417         /* CMD9 send CSD again, so we got the correct number of blocks */
 418         if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 419                      MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 420             return -18;
 421
 422         sd_parse_csd(&card_info[drive]);
 423         /* The OF is stored in the first blocks */
 424         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 425
 426         /*  CMD7 w/rca: Select card to put it in TRAN state */
 427         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 428             return -19;
 429     }
 430
 431     card_info[drive].initialized = 1;
 432
 433     return 0;
 434 }
 435
 436 static void sd_thread(void) NORETURN_ATTR;
 437 static void sd_thread(void)
 438 {
 439     struct queue_event ev;
 440     bool idle_notified = false;
 441
 442     while (1)
 443     {
 444         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 445
 446         switch ( ev.id )
 447         {
 448 #ifdef HAVE_HOTSWAP
 449         case SYS_HOTSWAP_INSERTED:
 450         case SYS_HOTSWAP_EXTRACTED:
 451         {
 452             int microsd_init = 1;
 453             fat_lock();          /* lock-out FAT activity first -
 454                                     prevent deadlocking via disk_mount that
 455                                     would cause a reverse-order attempt with
 456                                     another thread */
 457             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 458                                     into driver that bypass the fat cache */
 459
 460             /* We now have exclusive control of fat cache and ata */
 461
 462             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 463                                     descriptors aren't leaked and any busy
 464                                     ones are invalid if mounting */
 465
 466             /* Force card init for new card, re-init for re-inserted one or
 467              * clear if the last attempt to init failed with an error. */
 468             card_info[SD_SLOT_AS3525].initialized = 0;
 469
 470             if (ev.id == SYS_HOTSWAP_INSERTED)
 471             {
 472                 sd_enable(true);
 473                 init_pl180_controller(SD_SLOT_AS3525);
 474                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 475                 if (microsd_init < 0) /* initialisation failed */
 476                     panicf("microSD init failed : %d", microsd_init);
 477
 478                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 479             }
 480
 481             /*
 482              * Mount succeeded, or this was an EXTRACTED event,
 483              * in both cases notify the system about the changed filesystems
 484              */
 485             if (microsd_init)
 486                 queue_broadcast(SYS_FS_CHANGED, 0);
 487
 488             /* Access is now safe */
 489             mutex_unlock(&sd_mtx);
 490             fat_unlock();
 491             sd_enable(false);
 492         }
 493             break;
 494 #endif
 495         case SYS_TIMEOUT:
 496             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 497             {
 498                 idle_notified = false;
 499             }
 500             else
 501             {
 502                 /* never let a timer wrap confuse us */
 503                 next_yield = current_tick;
 504
 505                 if (!idle_notified)
 506                 {
 507                     call_storage_idle_notifys(false);
 508                     idle_notified = true;
 509                 }
 510             }
 511             break;
 512
 513         case SYS_USB_CONNECTED:
 514             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 515             /* Wait until the USB cable is extracted again */
 516             usb_wait_for_disconnect(&sd_queue);
 517
 518             break;
 519         }
 520     }
 521 }
 522
 523 static void init_pl180_controller(const int drive)
 524 {
 525     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 526     MCI_CLEAR(drive) = 0x7ff;
 527
 528     MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
 529     MCI_MASK1(drive) = 0;
 530 #ifdef HAVE_MULTIDRIVE
 531     VIC_INT_ENABLE =
 532         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 533     /* clear previous irq */
 534     GPIOA_IC = EXT_SD_BITS;
 535     /* enable edge detecting */
 536     GPIOA_IS &= ~EXT_SD_BITS;
 537     /* detect both raising and falling edges */
 538     GPIOA_IBE |= EXT_SD_BITS;
 539     /* enable the card detect interrupt */
 540     GPIOA_IE |= EXT_SD_BITS;
 541
 542 #else
 543     VIC_INT_ENABLE = INTERRUPT_NAND;
 544 #endif
 545
 546     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 547     mci_delay();
 548
 549     MCI_POWER(drive) |= MCI_POWER_ON;
 550     mci_delay();
 551
 552     MCI_SELECT(drive) = 0;
 553
 554     /* Pl180 clocks get turned on at start of card init */
 555 }
 556
 557 int sd_init(void)
 558 {
 559     int ret;
 560     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 561             |   (AS3525_IDE_DIV << 2)
 562             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 563
 564     bitset32(&CGU_PERI, CGU_NAF_CLOCK_ENABLE);
 565 #ifdef HAVE_MULTIDRIVE
 566     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 567     bitmod32(&CCU_IO, 1<<2, 3<<2);  /* bits 3:2 = 01, xpd is SD interface */
 568 #endif
 569
 570     semaphore_init(&transfer_completion_signal, 1, 0);
 571
 572     init_pl180_controller(INTERNAL_AS3525);
 573     ret = sd_init_card(INTERNAL_AS3525);
 574     if(ret < 0)
 575         return ret;
 576 #ifdef HAVE_MULTIDRIVE
 577     init_pl180_controller(SD_SLOT_AS3525);
 578 #endif
 579
 580     /* init mutex */
 581     mutex_init(&sd_mtx);
 582
 583     queue_init(&sd_queue, true);
 584     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 585             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 586
 587     sd_enabled = true;
 588     sd_enable(false);
 589
 590     return 0;
 591 }
 592
 593 #ifdef HAVE_HOTSWAP
 594 bool sd_removable(IF_MD_NONVOID(int drive))
 595 {
 596     return (drive == SD_SLOT_AS3525);
 597 }
 598
 599 bool sd_present(IF_MD_NONVOID(int drive))
 600 {
 601     return (drive == INTERNAL_AS3525) ? true : card_detect_target();
 602 }
 603 #endif /* HAVE_HOTSWAP */
 604
 605 static int sd_wait_for_tran_state(const int drive)
 606 {
 607     unsigned long response = 0;
 608     unsigned int timeout = current_tick + 5 * HZ;
 609
 610     while (1)
 611     {
 612         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
 613                     &response))
 614             return -1;
 615
 616         if (((response >> 9) & 0xf) == SD_TRAN)
 617             return 0;
 618
 619         if(TIME_AFTER(current_tick, timeout))
 620             return -2;
 621
 622         if (TIME_AFTER(current_tick, next_yield))
 623         {
 624             yield();
 625             next_yield = current_tick + MIN_YIELD_PERIOD;
 626         }
 627     }
 628 }
 629
 630 static int sd_select_bank(signed char bank)
 631 {
 632     int ret;
 633     unsigned loops = 0;
 634
 635     memset(uncached_buffer, 0, 512);
 636     if(bank == -1)
 637     {   /* enable bank switching */
 638         uncached_buffer[0] = 16;
 639         uncached_buffer[1] = 1;
 640         uncached_buffer[2] = 10;
 641     }
 642     else
 643         uncached_buffer[0] = bank;
 644
 645     do {
 646         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 647             panicf("SD bank %d error : 0x%x", bank,
 648                     transfer_error[INTERNAL_AS3525]);
 649
 650         ret = sd_wait_for_tran_state(INTERNAL_AS3525);
 651         if (ret < 0)
 652             return ret - 2;
 653
 654         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_NO_RESP,
 655                      NULL))
 656             return -1;
 657
 658         mci_delay();
 659
 660         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_RESP, NULL))
 661             return -2;
 662
 663         mci_delay();
 664
 665         dma_retain();
 666         /* we don't use the uncached buffer here, because we need the
 667          * physical memory address for DMA transfers */
 668         dma_enable_channel(0, AS3525_PHYSICAL_ADDR(&aligned_buffer[0]),
 669             MCI_FIFO(INTERNAL_AS3525), DMA_PERI_SD,
 670             DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 671
 672         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 673         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 674         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 675                                 (0<<1) /* transfer direction */ |
 676                                 (1<<3) /* DMA */                |
 677                                 (9<<4) /* 2^9 = 512 */ ;
 678
 679         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 680         semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 681
 682         /*  Wait for FIFO to empty, card may still be in PRG state  */
 683         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 684
 685         dma_release();
 686
 687     } while(transfer_error[INTERNAL_AS3525]);
 688
 689     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 690
 691     return 0;
 692 }
 693
 694 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 695                                int count, void* buf, const bool write)
 696 {
 697 #ifndef HAVE_MULTIDRIVE
 698     const int drive = 0;
 699 #endif
 700     int ret = 0;
 701     unsigned loops = 0;
 702     unsigned long response;
 703     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 704
 705     sd_enable(true);
 706     led(true);
 707
 708     if (card_info[drive].initialized <= 0)
 709     {
 710         ret = sd_init_card(drive);
 711         if (!(card_info[drive].initialized))
 712             goto sd_transfer_error_nodma;
 713     }
 714
 715     if(count < 0) /* XXX: why is it signed ? */
 716     {
 717         ret = -20;
 718         goto sd_transfer_error_nodma;
 719     }
 720     if((start+count) > card_info[drive].numblocks)
 721     {
 722         ret = -21;
 723         goto sd_transfer_error_nodma;
 724     }
 725
 726     /* skip SanDisk OF */
 727     if (drive == INTERNAL_AS3525)
 728         start += AMS_OF_SIZE;
 729
 730     last_disk_activity = current_tick;
 731
 732     dma_retain();
 733
 734     if(aligned)
 735     {   /* direct transfer, indirect is always uncached */
 736         if(write)
 737             commit_dcache_range(buf, count * SECTOR_SIZE);
 738         else
 739             discard_dcache_range(buf, count * SECTOR_SIZE);
 740     }
 741
 742     while(count)
 743     {
 744         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 745          * register, so we have to transfer maximum 127 sectors at a time. */
 746         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 747         void *dma_buf;
 748         const int cmd =
 749             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 750         unsigned long bank_start = start;
 751         unsigned long status;
 752
 753         /* Only switch banks for internal storage */
 754         if(drive == INTERNAL_AS3525)
 755         {
 756             unsigned int bank = 0;
 757             while(bank_start >= BLOCKS_PER_BANK)
 758             {
 759                 bank_start -= BLOCKS_PER_BANK;
 760                 bank++;
 761             }
 762
 763             /* Switch bank if needed */
 764             if(card_info[INTERNAL_AS3525].current_bank != bank)
 765             {
 766                 ret = sd_select_bank(bank);
 767                 if (ret < 0)
 768                 {
 769                     ret -= 20;
 770                     goto sd_transfer_error;
 771                 }
 772             }
 773
 774             /* Do not cross a bank boundary in a single transfer loop */
 775             if((transfer + bank_start) > BLOCKS_PER_BANK)
 776                 transfer = BLOCKS_PER_BANK - bank_start;
 777         }
 778
 779         /* Set bank_start to the correct unit (blocks or bytes) */
 780         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 781             bank_start *= SD_BLOCK_SIZE;
 782
 783         if(aligned)
 784         {
 785             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 786         }
 787         else
 788         {
 789             dma_buf = AS3525_PHYSICAL_ADDR(&aligned_buffer[0]);
 790             if(transfer > UNALIGNED_NUM_SECTORS)
 791                 transfer = UNALIGNED_NUM_SECTORS;
 792
 793             if(write)
 794                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 795         }
 796
 797         ret = sd_wait_for_tran_state(drive);
 798         if (ret < 0)
 799         {
 800             ret -= 2*20;
 801             goto sd_transfer_error;
 802         }
 803
 804         if(!send_cmd(drive, cmd, bank_start, MCI_RESP, &response))
 805         {
 806             ret -= 3*20;
 807             goto sd_transfer_error;
 808         }
 809
 810         if(write)
 811         {
 812             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 813                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 814                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 815
 816             /*Small delay for writes prevents data crc failures at lower freqs*/
 817 #ifdef HAVE_MULTIDRIVE
 818             if((drive == SD_SLOT_AS3525) && !hs_card)
 819             {
 820                 int write_delay = 125;
 821                 while(write_delay--);
 822             }
 823 #endif
 824         }
 825         else
 826             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 827                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 828                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 829
 830         MCI_DATA_TIMER(drive) = write ?
 831                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 832         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 833         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 834                                 (!write<<1) /* transfer direction */    |
 835                                 (1<<3) /* DMA */                        |
 836                                 (9<<4) /* 2^9 = 512 */ ;
 837
 838         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 839         semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 840
 841         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 842         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 843
 844         /*
 845          * If the write aborted early due to a tx underrun, disable the
 846          * dma channel here, otherwise there are still 4 words in the fifo
 847          * and the retried write will get corrupted.
 848          */
 849         dma_disable_channel(0);
 850
 851         last_disk_activity = current_tick;
 852
 853         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &status))
 854         {
 855             ret = -4*20;
 856             goto sd_transfer_error;
 857         }
 858
 859         if(!transfer_error[drive])
 860         {
 861             if(!write && !aligned)
 862                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 863             buf += transfer * SD_BLOCK_SIZE;
 864             start += transfer;
 865             count -= transfer;
 866             loops = 0;  /* reset errors counter */
 867         }
 868         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 869                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 870                                                   transfer_error[drive], drive);
 871     }
 872
 873 sd_transfer_error:
 874
 875     dma_release();
 876
 877 sd_transfer_error_nodma:
 878
 879     led(false);
 880     sd_enable(false);
 881
 882     if (ret)    /* error */
 883         card_info[drive].initialized = 0;
 884
 885     return ret;
 886 }
 887
 888 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 889                      void* buf)
 890 {
 891     int ret;
 892
 893     mutex_lock(&sd_mtx);
 894     ret = sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 895     mutex_unlock(&sd_mtx);
 896
 897     return ret;
 898 }
 899
 900 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 901                      const void* buf)
 902 {
 903 #ifdef VERIFY_WRITE
 904     unsigned long saved_start = start;
 905     int saved_count = count;
 906     void *saved_buf = (void*)buf;
 907 #endif
 908     int ret;
 909
 910     mutex_lock(&sd_mtx);
 911
 912     ret = sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 913
 914 #ifdef VERIFY_WRITE
 915     if (ret) {
 916         /* write failed, no point in verifying */
 917         mutex_unlock(&sd_mtx);
 918         return ret;
 919     }
 920
 921     count = saved_count;
 922     buf = saved_buf;
 923     start = saved_start;
 924     while (count) {
 925         int transfer = count;
 926         if(transfer > UNALIGNED_NUM_SECTORS)
 927             transfer = UNALIGNED_NUM_SECTORS;
 928
 929         sd_transfer_sectors(IF_MD2(drive,) start, transfer, aligned_buffer, false);
 930         if (memcmp(buf, aligned_buffer, transfer * 512) != 0) {
 931             /* try the write again in the hope to repair the damage */
 932             sd_transfer_sectors(IF_MD2(drive,) saved_start, saved_count, saved_buf, true);
 933             panicf("sd: verify failed: sec=%ld n=%d!", start, transfer);
 934         }
 935
 936         buf   += transfer * 512;
 937         count -= transfer;
 938         start += transfer;
 939     }
 940 #endif
 941
 942     mutex_unlock(&sd_mtx);
 943
 944     return ret;
 945 }
 946
 947 long sd_last_disk_activity(void)
 948 {
 949     return last_disk_activity;
 950 }
 951
 952 void sd_enable(bool on)
 953 {
 954 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 955     extern int buttonlight_is_on;
 956 #endif
 957
 958 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 959     static bool cpu_boosted = false;
 960 #endif
 961
 962     if (sd_enabled == on)
 963         return; /* nothing to do */
 964
 965     sd_enabled = on;
 966
 967     if(on)
 968     {
 969 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 970         /* buttonlight AMSes need a bit of special handling for the buttonlight
 971          * here due to the dual mapping of GPIOD and XPD */
 972         bitmod32(&CCU_IO, 1<<2, 3<<2);  /* XPD is SD-MCI interface (b3:2 = 01) */
 973         if (buttonlight_is_on)
 974             GPIOD_DIR &= ~(1<<7);
 975         else
 976             _buttonlight_off();
 977 #endif
 978
 979 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 980         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 981         {
 982             cpu_boosted = true;
 983             cpu_boost(true);
 984         }
 985 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 986     }
 987     else
 988     {
 989 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 990         if(cpu_boosted)
 991         {
 992             cpu_boost(false);
 993             cpu_boosted = false;
 994         }
 995 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 996
 997 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 998         bitmod32(&CCU_IO, 0<<2, 3<<2);  /* XPD is general purpose IO (b3:2 = 00) */
 999         if (buttonlight_is_on)
1000             _buttonlight_on();
1001 #endif
1002     }
1003 }
1004
1005 tCardInfo *card_get_info_target(int card_no)
1006 {
1007     return &card_info[card_no];
1008 }
1009
1010 #ifdef CONFIG_STORAGE_MULTI
1011 int sd_num_drives(int first_drive)
1012 {
1013     /* We don't care which logical drive number(s) we have been assigned */
1014     (void)first_drive;
1015
1016     return NUM_DRIVES;
1017 }
1018 #endif /* CONFIG_STORAGE_MULTI */