firmware/target/arm/as3525/sd-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  26 #include "fat.h"
  27 #include "thread.h"
  28 #include "led.h"
  29 #include "sdmmc.h"
  30 #include "system.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "gcc_extensions.h"
  36 #include "as3525.h"
  37 #include "pl180.h"  /* SD controller */
  38 #include "pl081.h"  /* DMA controller */
  39 #include "dma-target.h" /* DMA request lines */
  40 #include "clock-target.h"
  41 #include "panic.h"
  42 #ifdef HAVE_BUTTON_LIGHT
  43 #include "backlight-target.h"
  44 #endif
  45 #include "stdbool.h"
  46 #include "ata_idle_notify.h"
  47 #include "sd.h"
  48 #include "usb.h"
  49 /*#define LOGF_ENABLE*/
  50 #include "logf.h"
  51
  52 #ifdef HAVE_HOTSWAP
  53 #include "disk.h"
  54 #endif
  55
  56 //#define VERIFY_WRITE 1
  57
  58 /* command flags */
  59 #define MCI_NO_RESP     (0<<0)
  60 #define MCI_RESP        (1<<0)
  61 #define MCI_LONG_RESP   (1<<1)
  62 #define MCI_ACMD        (1<<2)
  63 #define MCI_NOCRC       (1<<3)
  64
  65 /* ARM PL180 registers */
  66 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  67 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  68 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  69 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  70 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  71 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  72 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  73 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  74 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  75 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  76 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  77 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  78 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  79 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  80 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  81 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  82 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  83 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  84 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  85
  86 #define MCI_DATA_ERROR    \
  87     ( MCI_DATA_CRC_FAIL   \
  88     | MCI_DATA_TIMEOUT    \
  89     | MCI_TX_UNDERRUN     \
  90     | MCI_RX_OVERRUN      \
  91     | MCI_START_BIT_ERR)
  92
  93 #define MCI_RESPONSE_ERROR    \
  94     ( MCI_CMD_TIMEOUT         \
  95     | MCI_CMD_CRC_FAIL)
  96
  97 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  98 /* volumes */
  99 #define     INTERNAL_AS3525 0   /* embedded SD card */
 100 #define     SD_SLOT_AS3525   1   /* SD slot if present */
 101
 102 static const int pl180_base[NUM_DRIVES] = {
 103             NAND_FLASH_BASE
 104 #ifdef HAVE_MULTIDRIVE
 105             , SD_MCI_BASE
 106 #endif
 107 };
 108
 109 static int sd_wait_for_tran_state(const int drive);
 110 static int sd_select_bank(signed char bank);
 111 static int sd_init_card(const int drive);
 112 static void init_pl180_controller(const int drive);
 113
 114 #define BLOCKS_PER_BANK 0x7a7800u
 115
 116 static tCardInfo card_info[NUM_DRIVES];
 117
 118 /* maximum timeouts recommanded in the SD Specification v2.00 */
 119 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 120 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 121
 122 /* for compatibility */
 123 static long last_disk_activity = -1;
 124
 125 #define MIN_YIELD_PERIOD 5  /* ticks */
 126 static long next_yield = 0;
 127
 128 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 129 static const char         sd_thread_name[] = "ata/sd";
 130 static struct mutex       sd_mtx;
 131 static struct event_queue sd_queue;
 132 bool sd_enabled = false;
 133
 134 #if defined(HAVE_MULTIDRIVE)
 135 static bool hs_card = false;
 136 #define EXT_SD_BITS (1<<2)
 137 #endif
 138
 139 static struct semaphore transfer_completion_signal;
 140 static volatile unsigned int transfer_error[NUM_DRIVES];
 141 #define PL180_MAX_TRANSFER_ERRORS 10
 142
 143 #define UNALIGNED_NUM_SECTORS 10
 144 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 145 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 146
 147
 148 static inline void mci_delay(void) { udelay(1000) ; }
 149
 150
 151 static inline bool card_detect_target(void)
 152 {
 153 #if defined(HAVE_MULTIDRIVE)
 154     return !(GPIOA_PIN(2));
 155 #else
 156     return false;
 157 #endif
 158 }
 159
 160
 161 #ifdef HAVE_HOTSWAP
 162 static int sd1_oneshot_callback(struct timeout *tmo)
 163 {
 164     (void)tmo;
 165
 166     /* This is called only if the state was stable for 300ms - check state
 167      * and post appropriate event. */
 168     if (card_detect_target())
 169     {
 170         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 171     }
 172     else
 173         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 174
 175     return 0;
 176 }
 177
 178 void sd_gpioa_isr(void)
 179 {
 180     static struct timeout sd1_oneshot;
 181
 182     if (GPIOA_MIS & EXT_SD_BITS)
 183     {
 184         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 185         GPIOA_IC = EXT_SD_BITS; /* acknowledge interrupt */
 186     }
 187 }
 188 #endif  /* HAVE_HOTSWAP */
 189
 190 void INT_NAND(void)
 191 {
 192     const int status = MCI_STATUS(INTERNAL_AS3525);
 193
 194     transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
 195
 196     semaphore_release(&transfer_completion_signal);
 197     MCI_CLEAR(INTERNAL_AS3525) = status;
 198 }
 199
 200 #ifdef HAVE_MULTIDRIVE
 201 void INT_MCI0(void)
 202 {
 203     const int status = MCI_STATUS(SD_SLOT_AS3525);
 204
 205     transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
 206
 207     semaphore_release(&transfer_completion_signal);
 208     MCI_CLEAR(SD_SLOT_AS3525) = status;
 209 }
 210 #endif
 211
 212 static bool send_cmd(const int drive, const int cmd, const int arg,
 213                      const int flags, long *response)
 214 {
 215     int status;
 216
 217     unsigned cmd_retries = 6;
 218     while(cmd_retries--)
 219     {
 220         if ((flags & MCI_ACMD) && /* send SD_APP_CMD before each try */
 221             !send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, response))
 222             return false;
 223
 224         /* Clear old status flags */
 225         MCI_CLEAR(drive) = 0x7ff;
 226
 227         /* Load command argument or clear if none */
 228         MCI_ARGUMENT(drive) = arg;
 229
 230         /* Construct MCI_COMMAND & enable CPSM */
 231         MCI_COMMAND(drive) =
 232            /*b0:5*/  cmd
 233            /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 234            /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 235            /* b8   | MCI_COMMAND_INTERRUPT */
 236            /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 237            /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 238
 239         /* Wait while cmd completes then disable CPSM */
 240         while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 241         MCI_COMMAND(drive) = 0;
 242
 243         status = MCI_STATUS(drive);
 244
 245         /*  Handle command responses */
 246         if(flags & MCI_RESP)                /* CMD expects response */
 247         {
 248             response[0] = MCI_RESP0(drive); /* Always prepare short response */
 249
 250             if(status & MCI_RESPONSE_ERROR) {/* timeout or crc failure */
 251                 if ((status & MCI_CMD_CRC_FAIL) &&
 252                     (flags & MCI_NOCRC))
 253                     break;
 254                 logf("sd cmd error: drive %d cmd %d arg %08x sd_status %08x resp0 %08lx",
 255                      drive, cmd, arg, status, response[0]);
 256                 continue;
 257             }
 258
 259             if((flags & MCI_RESP) &&
 260                !(flags & MCI_LONG_RESP) &&
 261                (response[0] & SD_R1_CARD_ERROR)) {
 262                 logf("sd card error: drive %d cmd %d arg %08x r1 %08lx",
 263                      drive, cmd, arg, response[0]);
 264             }
 265
 266             if(status & MCI_CMD_RESP_END)   /* Response passed CRC check */
 267             {
 268                 if(flags & MCI_LONG_RESP)
 269                 {   /* response[0] has already been read */
 270                     response[1] = MCI_RESP1(drive);
 271                     response[2] = MCI_RESP2(drive);
 272                     response[3] = MCI_RESP3(drive);
 273                 }
 274                 return true;
 275             }
 276         }
 277         else if(status & MCI_CMD_SENT)  /* CMD sent, no response required */
 278             return true;
 279     }
 280
 281     return false;
 282 }
 283
 284 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 285 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 286 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 287 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 288
 289 static int sd_init_card(const int drive)
 290 {
 291     unsigned long response;
 292     long init_timeout;
 293     bool sd_v2 = false;
 294
 295     card_info[drive].rca = 0;
 296
 297     /* MCLCK on and set to 400kHz ident frequency  */
 298     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 299
 300     /* 100 - 400kHz clock required for Identification Mode  */
 301     /*  Start of Card Identification Mode ************************************/
 302
 303     /* CMD0 Go Idle  */
 304     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 305         return -1;
 306     mci_delay();
 307
 308     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 309       Non v2 cards will not respond to this command*/
 310     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 311         if((response & 0xFFF) == 0x1AA)
 312             sd_v2 = true;
 313
 314     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 315     init_timeout = current_tick + HZ;
 316
 317     do {
 318         /* this timeout is the only valid error for this loop*/
 319         if(TIME_AFTER(current_tick, init_timeout))
 320             return -2;
 321
 322         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 323         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 324                         MCI_ACMD|MCI_NOCRC|MCI_RESP, &card_info[drive].ocr);
 325
 326     } while(!(card_info[drive].ocr & (1<<31)));
 327
 328     /* CMD2 send CID */
 329     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP,
 330                             card_info[drive].cid))
 331         return -3;
 332
 333     /* CMD3 send RCA */
 334     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP,
 335                 &card_info[drive].rca))
 336         return -4;
 337
 338     /*  End of Card Identification Mode   ************************************/
 339
 340 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 341
 342     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 343     if(sd_v2)
 344     {
 345         /*  CMD7 w/rca: Select card to put it in TRAN state */
 346         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 347             return -5;
 348
 349         if(sd_wait_for_tran_state(drive))
 350             return -6;
 351         /* CMD6 */
 352         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 353             return -7;
 354         sleep(HZ/10);
 355
 356         /*  go back to STBY state so we can read csd */
 357         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 358         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 359             return -8;
 360         mci_delay();
 361     }
 362 #endif /*  HAVE_MULTIDRIVE  */
 363
 364     /* CMD9 send CSD */
 365     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 366                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 367         return -9;
 368
 369     sd_parse_csd(&card_info[drive]);
 370
 371 #if defined(HAVE_MULTIDRIVE)
 372     hs_card = (card_info[drive].speed == 50000000);
 373 #endif
 374
 375     /* Boost MCICLK to operating speed */
 376     if(drive == INTERNAL_AS3525)
 377         MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
 378 #if defined(HAVE_MULTIDRIVE)
 379     else
 380         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
 381         MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
 382 #endif
 383
 384     /*  CMD7 w/rca: Select card to put it in TRAN state */
 385     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 386         return -10;
 387
 388 #if 0 /* FIXME : it seems that reading fails on some models */
 389     /*  Switch to to 4 bit widebus mode  */
 390     if(sd_wait_for_tran_state(drive) < 0)
 391         return -11;
 392     /* ACMD42  */
 393     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_ACMD|MCI_RESP, &response))
 394         return -15;
 395     /* ACMD6  */
 396     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_ACMD|MCI_RESP, &response))
 397         return -13;
 398     /* Now that card is widebus make controller aware */
 399     MCI_CLOCK(drive) |= MCI_CLOCK_WIDEBUS;
 400 #endif
 401
 402     /*
 403      * enable bank switching
 404      * without issuing this command, we only have access to 1/4 of the blocks
 405      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 406      * CSD register)
 407      */
 408     if(drive == INTERNAL_AS3525)
 409     {
 410         const int ret = sd_select_bank(-1);
 411         if(ret < 0)
 412             return ret -16;
 413
 414         /*  CMD7 w/rca = 0: Unselect card to put it in STBY state */
 415         if(!send_cmd(drive, SD_SELECT_CARD, 0, MCI_NO_RESP, NULL))
 416             return -17;
 417         mci_delay();
 418
 419         /* CMD9 send CSD again, so we got the correct number of blocks */
 420         if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 421                      MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 422             return -18;
 423
 424         sd_parse_csd(&card_info[drive]);
 425         /* The OF is stored in the first blocks */
 426         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 427
 428         /*  CMD7 w/rca: Select card to put it in TRAN state */
 429         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 430             return -19;
 431     }
 432
 433     card_info[drive].initialized = 1;
 434
 435     return 0;
 436 }
 437
 438 static void sd_thread(void) NORETURN_ATTR;
 439 static void sd_thread(void)
 440 {
 441     struct queue_event ev;
 442     bool idle_notified = false;
 443
 444     while (1)
 445     {
 446         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 447
 448         switch ( ev.id )
 449         {
 450 #ifdef HAVE_HOTSWAP
 451         case SYS_HOTSWAP_INSERTED:
 452         case SYS_HOTSWAP_EXTRACTED:
 453         {
 454             int microsd_init = 1;
 455             fat_lock();          /* lock-out FAT activity first -
 456                                     prevent deadlocking via disk_mount that
 457                                     would cause a reverse-order attempt with
 458                                     another thread */
 459             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 460                                     into driver that bypass the fat cache */
 461
 462             /* We now have exclusive control of fat cache and ata */
 463
 464             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 465                                     descriptors aren't leaked and any busy
 466                                     ones are invalid if mounting */
 467
 468             /* Force card init for new card, re-init for re-inserted one or
 469              * clear if the last attempt to init failed with an error. */
 470             card_info[SD_SLOT_AS3525].initialized = 0;
 471
 472             if (ev.id == SYS_HOTSWAP_INSERTED)
 473             {
 474                 sd_enable(true);
 475                 init_pl180_controller(SD_SLOT_AS3525);
 476                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 477                 if (microsd_init < 0) /* initialisation failed */
 478                     panicf("microSD init failed : %d", microsd_init);
 479
 480                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 481             }
 482
 483             /*
 484              * Mount succeeded, or this was an EXTRACTED event,
 485              * in both cases notify the system about the changed filesystems
 486              */
 487             if (microsd_init)
 488                 queue_broadcast(SYS_FS_CHANGED, 0);
 489
 490             /* Access is now safe */
 491             mutex_unlock(&sd_mtx);
 492             fat_unlock();
 493             sd_enable(false);
 494         }
 495             break;
 496 #endif
 497         case SYS_TIMEOUT:
 498             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 499             {
 500                 idle_notified = false;
 501             }
 502             else
 503             {
 504                 /* never let a timer wrap confuse us */
 505                 next_yield = current_tick;
 506
 507                 if (!idle_notified)
 508                 {
 509                     call_storage_idle_notifys(false);
 510                     idle_notified = true;
 511                 }
 512             }
 513             break;
 514
 515         case SYS_USB_CONNECTED:
 516             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 517             /* Wait until the USB cable is extracted again */
 518             usb_wait_for_disconnect(&sd_queue);
 519
 520             break;
 521         }
 522     }
 523 }
 524
 525 static void init_pl180_controller(const int drive)
 526 {
 527     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 528     MCI_CLEAR(drive) = 0x7ff;
 529
 530     MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
 531     MCI_MASK1(drive) = 0;
 532 #ifdef HAVE_MULTIDRIVE
 533     VIC_INT_ENABLE =
 534         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 535     /* clear previous irq */
 536     GPIOA_IC = EXT_SD_BITS;
 537     /* enable edge detecting */
 538     GPIOA_IS &= ~EXT_SD_BITS;
 539     /* detect both raising and falling edges */
 540     GPIOA_IBE |= EXT_SD_BITS;
 541     /* enable the card detect interrupt */
 542     GPIOA_IE |= EXT_SD_BITS;
 543
 544 #else
 545     VIC_INT_ENABLE = INTERRUPT_NAND;
 546 #endif
 547
 548     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 549     mci_delay();
 550
 551     MCI_POWER(drive) |= MCI_POWER_ON;
 552     mci_delay();
 553
 554     MCI_SELECT(drive) = 0;
 555
 556     /* Pl180 clocks get turned on at start of card init */
 557 }
 558
 559 int sd_init(void)
 560 {
 561     int ret;
 562     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 563             |   (AS3525_IDE_DIV << 2)
 564             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 565
 566     bitset32(&CGU_PERI, CGU_NAF_CLOCK_ENABLE);
 567 #ifdef HAVE_MULTIDRIVE
 568     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 569     bitmod32(&CCU_IO, 1<<2, 3<<2);  /* bits 3:2 = 01, xpd is SD interface */
 570 #endif
 571
 572     semaphore_init(&transfer_completion_signal, 1, 0);
 573
 574     init_pl180_controller(INTERNAL_AS3525);
 575     ret = sd_init_card(INTERNAL_AS3525);
 576     if(ret < 0)
 577         return ret;
 578 #ifdef HAVE_MULTIDRIVE
 579     init_pl180_controller(SD_SLOT_AS3525);
 580 #endif
 581
 582     /* init mutex */
 583     mutex_init(&sd_mtx);
 584
 585     queue_init(&sd_queue, true);
 586     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 587             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 588
 589     sd_enabled = true;
 590     sd_enable(false);
 591
 592     return 0;
 593 }
 594
 595 #ifdef HAVE_HOTSWAP
 596 bool sd_removable(IF_MD_NONVOID(int drive))
 597 {
 598     return (drive == SD_SLOT_AS3525);
 599 }
 600
 601 bool sd_present(IF_MD_NONVOID(int drive))
 602 {
 603     return (drive == INTERNAL_AS3525) ? true : card_detect_target();
 604 }
 605 #endif /* HAVE_HOTSWAP */
 606
 607 static int sd_wait_for_tran_state(const int drive)
 608 {
 609     unsigned long response = 0;
 610     unsigned int timeout = current_tick + 5 * HZ;
 611
 612     while (1)
 613     {
 614         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
 615                     &response))
 616             return -1;
 617
 618         if (((response >> 9) & 0xf) == SD_TRAN)
 619             return 0;
 620
 621         if(TIME_AFTER(current_tick, timeout))
 622             return -2;
 623
 624         if (TIME_AFTER(current_tick, next_yield))
 625         {
 626             yield();
 627             next_yield = current_tick + MIN_YIELD_PERIOD;
 628         }
 629     }
 630 }
 631
 632 static int sd_select_bank(signed char bank)
 633 {
 634     int ret;
 635     unsigned loops = 0;
 636
 637     memset(uncached_buffer, 0, 512);
 638     if(bank == -1)
 639     {   /* enable bank switching */
 640         uncached_buffer[0] = 16;
 641         uncached_buffer[1] = 1;
 642         uncached_buffer[2] = 10;
 643     }
 644     else
 645         uncached_buffer[0] = bank;
 646
 647     do {
 648         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 649             panicf("SD bank %d error : 0x%x", bank,
 650                     transfer_error[INTERNAL_AS3525]);
 651
 652         ret = sd_wait_for_tran_state(INTERNAL_AS3525);
 653         if (ret < 0)
 654             return ret - 2;
 655
 656         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_NO_RESP,
 657                      NULL))
 658             return -1;
 659
 660         mci_delay();
 661
 662         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_RESP, NULL))
 663             return -2;
 664
 665         mci_delay();
 666
 667         dma_retain();
 668         /* we don't use the uncached buffer here, because we need the
 669          * physical memory address for DMA transfers */
 670         dma_enable_channel(1, AS3525_PHYSICAL_ADDR(&aligned_buffer[0]),
 671             MCI_FIFO(INTERNAL_AS3525), DMA_PERI_SD,
 672             DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 673
 674         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 675         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 676         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 677                                 (0<<1) /* transfer direction */ |
 678                                 (1<<3) /* DMA */                |
 679                                 (9<<4) /* 2^9 = 512 */ ;
 680
 681         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 682         semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 683
 684         /*  Wait for FIFO to empty, card may still be in PRG state  */
 685         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 686
 687         dma_release();
 688
 689     } while(transfer_error[INTERNAL_AS3525]);
 690
 691     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 692
 693     return 0;
 694 }
 695
 696 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 697                                int count, void* buf, const bool write)
 698 {
 699 #ifndef HAVE_MULTIDRIVE
 700     const int drive = 0;
 701 #endif
 702     int ret = 0;
 703     unsigned loops = 0;
 704     unsigned long response;
 705     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 706
 707     sd_enable(true);
 708     led(true);
 709
 710     if (card_info[drive].initialized <= 0)
 711     {
 712         ret = sd_init_card(drive);
 713         if (!(card_info[drive].initialized))
 714             goto sd_transfer_error_nodma;
 715     }
 716
 717     if(count < 0) /* XXX: why is it signed ? */
 718     {
 719         ret = -20;
 720         goto sd_transfer_error_nodma;
 721     }
 722     if((start+count) > card_info[drive].numblocks)
 723     {
 724         ret = -21;
 725         goto sd_transfer_error_nodma;
 726     }
 727
 728     /* skip SanDisk OF */
 729     if (drive == INTERNAL_AS3525)
 730         start += AMS_OF_SIZE;
 731
 732     last_disk_activity = current_tick;
 733
 734     dma_retain();
 735
 736     if(aligned)
 737     {   /* direct transfer, indirect is always uncached */
 738         if(write)
 739             commit_dcache_range(buf, count * SECTOR_SIZE);
 740         else
 741             discard_dcache_range(buf, count * SECTOR_SIZE);
 742     }
 743
 744     while(count)
 745     {
 746         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 747          * register, so we have to transfer maximum 127 sectors at a time. */
 748         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 749         void *dma_buf;
 750         const int cmd =
 751             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 752         unsigned long bank_start = start;
 753         unsigned long status;
 754
 755         /* Only switch banks for internal storage */
 756         if(drive == INTERNAL_AS3525)
 757         {
 758             unsigned int bank = 0;
 759             while(bank_start >= BLOCKS_PER_BANK)
 760             {
 761                 bank_start -= BLOCKS_PER_BANK;
 762                 bank++;
 763             }
 764
 765             /* Switch bank if needed */
 766             if(card_info[INTERNAL_AS3525].current_bank != bank)
 767             {
 768                 ret = sd_select_bank(bank);
 769                 if (ret < 0)
 770                 {
 771                     ret -= 20;
 772                     goto sd_transfer_error;
 773                 }
 774             }
 775
 776             /* Do not cross a bank boundary in a single transfer loop */
 777             if((transfer + bank_start) > BLOCKS_PER_BANK)
 778                 transfer = BLOCKS_PER_BANK - bank_start;
 779         }
 780
 781         /* Set bank_start to the correct unit (blocks or bytes) */
 782         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 783             bank_start *= SD_BLOCK_SIZE;
 784
 785         if(aligned)
 786         {
 787             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 788         }
 789         else
 790         {
 791             dma_buf = AS3525_PHYSICAL_ADDR(&aligned_buffer[0]);
 792             if(transfer > UNALIGNED_NUM_SECTORS)
 793                 transfer = UNALIGNED_NUM_SECTORS;
 794
 795             if(write)
 796                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 797         }
 798
 799         ret = sd_wait_for_tran_state(drive);
 800         if (ret < 0)
 801         {
 802             ret -= 2*20;
 803             goto sd_transfer_error;
 804         }
 805
 806         if(!send_cmd(drive, cmd, bank_start, MCI_RESP, &response))
 807         {
 808             ret -= 3*20;
 809             goto sd_transfer_error;
 810         }
 811
 812         if(write)
 813         {
 814             dma_enable_channel(1, dma_buf, MCI_FIFO(drive),
 815                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 816                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 817
 818             /*Small delay for writes prevents data crc failures at lower freqs*/
 819 #ifdef HAVE_MULTIDRIVE
 820             if((drive == SD_SLOT_AS3525) && !hs_card)
 821             {
 822                 int write_delay = 125;
 823                 while(write_delay--);
 824             }
 825 #endif
 826         }
 827         else
 828             dma_enable_channel(1, MCI_FIFO(drive), dma_buf,
 829                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 830                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 831
 832         MCI_DATA_TIMER(drive) = write ?
 833                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 834         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 835         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 836                                 (!write<<1) /* transfer direction */    |
 837                                 (1<<3) /* DMA */                        |
 838                                 (9<<4) /* 2^9 = 512 */ ;
 839
 840         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 841         semaphore_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 842
 843         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 844         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 845
 846         /*
 847          * If the write aborted early due to a tx underrun, disable the
 848          * dma channel here, otherwise there are still 4 words in the fifo
 849          * and the retried write will get corrupted.
 850          */
 851         dma_disable_channel(1);
 852
 853         last_disk_activity = current_tick;
 854
 855         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &status))
 856         {
 857             ret = -4*20;
 858             goto sd_transfer_error;
 859         }
 860
 861         if(!transfer_error[drive])
 862         {
 863             if(!write && !aligned)
 864                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 865             buf += transfer * SD_BLOCK_SIZE;
 866             start += transfer;
 867             count -= transfer;
 868             loops = 0;  /* reset errors counter */
 869         }
 870         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 871                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 872                                                   transfer_error[drive], drive);
 873     }
 874
 875 sd_transfer_error:
 876
 877     dma_release();
 878
 879 sd_transfer_error_nodma:
 880
 881     led(false);
 882     sd_enable(false);
 883
 884     if (ret)    /* error */
 885         card_info[drive].initialized = 0;
 886
 887     return ret;
 888 }
 889
 890 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 891                      void* buf)
 892 {
 893     int ret;
 894
 895     mutex_lock(&sd_mtx);
 896     ret = sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 897     mutex_unlock(&sd_mtx);
 898
 899     return ret;
 900 }
 901
 902 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 903                      const void* buf)
 904 {
 905 #ifdef VERIFY_WRITE
 906     unsigned long saved_start = start;
 907     int saved_count = count;
 908     void *saved_buf = (void*)buf;
 909 #endif
 910     int ret;
 911
 912     mutex_lock(&sd_mtx);
 913
 914     ret = sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 915
 916 #ifdef VERIFY_WRITE
 917     if (ret) {
 918         /* write failed, no point in verifying */
 919         mutex_unlock(&sd_mtx);
 920         return ret;
 921     }
 922
 923     count = saved_count;
 924     buf = saved_buf;
 925     start = saved_start;
 926     while (count) {
 927         int transfer = count;
 928         if(transfer > UNALIGNED_NUM_SECTORS)
 929             transfer = UNALIGNED_NUM_SECTORS;
 930
 931         sd_transfer_sectors(IF_MD2(drive,) start, transfer, aligned_buffer, false);
 932         if (memcmp(buf, aligned_buffer, transfer * 512) != 0) {
 933             /* try the write again in the hope to repair the damage */
 934             sd_transfer_sectors(IF_MD2(drive,) saved_start, saved_count, saved_buf, true);
 935             panicf("sd: verify failed: sec=%ld n=%d!", start, transfer);
 936         }
 937
 938         buf   += transfer * 512;
 939         count -= transfer;
 940         start += transfer;
 941     }
 942 #endif
 943
 944     mutex_unlock(&sd_mtx);
 945
 946     return ret;
 947 }
 948
 949 long sd_last_disk_activity(void)
 950 {
 951     return last_disk_activity;
 952 }
 953
 954 void sd_enable(bool on)
 955 {
 956 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 957     extern int buttonlight_is_on;
 958 #endif
 959
 960 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 961     static bool cpu_boosted = false;
 962 #endif
 963
 964     if (sd_enabled == on)
 965         return; /* nothing to do */
 966
 967     sd_enabled = on;
 968
 969     if(on)
 970     {
 971 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 972         /* buttonlight AMSes need a bit of special handling for the buttonlight
 973          * here due to the dual mapping of GPIOD and XPD */
 974         bitmod32(&CCU_IO, 1<<2, 3<<2);  /* XPD is SD-MCI interface (b3:2 = 01) */
 975         if (buttonlight_is_on)
 976             GPIOD_DIR &= ~(1<<7);
 977         else
 978             _buttonlight_off();
 979 #endif
 980
 981 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 982         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 983         {
 984             cpu_boosted = true;
 985             cpu_boost(true);
 986         }
 987 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 988     }
 989     else
 990     {
 991 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 992         if(cpu_boosted)
 993         {
 994             cpu_boost(false);
 995             cpu_boosted = false;
 996         }
 997 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 998
 999 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
1000         bitmod32(&CCU_IO, 0<<2, 3<<2);  /* XPD is general purpose IO (b3:2 = 00) */
1001         if (buttonlight_is_on)
1002             _buttonlight_on();
1003 #endif
1004     }
1005 }
1006
1007 tCardInfo *card_get_info_target(int card_no)
1008 {
1009     return &card_info[card_no];
1010 }
1011
1012 #ifdef CONFIG_STORAGE_MULTI
1013 int sd_num_drives(int first_drive)
1014 {
1015     /* We don't care which logical drive number(s) we have been assigned */
1016     (void)first_drive;
1017
1018     return NUM_DRIVES;
1019 }
1020 #endif /* CONFIG_STORAGE_MULTI */