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Fix comment.
[maemo-rb.git] / firmware / target / arm / s5l8700 / ipodnano2g / nand-nano2g.c
blob8a4541a226405340ab157c5c355e783bbb3bc0ad
1 /***************************************************************************
2 * __________ __ ___.
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
7 * \/ \/ \/ \/ \/
8 * $Id$
9 *
10 * Copyright (C) 2009 by Michael Sparmann
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
16 *
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
19 *
20 ****************************************************************************/
21
22
23 #include "config.h"
24 #include "panic.h"
25 #include "system.h"
26 #include "kernel.h"
27 #include "cpu.h"
28 #include "inttypes.h"
29 #include "nand-target.h"
30 #include <pmu-target.h>
31 #include <mmu-arm.h>
32 #include <string.h>
33 #include "led.h"
34 #include "ata_idle_notify.h"
35
36
37 #define NAND_CMD_READ 0x00
38 #define NAND_CMD_PROGCNFRM 0x10
39 #define NAND_CMD_READ2 0x30
40 #define NAND_CMD_BLOCKERASE 0x60
41 #define NAND_CMD_GET_STATUS 0x70
42 #define NAND_CMD_PROGRAM 0x80
43 #define NAND_CMD_ERASECNFRM 0xD0
44 #define NAND_CMD_RESET 0xFF
45
46 #define NAND_STATUS_READY 0x40
47
48 static const struct nand_device_info_type nand_deviceinfotable[] =
49 {
50 {0x1580F1EC, 1024, 968, 0x40, 6, 2, 1, 2, 1},
51 {0x1580DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
52 {0x15C1DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
53 {0x1510DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
54 {0x95C1DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
55 {0x2514DCEC, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
56 {0x2514D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
57 {0x2555D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
58 {0x2555D5EC, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
59 {0x2585D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
60 {0x9580DCAD, 4096, 3872, 0x40, 6, 3, 2, 3, 2},
61 {0xA514D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
62 {0xA550D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
63 {0xA560D5AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
64 {0xA555D5AD, 8192, 7744, 0x80, 7, 3, 2, 3, 2},
65 {0xA585D598, 8320, 7744, 0x80, 7, 3, 1, 2, 1},
66 {0xA584D398, 4160, 3872, 0x80, 7, 3, 1, 2, 1},
67 {0x95D1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
68 {0x1580DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
69 {0x15C1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
70 {0x9590DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
71 {0xA594D32C, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
72 {0x2584DC2C, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
73 {0xA5D5D52C, 8192, 7744, 0x80, 7, 3, 2, 2, 1},
74 {0x95D1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
75 {0x1580DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
76 {0x15C1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
77 {0x9590DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
78 {0xA594D389, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
79 {0x2584DC89, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
80 {0xA5D5D589, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
81 {0xA514D320, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
82 {0xA555D520, 8192, 3872, 0x80, 7, 2, 1, 2, 1}
83 };
84
85 static uint8_t nand_tunk1[4];
86 static uint8_t nand_twp[4];
87 static uint8_t nand_tunk2[4];
88 static uint8_t nand_tunk3[4];
89 static int nand_type[4];
90 static int nand_powered = 0;
91 static int nand_interleaved = 0;
92 static int nand_cached = 0;
93 static long nand_last_activity_value = -1;
94 static long nand_stack[DEFAULT_STACK_SIZE];
95
96 static struct mutex nand_mtx;
97 static struct wakeup nand_wakeup;
98 static struct mutex ecc_mtx;
99 static struct wakeup ecc_wakeup;
100
101 static uint8_t nand_data[0x800] STORAGE_ALIGN_ATTR;
102 static uint8_t nand_ctrl[0x200] STORAGE_ALIGN_ATTR;
103 static uint8_t nand_spare[0x40] STORAGE_ALIGN_ATTR;
104 static uint8_t nand_ecc[0x30] STORAGE_ALIGN_ATTR;
105
106
107 static uint32_t nand_unlock(uint32_t rc)
108 {
109 led(false);
110 nand_last_activity_value = current_tick;
111 mutex_unlock(&nand_mtx);
112 return rc;
113 }
114
115 static uint32_t ecc_unlock(uint32_t rc)
116 {
117 mutex_unlock(&ecc_mtx);
118 return rc;
119 }
120
121 static uint32_t nand_timeout(long timeout)
122 {
123 if (TIME_AFTER(current_tick, timeout)) return 1;
124 else
125 {
126 yield();
127 return 0;
128 }
129 }
130
131 static uint32_t nand_wait_rbbdone(void)
132 {
133 long timeout = current_tick + HZ / 50;
134 while (!(FMCSTAT & FMCSTAT_RBBDONE))
135 if (nand_timeout(timeout)) return 1;
136 FMCSTAT = FMCSTAT_RBBDONE;
137 return 0;
138 }
139
140 static uint32_t nand_wait_cmddone(void)
141 {
142 long timeout = current_tick + HZ / 50;
143 while (!(FMCSTAT & FMCSTAT_CMDDONE))
144 if (nand_timeout(timeout)) return 1;
145 FMCSTAT = FMCSTAT_CMDDONE;
146 return 0;
147 }
148
149 static uint32_t nand_wait_addrdone(void)
150 {
151 long timeout = current_tick + HZ / 50;
152 while (!(FMCSTAT & FMCSTAT_ADDRDONE))
153 if (nand_timeout(timeout)) return 1;
154 FMCSTAT = FMCSTAT_ADDRDONE;
155 return 0;
156 }
157
158 static uint32_t nand_wait_chip_ready(uint32_t bank)
159 {
160 long timeout = current_tick + HZ / 50;
161 while (!(FMCSTAT & (FMCSTAT_BANK0READY << bank)))
162 if (nand_timeout(timeout)) return 1;
163 FMCSTAT = (FMCSTAT_BANK0READY << bank);
164 return 0;
165 }
166
167 static void nand_set_fmctrl0(uint32_t bank, uint32_t flags)
168 {
169 FMCTRL0 = (nand_tunk1[bank] << 16) | (nand_twp[bank] << 12)
170 | (1 << 11) | 1 | (1 << (bank + 1)) | flags;
171 }
172
173 static uint32_t nand_send_cmd(uint32_t cmd)
174 {
175 FMCMD = cmd;
176 return nand_wait_rbbdone();
177 }
178
179 static uint32_t nand_send_address(uint32_t page, uint32_t offset)
180 {
181 FMANUM = 4;
182 FMADDR0 = (page << 16) | offset;
183 FMADDR1 = (page >> 16) & 0xFF;
184 FMCTRL1 = FMCTRL1_DOTRANSADDR;
185 return nand_wait_cmddone();
186 }
187
188 uint32_t nand_reset(uint32_t bank)
189 {
190 nand_set_fmctrl0(bank, 0);
191 if (nand_send_cmd(NAND_CMD_RESET)) return 1;
192 if (nand_wait_chip_ready(bank)) return 1;
193 FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
194 sleep(0);
195 return 0;
196 }
197
198 static uint32_t nand_wait_status_ready(uint32_t bank)
199 {
200 long timeout = current_tick + HZ / 50;
201 nand_set_fmctrl0(bank, 0);
202 if ((FMCSTAT & (FMCSTAT_BANK0READY << bank)))
203 FMCSTAT = (FMCSTAT_BANK0READY << bank);
204 FMCTRL1 = FMCTRL1_CLEARRFIFO;
205 if (nand_send_cmd(NAND_CMD_GET_STATUS)) return 1;
206 while (1)
207 {
208 if (nand_timeout(timeout)) return 1;
209 FMDNUM = 0;
210 FMCTRL1 = FMCTRL1_DOREADDATA;
211 if (nand_wait_addrdone()) return 1;
212 if ((FMFIFO & NAND_STATUS_READY)) break;
213 FMCTRL1 = FMCTRL1_CLEARRFIFO;
214 }
215 FMCTRL1 = FMCTRL1_CLEARRFIFO;
216 return nand_send_cmd(NAND_CMD_READ);
217 }
218
219 static void nand_transfer_data_start(uint32_t bank, uint32_t direction,
220 void* buffer, uint32_t size)
221 {
222 nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
223 FMDNUM = size - 1;
224 FMCTRL1 = FMCTRL1_DOREADDATA << direction;
225 DMACON3 = (2 << DMACON_DEVICE_SHIFT)
226 | (direction << DMACON_DIRECTION_SHIFT)
227 | (2 << DMACON_DATA_SIZE_SHIFT)
228 | (3 << DMACON_BURST_LEN_SHIFT);
229 while ((DMAALLST & DMAALLST_CHAN3_MASK))
230 DMACOM3 = DMACOM_CLEARBOTHDONE;
231 DMABASE3 = (uint32_t)buffer;
232 DMATCNT3 = (size >> 4) - 1;
233 clean_dcache();
234 DMACOM3 = 4;
235 }
236
237 static uint32_t nand_transfer_data_collect(uint32_t direction)
238 {
239 long timeout = current_tick + HZ / 50;
240 while ((DMAALLST & DMAALLST_DMABUSY3))
241 if (nand_timeout(timeout)) return 1;
242 if (!direction) invalidate_dcache();
243 if (nand_wait_addrdone()) return 1;
244 if (!direction) FMCTRL1 = FMCTRL1_CLEARRFIFO | FMCTRL1_CLEARWFIFO;
245 else FMCTRL1 = FMCTRL1_CLEARRFIFO;
246 return 0;
247 }
248
249 static uint32_t nand_transfer_data(uint32_t bank, uint32_t direction,
250 void* buffer, uint32_t size)
251 {
252 nand_transfer_data_start(bank, direction, buffer, size);
253 uint32_t rc = nand_transfer_data_collect(direction);
254 return rc;
255 }
256
257 static void ecc_start(uint32_t size, void* databuffer, void* sparebuffer,
258 uint32_t type)
259 {
260 mutex_lock(&ecc_mtx);
261 ECC_INT_CLR = 1;
262 SRCPND = INTMSK_ECC;
263 ECC_UNK1 = size;
264 ECC_DATA_PTR = (uint32_t)databuffer;
265 ECC_SPARE_PTR = (uint32_t)sparebuffer;
266 clean_dcache();
267 ECC_CTRL = type;
268 }
269
270 static uint32_t ecc_collect(void)
271 {
272 long timeout = current_tick + HZ / 50;
273 while (!(SRCPND & INTMSK_ECC))
274 if (nand_timeout(timeout)) return ecc_unlock(1);
275 invalidate_dcache();
276 ECC_INT_CLR = 1;
277 SRCPND = INTMSK_ECC;
278 return ecc_unlock(ECC_RESULT);
279 }
280
281 static uint32_t ecc_decode(uint32_t size, void* databuffer, void* sparebuffer)
282 {
283 ecc_start(size, databuffer, sparebuffer, ECCCTRL_STARTDECODING);
284 uint32_t rc = ecc_collect();
285 return rc;
286 }
287
288 static uint32_t ecc_encode(uint32_t size, void* databuffer, void* sparebuffer)
289 {
290 ecc_start(size, databuffer, sparebuffer, ECCCTRL_STARTENCODING);
291 ecc_collect();
292 return 0;
293 }
294
295 static uint32_t nand_check_empty(uint8_t* buffer)
296 {
297 uint32_t i, count;
298 count = 0;
299 for (i = 0; i < 0x40; i++) if (buffer[i] != 0xFF) count++;
300 if (count < 2) return 1;
301 return 0;
302 }
303
304 static uint32_t nand_get_chip_type(uint32_t bank)
305 {
306 mutex_lock(&nand_mtx);
307 uint32_t result;
308 if (nand_reset(bank)) return nand_unlock(0xFFFFFFFE);
309 if (nand_send_cmd(0x90)) return nand_unlock(0xFFFFFFFD);
310 FMANUM = 0;
311 FMADDR0 = 0;
312 FMCTRL1 = FMCTRL1_DOTRANSADDR;
313 if (nand_wait_cmddone()) return nand_unlock(0xFFFFFFFC);
314 FMDNUM = 4;
315 FMCTRL1 = FMCTRL1_DOREADDATA;
316 if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFB);
317 result = FMFIFO;
318 FMCTRL1 = FMCTRL1_CLEARRFIFO;
319 return nand_unlock(result);
320 }
321
322 void nand_set_active(void)
323 {
324 nand_last_activity_value = current_tick;
325 }
326
327 long nand_last_activity(void)
328 {
329 return nand_last_activity_value;
330 }
331
332 void nand_power_up(void)
333 {
334 uint32_t i;
335 mutex_lock(&nand_mtx);
336 nand_last_activity_value = current_tick;
337 PWRCONEXT &= ~0x40;
338 PWRCON &= ~0x100000;
339 PCON2 = 0x33333333;
340 PDAT2 = 0;
341 PCON3 = 0x11113333;
342 PDAT3 = 0;
343 PCON4 = 0x33333333;
344 PDAT4 = 0;
345 PCON5 = (PCON5 & ~0xF) | 3;
346 PUNK5 = 1;
347 pmu_ldo_set_voltage(4, 0x15);
348 pmu_ldo_power_on(4);
349 sleep(HZ / 20);
350 nand_last_activity_value = current_tick;
351 for (i = 0; i < 4; i++)
352 if (nand_type[i] >= 0)
353 if (nand_reset(i))
354 panicf("nand_power_up: nand_reset(bank=%d) failed.",(unsigned int)i);
355 nand_powered = 1;
356 nand_last_activity_value = current_tick;
357 mutex_unlock(&nand_mtx);
358 }
359
360 void nand_power_down(void)
361 {
362 if (!nand_powered) return;
363 mutex_lock(&nand_mtx);
364 pmu_ldo_power_off(4);
365 PCON2 = 0x11111111;
366 PDAT2 = 0;
367 PCON3 = 0x11111111;
368 PDAT3 = 0;
369 PCON4 = 0x11111111;
370 PDAT4 = 0;
371 PCON5 = (PCON5 & ~0xF) | 1;
372 PUNK5 = 1;
373 PWRCONEXT |= 0x40;
374 PWRCON |= 0x100000;
375 nand_powered = 0;
376 mutex_unlock(&nand_mtx);
377 }
378
379 uint32_t nand_read_page(uint32_t bank, uint32_t page, void* databuffer,
380 void* sparebuffer, uint32_t doecc,
381 uint32_t checkempty)
382 {
383 uint8_t* data = nand_data;
384 uint8_t* spare = nand_spare;
385 if (databuffer && !((uint32_t)databuffer & 0xf))
386 data = (uint8_t*)databuffer;
387 if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
388 spare = (uint8_t*)sparebuffer;
389 mutex_lock(&nand_mtx);
390 nand_last_activity_value = current_tick;
391 led(true);
392 if (!nand_powered) nand_power_up();
393 uint32_t rc, eccresult;
394 nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
395 if (nand_send_cmd(NAND_CMD_READ)) return nand_unlock(1);
396 if (nand_send_address(page, databuffer ? 0 : 0x800))
397 return nand_unlock(1);
398 if (nand_send_cmd(NAND_CMD_READ2)) return nand_unlock(1);
399 if (nand_wait_status_ready(bank)) return nand_unlock(1);
400 if (databuffer)
401 if (nand_transfer_data(bank, 0, data, 0x800))
402 return nand_unlock(1);
403 rc = 0;
404 if (!doecc)
405 {
406 if (databuffer && data != databuffer) memcpy(databuffer, data, 0x800);
407 if (sparebuffer)
408 {
409 if (nand_transfer_data(bank, 0, spare, 0x40))
410 return nand_unlock(1);
411 if (sparebuffer && spare != sparebuffer)
412 memcpy(sparebuffer, spare, 0x800);
413 if (checkempty)
414 rc = nand_check_empty((uint8_t*)sparebuffer) << 1;
415 }
416 return nand_unlock(rc);
417 }
418 if (nand_transfer_data(bank, 0, spare, 0x40)) return nand_unlock(1);
419 if (databuffer)
420 {
421 memcpy(nand_ecc, &spare[0xC], 0x28);
422 rc |= (ecc_decode(3, data, nand_ecc) & 0xF) << 4;
423 if (data != databuffer) memcpy(databuffer, data, 0x800);
424 }
425 memset(nand_ctrl, 0xFF, 0x200);
426 memcpy(nand_ctrl, spare, 0xC);
427 memcpy(nand_ecc, &spare[0x34], 0xC);
428 eccresult = ecc_decode(0, nand_ctrl, nand_ecc);
429 rc |= (eccresult & 0xF) << 8;
430 if (sparebuffer)
431 {
432 if (spare != sparebuffer) memcpy(sparebuffer, spare, 0x40);
433 if (eccresult & 1) memset(sparebuffer, 0xFF, 0xC);
434 else memcpy(sparebuffer, nand_ctrl, 0xC);
435 }
436 if (checkempty) rc |= nand_check_empty(spare) << 1;
437
438 return nand_unlock(rc);
439 }
440
441 static uint32_t nand_write_page_int(uint32_t bank, uint32_t page,
442 void* databuffer, void* sparebuffer,
443 uint32_t doecc, uint32_t wait)
444 {
445 uint8_t* data = nand_data;
446 uint8_t* spare = nand_spare;
447 if (databuffer && !((uint32_t)databuffer & 0xf))
448 data = (uint8_t*)databuffer;
449 if (sparebuffer && !((uint32_t)sparebuffer & 0xf))
450 spare = (uint8_t*)sparebuffer;
451 mutex_lock(&nand_mtx);
452 nand_last_activity_value = current_tick;
453 led(true);
454 if (!nand_powered) nand_power_up();
455 if (sparebuffer)
456 {
457 if (spare != sparebuffer) memcpy(spare, sparebuffer, 0x40);
458 }
459 else memset(spare, 0xFF, 0x40);
460 nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
461 if (nand_send_cmd(NAND_CMD_PROGRAM)) return nand_unlock(1);
462 if (nand_send_address(page, databuffer ? 0 : 0x800))
463 return nand_unlock(1);
464 if (databuffer && data != databuffer) memcpy(data, databuffer, 0x800);
465 if (databuffer) nand_transfer_data_start(bank, 1, data, 0x800);
466 if (doecc)
467 {
468 if (ecc_encode(3, data, nand_ecc)) return nand_unlock(1);
469 memcpy(&spare[0xC], nand_ecc, 0x28);
470 memset(nand_ctrl, 0xFF, 0x200);
471 memcpy(nand_ctrl, spare, 0xC);
472 if (ecc_encode(0, nand_ctrl, nand_ecc)) return nand_unlock(1);
473 memcpy(&spare[0x34], nand_ecc, 0xC);
474 }
475 if (databuffer)
476 if (nand_transfer_data_collect(1))
477 return nand_unlock(1);
478 if (sparebuffer || doecc)
479 if (nand_transfer_data(bank, 1, spare, 0x40))
480 return nand_unlock(1);
481 if (nand_send_cmd(NAND_CMD_PROGCNFRM)) return nand_unlock(1);
482 if (wait) if (nand_wait_status_ready(bank)) return nand_unlock(1);
483 return nand_unlock(0);
484 }
485
486 uint32_t nand_block_erase(uint32_t bank, uint32_t page)
487 {
488 mutex_lock(&nand_mtx);
489 nand_last_activity_value = current_tick;
490 led(true);
491 if (!nand_powered) nand_power_up();
492 nand_set_fmctrl0(bank, 0);
493 if (nand_send_cmd(NAND_CMD_BLOCKERASE)) return nand_unlock(1);
494 FMANUM = 2;
495 FMADDR0 = page;
496 FMCTRL1 = FMCTRL1_DOTRANSADDR;
497 if (nand_wait_cmddone()) return nand_unlock(1);
498 if (nand_send_cmd(NAND_CMD_ERASECNFRM)) return nand_unlock(1);
499 if (nand_wait_status_ready(bank)) return nand_unlock(1);
500 return nand_unlock(0);
501 }
502
503 uint32_t nand_read_page_fast(uint32_t page, void* databuffer,
504 void* sparebuffer, uint32_t doecc,
505 uint32_t checkempty)
506 {
507 uint32_t i, rc = 0;
508 if (((uint32_t)databuffer & 0xf) || ((uint32_t)sparebuffer & 0xf)
509 || !databuffer || !sparebuffer || !doecc)
510 {
511 for (i = 0; i < 4; i++)
512 {
513 if (nand_type[i] < 0) continue;
514 void* databuf = (void*)0;
515 void* sparebuf = (void*)0;
516 if (databuffer) databuf = (void*)((uint32_t)databuffer + 0x800 * i);
517 if (sparebuffer) sparebuf = (void*)((uint32_t)sparebuffer + 0x40 * i);
518 uint32_t ret = nand_read_page(i, page, databuf, sparebuf, doecc, checkempty);
519 if (ret & 1) rc |= 1 << (i << 2);
520 if (ret & 2) rc |= 2 << (i << 2);
521 if (ret & 0x10) rc |= 4 << (i << 2);
522 if (ret & 0x100) rc |= 8 << (i << 2);
523 }
524 return rc;
525 }
526 mutex_lock(&nand_mtx);
527 nand_last_activity_value = current_tick;
528 led(true);
529 if (!nand_powered) nand_power_up();
530 uint8_t status[4];
531 for (i = 0; i < 4; i++) status[i] = (nand_type[i] < 0);
532 for (i = 0; i < 4; i++)
533 {
534 if (!status[i])
535 {
536 nand_set_fmctrl0(i, FMCTRL0_ENABLEDMA);
537 if (nand_send_cmd(NAND_CMD_READ))
538 status[i] = 1;
539 }
540 if (!status[i])
541 if (nand_send_address(page, 0))
542 status[i] = 1;
543 if (!status[i])
544 if (nand_send_cmd(NAND_CMD_READ2))
545 status[i] = 1;
546 }
547 if (!status[0])
548 if (nand_wait_status_ready(0))
549 status[0] = 1;
550 if (!status[0])
551 if (nand_transfer_data(0, 0, databuffer, 0x800))
552 status[0] = 1;
553 if (!status[0])
554 if (nand_transfer_data(0, 0, sparebuffer, 0x40))
555 status[0] = 1;
556 for (i = 1; i < 4; i++)
557 {
558 if (!status[i])
559 if (nand_wait_status_ready(i))
560 status[i] = 1;
561 if (!status[i])
562 nand_transfer_data_start(i, 0, (void*)((uint32_t)databuffer
563 + 0x800 * i), 0x800);
564 if (!status[i - 1])
565 {
566 memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0xC), 0x28);
567 ecc_start(3, (void*)((uint32_t)databuffer
568 + 0x800 * (i - 1)), nand_ecc, ECCCTRL_STARTDECODING);
569 }
570 if (!status[i])
571 if (nand_transfer_data_collect(0))
572 status[i] = 1;
573 if (!status[i])
574 nand_transfer_data_start(i, 0, (void*)((uint32_t)sparebuffer
575 + 0x40 * i), 0x40);
576 if (!status[i - 1])
577 if (ecc_collect() & 1)
578 status[i - 1] = 4;
579 if (!status[i - 1])
580 {
581 memset(nand_ctrl, 0xFF, 0x200);
582 memcpy(nand_ctrl, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xC);
583 memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0x34), 0xC);
584 ecc_start(0, nand_ctrl, nand_ecc, ECCCTRL_STARTDECODING);
585 }
586 if (!status[i])
587 if (nand_transfer_data_collect(0))
588 status[i] = 1;
589 if (!status[i - 1])
590 {
591 if (ecc_collect() & 1)
592 {
593 status[i - 1] |= 8;
594 memset((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xFF, 0xC);
595 }
596 else memcpy((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), nand_ctrl, 0xC);
597 if (checkempty)
598 status[i - 1] |= nand_check_empty((void*)((uint32_t)sparebuffer
599 + 0x40 * (i - 1))) << 1;
600 }
601 }
602 if (!status[i - 1])
603 {
604 memcpy(nand_ecc,(void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0xC), 0x28);
605 if (ecc_decode(3, (void*)((uint32_t)databuffer
606 + 0x800 * (i - 1)), nand_ecc) & 1)
607 status[i - 1] = 4;
608 }
609 if (!status[i - 1])
610 {
611 memset(nand_ctrl, 0xFF, 0x200);
612 memcpy(nand_ctrl, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xC);
613 memcpy(nand_ecc, (void*)((uint32_t)sparebuffer + 0x40 * (i - 1) + 0x34), 0xC);
614 if (ecc_decode(0, nand_ctrl, nand_ecc) & 1)
615 {
616 status[i - 1] |= 8;
617 memset((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), 0xFF, 0xC);
618 }
619 else memcpy((void*)((uint32_t)sparebuffer + 0x40 * (i - 1)), nand_ctrl, 0xC);
620 if (checkempty)
621 status[i - 1] |= nand_check_empty((void*)((uint32_t)sparebuffer
622 + 0x40 * (i - 1))) << 1;
623 }
624 for (i = 0; i < 4; i++)
625 if (nand_type[i] < 0)
626 rc |= status[i] << (i << 2);
627 return nand_unlock(rc);
628 }
629
630 uint32_t nand_write_page(uint32_t bank, uint32_t page, void* databuffer,
631 void* sparebuffer, uint32_t doecc)
632 {
633 return nand_write_page_int(bank, page, databuffer, sparebuffer, doecc, 1);
634 }
635
636 uint32_t nand_write_page_start(uint32_t bank, uint32_t page, void* databuffer,
637 void* sparebuffer, uint32_t doecc)
638 {
639 if (((uint32_t)databuffer & 0xf) || ((uint32_t)sparebuffer & 0xf)
640 || !databuffer || !sparebuffer || !doecc || !nand_interleaved)
641 return nand_write_page_int(bank, page, databuffer, sparebuffer, doecc, !nand_interleaved);
642
643 mutex_lock(&nand_mtx);
644 nand_last_activity_value = current_tick;
645 led(true);
646 if (!nand_powered) nand_power_up();
647 nand_set_fmctrl0(bank, FMCTRL0_ENABLEDMA);
648 if (nand_send_cmd(NAND_CMD_PROGRAM))
649 return nand_unlock(1);
650 if (nand_send_address(page, 0))
651 return nand_unlock(1);
652 nand_transfer_data_start(bank, 1, databuffer, 0x800);
653 if (ecc_encode(3, databuffer, nand_ecc))
654 return nand_unlock(1);
655 memcpy((void*)((uint32_t)sparebuffer + 0xC), nand_ecc, 0x28);
656 memset(nand_ctrl, 0xFF, 0x200);
657 memcpy(nand_ctrl, sparebuffer, 0xC);
658 if (ecc_encode(0, nand_ctrl, nand_ecc))
659 return nand_unlock(1);
660 memcpy((void*)((uint32_t)sparebuffer + 0x34), nand_ecc, 0xC);
661 if (nand_transfer_data_collect(0))
662 return nand_unlock(1);
663 if (nand_transfer_data(bank, 1, sparebuffer, 0x40))
664 return nand_unlock(1);
665 return nand_unlock(nand_send_cmd(NAND_CMD_PROGCNFRM));
666 }
667
668 uint32_t nand_write_page_collect(uint32_t bank)
669 {
670 return nand_wait_status_ready(bank);
671 }
672
673 #if 0 /* currently unused */
674 static uint32_t nand_block_erase_fast(uint32_t page)
675 {
676 uint32_t i, rc = 0;
677 mutex_lock(&nand_mtx);
678 nand_last_activity_value = current_tick;
679 led(true);
680 if (!nand_powered) nand_power_up();
681 for (i = 0; i < 4; i++)
682 {
683 if (nand_type[i] < 0) continue;
684 nand_set_fmctrl0(i, 0);
685 if (nand_send_cmd(NAND_CMD_BLOCKERASE))
686 {
687 rc |= 1 << i;
688 continue;
689 }
690 FMANUM = 2;
691 FMADDR0 = page;
692 FMCTRL1 = FMCTRL1_DOTRANSADDR;
693 if (nand_wait_cmddone())
694 {
695 rc |= 1 << i;
696 continue;
697 }
698 if (nand_send_cmd(NAND_CMD_ERASECNFRM)) rc |= 1 << i;
699 }
700 for (i = 0; i < 4; i++)
701 {
702 if (nand_type[i] < 0) continue;
703 if (rc & (1 << i)) continue;
704 if (nand_wait_status_ready(i)) rc |= 1 << i;
705 }
706 return nand_unlock(rc);
707 }
708 #endif
709
710 const struct nand_device_info_type* nand_get_device_type(uint32_t bank)
711 {
712 if (nand_type[bank] < 0)
713 return (struct nand_device_info_type*)0;
714 return &nand_deviceinfotable[nand_type[bank]];
715 }
716
717 static void nand_thread(void)
718 {
719 while (1)
720 {
721 if (TIME_AFTER(current_tick, nand_last_activity_value + HZ / 5)
722 && nand_powered)
723 {
724 call_storage_idle_notifys(false);
725 nand_power_down();
726 }
727 sleep(HZ / 10);
728 }
729 }
730
731 int nand_device_init(void)
732 {
733 mutex_init(&nand_mtx);
734 wakeup_init(&nand_wakeup);
735 mutex_init(&ecc_mtx);
736 wakeup_init(&ecc_wakeup);
737
738 uint32_t type;
739 uint32_t i, j;
740
741 /* Assume there are 0 banks, to prevent
742 nand_power_up from talking with them yet. */
743 for (i = 0; i < 4; i++) nand_type[i] = -1;
744 nand_power_up();
745
746 /* Now that the flash is powered on, detect how
747 many banks we really have and initialize them. */
748 for (i = 0; i < 4; i++)
749 {
750 nand_tunk1[i] = 7;
751 nand_twp[i] = 7;
752 nand_tunk2[i] = 7;
753 nand_tunk3[i] = 7;
754 type = nand_get_chip_type(i);
755 if (type >= 0xFFFFFFF0)
756 {
757 nand_type[i] = (int)type;
758 continue;
759 }
760 for (j = 0; ; j++)
761 {
762 if (j == ARRAYLEN(nand_deviceinfotable)) break;
763 else if (nand_deviceinfotable[j].id == type)
764 {
765 nand_type[i] = j;
766 break;
767 }
768 }
769 nand_tunk1[i] = nand_deviceinfotable[nand_type[i]].tunk1;
770 nand_twp[i] = nand_deviceinfotable[nand_type[i]].twp;
771 nand_tunk2[i] = nand_deviceinfotable[nand_type[i]].tunk2;
772 nand_tunk3[i] = nand_deviceinfotable[nand_type[i]].tunk3;
773 }
774 if (nand_type[0] < 0) return nand_type[0];
775 nand_interleaved = ((nand_deviceinfotable[nand_type[0]].id >> 22) & 1);
776 nand_cached = ((nand_deviceinfotable[nand_type[0]].id >> 23) & 1);
777
778 nand_last_activity_value = current_tick;
779 create_thread(nand_thread, nand_stack,
780 sizeof(nand_stack), 0, "nand"
781 IF_PRIO(, PRIORITY_USER_INTERFACE)
782 IF_COP(, CPU));
783
784 return 0;
785 }
thomasjfox's rockbox modifications (mameo port)