1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2009 by Michael Sparmann
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
29 #include "nand-target.h"
30 #include <pmu-target.h>
34 #include "ata_idle_notify.h"
37 #define NAND_CMD_READ 0x00
38 #define NAND_CMD_PROGCNFRM 0x10
39 #define NAND_CMD_READ2 0x30
40 #define NAND_CMD_BLOCKERASE 0x60
41 #define NAND_CMD_GET_STATUS 0x70
42 #define NAND_CMD_PROGRAM 0x80
43 #define NAND_CMD_ERASECNFRM 0xD0
44 #define NAND_CMD_RESET 0xFF
46 #define NAND_STATUS_READY 0x40
48 static const struct nand_device_info_type nand_deviceinfotable
[] =
50 {0x1580F1EC, 1024, 968, 0x40, 6, 2, 1, 2, 1},
51 {0x1580DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
52 {0x15C1DAEC, 2048, 1936, 0x40, 6, 2, 1, 2, 1},
53 {0x1510DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
54 {0x95C1DCEC, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
55 {0x2514DCEC, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
56 {0x2514D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
57 {0x2555D3EC, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
58 {0x2555D5EC, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
59 {0x2585D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
60 {0x9580DCAD, 4096, 3872, 0x40, 6, 3, 2, 3, 2},
61 {0xA514D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
62 {0xA550D3AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
63 {0xA560D5AD, 4096, 3872, 0x80, 7, 3, 2, 3, 2},
64 {0xA555D5AD, 8192, 7744, 0x80, 7, 3, 2, 3, 2},
65 {0xA585D598, 8320, 7744, 0x80, 7, 3, 1, 2, 1},
66 {0xA584D398, 4160, 3872, 0x80, 7, 3, 1, 2, 1},
67 {0x95D1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
68 {0x1580DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
69 {0x15C1D32C, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
70 {0x9590DC2C, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
71 {0xA594D32C, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
72 {0x2584DC2C, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
73 {0xA5D5D52C, 8192, 7744, 0x80, 7, 3, 2, 2, 1},
74 {0x95D1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
75 {0x1580DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
76 {0x15C1D389, 8192, 7744, 0x40, 6, 2, 1, 2, 1},
77 {0x9590DC89, 4096, 3872, 0x40, 6, 2, 1, 2, 1},
78 {0xA594D389, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
79 {0x2584DC89, 2048, 1936, 0x80, 7, 2, 1, 2, 1},
80 {0xA5D5D589, 8192, 7744, 0x80, 7, 2, 1, 2, 1},
81 {0xA514D320, 4096, 3872, 0x80, 7, 2, 1, 2, 1},
82 {0xA555D520, 8192, 3872, 0x80, 7, 2, 1, 2, 1}
85 static uint8_t nand_tunk1
[4];
86 static uint8_t nand_twp
[4];
87 static uint8_t nand_tunk2
[4];
88 static uint8_t nand_tunk3
[4];
89 static int nand_type
[4];
90 static int nand_powered
= 0;
91 static int nand_interleaved
= 0;
92 static int nand_cached
= 0;
93 static long nand_last_activity_value
= -1;
94 static long nand_stack
[DEFAULT_STACK_SIZE
];
96 static struct mutex nand_mtx
;
97 static struct semaphore nand_complete
;
98 static struct mutex ecc_mtx
;
99 static struct semaphore ecc_complete
;
101 static uint8_t nand_data
[0x800] STORAGE_ALIGN_ATTR
;
102 static uint8_t nand_ctrl
[0x200] STORAGE_ALIGN_ATTR
;
103 static uint8_t nand_spare
[0x40] STORAGE_ALIGN_ATTR
;
104 static uint8_t nand_ecc
[0x30] STORAGE_ALIGN_ATTR
;
107 static uint32_t nand_unlock(uint32_t rc
)
110 nand_last_activity_value
= current_tick
;
111 mutex_unlock(&nand_mtx
);
115 static uint32_t ecc_unlock(uint32_t rc
)
117 mutex_unlock(&ecc_mtx
);
121 static uint32_t nand_timeout(long timeout
)
123 if (TIME_AFTER(current_tick
, timeout
)) return 1;
131 static uint32_t nand_wait_rbbdone(void)
133 long timeout
= current_tick
+ HZ
/ 50;
134 while (!(FMCSTAT
& FMCSTAT_RBBDONE
))
135 if (nand_timeout(timeout
)) return 1;
136 FMCSTAT
= FMCSTAT_RBBDONE
;
140 static uint32_t nand_wait_cmddone(void)
142 long timeout
= current_tick
+ HZ
/ 50;
143 while (!(FMCSTAT
& FMCSTAT_CMDDONE
))
144 if (nand_timeout(timeout
)) return 1;
145 FMCSTAT
= FMCSTAT_CMDDONE
;
149 static uint32_t nand_wait_addrdone(void)
151 long timeout
= current_tick
+ HZ
/ 50;
152 while (!(FMCSTAT
& FMCSTAT_ADDRDONE
))
153 if (nand_timeout(timeout
)) return 1;
154 FMCSTAT
= FMCSTAT_ADDRDONE
;
158 static uint32_t nand_wait_chip_ready(uint32_t bank
)
160 long timeout
= current_tick
+ HZ
/ 50;
161 while (!(FMCSTAT
& (FMCSTAT_BANK0READY
<< bank
)))
162 if (nand_timeout(timeout
)) return 1;
163 FMCSTAT
= (FMCSTAT_BANK0READY
<< bank
);
167 static void nand_set_fmctrl0(uint32_t bank
, uint32_t flags
)
169 FMCTRL0
= (nand_tunk1
[bank
] << 16) | (nand_twp
[bank
] << 12)
170 | (1 << 11) | 1 | (1 << (bank
+ 1)) | flags
;
173 static uint32_t nand_send_cmd(uint32_t cmd
)
176 return nand_wait_rbbdone();
179 static uint32_t nand_send_address(uint32_t page
, uint32_t offset
)
182 FMADDR0
= (page
<< 16) | offset
;
183 FMADDR1
= (page
>> 16) & 0xFF;
184 FMCTRL1
= FMCTRL1_DOTRANSADDR
;
185 return nand_wait_cmddone();
188 uint32_t nand_reset(uint32_t bank
)
190 nand_set_fmctrl0(bank
, 0);
191 if (nand_send_cmd(NAND_CMD_RESET
)) return 1;
192 if (nand_wait_chip_ready(bank
)) return 1;
193 FMCTRL1
= FMCTRL1_CLEARRFIFO
| FMCTRL1_CLEARWFIFO
;
198 static uint32_t nand_wait_status_ready(uint32_t bank
)
200 long timeout
= current_tick
+ HZ
/ 50;
201 nand_set_fmctrl0(bank
, 0);
202 if ((FMCSTAT
& (FMCSTAT_BANK0READY
<< bank
)))
203 FMCSTAT
= (FMCSTAT_BANK0READY
<< bank
);
204 FMCTRL1
= FMCTRL1_CLEARRFIFO
;
205 if (nand_send_cmd(NAND_CMD_GET_STATUS
)) return 1;
208 if (nand_timeout(timeout
)) return 1;
210 FMCTRL1
= FMCTRL1_DOREADDATA
;
211 if (nand_wait_addrdone()) return 1;
212 if ((FMFIFO
& NAND_STATUS_READY
)) break;
213 FMCTRL1
= FMCTRL1_CLEARRFIFO
;
215 FMCTRL1
= FMCTRL1_CLEARRFIFO
;
216 return nand_send_cmd(NAND_CMD_READ
);
219 static void nand_transfer_data_start(uint32_t bank
, uint32_t direction
,
220 void* buffer
, uint32_t size
)
222 nand_set_fmctrl0(bank
, FMCTRL0_ENABLEDMA
);
224 FMCTRL1
= FMCTRL1_DOREADDATA
<< direction
;
225 DMACON3
= (2 << DMACON_DEVICE_SHIFT
)
226 | (direction
<< DMACON_DIRECTION_SHIFT
)
227 | (2 << DMACON_DATA_SIZE_SHIFT
)
228 | (3 << DMACON_BURST_LEN_SHIFT
);
229 while ((DMAALLST
& DMAALLST_CHAN3_MASK
))
230 DMACOM3
= DMACOM_CLEARBOTHDONE
;
231 DMABASE3
= (uint32_t)buffer
;
232 DMATCNT3
= (size
>> 4) - 1;
237 static uint32_t nand_transfer_data_collect(uint32_t direction
)
239 long timeout
= current_tick
+ HZ
/ 50;
240 while ((DMAALLST
& DMAALLST_DMABUSY3
))
241 if (nand_timeout(timeout
)) return 1;
242 if (!direction
) commit_discard_dcache();
243 if (nand_wait_addrdone()) return 1;
244 if (!direction
) FMCTRL1
= FMCTRL1_CLEARRFIFO
| FMCTRL1_CLEARWFIFO
;
245 else FMCTRL1
= FMCTRL1_CLEARRFIFO
;
249 static uint32_t nand_transfer_data(uint32_t bank
, uint32_t direction
,
250 void* buffer
, uint32_t size
)
252 nand_transfer_data_start(bank
, direction
, buffer
, size
);
253 uint32_t rc
= nand_transfer_data_collect(direction
);
257 static void ecc_start(uint32_t size
, void* databuffer
, void* sparebuffer
,
260 mutex_lock(&ecc_mtx
);
264 ECC_DATA_PTR
= (uint32_t)databuffer
;
265 ECC_SPARE_PTR
= (uint32_t)sparebuffer
;
270 static uint32_t ecc_collect(void)
272 long timeout
= current_tick
+ HZ
/ 50;
273 while (!(SRCPND
& INTMSK_ECC
))
274 if (nand_timeout(timeout
)) return ecc_unlock(1);
275 commit_discard_dcache();
278 return ecc_unlock(ECC_RESULT
);
281 static uint32_t ecc_decode(uint32_t size
, void* databuffer
, void* sparebuffer
)
283 ecc_start(size
, databuffer
, sparebuffer
, ECCCTRL_STARTDECODING
);
284 uint32_t rc
= ecc_collect();
288 static uint32_t ecc_encode(uint32_t size
, void* databuffer
, void* sparebuffer
)
290 ecc_start(size
, databuffer
, sparebuffer
, ECCCTRL_STARTENCODING
);
295 static uint32_t nand_check_empty(uint8_t* buffer
)
299 for (i
= 0; i
< 0x40; i
++) if (buffer
[i
] != 0xFF) count
++;
300 if (count
< 2) return 1;
304 static uint32_t nand_get_chip_type(uint32_t bank
)
306 mutex_lock(&nand_mtx
);
308 if (nand_reset(bank
)) return nand_unlock(0xFFFFFFFE);
309 if (nand_send_cmd(0x90)) return nand_unlock(0xFFFFFFFD);
312 FMCTRL1
= FMCTRL1_DOTRANSADDR
;
313 if (nand_wait_cmddone()) return nand_unlock(0xFFFFFFFC);
315 FMCTRL1
= FMCTRL1_DOREADDATA
;
316 if (nand_wait_addrdone()) return nand_unlock(0xFFFFFFFB);
318 FMCTRL1
= FMCTRL1_CLEARRFIFO
;
319 return nand_unlock(result
);
322 void nand_set_active(void)
324 nand_last_activity_value
= current_tick
;
327 long nand_last_activity(void)
329 return nand_last_activity_value
;
332 void nand_power_up(void)
335 mutex_lock(&nand_mtx
);
336 nand_last_activity_value
= current_tick
;
345 PCON5
= (PCON5
& ~0xF) | 3;
347 pmu_ldo_set_voltage(4, 0x15);
350 nand_last_activity_value
= current_tick
;
351 for (i
= 0; i
< 4; i
++)
352 if (nand_type
[i
] >= 0)
354 panicf("nand_power_up: nand_reset(bank=%d) failed.",(unsigned int)i
);
356 nand_last_activity_value
= current_tick
;
357 mutex_unlock(&nand_mtx
);
360 void nand_power_down(void)
362 if (!nand_powered
) return;
363 mutex_lock(&nand_mtx
);
364 pmu_ldo_power_off(4);
371 PCON5
= (PCON5
& ~0xF) | 1;
376 mutex_unlock(&nand_mtx
);
379 uint32_t nand_read_page(uint32_t bank
, uint32_t page
, void* databuffer
,
380 void* sparebuffer
, uint32_t doecc
,
383 uint8_t* data
= nand_data
;
384 uint8_t* spare
= nand_spare
;
385 if (databuffer
&& !((uint32_t)databuffer
& 0xf))
386 data
= (uint8_t*)databuffer
;
387 if (sparebuffer
&& !((uint32_t)sparebuffer
& 0xf))
388 spare
= (uint8_t*)sparebuffer
;
389 mutex_lock(&nand_mtx
);
390 nand_last_activity_value
= current_tick
;
392 if (!nand_powered
) nand_power_up();
393 uint32_t rc
, eccresult
;
394 nand_set_fmctrl0(bank
, FMCTRL0_ENABLEDMA
);
395 if (nand_send_cmd(NAND_CMD_READ
)) return nand_unlock(1);
396 if (nand_send_address(page
, databuffer
? 0 : 0x800))
397 return nand_unlock(1);
398 if (nand_send_cmd(NAND_CMD_READ2
)) return nand_unlock(1);
399 if (nand_wait_status_ready(bank
)) return nand_unlock(1);
401 if (nand_transfer_data(bank
, 0, data
, 0x800))
402 return nand_unlock(1);
406 if (databuffer
&& data
!= databuffer
) memcpy(databuffer
, data
, 0x800);
409 if (nand_transfer_data(bank
, 0, spare
, 0x40))
410 return nand_unlock(1);
411 if (sparebuffer
&& spare
!= sparebuffer
)
412 memcpy(sparebuffer
, spare
, 0x800);
414 rc
= nand_check_empty((uint8_t*)sparebuffer
) << 1;
416 return nand_unlock(rc
);
418 if (nand_transfer_data(bank
, 0, spare
, 0x40)) return nand_unlock(1);
421 memcpy(nand_ecc
, &spare
[0xC], 0x28);
422 rc
|= (ecc_decode(3, data
, nand_ecc
) & 0xF) << 4;
423 if (data
!= databuffer
) memcpy(databuffer
, data
, 0x800);
425 memset(nand_ctrl
, 0xFF, 0x200);
426 memcpy(nand_ctrl
, spare
, 0xC);
427 memcpy(nand_ecc
, &spare
[0x34], 0xC);
428 eccresult
= ecc_decode(0, nand_ctrl
, nand_ecc
);
429 rc
|= (eccresult
& 0xF) << 8;
432 if (spare
!= sparebuffer
) memcpy(sparebuffer
, spare
, 0x40);
433 if (eccresult
& 1) memset(sparebuffer
, 0xFF, 0xC);
434 else memcpy(sparebuffer
, nand_ctrl
, 0xC);
436 if (checkempty
) rc
|= nand_check_empty(spare
) << 1;
438 return nand_unlock(rc
);
441 static uint32_t nand_write_page_int(uint32_t bank
, uint32_t page
,
442 void* databuffer
, void* sparebuffer
,
443 uint32_t doecc
, uint32_t wait
)
445 uint8_t* data
= nand_data
;
446 uint8_t* spare
= nand_spare
;
447 if (databuffer
&& !((uint32_t)databuffer
& 0xf))
448 data
= (uint8_t*)databuffer
;
449 if (sparebuffer
&& !((uint32_t)sparebuffer
& 0xf))
450 spare
= (uint8_t*)sparebuffer
;
451 mutex_lock(&nand_mtx
);
452 nand_last_activity_value
= current_tick
;
454 if (!nand_powered
) nand_power_up();
457 if (spare
!= sparebuffer
) memcpy(spare
, sparebuffer
, 0x40);
459 else memset(spare
, 0xFF, 0x40);
460 nand_set_fmctrl0(bank
, FMCTRL0_ENABLEDMA
);
461 if (nand_send_cmd(NAND_CMD_PROGRAM
)) return nand_unlock(1);
462 if (nand_send_address(page
, databuffer
? 0 : 0x800))
463 return nand_unlock(1);
464 if (databuffer
&& data
!= databuffer
) memcpy(data
, databuffer
, 0x800);
465 if (databuffer
) nand_transfer_data_start(bank
, 1, data
, 0x800);
468 if (ecc_encode(3, data
, nand_ecc
)) return nand_unlock(1);
469 memcpy(&spare
[0xC], nand_ecc
, 0x28);
470 memset(nand_ctrl
, 0xFF, 0x200);
471 memcpy(nand_ctrl
, spare
, 0xC);
472 if (ecc_encode(0, nand_ctrl
, nand_ecc
)) return nand_unlock(1);
473 memcpy(&spare
[0x34], nand_ecc
, 0xC);
476 if (nand_transfer_data_collect(1))
477 return nand_unlock(1);
478 if (sparebuffer
|| doecc
)
479 if (nand_transfer_data(bank
, 1, spare
, 0x40))
480 return nand_unlock(1);
481 if (nand_send_cmd(NAND_CMD_PROGCNFRM
)) return nand_unlock(1);
482 if (wait
) if (nand_wait_status_ready(bank
)) return nand_unlock(1);
483 return nand_unlock(0);
486 uint32_t nand_block_erase(uint32_t bank
, uint32_t page
)
488 mutex_lock(&nand_mtx
);
489 nand_last_activity_value
= current_tick
;
491 if (!nand_powered
) nand_power_up();
492 nand_set_fmctrl0(bank
, 0);
493 if (nand_send_cmd(NAND_CMD_BLOCKERASE
)) return nand_unlock(1);
496 FMCTRL1
= FMCTRL1_DOTRANSADDR
;
497 if (nand_wait_cmddone()) return nand_unlock(1);
498 if (nand_send_cmd(NAND_CMD_ERASECNFRM
)) return nand_unlock(1);
499 if (nand_wait_status_ready(bank
)) return nand_unlock(1);
500 return nand_unlock(0);
503 uint32_t nand_read_page_fast(uint32_t page
, void* databuffer
,
504 void* sparebuffer
, uint32_t doecc
,
508 if (((uint32_t)databuffer
& 0xf) || ((uint32_t)sparebuffer
& 0xf)
509 || !databuffer
|| !sparebuffer
|| !doecc
)
511 for (i
= 0; i
< 4; i
++)
513 if (nand_type
[i
] < 0) continue;
514 void* databuf
= (void*)0;
515 void* sparebuf
= (void*)0;
516 if (databuffer
) databuf
= (void*)((uint32_t)databuffer
+ 0x800 * i
);
517 if (sparebuffer
) sparebuf
= (void*)((uint32_t)sparebuffer
+ 0x40 * i
);
518 uint32_t ret
= nand_read_page(i
, page
, databuf
, sparebuf
, doecc
, checkempty
);
519 if (ret
& 1) rc
|= 1 << (i
<< 2);
520 if (ret
& 2) rc
|= 2 << (i
<< 2);
521 if (ret
& 0x10) rc
|= 4 << (i
<< 2);
522 if (ret
& 0x100) rc
|= 8 << (i
<< 2);
526 mutex_lock(&nand_mtx
);
527 nand_last_activity_value
= current_tick
;
529 if (!nand_powered
) nand_power_up();
531 for (i
= 0; i
< 4; i
++) status
[i
] = (nand_type
[i
] < 0);
532 for (i
= 0; i
< 4; i
++)
536 nand_set_fmctrl0(i
, FMCTRL0_ENABLEDMA
);
537 if (nand_send_cmd(NAND_CMD_READ
))
541 if (nand_send_address(page
, 0))
544 if (nand_send_cmd(NAND_CMD_READ2
))
548 if (nand_wait_status_ready(0))
551 if (nand_transfer_data(0, 0, databuffer
, 0x800))
554 if (nand_transfer_data(0, 0, sparebuffer
, 0x40))
556 for (i
= 1; i
< 4; i
++)
559 if (nand_wait_status_ready(i
))
562 nand_transfer_data_start(i
, 0, (void*)((uint32_t)databuffer
563 + 0x800 * i
), 0x800);
566 memcpy(nand_ecc
, (void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1) + 0xC), 0x28);
567 ecc_start(3, (void*)((uint32_t)databuffer
568 + 0x800 * (i
- 1)), nand_ecc
, ECCCTRL_STARTDECODING
);
571 if (nand_transfer_data_collect(0))
574 nand_transfer_data_start(i
, 0, (void*)((uint32_t)sparebuffer
577 if (ecc_collect() & 1)
581 memset(nand_ctrl
, 0xFF, 0x200);
582 memcpy(nand_ctrl
, (void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1)), 0xC);
583 memcpy(nand_ecc
, (void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1) + 0x34), 0xC);
584 ecc_start(0, nand_ctrl
, nand_ecc
, ECCCTRL_STARTDECODING
);
587 if (nand_transfer_data_collect(0))
591 if (ecc_collect() & 1)
594 memset((void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1)), 0xFF, 0xC);
596 else memcpy((void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1)), nand_ctrl
, 0xC);
598 status
[i
- 1] |= nand_check_empty((void*)((uint32_t)sparebuffer
599 + 0x40 * (i
- 1))) << 1;
604 memcpy(nand_ecc
,(void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1) + 0xC), 0x28);
605 if (ecc_decode(3, (void*)((uint32_t)databuffer
606 + 0x800 * (i
- 1)), nand_ecc
) & 1)
611 memset(nand_ctrl
, 0xFF, 0x200);
612 memcpy(nand_ctrl
, (void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1)), 0xC);
613 memcpy(nand_ecc
, (void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1) + 0x34), 0xC);
614 if (ecc_decode(0, nand_ctrl
, nand_ecc
) & 1)
617 memset((void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1)), 0xFF, 0xC);
619 else memcpy((void*)((uint32_t)sparebuffer
+ 0x40 * (i
- 1)), nand_ctrl
, 0xC);
621 status
[i
- 1] |= nand_check_empty((void*)((uint32_t)sparebuffer
622 + 0x40 * (i
- 1))) << 1;
624 for (i
= 0; i
< 4; i
++)
625 if (nand_type
[i
] < 0)
626 rc
|= status
[i
] << (i
<< 2);
627 return nand_unlock(rc
);
630 uint32_t nand_write_page(uint32_t bank
, uint32_t page
, void* databuffer
,
631 void* sparebuffer
, uint32_t doecc
)
633 return nand_write_page_int(bank
, page
, databuffer
, sparebuffer
, doecc
, 1);
636 uint32_t nand_write_page_start(uint32_t bank
, uint32_t page
, void* databuffer
,
637 void* sparebuffer
, uint32_t doecc
)
639 if (((uint32_t)databuffer
& 0xf) || ((uint32_t)sparebuffer
& 0xf)
640 || !databuffer
|| !sparebuffer
|| !doecc
|| !nand_interleaved
)
641 return nand_write_page_int(bank
, page
, databuffer
, sparebuffer
, doecc
, !nand_interleaved
);
643 mutex_lock(&nand_mtx
);
644 nand_last_activity_value
= current_tick
;
646 if (!nand_powered
) nand_power_up();
647 nand_set_fmctrl0(bank
, FMCTRL0_ENABLEDMA
);
648 if (nand_send_cmd(NAND_CMD_PROGRAM
))
649 return nand_unlock(1);
650 if (nand_send_address(page
, 0))
651 return nand_unlock(1);
652 nand_transfer_data_start(bank
, 1, databuffer
, 0x800);
653 if (ecc_encode(3, databuffer
, nand_ecc
))
654 return nand_unlock(1);
655 memcpy((void*)((uint32_t)sparebuffer
+ 0xC), nand_ecc
, 0x28);
656 memset(nand_ctrl
, 0xFF, 0x200);
657 memcpy(nand_ctrl
, sparebuffer
, 0xC);
658 if (ecc_encode(0, nand_ctrl
, nand_ecc
))
659 return nand_unlock(1);
660 memcpy((void*)((uint32_t)sparebuffer
+ 0x34), nand_ecc
, 0xC);
661 if (nand_transfer_data_collect(0))
662 return nand_unlock(1);
663 if (nand_transfer_data(bank
, 1, sparebuffer
, 0x40))
664 return nand_unlock(1);
665 return nand_unlock(nand_send_cmd(NAND_CMD_PROGCNFRM
));
668 uint32_t nand_write_page_collect(uint32_t bank
)
670 return nand_wait_status_ready(bank
);
673 #if 0 /* currently unused */
674 static uint32_t nand_block_erase_fast(uint32_t page
)
677 mutex_lock(&nand_mtx
);
678 nand_last_activity_value
= current_tick
;
680 if (!nand_powered
) nand_power_up();
681 for (i
= 0; i
< 4; i
++)
683 if (nand_type
[i
] < 0) continue;
684 nand_set_fmctrl0(i
, 0);
685 if (nand_send_cmd(NAND_CMD_BLOCKERASE
))
692 FMCTRL1
= FMCTRL1_DOTRANSADDR
;
693 if (nand_wait_cmddone())
698 if (nand_send_cmd(NAND_CMD_ERASECNFRM
)) rc
|= 1 << i
;
700 for (i
= 0; i
< 4; i
++)
702 if (nand_type
[i
] < 0) continue;
703 if (rc
& (1 << i
)) continue;
704 if (nand_wait_status_ready(i
)) rc
|= 1 << i
;
706 return nand_unlock(rc
);
710 const struct nand_device_info_type
* nand_get_device_type(uint32_t bank
)
712 if (nand_type
[bank
] < 0)
713 return (struct nand_device_info_type
*)0;
714 return &nand_deviceinfotable
[nand_type
[bank
]];
717 static void nand_thread(void)
721 if (TIME_AFTER(current_tick
, nand_last_activity_value
+ HZ
/ 5)
724 call_storage_idle_notifys(false);
731 int nand_device_init(void)
733 mutex_init(&nand_mtx
);
734 semaphore_init(&nand_complete
, 1, 0);
735 mutex_init(&ecc_mtx
);
736 semaphore_init(&ecc_complete
, 1, 0);
741 /* Assume there are 0 banks, to prevent
742 nand_power_up from talking with them yet. */
743 for (i
= 0; i
< 4; i
++) nand_type
[i
] = -1;
746 /* Now that the flash is powered on, detect how
747 many banks we really have and initialize them. */
748 for (i
= 0; i
< 4; i
++)
754 type
= nand_get_chip_type(i
);
755 if (type
>= 0xFFFFFFF0)
757 nand_type
[i
] = (int)type
;
762 if (j
== ARRAYLEN(nand_deviceinfotable
)) break;
763 else if (nand_deviceinfotable
[j
].id
== type
)
769 nand_tunk1
[i
] = nand_deviceinfotable
[nand_type
[i
]].tunk1
;
770 nand_twp
[i
] = nand_deviceinfotable
[nand_type
[i
]].twp
;
771 nand_tunk2
[i
] = nand_deviceinfotable
[nand_type
[i
]].tunk2
;
772 nand_tunk3
[i
] = nand_deviceinfotable
[nand_type
[i
]].tunk3
;
774 if (nand_type
[0] < 0) return nand_type
[0];
775 nand_interleaved
= ((nand_deviceinfotable
[nand_type
[0]].id
>> 22) & 1);
776 nand_cached
= ((nand_deviceinfotable
[nand_type
[0]].id
>> 23) & 1);
778 nand_last_activity_value
= current_tick
;
779 create_thread(nand_thread
, nand_stack
,
780 sizeof(nand_stack
), 0, "nand"
781 IF_PRIO(, PRIORITY_USER_INTERFACE
)