1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2006 Daniel Ankers
11 * Copyright © 2008-2009 Rafaël Carré
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
23 #include "config.h" /* for HAVE_MULTIVOLUME */
26 #include "gcc_extensions.h"
36 #include "pl081.h" /* DMA controller */
37 #include "dma-target.h" /* DMA request lines */
38 #include "clock-target.h"
41 #include "ata_idle_notify.h"
49 #if defined(SANSA_FUZEV2)
50 #include "backlight-target.h"
57 #define INTERNAL_AS3525 0 /* embedded SD card */
58 #define SD_SLOT_AS3525 1 /* SD slot if present */
60 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
61 #define AMS_OF_SIZE 0xf000
64 #define MCI_NO_RESP (0<<0)
65 #define MCI_RESP (1<<0)
66 #define MCI_LONG_RESP (1<<1)
67 #define MCI_ACMD (1<<2)
69 /* controller registers */
70 #define SD_BASE 0xC6070000
72 #define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x))
74 #define MCI_CTRL SD_REG(0x00)
77 #define CTRL_RESET (1<<0)
78 #define FIFO_RESET (1<<1)
79 #define DMA_RESET (1<<2)
80 #define INT_ENABLE (1<<4)
81 #define DMA_ENABLE (1<<5)
82 #define READ_WAIT (1<<6)
83 #define SEND_IRQ_RESP (1<<7)
84 #define ABRT_READ_DATA (1<<8)
85 #define SEND_CCSD (1<<9)
86 #define SEND_AS_CCSD (1<<10)
87 #define EN_OD_PULLUP (1<<24)
90 #define MCI_PWREN SD_REG(0x04) /* power enable */
92 #define PWR_CRD_0 (1<<0)
93 #define PWR_CRD_1 (1<<1)
94 #define PWR_CRD_2 (1<<2)
95 #define PWR_CRD_3 (1<<3)
97 #define MCI_CLKDIV SD_REG(0x08) /* clock divider */
98 /* CLK_DIV_0 : bits 7:0
99 * CLK_DIV_1 : bits 15:8
100 * CLK_DIV_2 : bits 23:16
101 * CLK_DIV_3 : bits 31:24
104 #define MCI_CLKSRC SD_REG(0x0C) /* clock source */
105 /* CLK_SRC_CRD0: bits 1:0
106 * CLK_SRC_CRD1: bits 3:2
107 * CLK_SRC_CRD2: bits 5:4
108 * CLK_SRC_CRD3: bits 7:6
111 #define MCI_CLKENA SD_REG(0x10) /* clock enable */
113 #define CCLK_ENA_CRD0 (1<<0)
114 #define CCLK_ENA_CRD1 (1<<1)
115 #define CCLK_ENA_CRD2 (1<<2)
116 #define CCLK_ENA_CRD3 (1<<3)
117 #define CCLK_LP_CRD0 (1<<16) /* LP --> Low Power Mode? */
118 #define CCLK_LP_CRD1 (1<<17)
119 #define CCLK_LP_CRD2 (1<<18)
120 #define CCLK_LP_CRD3 (1<<19)
122 #define MCI_TMOUT SD_REG(0x14) /* timeout */
123 /* response timeout bits 0:7
124 * data timeout bits 8:31
127 #define MCI_CTYPE SD_REG(0x18) /* card type */
128 /* 1 bit per card, set = wide bus */
129 #define WIDTH4_CRD0 (1<<0)
130 #define WIDTH4_CRD1 (1<<1)
131 #define WIDTH4_CRD2 (1<<2)
132 #define WIDTH4_CRD3 (1<<3)
134 #define MCI_BLKSIZ SD_REG(0x1C) /* block size bits 0:15*/
135 #define MCI_BYTCNT SD_REG(0x20) /* byte count bits 0:31*/
136 #define MCI_MASK SD_REG(0x24) /* interrupt mask */
140 #define MCI_ARGUMENT SD_REG(0x28)
141 #define MCI_COMMAND SD_REG(0x2C)
143 /* command bits (bits 5:0 are the command index) */
144 #define CMD_RESP_EXP_BIT (1<<6)
145 #define CMD_RESP_LENGTH_BIT (1<<7)
146 #define CMD_CHECK_CRC_BIT (1<<8)
147 #define CMD_DATA_EXP_BIT (1<<9)
148 #define CMD_RW_BIT (1<<10)
149 #define CMD_TRANSMODE_BIT (1<<11)
150 #define CMD_SENT_AUTO_STOP_BIT (1<<12)
151 #define CMD_WAIT_PRV_DAT_BIT (1<<13)
152 #define CMD_ABRT_CMD_BIT (1<<14)
153 #define CMD_SEND_INIT_BIT (1<<15)
154 #define CMD_CARD_NO(x) ((x)<<16) /* 5 bits wide */
155 #define CMD_SEND_CLK_ONLY (1<<21)
156 #define CMD_READ_CEATA (1<<22)
157 #define CMD_CCS_EXPECTED (1<<23)
158 #define CMD_DONE_BIT (1<<31)
160 #define TRANSFER_CMD (cmd == SD_READ_MULTIPLE_BLOCK || \
161 cmd == SD_WRITE_MULTIPLE_BLOCK)
163 #define MCI_RESP0 SD_REG(0x30)
164 #define MCI_RESP1 SD_REG(0x34)
165 #define MCI_RESP2 SD_REG(0x38)
166 #define MCI_RESP3 SD_REG(0x3C)
168 #define MCI_MASK_STATUS SD_REG(0x40) /* masked interrupt status */
169 #define MCI_RAW_STATUS SD_REG(0x44) /* raw interrupt status, also used as
172 /* interrupt bits */ /* C D E (Cmd) (Data) (End) */
173 #define MCI_INT_CRDDET (1<<0) /* card detect */
174 #define MCI_INT_RE (1<<1) /* x response error */
175 #define MCI_INT_CD (1<<2) /* x command done */
176 #define MCI_INT_DTO (1<<3) /* x data transfer over */
177 #define MCI_INT_TXDR (1<<4) /* tx fifo data request */
178 #define MCI_INT_RXDR (1<<5) /* rx fifo data request */
179 #define MCI_INT_RCRC (1<<6) /* x response crc error */
180 #define MCI_INT_DCRC (1<<7) /* x data crc error */
181 #define MCI_INT_RTO (1<<8) /* x response timeout */
182 #define MCI_INT_DRTO (1<<9) /* x data read timeout */
183 #define MCI_INT_HTO (1<<10) /* x data starv timeout */
184 #define MCI_INT_FRUN (1<<11) /* x fifo over/underrun */
185 #define MCI_INT_HLE (1<<12) /* x x hw locked while error */
186 #define MCI_INT_SBE (1<<13) /* x start bit error */
187 #define MCI_INT_ACD (1<<14) /* auto command done */
188 #define MCI_INT_EBE (1<<15) /* x end bit error */
189 #define MCI_INT_SDIO (0xf<<16)
193 * & 0xBA80 = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
194 * MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
196 * & 0x428 = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
197 * & 0x418 = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
200 #define MCI_CMD_ERROR \
206 #define MCI_DATA_ERROR \
215 #define MCI_STATUS SD_REG(0x48)
217 #define FIFO_RX_WM (1<<0)
218 #define FIFO_TX_WM (1<<1)
219 #define FIFO_EMPTY (1<<2)
220 #define FIFO_FULL (1<<3)
221 #define CMD_FSM_STATE_B0 (1<<4)
222 #define CMD_FSM_STATE_B1 (1<<5)
223 #define CMD_FSM_STATE_B2 (1<<6)
224 #define CMD_FSM_STATE_B3 (1<<7)
225 #define DATA_3_STAT (1<<8)
226 #define DATA_BUSY (1<<9)
227 #define DATA_STAT_MC_BUSY (1<<10)
228 #define RESP_IDX_B0 (1<<11)
229 #define RESP_IDX_B1 (1<<12)
230 #define RESP_IDX_B2 (1<<13)
231 #define RESP_IDX_B3 (1<<14)
232 #define RESP_IDX_B4 (1<<15)
233 #define RESP_IDX_B5 (1<<16)
234 #define FIFO_CNT_B00 (1<<17)
235 #define FIFO_CNT_B01 (1<<18)
236 #define FIFO_CNT_B02 (1<<19)
237 #define FIFO_CNT_B03 (1<<20)
238 #define FIFO_CNT_B04 (1<<21)
239 #define FIFO_CNT_B05 (1<<22)
240 #define FIFO_CNT_B06 (1<<23)
241 #define FIFO_CNT_B07 (1<<24)
242 #define FIFO_CNT_B08 (1<<25)
243 #define FIFO_CNT_B09 (1<<26)
244 #define FIFO_CNT_B10 (1<<27)
245 #define FIFO_CNT_B11 (1<<28)
246 #define FIFO_CNT_B12 (1<<29)
247 #define DMA_ACK (1<<30)
248 #define START_CMD (1<<31)
250 #define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */
251 /* TX watermark : bits 11:0
252 * RX watermark : bits 27:16
253 * DMA MTRANS SIZE : bits 30:28
254 * bits 31, 15:12 : unused
256 #define MCI_FIFOTH_MASK 0x8000f000
258 #define MCI_CDETECT SD_REG(0x50) /* card detect */
260 #define CDETECT_CRD_0 (1<<0)
261 #define CDETECT_CRD_1 (1<<1)
262 #define CDETECT_CRD_2 (1<<2)
263 #define CDETECT_CRD_3 (1<<3)
265 #define MCI_WRTPRT SD_REG(0x54) /* write protect */
266 #define MCI_GPIO SD_REG(0x58)
267 #define MCI_TCBCNT SD_REG(0x5C) /* transferred CIU byte count (card)*/
268 #define MCI_TBBCNT SD_REG(0x60) /* transferred host/DMA to/from bytes (FIFO)*/
269 #define MCI_DEBNCE SD_REG(0x64) /* card detect debounce bits 23:0*/
270 #define MCI_USRID SD_REG(0x68) /* user id */
271 #define MCI_VERID SD_REG(0x6C) /* version id */
273 #define MCI_HCON SD_REG(0x70) /* hardware config */
275 * bits 5:1 : maximum card index
277 * bits 9:7 : DATA WIDTH
278 * bits 15:10 : ADDR WIDTH
279 * bits 17:16 : DMA IF
280 * bits 20:18 : DMA WIDTH
281 * bit 21 : FIFO RAM INSIDE
282 * bit 22 : IMPL HOLD REG
283 * bit 23 : SET CLK FALSE
284 * bits 25:24 : MAX CLK DIV IDX
285 * bit 26 : AREA OPTIM
288 #define MCI_BMOD SD_REG(0x80) /* bus mode */
296 #define MCI_PLDMND SD_REG(0x84) /* poll demand */
297 #define MCI_DBADDR SD_REG(0x88) /* descriptor base address */
298 #define MCI_IDSTS SD_REG(0x8C) /* internal DMAC status */
312 #define MCI_IDINTEN SD_REG(0x90) /* internal DMAC interrupt enable */
323 #define MCI_DSCADDR SD_REG(0x94) /* current host descriptor address */
324 #define MCI_BUFADDR SD_REG(0x98) /* current host buffer address */
326 #define MCI_FIFO ((unsigned long *) (SD_BASE+0x100))
328 #define UNALIGNED_NUM_SECTORS 10
329 static unsigned char aligned_buffer
[UNALIGNED_NUM_SECTORS
* SD_BLOCK_SIZE
] __attribute__((aligned(32))); /* align on cache line size */
330 static unsigned char *uncached_buffer
= AS3525_UNCACHED_ADDR(&aligned_buffer
[0]);
332 static tCardInfo card_info
[NUM_DRIVES
];
334 /* for compatibility */
335 static long last_disk_activity
= -1;
337 #define MIN_YIELD_PERIOD 5 /* ticks */
338 static long next_yield
= 0;
340 static long sd_stack
[(DEFAULT_STACK_SIZE
*2 + 0x200)/sizeof(long)];
341 static const char sd_thread_name
[] = "ata/sd";
342 static struct mutex sd_mtx SHAREDBSS_ATTR
;
343 static struct event_queue sd_queue
;
345 bool sd_enabled
= false;
348 static struct wakeup transfer_completion_signal
;
349 static struct wakeup command_completion_signal
;
350 static volatile bool retry
;
351 static volatile int cmd_error
;
353 #if defined(HAVE_MULTIDRIVE)
354 #define EXT_SD_BITS (1<<2)
357 static inline void mci_delay(void) { udelay(1000); }
361 MCI_CTRL
&= ~INT_ENABLE
;
362 /* use raw status here as we need to check some Ints that are masked */
363 const int status
= MCI_RAW_STATUS
;
365 MCI_RAW_STATUS
= status
; /* clear status */
367 if(status
& MCI_DATA_ERROR
)
370 if( status
& (MCI_INT_DTO
|MCI_DATA_ERROR
))
371 wakeup_signal(&transfer_completion_signal
);
373 cmd_error
= status
& MCI_CMD_ERROR
;
375 if(status
& MCI_INT_CD
)
376 wakeup_signal(&command_completion_signal
);
378 MCI_CTRL
|= INT_ENABLE
;
381 static inline bool card_detect_target(void)
383 #if defined(HAVE_MULTIDRIVE)
384 #if defined(SANSA_FUZEV2)
386 #elif defined(SANSA_CLIPPLUS)
387 return !(GPIOA_PIN(2));
389 #error "microSD pin not defined for your target"
396 static bool send_cmd(const int drive
, const int cmd
, const int arg
, const int flags
,
397 unsigned long *response
)
401 if ((flags
& MCI_ACMD
) && /* send SD_APP_CMD first */
402 !send_cmd(drive
, SD_APP_CMD
, card_info
[drive
].rca
, MCI_RESP
, response
))
405 #if defined(HAVE_MULTIDRIVE)
406 if(sd_present(SD_SLOT_AS3525
))
407 GPIOB_PIN(5) = (1-drive
) << 5;
412 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
413 if (amsv2_variant
== 1)
417 card_no
= CMD_CARD_NO(drive
);
419 /* Construct MCI_COMMAND */
422 /*b6 */ | ((flags
& MCI_RESP
) ? CMD_RESP_EXP_BIT
: 0)
423 /*b7 */ | ((flags
& MCI_LONG_RESP
) ? CMD_RESP_LENGTH_BIT
: 0)
424 /*b8 | CMD_CHECK_CRC_BIT unused */
425 /*b9 */ | (TRANSFER_CMD
? CMD_DATA_EXP_BIT
: 0)
426 /*b10 */ | ((cmd
== SD_WRITE_MULTIPLE_BLOCK
) ? CMD_RW_BIT
: 0)
427 /*b11 | CMD_TRANSMODE_BIT unused */
428 /*b12 | CMD_SENT_AUTO_STOP_BIT unused */
429 /*b13 */ | (TRANSFER_CMD
? CMD_WAIT_PRV_DAT_BIT
: 0)
430 /*b14 | CMD_ABRT_CMD_BIT unused */
431 /*b15 | CMD_SEND_INIT_BIT unused */
432 /*b20:16 */ | card_no
433 /*b21 | CMD_SEND_CLK_ONLY unused */
434 /*b22 | CMD_READ_CEATA unused */
435 /*b23 | CMD_CCS_EXPECTED unused */
436 /*b31 */ | CMD_DONE_BIT
;
438 #if defined(SANSA_FUZEV2)
439 if (amsv2_variant
== 0)
441 extern int buttonlight_is_on
;
442 if(buttonlight_is_on
)
448 wakeup_wait(&command_completion_signal
, TIMEOUT_BLOCK
);
450 /* Handle command responses & errors */
453 if(cmd_error
& (MCI_INT_RCRC
| MCI_INT_RTO
))
456 if(flags
& MCI_LONG_RESP
)
458 response
[0] = MCI_RESP3
;
459 response
[1] = MCI_RESP2
;
460 response
[2] = MCI_RESP1
;
461 response
[3] = MCI_RESP0
;
464 response
[0] = MCI_RESP0
;
469 static int sd_wait_for_tran_state(const int drive
)
471 unsigned long response
;
472 unsigned int timeout
= current_tick
+ 5*HZ
;
476 while(!(send_cmd(drive
, SD_SEND_STATUS
, card_info
[drive
].rca
, MCI_RESP
, &response
)));
478 if (((response
>> 9) & 0xf) == SD_TRAN
)
481 if(TIME_AFTER(current_tick
, timeout
))
482 return -10 * ((response
>> 9) & 0xf);
484 if (TIME_AFTER(current_tick
, next_yield
))
487 next_yield
= current_tick
+ MIN_YIELD_PERIOD
;
493 static int sd_init_card(const int drive
)
495 unsigned long response
;
499 card_info
[drive
].rca
= 0;
501 /* assume 24 MHz clock / 60 = 400 kHz */
502 MCI_CLKDIV
= (MCI_CLKDIV
& ~(0xFF)) | 0x3C; /* CLK_DIV_0 : bits 7:0 */
504 /* 100 - 400kHz clock required for Identification Mode */
505 /* Start of Card Identification Mode ************************************/
508 if(!send_cmd(drive
, SD_GO_IDLE_STATE
, 0, MCI_NO_RESP
, NULL
))
512 /* CMD8 Check for v2 sd card. Must be sent before using ACMD41
513 Non v2 cards will not respond to this command*/
514 if(send_cmd(drive
, SD_SEND_IF_COND
, 0x1AA, MCI_RESP
, &response
))
515 if((response
& 0xFFF) == 0x1AA)
518 /* timeout for initialization is 1sec, from SD Specification 2.00 */
519 init_timeout
= current_tick
+ HZ
;
522 /* this timeout is the only valid error for this loop*/
523 if(TIME_AFTER(current_tick
, init_timeout
))
526 /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
527 if(!send_cmd(drive
, SD_APP_OP_COND
, (0x00FF8000 | (sd_v2
? 1<<30 : 0)),
528 MCI_ACMD
|MCI_RESP
, &card_info
[drive
].ocr
))
530 } while(!(card_info
[drive
].ocr
& (1<<31)) );
533 if(!send_cmd(drive
, SD_ALL_SEND_CID
, 0, MCI_RESP
|MCI_LONG_RESP
, card_info
[drive
].cid
))
537 if(!send_cmd(drive
, SD_SEND_RELATIVE_ADDR
, 0, MCI_RESP
, &card_info
[drive
].rca
))
540 #ifdef HAVE_MULTIDRIVE
541 /* Make sure we have 2 unique rca numbers */
542 if(card_info
[INTERNAL_AS3525
].rca
== card_info
[SD_SLOT_AS3525
].rca
)
543 if(!send_cmd(drive
, SD_SEND_RELATIVE_ADDR
, 0, MCI_RESP
, &card_info
[drive
].rca
))
546 /* End of Card Identification Mode ************************************/
550 /* Attempt to switch cards to HS timings, non HS cards just ignore this */
551 /* CMD7 w/rca: Select card to put it in TRAN state */
552 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_NO_RESP
, NULL
))
555 if(sd_wait_for_tran_state(drive
))
559 if(!send_cmd(drive
, SD_SWITCH_FUNC
, 0x80fffff1, MCI_NO_RESP
, NULL
))
563 /* We need to go back to STBY state now so we can read csd */
564 /* CMD7 w/rca=0: Deselect card to put it in STBY state */
565 if(!send_cmd(drive
, SD_DESELECT_CARD
, 0, MCI_NO_RESP
, NULL
))
570 if(!send_cmd(drive
, SD_SEND_CSD
, card_info
[drive
].rca
,
571 MCI_RESP
|MCI_LONG_RESP
, card_info
[drive
].csd
))
574 sd_parse_csd(&card_info
[drive
]);
576 if(drive
== INTERNAL_AS3525
) /* The OF is stored in the first blocks */
577 card_info
[INTERNAL_AS3525
].numblocks
-= AMS_OF_SIZE
;
579 /* Card back to full speed */
580 MCI_CLKDIV
&= ~(0xFF); /* CLK_DIV_0 : bits 7:0 = 0x00 */
582 /* CMD7 w/rca: Select card to put it in TRAN state */
583 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_NO_RESP
, NULL
))
587 /* Switch to to 4 bit widebus mode */
588 if(sd_wait_for_tran_state(drive
) < 0)
591 if(!send_cmd(drive
, SD_SET_BUS_WIDTH
, 2, MCI_ACMD
|MCI_NO_RESP
, NULL
))
595 if(!send_cmd(drive
, SD_SET_CLR_CARD_DETECT
, 0, MCI_ACMD
|MCI_NO_RESP
, NULL
))
598 /* Now that card is widebus make controller aware */
599 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
600 if (amsv2_variant
== 1)
604 MCI_CTYPE
|= (1<<drive
);
606 #endif /* ! BOOTLOADER */
608 /* Set low power mode */
609 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
610 if (amsv2_variant
== 1)
614 MCI_CLKENA
|= 1<<(drive
+ 16);
616 card_info
[drive
].initialized
= 1;
621 static void sd_thread(void) NORETURN_ATTR
;
622 static void sd_thread(void)
624 struct queue_event ev
;
625 bool idle_notified
= false;
629 queue_wait_w_tmo(&sd_queue
, &ev
, HZ
);
634 case SYS_HOTSWAP_INSERTED
:
635 case SYS_HOTSWAP_EXTRACTED
:
637 int microsd_init
= 1;
638 fat_lock(); /* lock-out FAT activity first -
639 prevent deadlocking via disk_mount that
640 would cause a reverse-order attempt with
642 mutex_lock(&sd_mtx
); /* lock-out card activity - direct calls
643 into driver that bypass the fat cache */
645 /* We now have exclusive control of fat cache and ata */
647 disk_unmount(SD_SLOT_AS3525
); /* release "by force", ensure file
648 descriptors aren't leaked and any busy
649 ones are invalid if mounting */
650 /* Force card init for new card, re-init for re-inserted one or
651 * clear if the last attempt to init failed with an error. */
652 card_info
[SD_SLOT_AS3525
].initialized
= 0;
654 if (ev
.id
== SYS_HOTSWAP_INSERTED
)
657 microsd_init
= sd_init_card(SD_SLOT_AS3525
);
658 if (microsd_init
< 0) /* initialisation failed */
659 panicf("microSD init failed : %d", microsd_init
);
661 microsd_init
= disk_mount(SD_SLOT_AS3525
); /* 0 if fail */
665 * Mount succeeded, or this was an EXTRACTED event,
666 * in both cases notify the system about the changed filesystems
669 queue_broadcast(SYS_FS_CHANGED
, 0);
670 /* Access is now safe */
671 mutex_unlock(&sd_mtx
);
678 if (TIME_BEFORE(current_tick
, last_disk_activity
+(3*HZ
)))
680 idle_notified
= false;
684 /* never let a timer wrap confuse us */
685 next_yield
= current_tick
;
689 call_storage_idle_notifys(false);
690 idle_notified
= true;
695 case SYS_USB_CONNECTED
:
696 usb_acknowledge(SYS_USB_CONNECTED_ACK
);
697 /* Wait until the USB cable is extracted again */
698 usb_wait_for_disconnect(&sd_queue
);
701 case SYS_USB_DISCONNECTED
:
702 usb_acknowledge(SYS_USB_DISCONNECTED_ACK
);
708 static void init_controller(void)
710 int hcon_numcards
= ((MCI_HCON
>>1) & 0x1F) + 1;
711 int card_mask
= (1 << hcon_numcards
) - 1;
714 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
715 if (amsv2_variant
== 1)
719 pwr_mask
= card_mask
;
721 MCI_PWREN
&= ~pwr_mask
; /* power off all cards */
722 MCI_PWREN
= pwr_mask
; /* power up cards */
724 MCI_CTRL
|= CTRL_RESET
;
725 while(MCI_CTRL
& CTRL_RESET
)
728 MCI_RAW_STATUS
= 0xffffffff; /* Clear all MCI Interrupts */
730 MCI_TMOUT
= 0xffffffff; /* data b31:8, response b7:0 */
732 MCI_CTYPE
= 0x0; /* all cards 1 bit bus for now */
734 MCI_CLKENA
= card_mask
; /* Enables card clocks */
737 MCI_COMMAND
= CMD_DONE_BIT
|CMD_SEND_CLK_ONLY
|CMD_WAIT_PRV_DAT_BIT
;
738 while(MCI_COMMAND
& CMD_DONE_BIT
)
741 MCI_DEBNCE
= 0xfffff; /* default value */
743 /* Rx watermark = 63(sd reads) Tx watermark = 128 (sd writes) */
744 MCI_FIFOTH
= (MCI_FIFOTH
& MCI_FIFOTH_MASK
) | 0x503f0080;
746 /* RCRC & RTO interrupts should be set together with the CD interrupt but
747 * in practice sometimes incorrectly precede the CD interrupt. If we leave
748 * them masked for now we can check them in the isr by reading raw status when
749 * the CD int is triggered.
751 MCI_MASK
|= (MCI_DATA_ERROR
| MCI_INT_DTO
| MCI_INT_CD
);
753 MCI_CTRL
|= INT_ENABLE
| DMA_ENABLE
;
755 MCI_BLKSIZ
= SD_BLOCK_SIZE
;
762 bitset32(&CGU_PERI
, CGU_MCI_CLOCK_ENABLE
);
764 CGU_IDE
= (1<<7) /* AHB interface enable */
765 | (AS3525_IDE_DIV
<< 2)
766 | 1; /* clock source = PLLA */
768 CGU_MEMSTICK
= (1<<7) /* interface enable */
769 | (AS3525_MS_DIV
<< 2)
770 | 1; /* clock source = PLLA */
772 CGU_SDSLOT
= (1<<7) /* interface enable */
773 | (AS3525_SDSLOT_DIV
<< 2)
774 | 1; /* clock source = PLLA */
776 wakeup_init(&transfer_completion_signal
);
777 wakeup_init(&command_completion_signal
);
779 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
780 if (amsv2_variant
== 1)
784 #ifdef HAVE_MULTIDRIVE
785 /* clear previous irq */
786 GPIOA_IC
= EXT_SD_BITS
;
787 /* enable edge detecting */
788 GPIOA_IS
&= ~EXT_SD_BITS
;
789 /* detect both raising and falling edges */
790 GPIOA_IBE
|= EXT_SD_BITS
;
791 /* enable the card detect interrupt */
792 GPIOA_IE
|= EXT_SD_BITS
;
793 #endif /* HAVE_MULTIDRIVE */
796 /* Configure XPD for SD-MCI interface */
797 bitset32(&CCU_IO
, 1<<2);
800 VIC_INT_ENABLE
= INTERRUPT_NAND
;
803 ret
= sd_init_card(INTERNAL_AS3525
);
810 queue_init(&sd_queue
, true);
811 create_thread(sd_thread
, sd_stack
, sizeof(sd_stack
), 0,
812 sd_thread_name
IF_PRIO(, PRIORITY_USER_INTERFACE
) IF_COP(, CPU
));
821 static int sd_transfer_sectors(IF_MD2(int drive
,) unsigned long start
,
822 int count
, void* buf
, bool write
)
825 #ifndef HAVE_MULTIDRIVE
828 bool aligned
= !((uintptr_t)buf
& (CACHEALIGN_SIZE
- 1));
837 if (card_info
[drive
].initialized
<= 0)
839 ret
= sd_init_card(drive
);
840 if (!(card_info
[drive
].initialized
))
841 goto sd_transfer_error_no_dma
;
844 if(count
< 0) /* XXX: why is it signed ? */
847 goto sd_transfer_error_no_dma
;
849 if((start
+count
) > card_info
[drive
].numblocks
)
852 goto sd_transfer_error_no_dma
;
855 /* skip SanDisk OF */
856 if (drive
== INTERNAL_AS3525
)
857 start
+= AMS_OF_SIZE
;
859 /* CMD7 w/rca: Select card to put it in TRAN state */
860 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_NO_RESP
, NULL
))
863 goto sd_transfer_error_no_dma
;
866 last_disk_activity
= current_tick
;
870 { /* direct transfer, indirect is always uncached */
872 commit_dcache_range(buf
, count
* SECTOR_SIZE
);
874 discard_dcache_range(buf
, count
* SECTOR_SIZE
);
877 const int cmd
= write
? SD_WRITE_MULTIPLE_BLOCK
: SD_READ_MULTIPLE_BLOCK
;
882 unsigned int transfer
= count
;
886 dma_buf
= AS3525_PHYSICAL_ADDR(buf
);
890 dma_buf
= AS3525_PHYSICAL_ADDR(&aligned_buffer
[0]);
891 if(transfer
> UNALIGNED_NUM_SECTORS
)
892 transfer
= UNALIGNED_NUM_SECTORS
;
895 memcpy(uncached_buffer
, buf
, transfer
* SD_BLOCK_SIZE
);
898 /* Interrupt handler might set this to true during transfer */
901 MCI_BYTCNT
= transfer
* SD_BLOCK_SIZE
;
903 ret
= sd_wait_for_tran_state(drive
);
907 goto sd_transfer_error
;
911 if(!(card_info
[drive
].ocr
& (1<<30))) /* not SDHC */
912 arg
*= SD_BLOCK_SIZE
;
915 dma_enable_channel(0, dma_buf
, MCI_FIFO
, DMA_PERI_SD
,
916 DMAC_FLOWCTRL_PERI_MEM_TO_PERI
, true, false, 0, DMA_S8
, NULL
);
918 dma_enable_channel(0, MCI_FIFO
, dma_buf
, DMA_PERI_SD
,
919 DMAC_FLOWCTRL_PERI_PERI_TO_MEM
, false, true, 0, DMA_S8
, NULL
);
921 unsigned long dummy
; /* if we don't ask for a response, writing fails */
922 if(!send_cmd(drive
, cmd
, arg
, MCI_RESP
, &dummy
))
925 goto sd_transfer_error
;
928 wakeup_wait(&transfer_completion_signal
, TIMEOUT_BLOCK
);
930 last_disk_activity
= current_tick
;
934 /* wait for the card to exit programming state */
935 while(MCI_STATUS
& DATA_BUSY
) ;
938 if(!send_cmd(drive
, SD_STOP_TRANSMISSION
, 0, MCI_NO_RESP
, NULL
))
941 goto sd_transfer_error
;
946 if(!write
&& !aligned
)
947 memcpy(buf
, uncached_buffer
, transfer
* SD_BLOCK_SIZE
);
948 buf
+= transfer
* SD_BLOCK_SIZE
;
952 else /* reset controller if we had an error */
954 MCI_CTRL
|= (FIFO_RESET
|DMA_RESET
);
955 while(MCI_CTRL
& (FIFO_RESET
|DMA_RESET
))
959 } while(retry
|| count
);
963 /* CMD lines are separate, not common, so we need to actively deselect */
964 /* CMD7 w/rca =0 : deselects card & puts it in STBY state */
965 if(!send_cmd(drive
, SD_DESELECT_CARD
, 0, MCI_NO_RESP
, NULL
))
968 goto sd_transfer_error
;
975 mutex_unlock(&sd_mtx
);
982 sd_transfer_error_no_dma
:
984 card_info
[drive
].initialized
= 0;
985 mutex_unlock(&sd_mtx
);
989 int sd_read_sectors(IF_MD2(int drive
,) unsigned long start
, int count
,
992 return sd_transfer_sectors(IF_MD2(drive
,) start
, count
, buf
, false);
995 int sd_write_sectors(IF_MD2(int drive
,) unsigned long start
, int count
,
998 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
999 #ifdef HAVE_MULTIDRIVE
1007 return sd_transfer_sectors(IF_MD2(drive
,) start
, count
, (void*)buf
, true);
1008 #endif /* defined(BOOTLOADER) */
1012 long sd_last_disk_activity(void)
1014 return last_disk_activity
;
1017 void sd_enable(bool on
)
1021 bitset32(&CGU_PERI
, CGU_MCI_CLOCK_ENABLE
);
1022 CGU_IDE
|= (1<<7); /* AHB interface enable */
1023 CGU_MEMSTICK
|= (1<<7); /* interface enable */
1024 CGU_SDSLOT
|= (1<<7); /* interface enable */
1028 CGU_SDSLOT
&= ~(1<<7); /* interface enable */
1029 CGU_MEMSTICK
&= ~(1<<7); /* interface enable */
1030 CGU_IDE
&= ~(1<<7); /* AHB interface enable */
1031 bitclr32(&CGU_PERI
, CGU_MCI_CLOCK_ENABLE
);
1035 tCardInfo
*card_get_info_target(int card_no
)
1037 return &card_info
[card_no
];
1039 #endif /* BOOTLOADER */
1042 bool sd_removable(IF_MD_NONVOID(int drive
))
1047 bool sd_present(IF_MD_NONVOID(int drive
))
1049 return (drive
== 0) ? true : card_detect_target();
1052 static int sd1_oneshot_callback(struct timeout
*tmo
)
1056 /* This is called only if the state was stable for 300ms - check state
1057 * and post appropriate event. */
1058 if (card_detect_target())
1060 queue_broadcast(SYS_HOTSWAP_INSERTED
, 0);
1063 queue_broadcast(SYS_HOTSWAP_EXTRACTED
, 0);
1068 void sd_gpioa_isr(void)
1070 static struct timeout sd1_oneshot
;
1071 if (GPIOA_MIS
& EXT_SD_BITS
)
1072 timeout_register(&sd1_oneshot
, sd1_oneshot_callback
, (3*HZ
/10), 0);
1073 /* acknowledge interrupt */
1074 GPIOA_IC
= EXT_SD_BITS
;
1076 #endif /* HAVE_HOTSWAP */
1078 #ifdef CONFIG_STORAGE_MULTI
1079 int sd_num_drives(int first_drive
)
1081 /* We don't care which logical drive number(s) we have been assigned */
1086 #endif /* CONFIG_STORAGE_MULTI */