firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "gcc_extensions.h"
  27 #include "led.h"
  28 #include "sdmmc.h"
  29 #include "system.h"
  30 #include "kernel.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "as3525v2.h"
  36 #include "pl081.h"  /* DMA controller */
  37 #include "dma-target.h" /* DMA request lines */
  38 #include "clock-target.h"
  39 #include "panic.h"
  40 #include "stdbool.h"
  41 #include "ata_idle_notify.h"
  42 #include "sd.h"
  43 #include "usb.h"
  44
  45 #ifdef HAVE_HOTSWAP
  46 #include "disk.h"
  47 #endif
  48
  49 #if defined(SANSA_FUZEV2)
  50 #include "backlight-target.h"
  51 #endif
  52
  53 #include "lcd.h"
  54 #include <stdarg.h>
  55 #include "sysfont.h"
  56
  57 #define     INTERNAL_AS3525  0   /* embedded SD card */
  58 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  59
  60 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
  61 #define AMS_OF_SIZE 0xf000
  62
  63 /* command flags */
  64 #define MCI_NO_RESP     (0<<0)
  65 #define MCI_RESP        (1<<0)
  66 #define MCI_LONG_RESP   (1<<1)
  67
  68 /* controller registers */
  69 #define SD_BASE 0xC6070000
  70
  71 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  72
  73 #define MCI_CTRL        SD_REG(0x00)
  74
  75 /* control bits */
  76 #define CTRL_RESET      (1<<0)
  77 #define FIFO_RESET      (1<<1)
  78 #define DMA_RESET       (1<<2)
  79 #define INT_ENABLE      (1<<4)
  80 #define DMA_ENABLE      (1<<5)
  81 #define READ_WAIT       (1<<6)
  82 #define SEND_IRQ_RESP   (1<<7)
  83 #define ABRT_READ_DATA  (1<<8)
  84 #define SEND_CCSD       (1<<9)
  85 #define SEND_AS_CCSD    (1<<10)
  86 #define EN_OD_PULLUP    (1<<24)
  87
  88
  89 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  90
  91 #define PWR_CRD_0       (1<<0)
  92 #define PWR_CRD_1       (1<<1)
  93 #define PWR_CRD_2       (1<<2)
  94 #define PWR_CRD_3       (1<<3)
  95
  96 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  97 /* CLK_DIV_0 :    bits 7:0
  98  * CLK_DIV_1 :    bits 15:8
  99  * CLK_DIV_2 :    bits 23:16
 100  * CLK_DIV_3 :    bits 31:24
 101  */
 102
 103 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
 104 /* CLK_SRC_CRD0:  bits 1:0
 105  * CLK_SRC_CRD1:  bits 3:2
 106  * CLK_SRC_CRD2:  bits 5:4
 107  * CLK_SRC_CRD3:  bits 7:6
 108  */
 109
 110 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 111
 112 #define CCLK_ENA_CRD0   (1<<0)
 113 #define CCLK_ENA_CRD1   (1<<1)
 114 #define CCLK_ENA_CRD2   (1<<2)
 115 #define CCLK_ENA_CRD3   (1<<3)
 116 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 117 #define CCLK_LP_CRD1    (1<<17)
 118 #define CCLK_LP_CRD2    (1<<18)
 119 #define CCLK_LP_CRD3    (1<<19)
 120
 121 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 122 /* response timeout bits 0:7
 123  * data timeout bits     8:31
 124  */
 125
 126 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 127                                         /* 1 bit per card, set = wide bus */
 128 #define WIDTH4_CRD0     (1<<0)
 129 #define WIDTH4_CRD1     (1<<1)
 130 #define WIDTH4_CRD2     (1<<2)
 131 #define WIDTH4_CRD3     (1<<3)
 132
 133 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 134 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 135 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 136
 137
 138
 139 #define MCI_ARGUMENT    SD_REG(0x28)
 140 #define MCI_COMMAND     SD_REG(0x2C)
 141
 142 /* command bits (bits 5:0 are the command index) */
 143 #define CMD_RESP_EXP_BIT        (1<<6)
 144 #define CMD_RESP_LENGTH_BIT     (1<<7)
 145 #define CMD_CHECK_CRC_BIT       (1<<8)
 146 #define CMD_DATA_EXP_BIT        (1<<9)
 147 #define CMD_RW_BIT              (1<<10)
 148 #define CMD_TRANSMODE_BIT       (1<<11)
 149 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 150 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 151 #define CMD_ABRT_CMD_BIT        (1<<14)
 152 #define CMD_SEND_INIT_BIT       (1<<15)
 153 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 154 #define CMD_SEND_CLK_ONLY       (1<<21)
 155 #define CMD_READ_CEATA          (1<<22)
 156 #define CMD_CCS_EXPECTED        (1<<23)
 157 #define CMD_DONE_BIT            (1<<31)
 158
 159 #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
 160                        cmd == SD_WRITE_MULTIPLE_BLOCK)
 161
 162 #define MCI_RESP0       SD_REG(0x30)
 163 #define MCI_RESP1       SD_REG(0x34)
 164 #define MCI_RESP2       SD_REG(0x38)
 165 #define MCI_RESP3       SD_REG(0x3C)
 166
 167 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 168 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 169                                          * status clear */
 170
 171 /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
 172 #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
 173 #define MCI_INT_RE      (1<<1)      /* x         response error */
 174 #define MCI_INT_CD      (1<<2)      /*     x     command done */
 175 #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
 176 #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
 177 #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
 178 #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
 179 #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
 180 #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
 181 #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
 182 #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
 183 #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
 184 #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
 185 #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
 186 #define MCI_INT_ACD     (1<<14)     /*          auto command done */
 187 #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
 188 #define MCI_INT_SDIO    (0xf<<16)
 189
 190 /*
 191  *  STATUS register
 192  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 193  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 194  *  & 8         = MCI_INT_DTO
 195  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 196  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 197  */
 198
 199 #define MCI_CMD_ERROR    \
 200          (MCI_INT_RE   | \
 201           MCI_INT_RCRC | \
 202           MCI_INT_RTO  | \
 203           MCI_INT_HLE)
 204
 205 #define MCI_DATA_ERROR    \
 206         ( MCI_INT_DCRC  | \
 207           MCI_INT_DRTO  | \
 208           MCI_INT_HTO   | \
 209           MCI_INT_FRUN  | \
 210           MCI_INT_HLE   | \
 211           MCI_INT_SBE   | \
 212           MCI_INT_EBE)
 213
 214 #define MCI_STATUS      SD_REG(0x48)
 215
 216 #define FIFO_RX_WM              (1<<0)
 217 #define FIFO_TX_WM              (1<<1)
 218 #define FIFO_EMPTY              (1<<2)
 219 #define FIFO_FULL               (1<<3)
 220 #define CMD_FSM_STATE_B0        (1<<4)
 221 #define CMD_FSM_STATE_B1        (1<<5)
 222 #define CMD_FSM_STATE_B2        (1<<6)
 223 #define CMD_FSM_STATE_B3        (1<<7)
 224 #define DATA_3_STAT             (1<<8)
 225 #define DATA_BUSY               (1<<9)
 226 #define DATA_STAT_MC_BUSY       (1<<10)
 227 #define RESP_IDX_B0             (1<<11)
 228 #define RESP_IDX_B1             (1<<12)
 229 #define RESP_IDX_B2             (1<<13)
 230 #define RESP_IDX_B3             (1<<14)
 231 #define RESP_IDX_B4             (1<<15)
 232 #define RESP_IDX_B5             (1<<16)
 233 #define FIFO_CNT_B00            (1<<17)
 234 #define FIFO_CNT_B01            (1<<18)
 235 #define FIFO_CNT_B02            (1<<19)
 236 #define FIFO_CNT_B03            (1<<20)
 237 #define FIFO_CNT_B04            (1<<21)
 238 #define FIFO_CNT_B05            (1<<22)
 239 #define FIFO_CNT_B06            (1<<23)
 240 #define FIFO_CNT_B07            (1<<24)
 241 #define FIFO_CNT_B08            (1<<25)
 242 #define FIFO_CNT_B09            (1<<26)
 243 #define FIFO_CNT_B10            (1<<27)
 244 #define FIFO_CNT_B11            (1<<28)
 245 #define FIFO_CNT_B12            (1<<29)
 246 #define DMA_ACK                 (1<<30)
 247 #define START_CMD               (1<<31)
 248
 249 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 250 /* TX watermark :    bits 11:0
 251  * RX watermark :    bits 27:16
 252  * DMA MTRANS SIZE : bits 30:28
 253  * bits 31, 15:12 : unused
 254  */
 255 #define MCI_FIFOTH_MASK 0x8000f000
 256
 257 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 258
 259 #define CDETECT_CRD_0   (1<<0)
 260 #define CDETECT_CRD_1   (1<<1)
 261 #define CDETECT_CRD_2   (1<<2)
 262 #define CDETECT_CRD_3   (1<<3)
 263
 264 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 265 #define MCI_GPIO        SD_REG(0x58)
 266 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 267 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 268 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 269 #define MCI_USRID       SD_REG(0x68)    /* user id */
 270 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 271
 272 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 273 /* bit  0       : card type
 274  * bits 5:1     : maximum card index
 275  * bit  6       : BUS TYPE
 276  * bits 9:7     : DATA WIDTH
 277  * bits 15:10   : ADDR WIDTH
 278  * bits 17:16   : DMA IF
 279  * bits 20:18   : DMA WIDTH
 280  * bit  21      : FIFO RAM INSIDE
 281  * bit  22      : IMPL HOLD REG
 282  * bit  23      : SET CLK FALSE
 283  * bits 25:24   : MAX CLK DIV IDX
 284  * bit  26      : AREA OPTIM
 285  */
 286
 287 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 288 /* bit  0       : SWR
 289  * bit  1       : FB
 290  * bits 6:2     : DSL
 291  * bit  7       : DE
 292  * bit  10:8    : PBL
 293  */
 294
 295 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 296 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 297 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 298 /* bit  0       : TI
 299  * bit  1       : RI
 300  * bit  2       : FBE
 301  * bit  3       : unused
 302  * bit  4       : DU
 303  * bit  5       : CES
 304  * bits 7:6     : unused
 305  * bits 8       : NIS
 306  * bit  9       : AIS
 307  * bits 12:10   : EB
 308  * bits 16:13   : FSM
 309  */
 310
 311 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 312 /* bit  0       : TI
 313  * bit  1       : RI
 314  * bit  2       : FBE
 315  * bit  3       : unused
 316  * bit  4       : DU
 317  * bit  5       : CES
 318  * bits 7:6     : unused
 319  * bits 8       : NI
 320  * bit  9       : AI
 321  */
 322 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 323 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 324
 325 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 326
 327 #define UNALIGNED_NUM_SECTORS 10
 328 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 329 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 330
 331 static tCardInfo card_info[NUM_DRIVES];
 332
 333 /* for compatibility */
 334 static long last_disk_activity = -1;
 335
 336 #define MIN_YIELD_PERIOD 5  /* ticks */
 337 static long next_yield = 0;
 338
 339 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 340 static const char         sd_thread_name[] = "ata/sd";
 341 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 342 static struct event_queue sd_queue;
 343 #ifndef BOOTLOADER
 344 bool sd_enabled = false;
 345 #endif
 346
 347 static struct wakeup transfer_completion_signal;
 348 static struct wakeup command_completion_signal;
 349 static volatile bool retry;
 350 static volatile int cmd_error;
 351
 352 #if defined(HAVE_MULTIDRIVE)
 353 #define EXT_SD_BITS (1<<2)
 354 #endif
 355
 356 static inline void mci_delay(void) { udelay(1000); }
 357
 358 void INT_NAND(void)
 359 {
 360     MCI_CTRL &= ~INT_ENABLE;
 361     /* use raw status here as we need to check some Ints that are masked */
 362     const int status = MCI_RAW_STATUS;
 363
 364     MCI_RAW_STATUS = status;    /* clear status */
 365
 366     if(status & MCI_DATA_ERROR)
 367         retry = true;
 368
 369     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
 370         wakeup_signal(&transfer_completion_signal);
 371
 372     cmd_error = status & MCI_CMD_ERROR;
 373
 374     if(status & MCI_INT_CD)
 375         wakeup_signal(&command_completion_signal);
 376
 377     MCI_CTRL |= INT_ENABLE;
 378 }
 379
 380 static inline bool card_detect_target(void)
 381 {
 382 #if defined(HAVE_MULTIDRIVE)
 383 #if defined(SANSA_FUZEV2)
 384     return GPIOA_PIN(2);
 385 #elif defined(SANSA_CLIPPLUS)
 386     return !(GPIOA_PIN(2));
 387 #else
 388 #error "microSD pin not defined for your target"
 389 #endif
 390 #else
 391     return false;
 392 #endif
 393 }
 394
 395 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 396         unsigned long *response)
 397 {
 398     int card_no;
 399
 400 #if defined(HAVE_MULTIDRIVE)
 401     if(sd_present(SD_SLOT_AS3525))
 402         GPIOB_PIN(5) = (1-drive) << 5;
 403 #endif
 404
 405     MCI_ARGUMENT = arg;
 406
 407 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 408     if (amsv2_variant == 1)
 409         card_no = 1 << 16;
 410     else
 411 #endif
 412         card_no = CMD_CARD_NO(drive);
 413
 414     /* Construct MCI_COMMAND  */
 415     MCI_COMMAND =
 416       /*b5:0*/    cmd
 417       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
 418       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
 419       /*b8      | CMD_CHECK_CRC_BIT       unused  */
 420       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
 421       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
 422       /*b11     | CMD_TRANSMODE_BIT       unused  */
 423       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
 424       /*b13 */  | (TRANSFER_CMD                      ? CMD_WAIT_PRV_DAT_BIT:  0)
 425       /*b14     | CMD_ABRT_CMD_BIT        unused  */
 426       /*b15     | CMD_SEND_INIT_BIT       unused  */
 427    /*b20:16 */  |                                      card_no
 428       /*b21     | CMD_SEND_CLK_ONLY       unused  */
 429       /*b22     | CMD_READ_CEATA          unused  */
 430       /*b23     | CMD_CCS_EXPECTED        unused  */
 431       /*b31 */  |                                      CMD_DONE_BIT;
 432
 433 #if defined(SANSA_FUZEV2)
 434     if (amsv2_variant == 0)
 435     {
 436         extern int buttonlight_is_on;
 437         if(buttonlight_is_on)
 438             _buttonlight_on();
 439         else
 440             _buttonlight_off();
 441     }
 442 #endif
 443     wakeup_wait(&command_completion_signal, TIMEOUT_BLOCK);
 444
 445     /*  Handle command responses & errors */
 446     if(flags & MCI_RESP)
 447     {
 448         if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
 449             return false;
 450
 451         if(flags & MCI_LONG_RESP)
 452         {
 453             response[0] = MCI_RESP3;
 454             response[1] = MCI_RESP2;
 455             response[2] = MCI_RESP1;
 456             response[3] = MCI_RESP0;
 457         }
 458         else
 459             response[0] = MCI_RESP0;
 460     }
 461     return true;
 462 }
 463
 464 static int sd_wait_for_tran_state(const int drive)
 465 {
 466     unsigned long response;
 467     unsigned int timeout = current_tick + 5*HZ;
 468
 469     while (1)
 470     {
 471         while(!(send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP, &response)));
 472
 473         if (((response >> 9) & 0xf) == SD_TRAN)
 474             return 0;
 475
 476         if(TIME_AFTER(current_tick, timeout))
 477             return -10 * ((response >> 9) & 0xf);
 478
 479         if (TIME_AFTER(current_tick, next_yield))
 480         {
 481             yield();
 482             next_yield = current_tick + MIN_YIELD_PERIOD;
 483         }
 484     }
 485 }
 486
 487
 488 static int sd_init_card(const int drive)
 489 {
 490     unsigned long response;
 491     long init_timeout;
 492     bool sd_v2 = false;
 493
 494     /*  assume 24 MHz clock / 60 = 400 kHz  */
 495     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 496
 497     /* 100 - 400kHz clock required for Identification Mode  */
 498     /*  Start of Card Identification Mode ************************************/
 499
 500     /* CMD0 Go Idle  */
 501     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 502         return -1;
 503     mci_delay();
 504
 505     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 506       Non v2 cards will not respond to this command*/
 507     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 508         if((response & 0xFFF) == 0x1AA)
 509             sd_v2 = true;
 510
 511     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 512     init_timeout = current_tick + HZ;
 513
 514     do {
 515         /* this timeout is the only valid error for this loop*/
 516         if(TIME_AFTER(current_tick, init_timeout))
 517             return -2;
 518
 519         /* app_cmd */
 520         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 521
 522          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 523         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 524                         MCI_RESP, &card_info[drive].ocr))
 525             return -3;
 526     } while(!(card_info[drive].ocr & (1<<31)) );
 527
 528     /* CMD2 send CID */
 529     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 530         return -4;
 531
 532     /* CMD3 send RCA */
 533     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 534         return -5;
 535
 536 #ifdef HAVE_MULTIDRIVE
 537     /* Make sure we have 2 unique rca numbers */
 538     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 539         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 540             return -6;
 541 #endif
 542     /*  End of Card Identification Mode   ************************************/
 543
 544     if (sd_v2)
 545     {
 546         /* Attempt to switch cards to HS timings, non HS cards just ignore this */
 547         /*  CMD7 w/rca: Select card to put it in TRAN state */
 548         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 549             return -7;
 550
 551         if(sd_wait_for_tran_state(drive))
 552             return -8;
 553
 554         /* CMD6 */
 555         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 556             return -9;
 557         mci_delay();
 558
 559         /*  We need to go back to STBY state now so we can read csd */
 560         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 561         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 562             return -10;
 563     }
 564
 565     /* CMD9 send CSD */
 566     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 567                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 568         return -11;
 569
 570     sd_parse_csd(&card_info[drive]);
 571
 572     if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
 573         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 574
 575     /*  Card back to full speed  */
 576     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 577
 578     /*  CMD7 w/rca: Select card to put it in TRAN state */
 579     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 580         return -12;
 581
 582 #ifndef BOOTLOADER
 583     /*  Switch to to 4 bit widebus mode  */
 584     if(sd_wait_for_tran_state(drive) < 0)
 585         return -13;
 586     /* CMD55 */              /*  Response is requested due to timing issue  */
 587     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 588         return -14;
 589     /* ACMD6  */
 590     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_NO_RESP, NULL))
 591         return -15;
 592     mci_delay();
 593     /* CMD55 */             /*  Response is requested due to timing issue  */
 594     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 595         return -16;
 596     /* ACMD42  */
 597     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_NO_RESP, NULL))
 598         return -17;
 599
 600     /* Now that card is widebus make controller aware */
 601 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 602     if (amsv2_variant == 1)
 603         MCI_CTYPE |= 1<<1;
 604     else
 605 #endif
 606         MCI_CTYPE |= (1<<drive);
 607
 608 #endif /* ! BOOTLOADER */
 609
 610     /*  Set low power mode  */
 611 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 612     if (amsv2_variant == 1)
 613         MCI_CLKENA |= 1<<16;
 614     else
 615 #endif
 616         MCI_CLKENA |= 1<<(drive + 16);
 617
 618     card_info[drive].initialized = 1;
 619
 620     return 0;
 621 }
 622
 623 static void sd_thread(void) NORETURN_ATTR;
 624 static void sd_thread(void)
 625 {
 626     struct queue_event ev;
 627     bool idle_notified = false;
 628
 629     while (1)
 630     {
 631         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 632
 633         switch ( ev.id )
 634         {
 635 #ifdef HAVE_HOTSWAP
 636         case SYS_HOTSWAP_INSERTED:
 637         case SYS_HOTSWAP_EXTRACTED:
 638         {
 639             int microsd_init = 1;
 640             fat_lock();          /* lock-out FAT activity first -
 641                                     prevent deadlocking via disk_mount that
 642                                     would cause a reverse-order attempt with
 643                                     another thread */
 644             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 645                                     into driver that bypass the fat cache */
 646
 647             /* We now have exclusive control of fat cache and ata */
 648
 649             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 650                                     descriptors aren't leaked and any busy
 651                                     ones are invalid if mounting */
 652             /* Force card init for new card, re-init for re-inserted one or
 653              * clear if the last attempt to init failed with an error. */
 654             card_info[SD_SLOT_AS3525].initialized = 0;
 655
 656             if (ev.id == SYS_HOTSWAP_INSERTED)
 657             {
 658                 sd_enable(true);
 659                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 660                 if (microsd_init < 0) /* initialisation failed */
 661                     panicf("microSD init failed : %d", microsd_init);
 662
 663                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 664             }
 665
 666             /*
 667              * Mount succeeded, or this was an EXTRACTED event,
 668              * in both cases notify the system about the changed filesystems
 669              */
 670             if (microsd_init)
 671                 queue_broadcast(SYS_FS_CHANGED, 0);
 672             /* Access is now safe */
 673             mutex_unlock(&sd_mtx);
 674             fat_unlock();
 675             sd_enable(false);
 676         }
 677             break;
 678 #endif
 679         case SYS_TIMEOUT:
 680             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 681             {
 682                 idle_notified = false;
 683             }
 684             else
 685             {
 686                 /* never let a timer wrap confuse us */
 687                 next_yield = current_tick;
 688
 689                 if (!idle_notified)
 690                 {
 691                     call_storage_idle_notifys(false);
 692                     idle_notified = true;
 693                 }
 694             }
 695             break;
 696
 697         case SYS_USB_CONNECTED:
 698             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 699             /* Wait until the USB cable is extracted again */
 700             usb_wait_for_disconnect(&sd_queue);
 701
 702             break;
 703         case SYS_USB_DISCONNECTED:
 704             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 705             break;
 706         }
 707     }
 708 }
 709
 710 static void init_controller(void)
 711 {
 712     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 713     int card_mask = (1 << hcon_numcards) - 1;
 714     int pwr_mask;
 715
 716 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 717     if (amsv2_variant == 1)
 718         pwr_mask = 1 << 1;
 719     else
 720 #endif
 721         pwr_mask = card_mask;
 722
 723     MCI_PWREN &= ~pwr_mask;             /*  power off all cards  */
 724     MCI_PWREN = pwr_mask;               /*  power up cards  */
 725
 726     MCI_CTRL |= CTRL_RESET;
 727     while(MCI_CTRL & CTRL_RESET)
 728         ;
 729
 730     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
 731
 732     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 733
 734     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 735
 736     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
 737
 738     MCI_ARGUMENT = 0;
 739     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 740     while(MCI_COMMAND & CMD_DONE_BIT)
 741         ;
 742
 743     MCI_DEBNCE = 0xfffff;               /* default value */
 744
 745     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
 746     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
 747
 748 /*  RCRC & RTO interrupts should be set together with the CD interrupt but
 749  *  in practice sometimes incorrectly precede the CD interrupt.  If we leave
 750  *  them masked for now we can check them in the isr by reading raw status when
 751  *  the CD int is triggered.
 752  */
 753     MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO | MCI_INT_CD);
 754
 755     MCI_CTRL |= INT_ENABLE | DMA_ENABLE;
 756
 757     MCI_BLKSIZ = SD_BLOCK_SIZE;
 758 }
 759
 760 int sd_init(void)
 761 {
 762     int ret;
 763
 764     bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
 765
 766     CGU_IDE =   (1<<7)          /* AHB interface enable */
 767             |   (AS3525_IDE_DIV << 2)
 768             |   1;              /* clock source = PLLA */
 769
 770     CGU_MEMSTICK =  (1<<7)      /* interface enable */
 771                  |  (AS3525_MS_DIV << 2)
 772                  |  1;          /* clock source = PLLA */
 773
 774     CGU_SDSLOT = (1<<7)         /* interface enable */
 775                | (AS3525_SDSLOT_DIV << 2)
 776                | 1;             /* clock source = PLLA */
 777
 778     wakeup_init(&transfer_completion_signal);
 779     wakeup_init(&command_completion_signal);
 780
 781 #if defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS)
 782     if (amsv2_variant == 1)
 783         GPIOB_DIR |= 1 << 5;
 784 #endif
 785
 786 #ifdef HAVE_MULTIDRIVE
 787     /* clear previous irq */
 788     GPIOA_IC = EXT_SD_BITS;
 789     /* enable edge detecting */
 790     GPIOA_IS &= ~EXT_SD_BITS;
 791     /* detect both raising and falling edges */
 792     GPIOA_IBE |= EXT_SD_BITS;
 793     /* enable the card detect interrupt */
 794     GPIOA_IE |= EXT_SD_BITS;
 795 #endif /* HAVE_MULTIDRIVE */
 796
 797 #ifndef SANSA_CLIPV2
 798     /* Configure XPD for SD-MCI interface */
 799     bitset32(&CCU_IO, 1<<2);
 800 #endif
 801
 802     VIC_INT_ENABLE = INTERRUPT_NAND;
 803
 804     init_controller();
 805     ret = sd_init_card(INTERNAL_AS3525);
 806     if(ret < 0)
 807         return ret;
 808
 809     /* init mutex */
 810     mutex_init(&sd_mtx);
 811
 812     queue_init(&sd_queue, true);
 813     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 814             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 815
 816 #ifndef BOOTLOADER
 817     sd_enabled = true;
 818     sd_enable(false);
 819 #endif
 820     return 0;
 821 }
 822
 823 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 824                                 int count, void* buf, bool write)
 825 {
 826     int ret = 0;
 827 #ifndef HAVE_MULTIDRIVE
 828     const int drive = 0;
 829 #endif
 830     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 831
 832
 833     mutex_lock(&sd_mtx);
 834 #ifndef BOOTLOADER
 835     sd_enable(true);
 836     led(true);
 837 #endif
 838
 839     if (card_info[drive].initialized <= 0)
 840     {
 841         ret = sd_init_card(drive);
 842         if (!(card_info[drive].initialized))
 843             goto sd_transfer_error_no_dma;
 844     }
 845
 846     if(count < 0) /* XXX: why is it signed ? */
 847     {
 848         ret = -18;
 849         goto sd_transfer_error_no_dma;
 850     }
 851     if((start+count) > card_info[drive].numblocks)
 852     {
 853         ret = -19;
 854         goto sd_transfer_error_no_dma;
 855     }
 856
 857     /* skip SanDisk OF */
 858     if (drive == INTERNAL_AS3525)
 859         start += AMS_OF_SIZE;
 860
 861     /*  CMD7 w/rca: Select card to put it in TRAN state */
 862     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 863     {
 864         ret = -20;
 865         goto sd_transfer_error_no_dma;
 866     }
 867
 868     last_disk_activity = current_tick;
 869     dma_retain();
 870
 871     if(aligned)
 872     {   /* direct transfer, indirect is always uncached */
 873         if(write)
 874             commit_dcache_range(buf, count * SECTOR_SIZE);
 875         else
 876             discard_dcache_range(buf, count * SECTOR_SIZE);
 877     }
 878
 879     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 880
 881     do
 882     {
 883         void *dma_buf;
 884         unsigned int transfer = count;
 885
 886         if(aligned)
 887         {
 888             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 889         }
 890         else
 891         {
 892             dma_buf = AS3525_PHYSICAL_ADDR(&aligned_buffer[0]);
 893             if(transfer > UNALIGNED_NUM_SECTORS)
 894                 transfer = UNALIGNED_NUM_SECTORS;
 895
 896             if(write)
 897                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 898         }
 899
 900         /* Interrupt handler might set this to true during transfer */
 901         retry = false;
 902
 903         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 904
 905         ret = sd_wait_for_tran_state(drive);
 906         if (ret < 0)
 907         {
 908             ret -= 25;
 909             goto sd_transfer_error;
 910         }
 911
 912         int arg = start;
 913         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 914             arg *= SD_BLOCK_SIZE;
 915
 916         if(write)
 917             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 918                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 919         else
 920             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 921                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 922
 923         unsigned long dummy; /* if we don't ask for a response, writing fails */
 924         if(!send_cmd(drive, cmd, arg, MCI_RESP, &dummy))
 925         {
 926             ret = -21;
 927             goto sd_transfer_error;
 928         }
 929
 930         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 931
 932         last_disk_activity = current_tick;
 933
 934         if(write)
 935         {
 936             /* wait for the card to exit programming state */
 937             while(MCI_STATUS & DATA_BUSY) ;
 938         }
 939
 940         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 941         {
 942             ret = -22;
 943             goto sd_transfer_error;
 944         }
 945
 946         if(!retry)
 947         {
 948             if(!write && !aligned)
 949                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 950             buf += transfer * SD_BLOCK_SIZE;
 951             start += transfer;
 952             count -= transfer;
 953         }
 954         else   /*  reset controller if we had an error  */
 955         {
 956             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 957             while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 958                 ;
 959         }
 960
 961     } while(retry || count);
 962
 963     dma_release();
 964
 965     /* CMD lines are separate, not common, so we need to actively deselect */
 966     /*  CMD7 w/rca =0 : deselects card & puts it in STBY state */
 967     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 968     {
 969         ret = -23;
 970         goto sd_transfer_error;
 971     }
 972
 973 #ifndef BOOTLOADER
 974     sd_enable(false);
 975     led(false);
 976 #endif
 977     mutex_unlock(&sd_mtx);
 978     return 0;
 979
 980 sd_transfer_error:
 981
 982     dma_release();
 983
 984 sd_transfer_error_no_dma:
 985
 986     card_info[drive].initialized = 0;
 987     mutex_unlock(&sd_mtx);
 988     return ret;
 989 }
 990
 991 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 992                     void* buf)
 993 {
 994     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 995 }
 996
 997 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 998                      const void* buf)
 999 {
1000 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
1001 #ifdef HAVE_MULTIDRIVE
1002     (void) drive;
1003 #endif
1004     (void) start;
1005     (void) count;
1006     (void) buf;
1007     return -1;
1008 #else
1009     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
1010 #endif /* defined(BOOTLOADER) */
1011 }
1012
1013 #ifndef BOOTLOADER
1014 long sd_last_disk_activity(void)
1015 {
1016     return last_disk_activity;
1017 }
1018
1019 void sd_enable(bool on)
1020 {
1021     if (on)
1022     {
1023         bitset32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1024         CGU_IDE |= (1<<7);                  /* AHB interface enable */
1025         CGU_MEMSTICK |= (1<<7);             /* interface enable */
1026         CGU_SDSLOT |= (1<<7);               /* interface enable */
1027     }
1028     else
1029     {
1030         CGU_SDSLOT &= ~(1<<7);              /* interface enable */
1031         CGU_MEMSTICK &= ~(1<<7);            /* interface enable */
1032         CGU_IDE &= ~(1<<7);                 /* AHB interface enable */
1033         bitclr32(&CGU_PERI, CGU_MCI_CLOCK_ENABLE);
1034     }
1035 }
1036
1037 tCardInfo *card_get_info_target(int card_no)
1038 {
1039     return &card_info[card_no];
1040 }
1041 #endif /* BOOTLOADER */
1042
1043 #ifdef HAVE_HOTSWAP
1044 bool sd_removable(IF_MD_NONVOID(int drive))
1045 {
1046     return (drive==1);
1047 }
1048
1049 bool sd_present(IF_MD_NONVOID(int drive))
1050 {
1051     return (drive == 0) ? true : card_detect_target();
1052 }
1053
1054 static int sd1_oneshot_callback(struct timeout *tmo)
1055 {
1056     (void)tmo;
1057
1058     /* This is called only if the state was stable for 300ms - check state
1059      * and post appropriate event. */
1060     if (card_detect_target())
1061     {
1062         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
1063     }
1064     else
1065         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
1066
1067     return 0;
1068 }
1069
1070 void sd_gpioa_isr(void)
1071 {
1072     static struct timeout sd1_oneshot;
1073     if (GPIOA_MIS & EXT_SD_BITS)
1074         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
1075     /* acknowledge interrupt */
1076     GPIOA_IC = EXT_SD_BITS;
1077 }
1078 #endif /* HAVE_HOTSWAP */
1079
1080 #ifdef CONFIG_STORAGE_MULTI
1081 int sd_num_drives(int first_drive)
1082 {
1083     /* We don't care which logical drive number(s) we have been assigned */
1084     (void)first_drive;
1085
1086     return NUM_DRIVES;
1087 }
1088 #endif /* CONFIG_STORAGE_MULTI */