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sparc64: Set IRQF_DISABLED on LDC channel IRQs.
[linux-2.6/verdex.git] / arch / arm / mach-omap2 / gpmc.c
blobf91934b2b092dc7ca199f853de520637baa32d08
1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #undef DEBUG
16
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/ioport.h>
22 #include <linux/spinlock.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
25
26 #include <asm/mach-types.h>
27 #include <mach/gpmc.h>
28
29 #include <mach/sdrc.h>
30
31 /* GPMC register offsets */
32 #define GPMC_REVISION 0x00
33 #define GPMC_SYSCONFIG 0x10
34 #define GPMC_SYSSTATUS 0x14
35 #define GPMC_IRQSTATUS 0x18
36 #define GPMC_IRQENABLE 0x1c
37 #define GPMC_TIMEOUT_CONTROL 0x40
38 #define GPMC_ERR_ADDRESS 0x44
39 #define GPMC_ERR_TYPE 0x48
40 #define GPMC_CONFIG 0x50
41 #define GPMC_STATUS 0x54
42 #define GPMC_PREFETCH_CONFIG1 0x1e0
43 #define GPMC_PREFETCH_CONFIG2 0x1e4
44 #define GPMC_PREFETCH_CONTROL 0x1ec
45 #define GPMC_PREFETCH_STATUS 0x1f0
46 #define GPMC_ECC_CONFIG 0x1f4
47 #define GPMC_ECC_CONTROL 0x1f8
48 #define GPMC_ECC_SIZE_CONFIG 0x1fc
49
50 #define GPMC_CS0 0x60
51 #define GPMC_CS_SIZE 0x30
52
53 #define GPMC_MEM_START 0x00000000
54 #define GPMC_MEM_END 0x3FFFFFFF
55 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
56
57 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
58 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
59
60 static struct resource gpmc_mem_root;
61 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
62 static DEFINE_SPINLOCK(gpmc_mem_lock);
63 static unsigned gpmc_cs_map;
64
65 static void __iomem *gpmc_base;
66
67 static struct clk *gpmc_l3_clk;
68
69 static void gpmc_write_reg(int idx, u32 val)
70 {
71 __raw_writel(val, gpmc_base + idx);
72 }
73
74 static u32 gpmc_read_reg(int idx)
75 {
76 return __raw_readl(gpmc_base + idx);
77 }
78
79 void gpmc_cs_write_reg(int cs, int idx, u32 val)
80 {
81 void __iomem *reg_addr;
82
83 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
84 __raw_writel(val, reg_addr);
85 }
86
87 u32 gpmc_cs_read_reg(int cs, int idx)
88 {
89 void __iomem *reg_addr;
90
91 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
92 return __raw_readl(reg_addr);
93 }
94
95 /* TODO: Add support for gpmc_fck to clock framework and use it */
96 unsigned long gpmc_get_fclk_period(void)
97 {
98 unsigned long rate = clk_get_rate(gpmc_l3_clk);
99
100 if (rate == 0) {
101 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
102 return 0;
103 }
104
105 rate /= 1000;
106 rate = 1000000000 / rate; /* In picoseconds */
107
108 return rate;
109 }
110
111 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
112 {
113 unsigned long tick_ps;
114
115 /* Calculate in picosecs to yield more exact results */
116 tick_ps = gpmc_get_fclk_period();
117
118 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
119 }
120
121 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
122 {
123 return ticks * gpmc_get_fclk_period() / 1000;
124 }
125
126 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
127 {
128 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
129
130 return ticks * gpmc_get_fclk_period() / 1000;
131 }
132
133 #ifdef DEBUG
134 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
135 int time, const char *name)
136 #else
137 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
138 int time)
139 #endif
140 {
141 u32 l;
142 int ticks, mask, nr_bits;
143
144 if (time == 0)
145 ticks = 0;
146 else
147 ticks = gpmc_ns_to_ticks(time);
148 nr_bits = end_bit - st_bit + 1;
149 if (ticks >= 1 << nr_bits) {
150 #ifdef DEBUG
151 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
152 cs, name, time, ticks, 1 << nr_bits);
153 #endif
154 return -1;
155 }
156
157 mask = (1 << nr_bits) - 1;
158 l = gpmc_cs_read_reg(cs, reg);
159 #ifdef DEBUG
160 printk(KERN_INFO
161 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
162 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
163 (l >> st_bit) & mask, time);
164 #endif
165 l &= ~(mask << st_bit);
166 l |= ticks << st_bit;
167 gpmc_cs_write_reg(cs, reg, l);
168
169 return 0;
170 }
171
172 #ifdef DEBUG
173 #define GPMC_SET_ONE(reg, st, end, field) \
174 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
175 t->field, #field) < 0) \
176 return -1
177 #else
178 #define GPMC_SET_ONE(reg, st, end, field) \
179 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
180 return -1
181 #endif
182
183 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
184 {
185 int div;
186 u32 l;
187
188 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
189 div = l / gpmc_get_fclk_period();
190 if (div > 4)
191 return -1;
192 if (div <= 0)
193 div = 1;
194
195 return div;
196 }
197
198 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
199 {
200 int div;
201 u32 l;
202
203 div = gpmc_cs_calc_divider(cs, t->sync_clk);
204 if (div < 0)
205 return -1;
206
207 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
208 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
209 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
210
211 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
212 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
213 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
214
215 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
216 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
217 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
218 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
219
220 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
221 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
222 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
223
224 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
225
226 if (cpu_is_omap34xx()) {
227 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
228 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
229 }
230
231 /* caller is expected to have initialized CONFIG1 to cover
232 * at least sync vs async
233 */
234 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
235 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
236 #ifdef DEBUG
237 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
238 cs, (div * gpmc_get_fclk_period()) / 1000, div);
239 #endif
240 l &= ~0x03;
241 l |= (div - 1);
242 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
243 }
244
245 return 0;
246 }
247
248 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
249 {
250 u32 l;
251 u32 mask;
252
253 mask = (1 << GPMC_SECTION_SHIFT) - size;
254 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
255 l &= ~0x3f;
256 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
257 l &= ~(0x0f << 8);
258 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
259 l |= 1 << 6; /* CSVALID */
260 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
261 }
262
263 static void gpmc_cs_disable_mem(int cs)
264 {
265 u32 l;
266
267 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
268 l &= ~(1 << 6); /* CSVALID */
269 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
270 }
271
272 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
273 {
274 u32 l;
275 u32 mask;
276
277 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
278 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
279 mask = (l >> 8) & 0x0f;
280 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
281 }
282
283 static int gpmc_cs_mem_enabled(int cs)
284 {
285 u32 l;
286
287 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
288 return l & (1 << 6);
289 }
290
291 int gpmc_cs_set_reserved(int cs, int reserved)
292 {
293 if (cs > GPMC_CS_NUM)
294 return -ENODEV;
295
296 gpmc_cs_map &= ~(1 << cs);
297 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
298
299 return 0;
300 }
301
302 int gpmc_cs_reserved(int cs)
303 {
304 if (cs > GPMC_CS_NUM)
305 return -ENODEV;
306
307 return gpmc_cs_map & (1 << cs);
308 }
309
310 static unsigned long gpmc_mem_align(unsigned long size)
311 {
312 int order;
313
314 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
315 order = GPMC_CHUNK_SHIFT - 1;
316 do {
317 size >>= 1;
318 order++;
319 } while (size);
320 size = 1 << order;
321 return size;
322 }
323
324 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
325 {
326 struct resource *res = &gpmc_cs_mem[cs];
327 int r;
328
329 size = gpmc_mem_align(size);
330 spin_lock(&gpmc_mem_lock);
331 res->start = base;
332 res->end = base + size - 1;
333 r = request_resource(&gpmc_mem_root, res);
334 spin_unlock(&gpmc_mem_lock);
335
336 return r;
337 }
338
339 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
340 {
341 struct resource *res = &gpmc_cs_mem[cs];
342 int r = -1;
343
344 if (cs > GPMC_CS_NUM)
345 return -ENODEV;
346
347 size = gpmc_mem_align(size);
348 if (size > (1 << GPMC_SECTION_SHIFT))
349 return -ENOMEM;
350
351 spin_lock(&gpmc_mem_lock);
352 if (gpmc_cs_reserved(cs)) {
353 r = -EBUSY;
354 goto out;
355 }
356 if (gpmc_cs_mem_enabled(cs))
357 r = adjust_resource(res, res->start & ~(size - 1), size);
358 if (r < 0)
359 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
360 size, NULL, NULL);
361 if (r < 0)
362 goto out;
363
364 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
365 *base = res->start;
366 gpmc_cs_set_reserved(cs, 1);
367 out:
368 spin_unlock(&gpmc_mem_lock);
369 return r;
370 }
371 EXPORT_SYMBOL(gpmc_cs_request);
372
373 void gpmc_cs_free(int cs)
374 {
375 spin_lock(&gpmc_mem_lock);
376 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
377 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
378 BUG();
379 spin_unlock(&gpmc_mem_lock);
380 return;
381 }
382 gpmc_cs_disable_mem(cs);
383 release_resource(&gpmc_cs_mem[cs]);
384 gpmc_cs_set_reserved(cs, 0);
385 spin_unlock(&gpmc_mem_lock);
386 }
387 EXPORT_SYMBOL(gpmc_cs_free);
388
389 static void __init gpmc_mem_init(void)
390 {
391 int cs;
392 unsigned long boot_rom_space = 0;
393
394 /* never allocate the first page, to facilitate bug detection;
395 * even if we didn't boot from ROM.
396 */
397 boot_rom_space = BOOT_ROM_SPACE;
398 /* In apollon the CS0 is mapped as 0x0000 0000 */
399 if (machine_is_omap_apollon())
400 boot_rom_space = 0;
401 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
402 gpmc_mem_root.end = GPMC_MEM_END;
403
404 /* Reserve all regions that has been set up by bootloader */
405 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
406 u32 base, size;
407
408 if (!gpmc_cs_mem_enabled(cs))
409 continue;
410 gpmc_cs_get_memconf(cs, &base, &size);
411 if (gpmc_cs_insert_mem(cs, base, size) < 0)
412 BUG();
413 }
414 }
415
416 void __init gpmc_init(void)
417 {
418 u32 l;
419 char *ck;
420
421 if (cpu_is_omap24xx()) {
422 ck = "core_l3_ck";
423 if (cpu_is_omap2420())
424 l = OMAP2420_GPMC_BASE;
425 else
426 l = OMAP34XX_GPMC_BASE;
427 } else if (cpu_is_omap34xx()) {
428 ck = "gpmc_fck";
429 l = OMAP34XX_GPMC_BASE;
430 } else if (cpu_is_omap44xx()) {
431 ck = "gpmc_fck";
432 l = OMAP44XX_GPMC_BASE;
433 }
434
435 gpmc_l3_clk = clk_get(NULL, ck);
436 if (IS_ERR(gpmc_l3_clk)) {
437 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
438 BUG();
439 }
440
441 gpmc_base = ioremap(l, SZ_4K);
442 if (!gpmc_base) {
443 clk_put(gpmc_l3_clk);
444 printk(KERN_ERR "Could not get GPMC register memory\n");
445 BUG();
446 }
447
448 l = gpmc_read_reg(GPMC_REVISION);
449 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
450 /* Set smart idle mode and automatic L3 clock gating */
451 l = gpmc_read_reg(GPMC_SYSCONFIG);
452 l &= 0x03 << 3;
453 l |= (0x02 << 3) | (1 << 0);
454 gpmc_write_reg(GPMC_SYSCONFIG, l);
455
456 gpmc_mem_init();
457 }
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