[ARM] pxa: update defconfig for Verdex Pro
[linux-2.6/verdex.git] / arch / arm / mach-omap2 / gpmc.c
blob15876828db23b05abd24c4ab36eac7e6c9040a7d
1 /*
2 * GPMC support functions
4 * Copyright (C) 2005-2006 Nokia Corporation
6 * Author: Juha Yrjola
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 #undef DEBUG
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/ioport.h>
22 #include <linux/spinlock.h>
23 #include <linux/io.h>
24 #include <linux/module.h>
26 #include <asm/mach-types.h>
27 #include <mach/gpmc.h>
29 #include <mach/sdrc.h>
31 /* GPMC register offsets */
32 #define GPMC_REVISION 0x00
33 #define GPMC_SYSCONFIG 0x10
34 #define GPMC_SYSSTATUS 0x14
35 #define GPMC_IRQSTATUS 0x18
36 #define GPMC_IRQENABLE 0x1c
37 #define GPMC_TIMEOUT_CONTROL 0x40
38 #define GPMC_ERR_ADDRESS 0x44
39 #define GPMC_ERR_TYPE 0x48
40 #define GPMC_CONFIG 0x50
41 #define GPMC_STATUS 0x54
42 #define GPMC_PREFETCH_CONFIG1 0x1e0
43 #define GPMC_PREFETCH_CONFIG2 0x1e4
44 #define GPMC_PREFETCH_CONTROL 0x1ec
45 #define GPMC_PREFETCH_STATUS 0x1f0
46 #define GPMC_ECC_CONFIG 0x1f4
47 #define GPMC_ECC_CONTROL 0x1f8
48 #define GPMC_ECC_SIZE_CONFIG 0x1fc
50 #define GPMC_CS0 0x60
51 #define GPMC_CS_SIZE 0x30
53 #define GPMC_MEM_START 0x00000000
54 #define GPMC_MEM_END 0x3FFFFFFF
55 #define BOOT_ROM_SPACE 0x100000 /* 1MB */
57 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
58 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
60 #define PREFETCH_FIFOTHRESHOLD (0x40 << 8)
61 #define CS_NUM_SHIFT 24
62 #define ENABLE_PREFETCH (0x1 << 7)
63 #define DMA_MPU_MODE 2
65 static struct resource gpmc_mem_root;
66 static struct resource gpmc_cs_mem[GPMC_CS_NUM];
67 static DEFINE_SPINLOCK(gpmc_mem_lock);
68 static unsigned gpmc_cs_map;
70 static void __iomem *gpmc_base;
72 static struct clk *gpmc_l3_clk;
74 static void gpmc_write_reg(int idx, u32 val)
76 __raw_writel(val, gpmc_base + idx);
79 static u32 gpmc_read_reg(int idx)
81 return __raw_readl(gpmc_base + idx);
84 void gpmc_cs_write_reg(int cs, int idx, u32 val)
86 void __iomem *reg_addr;
88 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
89 __raw_writel(val, reg_addr);
92 u32 gpmc_cs_read_reg(int cs, int idx)
94 void __iomem *reg_addr;
96 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
97 return __raw_readl(reg_addr);
100 /* TODO: Add support for gpmc_fck to clock framework and use it */
101 unsigned long gpmc_get_fclk_period(void)
103 unsigned long rate = clk_get_rate(gpmc_l3_clk);
105 if (rate == 0) {
106 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
107 return 0;
110 rate /= 1000;
111 rate = 1000000000 / rate; /* In picoseconds */
113 return rate;
116 unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
118 unsigned long tick_ps;
120 /* Calculate in picosecs to yield more exact results */
121 tick_ps = gpmc_get_fclk_period();
123 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
126 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
128 return ticks * gpmc_get_fclk_period() / 1000;
131 unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
133 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
135 return ticks * gpmc_get_fclk_period() / 1000;
138 #ifdef DEBUG
139 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
140 int time, const char *name)
141 #else
142 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
143 int time)
144 #endif
146 u32 l;
147 int ticks, mask, nr_bits;
149 if (time == 0)
150 ticks = 0;
151 else
152 ticks = gpmc_ns_to_ticks(time);
153 nr_bits = end_bit - st_bit + 1;
154 if (ticks >= 1 << nr_bits) {
155 #ifdef DEBUG
156 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
157 cs, name, time, ticks, 1 << nr_bits);
158 #endif
159 return -1;
162 mask = (1 << nr_bits) - 1;
163 l = gpmc_cs_read_reg(cs, reg);
164 #ifdef DEBUG
165 printk(KERN_INFO
166 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
167 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
168 (l >> st_bit) & mask, time);
169 #endif
170 l &= ~(mask << st_bit);
171 l |= ticks << st_bit;
172 gpmc_cs_write_reg(cs, reg, l);
174 return 0;
177 #ifdef DEBUG
178 #define GPMC_SET_ONE(reg, st, end, field) \
179 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
180 t->field, #field) < 0) \
181 return -1
182 #else
183 #define GPMC_SET_ONE(reg, st, end, field) \
184 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
185 return -1
186 #endif
188 int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
190 int div;
191 u32 l;
193 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
194 div = l / gpmc_get_fclk_period();
195 if (div > 4)
196 return -1;
197 if (div <= 0)
198 div = 1;
200 return div;
203 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
205 int div;
206 u32 l;
208 div = gpmc_cs_calc_divider(cs, t->sync_clk);
209 if (div < 0)
210 return -1;
212 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
213 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
214 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
216 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
217 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
218 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
220 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
221 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
222 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
223 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
225 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
226 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
227 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
229 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
231 if (cpu_is_omap34xx()) {
232 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
233 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
236 /* caller is expected to have initialized CONFIG1 to cover
237 * at least sync vs async
239 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
240 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
241 #ifdef DEBUG
242 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
243 cs, (div * gpmc_get_fclk_period()) / 1000, div);
244 #endif
245 l &= ~0x03;
246 l |= (div - 1);
247 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
250 return 0;
253 static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
255 u32 l;
256 u32 mask;
258 mask = (1 << GPMC_SECTION_SHIFT) - size;
259 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
260 l &= ~0x3f;
261 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
262 l &= ~(0x0f << 8);
263 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
264 l |= 1 << 6; /* CSVALID */
265 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
268 static void gpmc_cs_disable_mem(int cs)
270 u32 l;
272 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
273 l &= ~(1 << 6); /* CSVALID */
274 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
277 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
279 u32 l;
280 u32 mask;
282 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
283 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
284 mask = (l >> 8) & 0x0f;
285 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
288 static int gpmc_cs_mem_enabled(int cs)
290 u32 l;
292 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
293 return l & (1 << 6);
296 int gpmc_cs_set_reserved(int cs, int reserved)
298 if (cs > GPMC_CS_NUM)
299 return -ENODEV;
301 gpmc_cs_map &= ~(1 << cs);
302 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
304 return 0;
307 int gpmc_cs_reserved(int cs)
309 if (cs > GPMC_CS_NUM)
310 return -ENODEV;
312 return gpmc_cs_map & (1 << cs);
315 static unsigned long gpmc_mem_align(unsigned long size)
317 int order;
319 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
320 order = GPMC_CHUNK_SHIFT - 1;
321 do {
322 size >>= 1;
323 order++;
324 } while (size);
325 size = 1 << order;
326 return size;
329 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
331 struct resource *res = &gpmc_cs_mem[cs];
332 int r;
334 size = gpmc_mem_align(size);
335 spin_lock(&gpmc_mem_lock);
336 res->start = base;
337 res->end = base + size - 1;
338 r = request_resource(&gpmc_mem_root, res);
339 spin_unlock(&gpmc_mem_lock);
341 return r;
344 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
346 struct resource *res = &gpmc_cs_mem[cs];
347 int r = -1;
349 if (cs > GPMC_CS_NUM)
350 return -ENODEV;
352 size = gpmc_mem_align(size);
353 if (size > (1 << GPMC_SECTION_SHIFT))
354 return -ENOMEM;
356 spin_lock(&gpmc_mem_lock);
357 if (gpmc_cs_reserved(cs)) {
358 r = -EBUSY;
359 goto out;
361 if (gpmc_cs_mem_enabled(cs))
362 r = adjust_resource(res, res->start & ~(size - 1), size);
363 if (r < 0)
364 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
365 size, NULL, NULL);
366 if (r < 0)
367 goto out;
369 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
370 *base = res->start;
371 gpmc_cs_set_reserved(cs, 1);
372 out:
373 spin_unlock(&gpmc_mem_lock);
374 return r;
376 EXPORT_SYMBOL(gpmc_cs_request);
378 void gpmc_cs_free(int cs)
380 spin_lock(&gpmc_mem_lock);
381 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
382 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
383 BUG();
384 spin_unlock(&gpmc_mem_lock);
385 return;
387 gpmc_cs_disable_mem(cs);
388 release_resource(&gpmc_cs_mem[cs]);
389 gpmc_cs_set_reserved(cs, 0);
390 spin_unlock(&gpmc_mem_lock);
392 EXPORT_SYMBOL(gpmc_cs_free);
395 * gpmc_prefetch_enable - configures and starts prefetch transfer
396 * @cs: nand cs (chip select) number
397 * @dma_mode: dma mode enable (1) or disable (0)
398 * @u32_count: number of bytes to be transferred
399 * @is_write: prefetch read(0) or write post(1) mode
401 int gpmc_prefetch_enable(int cs, int dma_mode,
402 unsigned int u32_count, int is_write)
404 uint32_t prefetch_config1;
406 if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
407 /* Set the amount of bytes to be prefetched */
408 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
410 /* Set dma/mpu mode, the prefetch read / post write and
411 * enable the engine. Set which cs is has requested for.
413 prefetch_config1 = ((cs << CS_NUM_SHIFT) |
414 PREFETCH_FIFOTHRESHOLD |
415 ENABLE_PREFETCH |
416 (dma_mode << DMA_MPU_MODE) |
417 (0x1 & is_write));
418 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, prefetch_config1);
419 } else {
420 return -EBUSY;
422 /* Start the prefetch engine */
423 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x1);
425 return 0;
427 EXPORT_SYMBOL(gpmc_prefetch_enable);
430 * gpmc_prefetch_reset - disables and stops the prefetch engine
432 void gpmc_prefetch_reset(void)
434 /* Stop the PFPW engine */
435 gpmc_write_reg(GPMC_PREFETCH_CONTROL, 0x0);
437 /* Reset/disable the PFPW engine */
438 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, 0x0);
440 EXPORT_SYMBOL(gpmc_prefetch_reset);
443 * gpmc_prefetch_status - reads prefetch status of engine
445 int gpmc_prefetch_status(void)
447 return gpmc_read_reg(GPMC_PREFETCH_STATUS);
449 EXPORT_SYMBOL(gpmc_prefetch_status);
451 static void __init gpmc_mem_init(void)
453 int cs;
454 unsigned long boot_rom_space = 0;
456 /* never allocate the first page, to facilitate bug detection;
457 * even if we didn't boot from ROM.
459 boot_rom_space = BOOT_ROM_SPACE;
460 /* In apollon the CS0 is mapped as 0x0000 0000 */
461 if (machine_is_omap_apollon())
462 boot_rom_space = 0;
463 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
464 gpmc_mem_root.end = GPMC_MEM_END;
466 /* Reserve all regions that has been set up by bootloader */
467 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
468 u32 base, size;
470 if (!gpmc_cs_mem_enabled(cs))
471 continue;
472 gpmc_cs_get_memconf(cs, &base, &size);
473 if (gpmc_cs_insert_mem(cs, base, size) < 0)
474 BUG();
478 void __init gpmc_init(void)
480 u32 l;
481 char *ck;
483 if (cpu_is_omap24xx()) {
484 ck = "core_l3_ck";
485 if (cpu_is_omap2420())
486 l = OMAP2420_GPMC_BASE;
487 else
488 l = OMAP34XX_GPMC_BASE;
489 } else if (cpu_is_omap34xx()) {
490 ck = "gpmc_fck";
491 l = OMAP34XX_GPMC_BASE;
492 } else if (cpu_is_omap44xx()) {
493 ck = "gpmc_fck";
494 l = OMAP44XX_GPMC_BASE;
497 gpmc_l3_clk = clk_get(NULL, ck);
498 if (IS_ERR(gpmc_l3_clk)) {
499 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
500 BUG();
503 gpmc_base = ioremap(l, SZ_4K);
504 if (!gpmc_base) {
505 clk_put(gpmc_l3_clk);
506 printk(KERN_ERR "Could not get GPMC register memory\n");
507 BUG();
510 l = gpmc_read_reg(GPMC_REVISION);
511 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
512 /* Set smart idle mode and automatic L3 clock gating */
513 l = gpmc_read_reg(GPMC_SYSCONFIG);
514 l &= 0x03 << 3;
515 l |= (0x02 << 3) | (1 << 0);
516 gpmc_write_reg(GPMC_SYSCONFIG, l);
517 gpmc_mem_init();