arch/arm/plat-omap/gpio.c

   1 /*
   2  *  linux/arch/arm/plat-omap/gpio.c
   3  *
   4  * Support functions for OMAP GPIO
   5  *
   6  * Copyright (C) 2003-2005 Nokia Corporation
   7  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/sysdev.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20
  21 #include <asm/hardware.h>
  22 #include <asm/irq.h>
  23 #include <asm/arch/irqs.h>
  24 #include <asm/arch/gpio.h>
  25 #include <asm/mach/irq.h>
  26
  27 #include <asm/io.h>
  28
  29 /*
  30  * OMAP1510 GPIO registers
  31  */
  32 #define OMAP1510_GPIO_BASE              (void __iomem *)0xfffce000
  33 #define OMAP1510_GPIO_DATA_INPUT        0x00
  34 #define OMAP1510_GPIO_DATA_OUTPUT       0x04
  35 #define OMAP1510_GPIO_DIR_CONTROL       0x08
  36 #define OMAP1510_GPIO_INT_CONTROL       0x0c
  37 #define OMAP1510_GPIO_INT_MASK          0x10
  38 #define OMAP1510_GPIO_INT_STATUS        0x14
  39 #define OMAP1510_GPIO_PIN_CONTROL       0x18
  40
  41 #define OMAP1510_IH_GPIO_BASE           64
  42
  43 /*
  44  * OMAP1610 specific GPIO registers
  45  */
  46 #define OMAP1610_GPIO1_BASE             (void __iomem *)0xfffbe400
  47 #define OMAP1610_GPIO2_BASE             (void __iomem *)0xfffbec00
  48 #define OMAP1610_GPIO3_BASE             (void __iomem *)0xfffbb400
  49 #define OMAP1610_GPIO4_BASE             (void __iomem *)0xfffbbc00
  50 #define OMAP1610_GPIO_REVISION          0x0000
  51 #define OMAP1610_GPIO_SYSCONFIG         0x0010
  52 #define OMAP1610_GPIO_SYSSTATUS         0x0014
  53 #define OMAP1610_GPIO_IRQSTATUS1        0x0018
  54 #define OMAP1610_GPIO_IRQENABLE1        0x001c
  55 #define OMAP1610_GPIO_WAKEUPENABLE      0x0028
  56 #define OMAP1610_GPIO_DATAIN            0x002c
  57 #define OMAP1610_GPIO_DATAOUT           0x0030
  58 #define OMAP1610_GPIO_DIRECTION         0x0034
  59 #define OMAP1610_GPIO_EDGE_CTRL1        0x0038
  60 #define OMAP1610_GPIO_EDGE_CTRL2        0x003c
  61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
  62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
  63 #define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
  64 #define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
  65 #define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
  66 #define OMAP1610_GPIO_SET_DATAOUT       0x00f0
  67
  68 /*
  69  * OMAP730 specific GPIO registers
  70  */
  71 #define OMAP730_GPIO1_BASE              (void __iomem *)0xfffbc000
  72 #define OMAP730_GPIO2_BASE              (void __iomem *)0xfffbc800
  73 #define OMAP730_GPIO3_BASE              (void __iomem *)0xfffbd000
  74 #define OMAP730_GPIO4_BASE              (void __iomem *)0xfffbd800
  75 #define OMAP730_GPIO5_BASE              (void __iomem *)0xfffbe000
  76 #define OMAP730_GPIO6_BASE              (void __iomem *)0xfffbe800
  77 #define OMAP730_GPIO_DATA_INPUT         0x00
  78 #define OMAP730_GPIO_DATA_OUTPUT        0x04
  79 #define OMAP730_GPIO_DIR_CONTROL        0x08
  80 #define OMAP730_GPIO_INT_CONTROL        0x0c
  81 #define OMAP730_GPIO_INT_MASK           0x10
  82 #define OMAP730_GPIO_INT_STATUS         0x14
  83
  84 /*
  85  * omap24xx specific GPIO registers
  86  */
  87 #define OMAP242X_GPIO1_BASE             (void __iomem *)0x48018000
  88 #define OMAP242X_GPIO2_BASE             (void __iomem *)0x4801a000
  89 #define OMAP242X_GPIO3_BASE             (void __iomem *)0x4801c000
  90 #define OMAP242X_GPIO4_BASE             (void __iomem *)0x4801e000
  91
  92 #define OMAP243X_GPIO1_BASE             (void __iomem *)0x4900C000
  93 #define OMAP243X_GPIO2_BASE             (void __iomem *)0x4900E000
  94 #define OMAP243X_GPIO3_BASE             (void __iomem *)0x49010000
  95 #define OMAP243X_GPIO4_BASE             (void __iomem *)0x49012000
  96 #define OMAP243X_GPIO5_BASE             (void __iomem *)0x480B6000
  97
  98 #define OMAP24XX_GPIO_REVISION          0x0000
  99 #define OMAP24XX_GPIO_SYSCONFIG         0x0010
 100 #define OMAP24XX_GPIO_SYSSTATUS         0x0014
 101 #define OMAP24XX_GPIO_IRQSTATUS1        0x0018
 102 #define OMAP24XX_GPIO_IRQSTATUS2        0x0028
 103 #define OMAP24XX_GPIO_IRQENABLE2        0x002c
 104 #define OMAP24XX_GPIO_IRQENABLE1        0x001c
 105 #define OMAP24XX_GPIO_CTRL              0x0030
 106 #define OMAP24XX_GPIO_OE                0x0034
 107 #define OMAP24XX_GPIO_DATAIN            0x0038
 108 #define OMAP24XX_GPIO_DATAOUT           0x003c
 109 #define OMAP24XX_GPIO_LEVELDETECT0      0x0040
 110 #define OMAP24XX_GPIO_LEVELDETECT1      0x0044
 111 #define OMAP24XX_GPIO_RISINGDETECT      0x0048
 112 #define OMAP24XX_GPIO_FALLINGDETECT     0x004c
 113 #define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
 114 #define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
 115 #define OMAP24XX_GPIO_CLEARWKUENA       0x0080
 116 #define OMAP24XX_GPIO_SETWKUENA         0x0084
 117 #define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
 118 #define OMAP24XX_GPIO_SETDATAOUT        0x0094
 119
 120 /*
 121  * omap34xx specific GPIO registers
 122  */
 123
 124 #define OMAP34XX_GPIO1_BASE             (void __iomem *)0x48310000
 125 #define OMAP34XX_GPIO2_BASE             (void __iomem *)0x49050000
 126 #define OMAP34XX_GPIO3_BASE             (void __iomem *)0x49052000
 127 #define OMAP34XX_GPIO4_BASE             (void __iomem *)0x49054000
 128 #define OMAP34XX_GPIO5_BASE             (void __iomem *)0x49056000
 129 #define OMAP34XX_GPIO6_BASE             (void __iomem *)0x49058000
 130
 131
 132 struct gpio_bank {
 133         void __iomem *base;
 134         u16 irq;
 135         u16 virtual_irq_start;
 136         int method;
 137         u32 reserved_map;
 138 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 139         u32 suspend_wakeup;
 140         u32 saved_wakeup;
 141 #endif
 142 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 143         u32 non_wakeup_gpios;
 144         u32 enabled_non_wakeup_gpios;
 145
 146         u32 saved_datain;
 147         u32 saved_fallingdetect;
 148         u32 saved_risingdetect;
 149 #endif
 150         spinlock_t lock;
 151 };
 152
 153 #define METHOD_MPUIO            0
 154 #define METHOD_GPIO_1510        1
 155 #define METHOD_GPIO_1610        2
 156 #define METHOD_GPIO_730         3
 157 #define METHOD_GPIO_24XX        4
 158
 159 #ifdef CONFIG_ARCH_OMAP16XX
 160 static struct gpio_bank gpio_bank_1610[5] = {
 161         { OMAP_MPUIO_BASE,     INT_MPUIO,           IH_MPUIO_BASE,     METHOD_MPUIO},
 162         { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
 163         { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
 164         { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
 165         { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
 166 };
 167 #endif
 168
 169 #ifdef CONFIG_ARCH_OMAP15XX
 170 static struct gpio_bank gpio_bank_1510[2] = {
 171         { OMAP_MPUIO_BASE,    INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
 172         { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
 173 };
 174 #endif
 175
 176 #ifdef CONFIG_ARCH_OMAP730
 177 static struct gpio_bank gpio_bank_730[7] = {
 178         { OMAP_MPUIO_BASE,     INT_730_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
 179         { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_730 },
 180         { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
 181         { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
 182         { OMAP730_GPIO4_BASE,  INT_730_GPIO_BANK4,  IH_GPIO_BASE + 96,  METHOD_GPIO_730 },
 183         { OMAP730_GPIO5_BASE,  INT_730_GPIO_BANK5,  IH_GPIO_BASE + 128, METHOD_GPIO_730 },
 184         { OMAP730_GPIO6_BASE,  INT_730_GPIO_BANK6,  IH_GPIO_BASE + 160, METHOD_GPIO_730 },
 185 };
 186 #endif
 187
 188 #ifdef CONFIG_ARCH_OMAP24XX
 189
 190 static struct gpio_bank gpio_bank_242x[4] = {
 191         { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
 192         { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
 193         { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
 194         { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
 195 };
 196
 197 static struct gpio_bank gpio_bank_243x[5] = {
 198         { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
 199         { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
 200         { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
 201         { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
 202         { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
 203 };
 204
 205 #endif
 206
 207 #ifdef CONFIG_ARCH_OMAP34XX
 208 static struct gpio_bank gpio_bank_34xx[6] = {
 209         { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,       METHOD_GPIO_24XX },
 210         { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,  METHOD_GPIO_24XX },
 211         { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,  METHOD_GPIO_24XX },
 212         { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,  METHOD_GPIO_24XX },
 213         { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
 214         { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
 215 };
 216
 217 #endif
 218
 219 static struct gpio_bank *gpio_bank;
 220 static int gpio_bank_count;
 221
 222 static inline struct gpio_bank *get_gpio_bank(int gpio)
 223 {
 224         if (cpu_is_omap15xx()) {
 225                 if (OMAP_GPIO_IS_MPUIO(gpio))
 226                         return &gpio_bank[0];
 227                 return &gpio_bank[1];
 228         }
 229         if (cpu_is_omap16xx()) {
 230                 if (OMAP_GPIO_IS_MPUIO(gpio))
 231                         return &gpio_bank[0];
 232                 return &gpio_bank[1 + (gpio >> 4)];
 233         }
 234         if (cpu_is_omap730()) {
 235                 if (OMAP_GPIO_IS_MPUIO(gpio))
 236                         return &gpio_bank[0];
 237                 return &gpio_bank[1 + (gpio >> 5)];
 238         }
 239         if (cpu_is_omap24xx())
 240                 return &gpio_bank[gpio >> 5];
 241         if (cpu_is_omap34xx())
 242                 return &gpio_bank[gpio >> 5];
 243 }
 244
 245 static inline int get_gpio_index(int gpio)
 246 {
 247         if (cpu_is_omap730())
 248                 return gpio & 0x1f;
 249         if (cpu_is_omap24xx())
 250                 return gpio & 0x1f;
 251         if (cpu_is_omap34xx())
 252                 return gpio & 0x1f;
 253         return gpio & 0x0f;
 254 }
 255
 256 static inline int gpio_valid(int gpio)
 257 {
 258         if (gpio < 0)
 259                 return -1;
 260         if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
 261                 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
 262                         return -1;
 263                 return 0;
 264         }
 265         if (cpu_is_omap15xx() && gpio < 16)
 266                 return 0;
 267         if ((cpu_is_omap16xx()) && gpio < 64)
 268                 return 0;
 269         if (cpu_is_omap730() && gpio < 192)
 270                 return 0;
 271         if (cpu_is_omap24xx() && gpio < 128)
 272                 return 0;
 273         if (cpu_is_omap34xx() && gpio < 160)
 274                 return 0;
 275         return -1;
 276 }
 277
 278 static int check_gpio(int gpio)
 279 {
 280         if (unlikely(gpio_valid(gpio)) < 0) {
 281                 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
 282                 dump_stack();
 283                 return -1;
 284         }
 285         return 0;
 286 }
 287
 288 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 289 {
 290         void __iomem *reg = bank->base;
 291         u32 l;
 292
 293         switch (bank->method) {
 294 #ifdef CONFIG_ARCH_OMAP1
 295         case METHOD_MPUIO:
 296                 reg += OMAP_MPUIO_IO_CNTL;
 297                 break;
 298 #endif
 299 #ifdef CONFIG_ARCH_OMAP15XX
 300         case METHOD_GPIO_1510:
 301                 reg += OMAP1510_GPIO_DIR_CONTROL;
 302                 break;
 303 #endif
 304 #ifdef CONFIG_ARCH_OMAP16XX
 305         case METHOD_GPIO_1610:
 306                 reg += OMAP1610_GPIO_DIRECTION;
 307                 break;
 308 #endif
 309 #ifdef CONFIG_ARCH_OMAP730
 310         case METHOD_GPIO_730:
 311                 reg += OMAP730_GPIO_DIR_CONTROL;
 312                 break;
 313 #endif
 314 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 315         case METHOD_GPIO_24XX:
 316                 reg += OMAP24XX_GPIO_OE;
 317                 break;
 318 #endif
 319         default:
 320                 WARN_ON(1);
 321                 return;
 322         }
 323         l = __raw_readl(reg);
 324         if (is_input)
 325                 l |= 1 << gpio;
 326         else
 327                 l &= ~(1 << gpio);
 328         __raw_writel(l, reg);
 329 }
 330
 331 void omap_set_gpio_direction(int gpio, int is_input)
 332 {
 333         struct gpio_bank *bank;
 334
 335         if (check_gpio(gpio) < 0)
 336                 return;
 337         bank = get_gpio_bank(gpio);
 338         spin_lock(&bank->lock);
 339         _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
 340         spin_unlock(&bank->lock);
 341 }
 342
 343 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 344 {
 345         void __iomem *reg = bank->base;
 346         u32 l = 0;
 347
 348         switch (bank->method) {
 349 #ifdef CONFIG_ARCH_OMAP1
 350         case METHOD_MPUIO:
 351                 reg += OMAP_MPUIO_OUTPUT;
 352                 l = __raw_readl(reg);
 353                 if (enable)
 354                         l |= 1 << gpio;
 355                 else
 356                         l &= ~(1 << gpio);
 357                 break;
 358 #endif
 359 #ifdef CONFIG_ARCH_OMAP15XX
 360         case METHOD_GPIO_1510:
 361                 reg += OMAP1510_GPIO_DATA_OUTPUT;
 362                 l = __raw_readl(reg);
 363                 if (enable)
 364                         l |= 1 << gpio;
 365                 else
 366                         l &= ~(1 << gpio);
 367                 break;
 368 #endif
 369 #ifdef CONFIG_ARCH_OMAP16XX
 370         case METHOD_GPIO_1610:
 371                 if (enable)
 372                         reg += OMAP1610_GPIO_SET_DATAOUT;
 373                 else
 374                         reg += OMAP1610_GPIO_CLEAR_DATAOUT;
 375                 l = 1 << gpio;
 376                 break;
 377 #endif
 378 #ifdef CONFIG_ARCH_OMAP730
 379         case METHOD_GPIO_730:
 380                 reg += OMAP730_GPIO_DATA_OUTPUT;
 381                 l = __raw_readl(reg);
 382                 if (enable)
 383                         l |= 1 << gpio;
 384                 else
 385                         l &= ~(1 << gpio);
 386                 break;
 387 #endif
 388 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 389         case METHOD_GPIO_24XX:
 390                 if (enable)
 391                         reg += OMAP24XX_GPIO_SETDATAOUT;
 392                 else
 393                         reg += OMAP24XX_GPIO_CLEARDATAOUT;
 394                 l = 1 << gpio;
 395                 break;
 396 #endif
 397         default:
 398                 WARN_ON(1);
 399                 return;
 400         }
 401         __raw_writel(l, reg);
 402 }
 403
 404 void omap_set_gpio_dataout(int gpio, int enable)
 405 {
 406         struct gpio_bank *bank;
 407
 408         if (check_gpio(gpio) < 0)
 409                 return;
 410         bank = get_gpio_bank(gpio);
 411         spin_lock(&bank->lock);
 412         _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
 413         spin_unlock(&bank->lock);
 414 }
 415
 416 int omap_get_gpio_datain(int gpio)
 417 {
 418         struct gpio_bank *bank;
 419         void __iomem *reg;
 420
 421         if (check_gpio(gpio) < 0)
 422                 return -EINVAL;
 423         bank = get_gpio_bank(gpio);
 424         reg = bank->base;
 425         switch (bank->method) {
 426 #ifdef CONFIG_ARCH_OMAP1
 427         case METHOD_MPUIO:
 428                 reg += OMAP_MPUIO_INPUT_LATCH;
 429                 break;
 430 #endif
 431 #ifdef CONFIG_ARCH_OMAP15XX
 432         case METHOD_GPIO_1510:
 433                 reg += OMAP1510_GPIO_DATA_INPUT;
 434                 break;
 435 #endif
 436 #ifdef CONFIG_ARCH_OMAP16XX
 437         case METHOD_GPIO_1610:
 438                 reg += OMAP1610_GPIO_DATAIN;
 439                 break;
 440 #endif
 441 #ifdef CONFIG_ARCH_OMAP730
 442         case METHOD_GPIO_730:
 443                 reg += OMAP730_GPIO_DATA_INPUT;
 444                 break;
 445 #endif
 446 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 447         case METHOD_GPIO_24XX:
 448                 reg += OMAP24XX_GPIO_DATAIN;
 449                 break;
 450 #endif
 451         default:
 452                 return -EINVAL;
 453         }
 454         return (__raw_readl(reg)
 455                         & (1 << get_gpio_index(gpio))) != 0;
 456 }
 457
 458 #define MOD_REG_BIT(reg, bit_mask, set) \
 459 do {    \
 460         int l = __raw_readl(base + reg); \
 461         if (set) l |= bit_mask; \
 462         else l &= ~bit_mask; \
 463         __raw_writel(l, base + reg); \
 464 } while(0)
 465
 466 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 467 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 468 {
 469         void __iomem *base = bank->base;
 470         u32 gpio_bit = 1 << gpio;
 471
 472         MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
 473                 trigger & __IRQT_LOWLVL);
 474         MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
 475                 trigger & __IRQT_HIGHLVL);
 476         MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
 477                 trigger & __IRQT_RISEDGE);
 478         MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
 479                 trigger & __IRQT_FALEDGE);
 480         if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 481                 if (trigger != 0)
 482                         __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_SETWKUENA);
 483                 else
 484                         __raw_writel(1 << gpio, bank->base + OMAP24XX_GPIO_CLEARWKUENA);
 485         } else {
 486                 if (trigger != 0)
 487                         bank->enabled_non_wakeup_gpios |= gpio_bit;
 488                 else
 489                         bank->enabled_non_wakeup_gpios &= ~gpio_bit;
 490         }
 491         /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
 492          * triggering requested. */
 493 }
 494 #endif
 495
 496 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
 497 {
 498         void __iomem *reg = bank->base;
 499         u32 l = 0;
 500
 501         switch (bank->method) {
 502 #ifdef CONFIG_ARCH_OMAP1
 503         case METHOD_MPUIO:
 504                 reg += OMAP_MPUIO_GPIO_INT_EDGE;
 505                 l = __raw_readl(reg);
 506                 if (trigger & __IRQT_RISEDGE)
 507                         l |= 1 << gpio;
 508                 else if (trigger & __IRQT_FALEDGE)
 509                         l &= ~(1 << gpio);
 510                 else
 511                         goto bad;
 512                 break;
 513 #endif
 514 #ifdef CONFIG_ARCH_OMAP15XX
 515         case METHOD_GPIO_1510:
 516                 reg += OMAP1510_GPIO_INT_CONTROL;
 517                 l = __raw_readl(reg);
 518                 if (trigger & __IRQT_RISEDGE)
 519                         l |= 1 << gpio;
 520                 else if (trigger & __IRQT_FALEDGE)
 521                         l &= ~(1 << gpio);
 522                 else
 523                         goto bad;
 524                 break;
 525 #endif
 526 #ifdef CONFIG_ARCH_OMAP16XX
 527         case METHOD_GPIO_1610:
 528                 if (gpio & 0x08)
 529                         reg += OMAP1610_GPIO_EDGE_CTRL2;
 530                 else
 531                         reg += OMAP1610_GPIO_EDGE_CTRL1;
 532                 gpio &= 0x07;
 533                 l = __raw_readl(reg);
 534                 l &= ~(3 << (gpio << 1));
 535                 if (trigger & __IRQT_RISEDGE)
 536                         l |= 2 << (gpio << 1);
 537                 if (trigger & __IRQT_FALEDGE)
 538                         l |= 1 << (gpio << 1);
 539                 if (trigger)
 540                         /* Enable wake-up during idle for dynamic tick */
 541                         __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
 542                 else
 543                         __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
 544                 break;
 545 #endif
 546 #ifdef CONFIG_ARCH_OMAP730
 547         case METHOD_GPIO_730:
 548                 reg += OMAP730_GPIO_INT_CONTROL;
 549                 l = __raw_readl(reg);
 550                 if (trigger & __IRQT_RISEDGE)
 551                         l |= 1 << gpio;
 552                 else if (trigger & __IRQT_FALEDGE)
 553                         l &= ~(1 << gpio);
 554                 else
 555                         goto bad;
 556                 break;
 557 #endif
 558 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 559         case METHOD_GPIO_24XX:
 560                 set_24xx_gpio_triggering(bank, gpio, trigger);
 561                 break;
 562 #endif
 563         default:
 564                 goto bad;
 565         }
 566         __raw_writel(l, reg);
 567         return 0;
 568 bad:
 569         return -EINVAL;
 570 }
 571
 572 static int gpio_irq_type(unsigned irq, unsigned type)
 573 {
 574         struct gpio_bank *bank;
 575         unsigned gpio;
 576         int retval;
 577
 578         if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
 579                 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
 580         else
 581                 gpio = irq - IH_GPIO_BASE;
 582
 583         if (check_gpio(gpio) < 0)
 584                 return -EINVAL;
 585
 586         if (type & ~IRQ_TYPE_SENSE_MASK)
 587                 return -EINVAL;
 588
 589         /* OMAP1 allows only only edge triggering */
 590         if (!cpu_class_is_omap2()
 591                         && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
 592                 return -EINVAL;
 593
 594         bank = get_irq_chip_data(irq);
 595         spin_lock(&bank->lock);
 596         retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
 597         if (retval == 0) {
 598                 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
 599                 irq_desc[irq].status |= type;
 600         }
 601         spin_unlock(&bank->lock);
 602         return retval;
 603 }
 604
 605 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
 606 {
 607         void __iomem *reg = bank->base;
 608
 609         switch (bank->method) {
 610 #ifdef CONFIG_ARCH_OMAP1
 611         case METHOD_MPUIO:
 612                 /* MPUIO irqstatus is reset by reading the status register,
 613                  * so do nothing here */
 614                 return;
 615 #endif
 616 #ifdef CONFIG_ARCH_OMAP15XX
 617         case METHOD_GPIO_1510:
 618                 reg += OMAP1510_GPIO_INT_STATUS;
 619                 break;
 620 #endif
 621 #ifdef CONFIG_ARCH_OMAP16XX
 622         case METHOD_GPIO_1610:
 623                 reg += OMAP1610_GPIO_IRQSTATUS1;
 624                 break;
 625 #endif
 626 #ifdef CONFIG_ARCH_OMAP730
 627         case METHOD_GPIO_730:
 628                 reg += OMAP730_GPIO_INT_STATUS;
 629                 break;
 630 #endif
 631 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 632         case METHOD_GPIO_24XX:
 633                 reg += OMAP24XX_GPIO_IRQSTATUS1;
 634                 break;
 635 #endif
 636         default:
 637                 WARN_ON(1);
 638                 return;
 639         }
 640         __raw_writel(gpio_mask, reg);
 641
 642         /* Workaround for clearing DSP GPIO interrupts to allow retention */
 643 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 644         if (cpu_is_omap24xx() || cpu_is_omap34xx())
 645                 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
 646 #endif
 647 }
 648
 649 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
 650 {
 651         _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
 652 }
 653
 654 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
 655 {
 656         void __iomem *reg = bank->base;
 657         int inv = 0;
 658         u32 l;
 659         u32 mask;
 660
 661         switch (bank->method) {
 662 #ifdef CONFIG_ARCH_OMAP1
 663         case METHOD_MPUIO:
 664                 reg += OMAP_MPUIO_GPIO_MASKIT;
 665                 mask = 0xffff;
 666                 inv = 1;
 667                 break;
 668 #endif
 669 #ifdef CONFIG_ARCH_OMAP15XX
 670         case METHOD_GPIO_1510:
 671                 reg += OMAP1510_GPIO_INT_MASK;
 672                 mask = 0xffff;
 673                 inv = 1;
 674                 break;
 675 #endif
 676 #ifdef CONFIG_ARCH_OMAP16XX
 677         case METHOD_GPIO_1610:
 678                 reg += OMAP1610_GPIO_IRQENABLE1;
 679                 mask = 0xffff;
 680                 break;
 681 #endif
 682 #ifdef CONFIG_ARCH_OMAP730
 683         case METHOD_GPIO_730:
 684                 reg += OMAP730_GPIO_INT_MASK;
 685                 mask = 0xffffffff;
 686                 inv = 1;
 687                 break;
 688 #endif
 689 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 690         case METHOD_GPIO_24XX:
 691                 reg += OMAP24XX_GPIO_IRQENABLE1;
 692                 mask = 0xffffffff;
 693                 break;
 694 #endif
 695         default:
 696                 WARN_ON(1);
 697                 return 0;
 698         }
 699
 700         l = __raw_readl(reg);
 701         if (inv)
 702                 l = ~l;
 703         l &= mask;
 704         return l;
 705 }
 706
 707 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
 708 {
 709         void __iomem *reg = bank->base;
 710         u32 l;
 711
 712         switch (bank->method) {
 713 #ifdef CONFIG_ARCH_OMAP1
 714         case METHOD_MPUIO:
 715                 reg += OMAP_MPUIO_GPIO_MASKIT;
 716                 l = __raw_readl(reg);
 717                 if (enable)
 718                         l &= ~(gpio_mask);
 719                 else
 720                         l |= gpio_mask;
 721                 break;
 722 #endif
 723 #ifdef CONFIG_ARCH_OMAP15XX
 724         case METHOD_GPIO_1510:
 725                 reg += OMAP1510_GPIO_INT_MASK;
 726                 l = __raw_readl(reg);
 727                 if (enable)
 728                         l &= ~(gpio_mask);
 729                 else
 730                         l |= gpio_mask;
 731                 break;
 732 #endif
 733 #ifdef CONFIG_ARCH_OMAP16XX
 734         case METHOD_GPIO_1610:
 735                 if (enable)
 736                         reg += OMAP1610_GPIO_SET_IRQENABLE1;
 737                 else
 738                         reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
 739                 l = gpio_mask;
 740                 break;
 741 #endif
 742 #ifdef CONFIG_ARCH_OMAP730
 743         case METHOD_GPIO_730:
 744                 reg += OMAP730_GPIO_INT_MASK;
 745                 l = __raw_readl(reg);
 746                 if (enable)
 747                         l &= ~(gpio_mask);
 748                 else
 749                         l |= gpio_mask;
 750                 break;
 751 #endif
 752 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 753         case METHOD_GPIO_24XX:
 754                 if (enable)
 755                         reg += OMAP24XX_GPIO_SETIRQENABLE1;
 756                 else
 757                         reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
 758                 l = gpio_mask;
 759                 break;
 760 #endif
 761         default:
 762                 WARN_ON(1);
 763                 return;
 764         }
 765         __raw_writel(l, reg);
 766 }
 767
 768 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
 769 {
 770         _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
 771 }
 772
 773 /*
 774  * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
 775  * 1510 does not seem to have a wake-up register. If JTAG is connected
 776  * to the target, system will wake up always on GPIO events. While
 777  * system is running all registered GPIO interrupts need to have wake-up
 778  * enabled. When system is suspended, only selected GPIO interrupts need
 779  * to have wake-up enabled.
 780  */
 781 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
 782 {
 783         switch (bank->method) {
 784 #ifdef CONFIG_ARCH_OMAP16XX
 785         case METHOD_MPUIO:
 786         case METHOD_GPIO_1610:
 787                 spin_lock(&bank->lock);
 788                 if (enable) {
 789                         bank->suspend_wakeup |= (1 << gpio);
 790                         enable_irq_wake(bank->irq);
 791                 } else {
 792                         disable_irq_wake(bank->irq);
 793                         bank->suspend_wakeup &= ~(1 << gpio);
 794                 }
 795                 spin_unlock(&bank->lock);
 796                 return 0;
 797 #endif
 798 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 799         case METHOD_GPIO_24XX:
 800                 if (bank->non_wakeup_gpios & (1 << gpio)) {
 801                         printk(KERN_ERR "Unable to modify wakeup on "
 802                                         "non-wakeup GPIO%d\n",
 803                                         (bank - gpio_bank) * 32 + gpio);
 804                         return -EINVAL;
 805                 }
 806                 spin_lock(&bank->lock);
 807                 if (enable) {
 808                         bank->suspend_wakeup |= (1 << gpio);
 809                         enable_irq_wake(bank->irq);
 810                 } else {
 811                         disable_irq_wake(bank->irq);
 812                         bank->suspend_wakeup &= ~(1 << gpio);
 813                 }
 814                 spin_unlock(&bank->lock);
 815                 return 0;
 816 #endif
 817         default:
 818                 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
 819                        bank->method);
 820                 return -EINVAL;
 821         }
 822 }
 823
 824 static void _reset_gpio(struct gpio_bank *bank, int gpio)
 825 {
 826         _set_gpio_direction(bank, get_gpio_index(gpio), 1);
 827         _set_gpio_irqenable(bank, gpio, 0);
 828         _clear_gpio_irqstatus(bank, gpio);
 829         _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
 830 }
 831
 832 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
 833 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
 834 {
 835         unsigned int gpio = irq - IH_GPIO_BASE;
 836         struct gpio_bank *bank;
 837         int retval;
 838
 839         if (check_gpio(gpio) < 0)
 840                 return -ENODEV;
 841         bank = get_irq_chip_data(irq);
 842         retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
 843
 844         return retval;
 845 }
 846
 847 int omap_request_gpio(int gpio)
 848 {
 849         struct gpio_bank *bank;
 850
 851         if (check_gpio(gpio) < 0)
 852                 return -EINVAL;
 853
 854         bank = get_gpio_bank(gpio);
 855         spin_lock(&bank->lock);
 856         if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
 857                 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
 858                 dump_stack();
 859                 spin_unlock(&bank->lock);
 860                 return -1;
 861         }
 862         bank->reserved_map |= (1 << get_gpio_index(gpio));
 863
 864         /* Set trigger to none. You need to enable the desired trigger with
 865          * request_irq() or set_irq_type().
 866          */
 867         _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
 868
 869 #ifdef CONFIG_ARCH_OMAP15XX
 870         if (bank->method == METHOD_GPIO_1510) {
 871                 void __iomem *reg;
 872
 873                 /* Claim the pin for MPU */
 874                 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
 875                 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
 876         }
 877 #endif
 878         spin_unlock(&bank->lock);
 879
 880         return 0;
 881 }
 882
 883 void omap_free_gpio(int gpio)
 884 {
 885         struct gpio_bank *bank;
 886
 887         if (check_gpio(gpio) < 0)
 888                 return;
 889         bank = get_gpio_bank(gpio);
 890         spin_lock(&bank->lock);
 891         if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
 892                 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
 893                 dump_stack();
 894                 spin_unlock(&bank->lock);
 895                 return;
 896         }
 897 #ifdef CONFIG_ARCH_OMAP16XX
 898         if (bank->method == METHOD_GPIO_1610) {
 899                 /* Disable wake-up during idle for dynamic tick */
 900                 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
 901                 __raw_writel(1 << get_gpio_index(gpio), reg);
 902         }
 903 #endif
 904 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 905         if (bank->method == METHOD_GPIO_24XX) {
 906                 /* Disable wake-up during idle for dynamic tick */
 907                 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
 908                 __raw_writel(1 << get_gpio_index(gpio), reg);
 909         }
 910 #endif
 911         bank->reserved_map &= ~(1 << get_gpio_index(gpio));
 912         _reset_gpio(bank, gpio);
 913         spin_unlock(&bank->lock);
 914 }
 915
 916 /*
 917  * We need to unmask the GPIO bank interrupt as soon as possible to
 918  * avoid missing GPIO interrupts for other lines in the bank.
 919  * Then we need to mask-read-clear-unmask the triggered GPIO lines
 920  * in the bank to avoid missing nested interrupts for a GPIO line.
 921  * If we wait to unmask individual GPIO lines in the bank after the
 922  * line's interrupt handler has been run, we may miss some nested
 923  * interrupts.
 924  */
 925 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 926 {
 927         void __iomem *isr_reg = NULL;
 928         u32 isr;
 929         unsigned int gpio_irq;
 930         struct gpio_bank *bank;
 931         u32 retrigger = 0;
 932         int unmasked = 0;
 933
 934         desc->chip->ack(irq);
 935
 936         bank = get_irq_data(irq);
 937 #ifdef CONFIG_ARCH_OMAP1
 938         if (bank->method == METHOD_MPUIO)
 939                 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
 940 #endif
 941 #ifdef CONFIG_ARCH_OMAP15XX
 942         if (bank->method == METHOD_GPIO_1510)
 943                 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
 944 #endif
 945 #if defined(CONFIG_ARCH_OMAP16XX)
 946         if (bank->method == METHOD_GPIO_1610)
 947                 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
 948 #endif
 949 #ifdef CONFIG_ARCH_OMAP730
 950         if (bank->method == METHOD_GPIO_730)
 951                 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
 952 #endif
 953 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
 954         if (bank->method == METHOD_GPIO_24XX)
 955                 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
 956 #endif
 957         while(1) {
 958                 u32 isr_saved, level_mask = 0;
 959                 u32 enabled;
 960
 961                 enabled = _get_gpio_irqbank_mask(bank);
 962                 isr_saved = isr = __raw_readl(isr_reg) & enabled;
 963
 964                 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
 965                         isr &= 0x0000ffff;
 966
 967                 if (cpu_class_is_omap2()) {
 968                         level_mask =
 969                                 __raw_readl(bank->base +
 970                                         OMAP24XX_GPIO_LEVELDETECT0) |
 971                                 __raw_readl(bank->base +
 972                                         OMAP24XX_GPIO_LEVELDETECT1);
 973                         level_mask &= enabled;
 974                 }
 975
 976                 /* clear edge sensitive interrupts before handler(s) are
 977                 called so that we don't miss any interrupt occurred while
 978                 executing them */
 979                 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
 980                 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
 981                 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
 982
 983                 /* if there is only edge sensitive GPIO pin interrupts
 984                 configured, we could unmask GPIO bank interrupt immediately */
 985                 if (!level_mask && !unmasked) {
 986                         unmasked = 1;
 987                         desc->chip->unmask(irq);
 988                 }
 989
 990                 isr |= retrigger;
 991                 retrigger = 0;
 992                 if (!isr)
 993                         break;
 994
 995                 gpio_irq = bank->virtual_irq_start;
 996                 for (; isr != 0; isr >>= 1, gpio_irq++) {
 997                         struct irq_desc *d;
 998                         int irq_mask;
 999                         if (!(isr & 1))
1000                                 continue;
1001                         d = irq_desc + gpio_irq;
1002                         /* Don't run the handler if it's already running
1003                          * or was disabled lazely.
1004                          */
1005                         if (unlikely((d->depth ||
1006                                       (d->status & IRQ_INPROGRESS)))) {
1007                                 irq_mask = 1 <<
1008                                         (gpio_irq - bank->virtual_irq_start);
1009                                 /* The unmasking will be done by
1010                                  * enable_irq in case it is disabled or
1011                                  * after returning from the handler if
1012                                  * it's already running.
1013                                  */
1014                                 _enable_gpio_irqbank(bank, irq_mask, 0);
1015                                 if (!d->depth) {
1016                                         /* Level triggered interrupts
1017                                          * won't ever be reentered
1018                                          */
1019                                         BUG_ON(level_mask & irq_mask);
1020                                         d->status |= IRQ_PENDING;
1021                                 }
1022                                 continue;
1023                         }
1024
1025                         desc_handle_irq(gpio_irq, d);
1026
1027                         if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1028                                 irq_mask = 1 <<
1029                                         (gpio_irq - bank->virtual_irq_start);
1030                                 d->status &= ~IRQ_PENDING;
1031                                 _enable_gpio_irqbank(bank, irq_mask, 1);
1032                                 retrigger |= irq_mask;
1033                         }
1034                 }
1035
1036                 if (cpu_class_is_omap2()) {
1037                         /* clear level sensitive interrupts after handler(s) */
1038                         _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1039                         _clear_gpio_irqbank(bank, isr_saved & level_mask);
1040                         _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1041                 }
1042
1043         }
1044         /* if bank has any level sensitive GPIO pin interrupt
1045         configured, we must unmask the bank interrupt only after
1046         handler(s) are executed in order to avoid spurious bank
1047         interrupt */
1048         if (!unmasked)
1049                 desc->chip->unmask(irq);
1050
1051 }
1052
1053 static void gpio_irq_shutdown(unsigned int irq)
1054 {
1055         unsigned int gpio = irq - IH_GPIO_BASE;
1056         struct gpio_bank *bank = get_irq_chip_data(irq);
1057
1058         _reset_gpio(bank, gpio);
1059 }
1060
1061 static void gpio_ack_irq(unsigned int irq)
1062 {
1063         unsigned int gpio = irq - IH_GPIO_BASE;
1064         struct gpio_bank *bank = get_irq_chip_data(irq);
1065
1066         _clear_gpio_irqstatus(bank, gpio);
1067 }
1068
1069 static void gpio_mask_irq(unsigned int irq)
1070 {
1071         unsigned int gpio = irq - IH_GPIO_BASE;
1072         struct gpio_bank *bank = get_irq_chip_data(irq);
1073
1074         _set_gpio_irqenable(bank, gpio, 0);
1075 }
1076
1077 static void gpio_unmask_irq(unsigned int irq)
1078 {
1079         unsigned int gpio = irq - IH_GPIO_BASE;
1080         unsigned int gpio_idx = get_gpio_index(gpio);
1081         struct gpio_bank *bank = get_irq_chip_data(irq);
1082
1083         _set_gpio_irqenable(bank, gpio_idx, 1);
1084 }
1085
1086 static struct irq_chip gpio_irq_chip = {
1087         .name           = "GPIO",
1088         .shutdown       = gpio_irq_shutdown,
1089         .ack            = gpio_ack_irq,
1090         .mask           = gpio_mask_irq,
1091         .unmask         = gpio_unmask_irq,
1092         .set_type       = gpio_irq_type,
1093         .set_wake       = gpio_wake_enable,
1094 };
1095
1096 /*---------------------------------------------------------------------*/
1097
1098 #ifdef CONFIG_ARCH_OMAP1
1099
1100 /* MPUIO uses the always-on 32k clock */
1101
1102 static void mpuio_ack_irq(unsigned int irq)
1103 {
1104         /* The ISR is reset automatically, so do nothing here. */
1105 }
1106
1107 static void mpuio_mask_irq(unsigned int irq)
1108 {
1109         unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1110         struct gpio_bank *bank = get_irq_chip_data(irq);
1111
1112         _set_gpio_irqenable(bank, gpio, 0);
1113 }
1114
1115 static void mpuio_unmask_irq(unsigned int irq)
1116 {
1117         unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1118         struct gpio_bank *bank = get_irq_chip_data(irq);
1119
1120         _set_gpio_irqenable(bank, gpio, 1);
1121 }
1122
1123 static struct irq_chip mpuio_irq_chip = {
1124         .name           = "MPUIO",
1125         .ack            = mpuio_ack_irq,
1126         .mask           = mpuio_mask_irq,
1127         .unmask         = mpuio_unmask_irq,
1128         .set_type       = gpio_irq_type,
1129 #ifdef CONFIG_ARCH_OMAP16XX
1130         /* REVISIT: assuming only 16xx supports MPUIO wake events */
1131         .set_wake       = gpio_wake_enable,
1132 #endif
1133 };
1134
1135
1136 #define bank_is_mpuio(bank)     ((bank)->method == METHOD_MPUIO)
1137
1138
1139 #ifdef CONFIG_ARCH_OMAP16XX
1140
1141 #include <linux/platform_device.h>
1142
1143 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1144 {
1145         struct gpio_bank        *bank = platform_get_drvdata(pdev);
1146         void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1147
1148         spin_lock(&bank->lock);
1149         bank->saved_wakeup = __raw_readl(mask_reg);
1150         __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1151         spin_unlock(&bank->lock);
1152
1153         return 0;
1154 }
1155
1156 static int omap_mpuio_resume_early(struct platform_device *pdev)
1157 {
1158         struct gpio_bank        *bank = platform_get_drvdata(pdev);
1159         void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1160
1161         spin_lock(&bank->lock);
1162         __raw_writel(bank->saved_wakeup, mask_reg);
1163         spin_unlock(&bank->lock);
1164
1165         return 0;
1166 }
1167
1168 /* use platform_driver for this, now that there's no longer any
1169  * point to sys_device (other than not disturbing old code).
1170  */
1171 static struct platform_driver omap_mpuio_driver = {
1172         .suspend_late   = omap_mpuio_suspend_late,
1173         .resume_early   = omap_mpuio_resume_early,
1174         .driver         = {
1175                 .name   = "mpuio",
1176         },
1177 };
1178
1179 static struct platform_device omap_mpuio_device = {
1180         .name           = "mpuio",
1181         .id             = -1,
1182         .dev = {
1183                 .driver = &omap_mpuio_driver.driver,
1184         }
1185         /* could list the /proc/iomem resources */
1186 };
1187
1188 static inline void mpuio_init(void)
1189 {
1190         platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1191
1192         if (platform_driver_register(&omap_mpuio_driver) == 0)
1193                 (void) platform_device_register(&omap_mpuio_device);
1194 }
1195
1196 #else
1197 static inline void mpuio_init(void) {}
1198 #endif  /* 16xx */
1199
1200 #else
1201
1202 extern struct irq_chip mpuio_irq_chip;
1203
1204 #define bank_is_mpuio(bank)     0
1205 static inline void mpuio_init(void) {}
1206
1207 #endif
1208
1209 /*---------------------------------------------------------------------*/
1210
1211 static int initialized;
1212 #if !defined(CONFIG_ARCH_OMAP3)
1213 static struct clk * gpio_ick;
1214 #endif
1215
1216 #if defined(CONFIG_ARCH_OMAP2)
1217 static struct clk * gpio_fck;
1218 #endif
1219
1220 #if defined(CONFIG_ARCH_OMAP2430)
1221 static struct clk * gpio5_ick;
1222 static struct clk * gpio5_fck;
1223 #endif
1224
1225 #if defined(CONFIG_ARCH_OMAP3)
1226 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1227 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1228 #endif
1229
1230 static int __init _omap_gpio_init(void)
1231 {
1232         int i;
1233         struct gpio_bank *bank;
1234 #if defined(CONFIG_ARCH_OMAP3)
1235         char clk_name[11];
1236 #endif
1237
1238         initialized = 1;
1239
1240 #if defined(CONFIG_ARCH_OMAP1)
1241         if (cpu_is_omap15xx()) {
1242                 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1243                 if (IS_ERR(gpio_ick))
1244                         printk("Could not get arm_gpio_ck\n");
1245                 else
1246                         clk_enable(gpio_ick);
1247         }
1248 #endif
1249 #if defined(CONFIG_ARCH_OMAP2)
1250         if (cpu_class_is_omap2()) {
1251                 gpio_ick = clk_get(NULL, "gpios_ick");
1252                 if (IS_ERR(gpio_ick))
1253                         printk("Could not get gpios_ick\n");
1254                 else
1255                         clk_enable(gpio_ick);
1256                 gpio_fck = clk_get(NULL, "gpios_fck");
1257                 if (IS_ERR(gpio_fck))
1258                         printk("Could not get gpios_fck\n");
1259                 else
1260                         clk_enable(gpio_fck);
1261
1262                 /*
1263                  * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1264                  */
1265 #if defined(CONFIG_ARCH_OMAP2430)
1266                 if (cpu_is_omap2430()) {
1267                         gpio5_ick = clk_get(NULL, "gpio5_ick");
1268                         if (IS_ERR(gpio5_ick))
1269                                 printk("Could not get gpio5_ick\n");
1270                         else
1271                                 clk_enable(gpio5_ick);
1272                         gpio5_fck = clk_get(NULL, "gpio5_fck");
1273                         if (IS_ERR(gpio5_fck))
1274                                 printk("Could not get gpio5_fck\n");
1275                         else
1276                                 clk_enable(gpio5_fck);
1277                 }
1278 #endif
1279         }
1280 #endif
1281
1282 #if defined(CONFIG_ARCH_OMAP3)
1283         if (cpu_is_omap34xx()) {
1284                 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1285                         sprintf(clk_name, "gpio%d_ick", i + 1);
1286                         gpio_iclks[i] = clk_get(NULL, clk_name);
1287                         if (IS_ERR(gpio_iclks[i]))
1288                                 printk(KERN_ERR "Could not get %s\n", clk_name);
1289                         else
1290                                 clk_enable(gpio_iclks[i]);
1291                         sprintf(clk_name, "gpio%d_fck", i + 1);
1292                         gpio_fclks[i] = clk_get(NULL, clk_name);
1293                         if (IS_ERR(gpio_fclks[i]))
1294                                 printk(KERN_ERR "Could not get %s\n", clk_name);
1295                         else
1296                                 clk_enable(gpio_fclks[i]);
1297                 }
1298         }
1299 #endif
1300
1301
1302 #ifdef CONFIG_ARCH_OMAP15XX
1303         if (cpu_is_omap15xx()) {
1304                 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1305                 gpio_bank_count = 2;
1306                 gpio_bank = gpio_bank_1510;
1307         }
1308 #endif
1309 #if defined(CONFIG_ARCH_OMAP16XX)
1310         if (cpu_is_omap16xx()) {
1311                 u32 rev;
1312
1313                 gpio_bank_count = 5;
1314                 gpio_bank = gpio_bank_1610;
1315                 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1316                 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1317                        (rev >> 4) & 0x0f, rev & 0x0f);
1318         }
1319 #endif
1320 #ifdef CONFIG_ARCH_OMAP730
1321         if (cpu_is_omap730()) {
1322                 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1323                 gpio_bank_count = 7;
1324                 gpio_bank = gpio_bank_730;
1325         }
1326 #endif
1327
1328 #ifdef CONFIG_ARCH_OMAP24XX
1329         if (cpu_is_omap242x()) {
1330                 int rev;
1331
1332                 gpio_bank_count = 4;
1333                 gpio_bank = gpio_bank_242x;
1334                 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1335                 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1336                         (rev >> 4) & 0x0f, rev & 0x0f);
1337         }
1338         if (cpu_is_omap243x()) {
1339                 int rev;
1340
1341                 gpio_bank_count = 5;
1342                 gpio_bank = gpio_bank_243x;
1343                 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1344                 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1345                         (rev >> 4) & 0x0f, rev & 0x0f);
1346         }
1347 #endif
1348 #ifdef CONFIG_ARCH_OMAP34XX
1349         if (cpu_is_omap34xx()) {
1350                 int rev;
1351
1352                 gpio_bank_count = OMAP34XX_NR_GPIOS;
1353                 gpio_bank = gpio_bank_34xx;
1354                 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1355                 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1356                         (rev >> 4) & 0x0f, rev & 0x0f);
1357         }
1358 #endif
1359         for (i = 0; i < gpio_bank_count; i++) {
1360                 int j, gpio_count = 16;
1361
1362                 bank = &gpio_bank[i];
1363                 bank->reserved_map = 0;
1364                 bank->base = IO_ADDRESS(bank->base);
1365                 spin_lock_init(&bank->lock);
1366                 if (bank_is_mpuio(bank))
1367                         omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1368                 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1369                         __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1370                         __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1371                 }
1372                 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1373                         __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1374                         __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1375                         __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1376                 }
1377                 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1378                         __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1379                         __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1380
1381                         gpio_count = 32; /* 730 has 32-bit GPIOs */
1382                 }
1383
1384 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1385                 if (bank->method == METHOD_GPIO_24XX) {
1386                         static const u32 non_wakeup_gpios[] = {
1387                                 0xe203ffc0, 0x08700040
1388                         };
1389
1390                         __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1391                         __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1392                         __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1393
1394                         /* Initialize interface clock ungated, module enabled */
1395                         __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1396                         if (i < ARRAY_SIZE(non_wakeup_gpios))
1397                                 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1398                         gpio_count = 32;
1399                 }
1400 #endif
1401                 for (j = bank->virtual_irq_start;
1402                      j < bank->virtual_irq_start + gpio_count; j++) {
1403                         set_irq_chip_data(j, bank);
1404                         if (bank_is_mpuio(bank))
1405                                 set_irq_chip(j, &mpuio_irq_chip);
1406                         else
1407                                 set_irq_chip(j, &gpio_irq_chip);
1408                         set_irq_handler(j, handle_simple_irq);
1409                         set_irq_flags(j, IRQF_VALID);
1410                 }
1411                 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1412                 set_irq_data(bank->irq, bank);
1413         }
1414
1415         /* Enable system clock for GPIO module.
1416          * The CAM_CLK_CTRL *is* really the right place. */
1417         if (cpu_is_omap16xx())
1418                 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1419
1420         /* Enable autoidle for the OCP interface */
1421         if (cpu_is_omap24xx())
1422                 omap_writel(1 << 0, 0x48019010);
1423         if (cpu_is_omap34xx())
1424                 omap_writel(1 << 0, 0x48306814);
1425
1426         return 0;
1427 }
1428
1429 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1430 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1431 {
1432         int i;
1433
1434         if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1435                 return 0;
1436
1437         for (i = 0; i < gpio_bank_count; i++) {
1438                 struct gpio_bank *bank = &gpio_bank[i];
1439                 void __iomem *wake_status;
1440                 void __iomem *wake_clear;
1441                 void __iomem *wake_set;
1442
1443                 switch (bank->method) {
1444 #ifdef CONFIG_ARCH_OMAP16XX
1445                 case METHOD_GPIO_1610:
1446                         wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1447                         wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1448                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1449                         break;
1450 #endif
1451 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1452                 case METHOD_GPIO_24XX:
1453                         wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1454                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1455                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1456                         break;
1457 #endif
1458                 default:
1459                         continue;
1460                 }
1461
1462                 spin_lock(&bank->lock);
1463                 bank->saved_wakeup = __raw_readl(wake_status);
1464                 __raw_writel(0xffffffff, wake_clear);
1465                 __raw_writel(bank->suspend_wakeup, wake_set);
1466                 spin_unlock(&bank->lock);
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int omap_gpio_resume(struct sys_device *dev)
1473 {
1474         int i;
1475
1476         if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1477                 return 0;
1478
1479         for (i = 0; i < gpio_bank_count; i++) {
1480                 struct gpio_bank *bank = &gpio_bank[i];
1481                 void __iomem *wake_clear;
1482                 void __iomem *wake_set;
1483
1484                 switch (bank->method) {
1485 #ifdef CONFIG_ARCH_OMAP16XX
1486                 case METHOD_GPIO_1610:
1487                         wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1488                         wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1489                         break;
1490 #endif
1491 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1492                 case METHOD_GPIO_24XX:
1493                         wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1494                         wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1495                         break;
1496 #endif
1497                 default:
1498                         continue;
1499                 }
1500
1501                 spin_lock(&bank->lock);
1502                 __raw_writel(0xffffffff, wake_clear);
1503                 __raw_writel(bank->saved_wakeup, wake_set);
1504                 spin_unlock(&bank->lock);
1505         }
1506
1507         return 0;
1508 }
1509
1510 static struct sysdev_class omap_gpio_sysclass = {
1511         .name           = "gpio",
1512         .suspend        = omap_gpio_suspend,
1513         .resume         = omap_gpio_resume,
1514 };
1515
1516 static struct sys_device omap_gpio_device = {
1517         .id             = 0,
1518         .cls            = &omap_gpio_sysclass,
1519 };
1520
1521 #endif
1522
1523 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1524
1525 static int workaround_enabled;
1526
1527 void omap2_gpio_prepare_for_retention(void)
1528 {
1529         int i, c = 0;
1530
1531         /* Remove triggering for all non-wakeup GPIOs.  Otherwise spurious
1532          * IRQs will be generated.  See OMAP2420 Errata item 1.101. */
1533         for (i = 0; i < gpio_bank_count; i++) {
1534                 struct gpio_bank *bank = &gpio_bank[i];
1535                 u32 l1, l2;
1536
1537                 if (!(bank->enabled_non_wakeup_gpios))
1538                         continue;
1539 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1540                 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1541                 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1542                 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1543 #endif
1544                 bank->saved_fallingdetect = l1;
1545                 bank->saved_risingdetect = l2;
1546                 l1 &= ~bank->enabled_non_wakeup_gpios;
1547                 l2 &= ~bank->enabled_non_wakeup_gpios;
1548 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1549                 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1550                 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1551 #endif
1552                 c++;
1553         }
1554         if (!c) {
1555                 workaround_enabled = 0;
1556                 return;
1557         }
1558         workaround_enabled = 1;
1559 }
1560
1561 void omap2_gpio_resume_after_retention(void)
1562 {
1563         int i;
1564
1565         if (!workaround_enabled)
1566                 return;
1567         for (i = 0; i < gpio_bank_count; i++) {
1568                 struct gpio_bank *bank = &gpio_bank[i];
1569                 u32 l;
1570
1571                 if (!(bank->enabled_non_wakeup_gpios))
1572                         continue;
1573 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1574                 __raw_writel(bank->saved_fallingdetect,
1575                                  bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1576                 __raw_writel(bank->saved_risingdetect,
1577                                  bank->base + OMAP24XX_GPIO_RISINGDETECT);
1578 #endif
1579                 /* Check if any of the non-wakeup interrupt GPIOs have changed
1580                  * state.  If so, generate an IRQ by software.  This is
1581                  * horribly racy, but it's the best we can do to work around
1582                  * this silicon bug. */
1583 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1584                 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1585 #endif
1586                 l ^= bank->saved_datain;
1587                 l &= bank->non_wakeup_gpios;
1588                 if (l) {
1589                         u32 old0, old1;
1590 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1591                         old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1592                         old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1593                         __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1594                         __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1595                         __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1596                         __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1597 #endif
1598                 }
1599         }
1600
1601 }
1602
1603 #endif
1604
1605 /*
1606  * This may get called early from board specific init
1607  * for boards that have interrupts routed via FPGA.
1608  */
1609 int __init omap_gpio_init(void)
1610 {
1611         if (!initialized)
1612                 return _omap_gpio_init();
1613         else
1614                 return 0;
1615 }
1616
1617 static int __init omap_gpio_sysinit(void)
1618 {
1619         int ret = 0;
1620
1621         if (!initialized)
1622                 ret = _omap_gpio_init();
1623
1624         mpuio_init();
1625
1626 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1627         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1628                 if (ret == 0) {
1629                         ret = sysdev_class_register(&omap_gpio_sysclass);
1630                         if (ret == 0)
1631                                 ret = sysdev_register(&omap_gpio_device);
1632                 }
1633         }
1634 #endif
1635
1636         return ret;
1637 }
1638
1639 EXPORT_SYMBOL(omap_request_gpio);
1640 EXPORT_SYMBOL(omap_free_gpio);
1641 EXPORT_SYMBOL(omap_set_gpio_direction);
1642 EXPORT_SYMBOL(omap_set_gpio_dataout);
1643 EXPORT_SYMBOL(omap_get_gpio_datain);
1644
1645 arch_initcall(omap_gpio_sysinit);
1646
1647
1648 #ifdef  CONFIG_DEBUG_FS
1649
1650 #include <linux/debugfs.h>
1651 #include <linux/seq_file.h>
1652
1653 static int gpio_is_input(struct gpio_bank *bank, int mask)
1654 {
1655         void __iomem *reg = bank->base;
1656
1657         switch (bank->method) {
1658         case METHOD_MPUIO:
1659                 reg += OMAP_MPUIO_IO_CNTL;
1660                 break;
1661         case METHOD_GPIO_1510:
1662                 reg += OMAP1510_GPIO_DIR_CONTROL;
1663                 break;
1664         case METHOD_GPIO_1610:
1665                 reg += OMAP1610_GPIO_DIRECTION;
1666                 break;
1667         case METHOD_GPIO_730:
1668                 reg += OMAP730_GPIO_DIR_CONTROL;
1669                 break;
1670         case METHOD_GPIO_24XX:
1671                 reg += OMAP24XX_GPIO_OE;
1672                 break;
1673         }
1674         return __raw_readl(reg) & mask;
1675 }
1676
1677
1678 static int dbg_gpio_show(struct seq_file *s, void *unused)
1679 {
1680         unsigned        i, j, gpio;
1681
1682         for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1683                 struct gpio_bank        *bank = gpio_bank + i;
1684                 unsigned                bankwidth = 16;
1685                 u32                     mask = 1;
1686
1687                 if (bank_is_mpuio(bank))
1688                         gpio = OMAP_MPUIO(0);
1689                 else if (cpu_class_is_omap2() || cpu_is_omap730())
1690                         bankwidth = 32;
1691
1692                 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1693                         unsigned        irq, value, is_in, irqstat;
1694
1695                         if (!(bank->reserved_map & mask))
1696                                 continue;
1697
1698                         irq = bank->virtual_irq_start + j;
1699                         value = omap_get_gpio_datain(gpio);
1700                         is_in = gpio_is_input(bank, mask);
1701
1702                         if (bank_is_mpuio(bank))
1703                                 seq_printf(s, "MPUIO %2d: ", j);
1704                         else
1705                                 seq_printf(s, "GPIO %3d: ", gpio);
1706                         seq_printf(s, "%s %s",
1707                                         is_in ? "in " : "out",
1708                                         value ? "hi"  : "lo");
1709
1710                         irqstat = irq_desc[irq].status;
1711                         if (is_in && ((bank->suspend_wakeup & mask)
1712                                         || irqstat & IRQ_TYPE_SENSE_MASK)) {
1713                                 char    *trigger = NULL;
1714
1715                                 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1716                                 case IRQ_TYPE_EDGE_FALLING:
1717                                         trigger = "falling";
1718                                         break;
1719                                 case IRQ_TYPE_EDGE_RISING:
1720                                         trigger = "rising";
1721                                         break;
1722                                 case IRQ_TYPE_EDGE_BOTH:
1723                                         trigger = "bothedge";
1724                                         break;
1725                                 case IRQ_TYPE_LEVEL_LOW:
1726                                         trigger = "low";
1727                                         break;
1728                                 case IRQ_TYPE_LEVEL_HIGH:
1729                                         trigger = "high";
1730                                         break;
1731                                 case IRQ_TYPE_NONE:
1732                                         trigger = "(unspecified)";
1733                                         break;
1734                                 }
1735                                 seq_printf(s, ", irq-%d %s%s",
1736                                                 irq, trigger,
1737                                                 (bank->suspend_wakeup & mask)
1738                                                         ? " wakeup" : "");
1739                         }
1740                         seq_printf(s, "\n");
1741                 }
1742
1743                 if (bank_is_mpuio(bank)) {
1744                         seq_printf(s, "\n");
1745                         gpio = 0;
1746                 }
1747         }
1748         return 0;
1749 }
1750
1751 static int dbg_gpio_open(struct inode *inode, struct file *file)
1752 {
1753         return single_open(file, dbg_gpio_show, &inode->i_private);
1754 }
1755
1756 static const struct file_operations debug_fops = {
1757         .open           = dbg_gpio_open,
1758         .read           = seq_read,
1759         .llseek         = seq_lseek,
1760         .release        = single_release,
1761 };
1762
1763 static int __init omap_gpio_debuginit(void)
1764 {
1765         (void) debugfs_create_file("omap_gpio", S_IRUGO,
1766                                         NULL, NULL, &debug_fops);
1767         return 0;
1768 }
1769 late_initcall(omap_gpio_debuginit);
1770 #endif