2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
22 #include <mach/hardware.h>
24 #include <mach/irqs.h>
25 #include <mach/gpio.h>
26 #include <asm/mach/irq.h>
29 * OMAP1510 GPIO registers
31 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
32 #define OMAP1510_GPIO_DATA_INPUT 0x00
33 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
34 #define OMAP1510_GPIO_DIR_CONTROL 0x08
35 #define OMAP1510_GPIO_INT_CONTROL 0x0c
36 #define OMAP1510_GPIO_INT_MASK 0x10
37 #define OMAP1510_GPIO_INT_STATUS 0x14
38 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40 #define OMAP1510_IH_GPIO_BASE 64
43 * OMAP1610 specific GPIO registers
45 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP730 specific GPIO registers
70 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
76 #define OMAP730_GPIO_DATA_INPUT 0x00
77 #define OMAP730_GPIO_DATA_OUTPUT 0x04
78 #define OMAP730_GPIO_DIR_CONTROL 0x08
79 #define OMAP730_GPIO_INT_CONTROL 0x0c
80 #define OMAP730_GPIO_INT_MASK 0x10
81 #define OMAP730_GPIO_INT_STATUS 0x14
84 * omap24xx specific GPIO registers
86 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
91 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
97 #define OMAP24XX_GPIO_REVISION 0x0000
98 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
99 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
100 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
101 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
103 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
104 #define OMAP24XX_GPIO_WAKE_EN 0x0020
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
123 * omap34xx specific GPIO registers
126 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
133 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
138 u16 virtual_irq_start
;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios
;
146 u32 enabled_non_wakeup_gpios
;
149 u32 saved_fallingdetect
;
150 u32 saved_risingdetect
;
154 struct gpio_chip chip
;
158 #define METHOD_MPUIO 0
159 #define METHOD_GPIO_1510 1
160 #define METHOD_GPIO_1610 2
161 #define METHOD_GPIO_730 3
162 #define METHOD_GPIO_24XX 4
164 #ifdef CONFIG_ARCH_OMAP16XX
165 static struct gpio_bank gpio_bank_1610
[5] = {
166 { OMAP_MPUIO_VBASE
, INT_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
167 { OMAP1610_GPIO1_BASE
, INT_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_1610
},
168 { OMAP1610_GPIO2_BASE
, INT_1610_GPIO_BANK2
, IH_GPIO_BASE
+ 16, METHOD_GPIO_1610
},
169 { OMAP1610_GPIO3_BASE
, INT_1610_GPIO_BANK3
, IH_GPIO_BASE
+ 32, METHOD_GPIO_1610
},
170 { OMAP1610_GPIO4_BASE
, INT_1610_GPIO_BANK4
, IH_GPIO_BASE
+ 48, METHOD_GPIO_1610
},
174 #ifdef CONFIG_ARCH_OMAP15XX
175 static struct gpio_bank gpio_bank_1510
[2] = {
176 { OMAP_MPUIO_VBASE
, INT_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
177 { OMAP1510_GPIO_BASE
, INT_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_1510
}
181 #ifdef CONFIG_ARCH_OMAP730
182 static struct gpio_bank gpio_bank_730
[7] = {
183 { OMAP_MPUIO_VBASE
, INT_730_MPUIO
, IH_MPUIO_BASE
, METHOD_MPUIO
},
184 { OMAP730_GPIO1_BASE
, INT_730_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_730
},
185 { OMAP730_GPIO2_BASE
, INT_730_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_730
},
186 { OMAP730_GPIO3_BASE
, INT_730_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_730
},
187 { OMAP730_GPIO4_BASE
, INT_730_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_730
},
188 { OMAP730_GPIO5_BASE
, INT_730_GPIO_BANK5
, IH_GPIO_BASE
+ 128, METHOD_GPIO_730
},
189 { OMAP730_GPIO6_BASE
, INT_730_GPIO_BANK6
, IH_GPIO_BASE
+ 160, METHOD_GPIO_730
},
193 #ifdef CONFIG_ARCH_OMAP24XX
195 static struct gpio_bank gpio_bank_242x
[4] = {
196 { OMAP242X_GPIO1_BASE
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_24XX
},
197 { OMAP242X_GPIO2_BASE
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_24XX
},
198 { OMAP242X_GPIO3_BASE
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_24XX
},
199 { OMAP242X_GPIO4_BASE
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_24XX
},
202 static struct gpio_bank gpio_bank_243x
[5] = {
203 { OMAP243X_GPIO1_BASE
, INT_24XX_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_24XX
},
204 { OMAP243X_GPIO2_BASE
, INT_24XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_24XX
},
205 { OMAP243X_GPIO3_BASE
, INT_24XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_24XX
},
206 { OMAP243X_GPIO4_BASE
, INT_24XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_24XX
},
207 { OMAP243X_GPIO5_BASE
, INT_24XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128, METHOD_GPIO_24XX
},
212 #ifdef CONFIG_ARCH_OMAP34XX
213 static struct gpio_bank gpio_bank_34xx
[6] = {
214 { OMAP34XX_GPIO1_BASE
, INT_34XX_GPIO_BANK1
, IH_GPIO_BASE
, METHOD_GPIO_24XX
},
215 { OMAP34XX_GPIO2_BASE
, INT_34XX_GPIO_BANK2
, IH_GPIO_BASE
+ 32, METHOD_GPIO_24XX
},
216 { OMAP34XX_GPIO3_BASE
, INT_34XX_GPIO_BANK3
, IH_GPIO_BASE
+ 64, METHOD_GPIO_24XX
},
217 { OMAP34XX_GPIO4_BASE
, INT_34XX_GPIO_BANK4
, IH_GPIO_BASE
+ 96, METHOD_GPIO_24XX
},
218 { OMAP34XX_GPIO5_BASE
, INT_34XX_GPIO_BANK5
, IH_GPIO_BASE
+ 128, METHOD_GPIO_24XX
},
219 { OMAP34XX_GPIO6_BASE
, INT_34XX_GPIO_BANK6
, IH_GPIO_BASE
+ 160, METHOD_GPIO_24XX
},
224 static struct gpio_bank
*gpio_bank
;
225 static int gpio_bank_count
;
227 static inline struct gpio_bank
*get_gpio_bank(int gpio
)
229 if (cpu_is_omap15xx()) {
230 if (OMAP_GPIO_IS_MPUIO(gpio
))
231 return &gpio_bank
[0];
232 return &gpio_bank
[1];
234 if (cpu_is_omap16xx()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio
))
236 return &gpio_bank
[0];
237 return &gpio_bank
[1 + (gpio
>> 4)];
239 if (cpu_is_omap730()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio
))
241 return &gpio_bank
[0];
242 return &gpio_bank
[1 + (gpio
>> 5)];
244 if (cpu_is_omap24xx())
245 return &gpio_bank
[gpio
>> 5];
246 if (cpu_is_omap34xx())
247 return &gpio_bank
[gpio
>> 5];
252 static inline int get_gpio_index(int gpio
)
254 if (cpu_is_omap730())
256 if (cpu_is_omap24xx())
258 if (cpu_is_omap34xx())
263 static inline int gpio_valid(int gpio
)
267 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio
)) {
268 if (gpio
>= OMAP_MAX_GPIO_LINES
+ 16)
272 if (cpu_is_omap15xx() && gpio
< 16)
274 if ((cpu_is_omap16xx()) && gpio
< 64)
276 if (cpu_is_omap730() && gpio
< 192)
278 if (cpu_is_omap24xx() && gpio
< 128)
280 if (cpu_is_omap34xx() && gpio
< 160)
285 static int check_gpio(int gpio
)
287 if (unlikely(gpio_valid(gpio
)) < 0) {
288 printk(KERN_ERR
"omap-gpio: invalid GPIO %d\n", gpio
);
295 static void _set_gpio_direction(struct gpio_bank
*bank
, int gpio
, int is_input
)
297 void __iomem
*reg
= bank
->base
;
300 switch (bank
->method
) {
301 #ifdef CONFIG_ARCH_OMAP1
303 reg
+= OMAP_MPUIO_IO_CNTL
;
306 #ifdef CONFIG_ARCH_OMAP15XX
307 case METHOD_GPIO_1510
:
308 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
311 #ifdef CONFIG_ARCH_OMAP16XX
312 case METHOD_GPIO_1610
:
313 reg
+= OMAP1610_GPIO_DIRECTION
;
316 #ifdef CONFIG_ARCH_OMAP730
317 case METHOD_GPIO_730
:
318 reg
+= OMAP730_GPIO_DIR_CONTROL
;
321 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
322 case METHOD_GPIO_24XX
:
323 reg
+= OMAP24XX_GPIO_OE
;
330 l
= __raw_readl(reg
);
335 __raw_writel(l
, reg
);
338 static void _set_gpio_dataout(struct gpio_bank
*bank
, int gpio
, int enable
)
340 void __iomem
*reg
= bank
->base
;
343 switch (bank
->method
) {
344 #ifdef CONFIG_ARCH_OMAP1
346 reg
+= OMAP_MPUIO_OUTPUT
;
347 l
= __raw_readl(reg
);
354 #ifdef CONFIG_ARCH_OMAP15XX
355 case METHOD_GPIO_1510
:
356 reg
+= OMAP1510_GPIO_DATA_OUTPUT
;
357 l
= __raw_readl(reg
);
364 #ifdef CONFIG_ARCH_OMAP16XX
365 case METHOD_GPIO_1610
:
367 reg
+= OMAP1610_GPIO_SET_DATAOUT
;
369 reg
+= OMAP1610_GPIO_CLEAR_DATAOUT
;
373 #ifdef CONFIG_ARCH_OMAP730
374 case METHOD_GPIO_730
:
375 reg
+= OMAP730_GPIO_DATA_OUTPUT
;
376 l
= __raw_readl(reg
);
383 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
384 case METHOD_GPIO_24XX
:
386 reg
+= OMAP24XX_GPIO_SETDATAOUT
;
388 reg
+= OMAP24XX_GPIO_CLEARDATAOUT
;
396 __raw_writel(l
, reg
);
399 static int __omap_get_gpio_datain(int gpio
)
401 struct gpio_bank
*bank
;
404 if (check_gpio(gpio
) < 0)
406 bank
= get_gpio_bank(gpio
);
408 switch (bank
->method
) {
409 #ifdef CONFIG_ARCH_OMAP1
411 reg
+= OMAP_MPUIO_INPUT_LATCH
;
414 #ifdef CONFIG_ARCH_OMAP15XX
415 case METHOD_GPIO_1510
:
416 reg
+= OMAP1510_GPIO_DATA_INPUT
;
419 #ifdef CONFIG_ARCH_OMAP16XX
420 case METHOD_GPIO_1610
:
421 reg
+= OMAP1610_GPIO_DATAIN
;
424 #ifdef CONFIG_ARCH_OMAP730
425 case METHOD_GPIO_730
:
426 reg
+= OMAP730_GPIO_DATA_INPUT
;
429 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
430 case METHOD_GPIO_24XX
:
431 reg
+= OMAP24XX_GPIO_DATAIN
;
437 return (__raw_readl(reg
)
438 & (1 << get_gpio_index(gpio
))) != 0;
441 #define MOD_REG_BIT(reg, bit_mask, set) \
443 int l = __raw_readl(base + reg); \
444 if (set) l |= bit_mask; \
445 else l &= ~bit_mask; \
446 __raw_writel(l, base + reg); \
449 void omap_set_gpio_debounce(int gpio
, int enable
)
451 struct gpio_bank
*bank
;
454 u32 val
, l
= 1 << get_gpio_index(gpio
);
456 if (cpu_class_is_omap1())
459 bank
= get_gpio_bank(gpio
);
461 reg
+= OMAP24XX_GPIO_DEBOUNCE_EN
;
463 spin_lock_irqsave(&bank
->lock
, flags
);
464 val
= __raw_readl(reg
);
466 if (enable
&& !(val
& l
))
468 else if (!enable
&& (val
& l
))
473 if (cpu_is_omap34xx()) {
475 clk_enable(bank
->dbck
);
477 clk_disable(bank
->dbck
);
480 __raw_writel(val
, reg
);
482 spin_unlock_irqrestore(&bank
->lock
, flags
);
484 EXPORT_SYMBOL(omap_set_gpio_debounce
);
486 void omap_set_gpio_debounce_time(int gpio
, int enc_time
)
488 struct gpio_bank
*bank
;
491 if (cpu_class_is_omap1())
494 bank
= get_gpio_bank(gpio
);
498 reg
+= OMAP24XX_GPIO_DEBOUNCE_VAL
;
499 __raw_writel(enc_time
, reg
);
501 EXPORT_SYMBOL(omap_set_gpio_debounce_time
);
503 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
504 static inline void set_24xx_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
507 void __iomem
*base
= bank
->base
;
508 u32 gpio_bit
= 1 << gpio
;
510 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0
, gpio_bit
,
511 trigger
& IRQ_TYPE_LEVEL_LOW
);
512 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1
, gpio_bit
,
513 trigger
& IRQ_TYPE_LEVEL_HIGH
);
514 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT
, gpio_bit
,
515 trigger
& IRQ_TYPE_EDGE_RISING
);
516 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT
, gpio_bit
,
517 trigger
& IRQ_TYPE_EDGE_FALLING
);
519 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
521 __raw_writel(1 << gpio
, bank
->base
522 + OMAP24XX_GPIO_SETWKUENA
);
524 __raw_writel(1 << gpio
, bank
->base
525 + OMAP24XX_GPIO_CLEARWKUENA
);
528 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
530 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
534 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
) |
535 __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
539 static int _set_gpio_triggering(struct gpio_bank
*bank
, int gpio
, int trigger
)
541 void __iomem
*reg
= bank
->base
;
544 switch (bank
->method
) {
545 #ifdef CONFIG_ARCH_OMAP1
547 reg
+= OMAP_MPUIO_GPIO_INT_EDGE
;
548 l
= __raw_readl(reg
);
549 if (trigger
& IRQ_TYPE_EDGE_RISING
)
551 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
557 #ifdef CONFIG_ARCH_OMAP15XX
558 case METHOD_GPIO_1510
:
559 reg
+= OMAP1510_GPIO_INT_CONTROL
;
560 l
= __raw_readl(reg
);
561 if (trigger
& IRQ_TYPE_EDGE_RISING
)
563 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
569 #ifdef CONFIG_ARCH_OMAP16XX
570 case METHOD_GPIO_1610
:
572 reg
+= OMAP1610_GPIO_EDGE_CTRL2
;
574 reg
+= OMAP1610_GPIO_EDGE_CTRL1
;
576 l
= __raw_readl(reg
);
577 l
&= ~(3 << (gpio
<< 1));
578 if (trigger
& IRQ_TYPE_EDGE_RISING
)
579 l
|= 2 << (gpio
<< 1);
580 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
581 l
|= 1 << (gpio
<< 1);
583 /* Enable wake-up during idle for dynamic tick */
584 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
);
586 __raw_writel(1 << gpio
, bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
);
589 #ifdef CONFIG_ARCH_OMAP730
590 case METHOD_GPIO_730
:
591 reg
+= OMAP730_GPIO_INT_CONTROL
;
592 l
= __raw_readl(reg
);
593 if (trigger
& IRQ_TYPE_EDGE_RISING
)
595 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
601 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
602 case METHOD_GPIO_24XX
:
603 set_24xx_gpio_triggering(bank
, gpio
, trigger
);
609 __raw_writel(l
, reg
);
615 static int gpio_irq_type(unsigned irq
, unsigned type
)
617 struct gpio_bank
*bank
;
622 if (!cpu_class_is_omap2() && irq
> IH_MPUIO_BASE
)
623 gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
625 gpio
= irq
- IH_GPIO_BASE
;
627 if (check_gpio(gpio
) < 0)
630 if (type
& ~IRQ_TYPE_SENSE_MASK
)
633 /* OMAP1 allows only only edge triggering */
634 if (!cpu_class_is_omap2()
635 && (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
638 bank
= get_irq_chip_data(irq
);
639 spin_lock_irqsave(&bank
->lock
, flags
);
640 retval
= _set_gpio_triggering(bank
, get_gpio_index(gpio
), type
);
642 irq_desc
[irq
].status
&= ~IRQ_TYPE_SENSE_MASK
;
643 irq_desc
[irq
].status
|= type
;
645 spin_unlock_irqrestore(&bank
->lock
, flags
);
647 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
648 __set_irq_handler_unlocked(irq
, handle_level_irq
);
649 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
650 __set_irq_handler_unlocked(irq
, handle_edge_irq
);
655 static void _clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
657 void __iomem
*reg
= bank
->base
;
659 switch (bank
->method
) {
660 #ifdef CONFIG_ARCH_OMAP1
662 /* MPUIO irqstatus is reset by reading the status register,
663 * so do nothing here */
666 #ifdef CONFIG_ARCH_OMAP15XX
667 case METHOD_GPIO_1510
:
668 reg
+= OMAP1510_GPIO_INT_STATUS
;
671 #ifdef CONFIG_ARCH_OMAP16XX
672 case METHOD_GPIO_1610
:
673 reg
+= OMAP1610_GPIO_IRQSTATUS1
;
676 #ifdef CONFIG_ARCH_OMAP730
677 case METHOD_GPIO_730
:
678 reg
+= OMAP730_GPIO_INT_STATUS
;
681 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
682 case METHOD_GPIO_24XX
:
683 reg
+= OMAP24XX_GPIO_IRQSTATUS1
;
690 __raw_writel(gpio_mask
, reg
);
692 /* Workaround for clearing DSP GPIO interrupts to allow retention */
693 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
694 if (cpu_is_omap24xx() || cpu_is_omap34xx())
695 __raw_writel(gpio_mask
, bank
->base
+ OMAP24XX_GPIO_IRQSTATUS2
);
699 static inline void _clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
701 _clear_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
));
704 static u32
_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
706 void __iomem
*reg
= bank
->base
;
711 switch (bank
->method
) {
712 #ifdef CONFIG_ARCH_OMAP1
714 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
719 #ifdef CONFIG_ARCH_OMAP15XX
720 case METHOD_GPIO_1510
:
721 reg
+= OMAP1510_GPIO_INT_MASK
;
726 #ifdef CONFIG_ARCH_OMAP16XX
727 case METHOD_GPIO_1610
:
728 reg
+= OMAP1610_GPIO_IRQENABLE1
;
732 #ifdef CONFIG_ARCH_OMAP730
733 case METHOD_GPIO_730
:
734 reg
+= OMAP730_GPIO_INT_MASK
;
739 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
740 case METHOD_GPIO_24XX
:
741 reg
+= OMAP24XX_GPIO_IRQENABLE1
;
750 l
= __raw_readl(reg
);
757 static void _enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
, int enable
)
759 void __iomem
*reg
= bank
->base
;
762 switch (bank
->method
) {
763 #ifdef CONFIG_ARCH_OMAP1
765 reg
+= OMAP_MPUIO_GPIO_MASKIT
;
766 l
= __raw_readl(reg
);
773 #ifdef CONFIG_ARCH_OMAP15XX
774 case METHOD_GPIO_1510
:
775 reg
+= OMAP1510_GPIO_INT_MASK
;
776 l
= __raw_readl(reg
);
783 #ifdef CONFIG_ARCH_OMAP16XX
784 case METHOD_GPIO_1610
:
786 reg
+= OMAP1610_GPIO_SET_IRQENABLE1
;
788 reg
+= OMAP1610_GPIO_CLEAR_IRQENABLE1
;
792 #ifdef CONFIG_ARCH_OMAP730
793 case METHOD_GPIO_730
:
794 reg
+= OMAP730_GPIO_INT_MASK
;
795 l
= __raw_readl(reg
);
802 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
803 case METHOD_GPIO_24XX
:
805 reg
+= OMAP24XX_GPIO_SETIRQENABLE1
;
807 reg
+= OMAP24XX_GPIO_CLEARIRQENABLE1
;
815 __raw_writel(l
, reg
);
818 static inline void _set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
, int enable
)
820 _enable_gpio_irqbank(bank
, 1 << get_gpio_index(gpio
), enable
);
824 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
825 * 1510 does not seem to have a wake-up register. If JTAG is connected
826 * to the target, system will wake up always on GPIO events. While
827 * system is running all registered GPIO interrupts need to have wake-up
828 * enabled. When system is suspended, only selected GPIO interrupts need
829 * to have wake-up enabled.
831 static int _set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
835 switch (bank
->method
) {
836 #ifdef CONFIG_ARCH_OMAP16XX
838 case METHOD_GPIO_1610
:
839 spin_lock_irqsave(&bank
->lock
, flags
);
841 bank
->suspend_wakeup
|= (1 << gpio
);
842 enable_irq_wake(bank
->irq
);
844 disable_irq_wake(bank
->irq
);
845 bank
->suspend_wakeup
&= ~(1 << gpio
);
847 spin_unlock_irqrestore(&bank
->lock
, flags
);
850 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
851 case METHOD_GPIO_24XX
:
852 if (bank
->non_wakeup_gpios
& (1 << gpio
)) {
853 printk(KERN_ERR
"Unable to modify wakeup on "
854 "non-wakeup GPIO%d\n",
855 (bank
- gpio_bank
) * 32 + gpio
);
858 spin_lock_irqsave(&bank
->lock
, flags
);
860 bank
->suspend_wakeup
|= (1 << gpio
);
861 enable_irq_wake(bank
->irq
);
863 disable_irq_wake(bank
->irq
);
864 bank
->suspend_wakeup
&= ~(1 << gpio
);
866 spin_unlock_irqrestore(&bank
->lock
, flags
);
870 printk(KERN_ERR
"Can't enable GPIO wakeup for method %i\n",
876 static void _reset_gpio(struct gpio_bank
*bank
, int gpio
)
878 _set_gpio_direction(bank
, get_gpio_index(gpio
), 1);
879 _set_gpio_irqenable(bank
, gpio
, 0);
880 _clear_gpio_irqstatus(bank
, gpio
);
881 _set_gpio_triggering(bank
, get_gpio_index(gpio
), IRQ_TYPE_NONE
);
884 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
885 static int gpio_wake_enable(unsigned int irq
, unsigned int enable
)
887 unsigned int gpio
= irq
- IH_GPIO_BASE
;
888 struct gpio_bank
*bank
;
891 if (check_gpio(gpio
) < 0)
893 bank
= get_irq_chip_data(irq
);
894 retval
= _set_gpio_wakeup(bank
, get_gpio_index(gpio
), enable
);
899 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
901 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
904 spin_lock_irqsave(&bank
->lock
, flags
);
906 /* Set trigger to none. You need to enable the desired trigger with
907 * request_irq() or set_irq_type().
909 _set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
911 #ifdef CONFIG_ARCH_OMAP15XX
912 if (bank
->method
== METHOD_GPIO_1510
) {
915 /* Claim the pin for MPU */
916 reg
= bank
->base
+ OMAP1510_GPIO_PIN_CONTROL
;
917 __raw_writel(__raw_readl(reg
) | (1 << offset
), reg
);
920 spin_unlock_irqrestore(&bank
->lock
, flags
);
925 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
927 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
930 spin_lock_irqsave(&bank
->lock
, flags
);
931 #ifdef CONFIG_ARCH_OMAP16XX
932 if (bank
->method
== METHOD_GPIO_1610
) {
933 /* Disable wake-up during idle for dynamic tick */
934 void __iomem
*reg
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
935 __raw_writel(1 << offset
, reg
);
938 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
939 if (bank
->method
== METHOD_GPIO_24XX
) {
940 /* Disable wake-up during idle for dynamic tick */
941 void __iomem
*reg
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
942 __raw_writel(1 << offset
, reg
);
945 _reset_gpio(bank
, bank
->chip
.base
+ offset
);
946 spin_unlock_irqrestore(&bank
->lock
, flags
);
950 * We need to unmask the GPIO bank interrupt as soon as possible to
951 * avoid missing GPIO interrupts for other lines in the bank.
952 * Then we need to mask-read-clear-unmask the triggered GPIO lines
953 * in the bank to avoid missing nested interrupts for a GPIO line.
954 * If we wait to unmask individual GPIO lines in the bank after the
955 * line's interrupt handler has been run, we may miss some nested
958 static void gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
960 void __iomem
*isr_reg
= NULL
;
962 unsigned int gpio_irq
;
963 struct gpio_bank
*bank
;
967 desc
->chip
->ack(irq
);
969 bank
= get_irq_data(irq
);
970 #ifdef CONFIG_ARCH_OMAP1
971 if (bank
->method
== METHOD_MPUIO
)
972 isr_reg
= bank
->base
+ OMAP_MPUIO_GPIO_INT
;
974 #ifdef CONFIG_ARCH_OMAP15XX
975 if (bank
->method
== METHOD_GPIO_1510
)
976 isr_reg
= bank
->base
+ OMAP1510_GPIO_INT_STATUS
;
978 #if defined(CONFIG_ARCH_OMAP16XX)
979 if (bank
->method
== METHOD_GPIO_1610
)
980 isr_reg
= bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
;
982 #ifdef CONFIG_ARCH_OMAP730
983 if (bank
->method
== METHOD_GPIO_730
)
984 isr_reg
= bank
->base
+ OMAP730_GPIO_INT_STATUS
;
986 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
987 if (bank
->method
== METHOD_GPIO_24XX
)
988 isr_reg
= bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
;
991 u32 isr_saved
, level_mask
= 0;
994 enabled
= _get_gpio_irqbank_mask(bank
);
995 isr_saved
= isr
= __raw_readl(isr_reg
) & enabled
;
997 if (cpu_is_omap15xx() && (bank
->method
== METHOD_MPUIO
))
1000 if (cpu_class_is_omap2()) {
1001 level_mask
= bank
->level_mask
& enabled
;
1004 /* clear edge sensitive interrupts before handler(s) are
1005 called so that we don't miss any interrupt occurred while
1007 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 0);
1008 _clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
1009 _enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
, 1);
1011 /* if there is only edge sensitive GPIO pin interrupts
1012 configured, we could unmask GPIO bank interrupt immediately */
1013 if (!level_mask
&& !unmasked
) {
1015 desc
->chip
->unmask(irq
);
1023 gpio_irq
= bank
->virtual_irq_start
;
1024 for (; isr
!= 0; isr
>>= 1, gpio_irq
++) {
1028 generic_handle_irq(gpio_irq
);
1031 /* if bank has any level sensitive GPIO pin interrupt
1032 configured, we must unmask the bank interrupt only after
1033 handler(s) are executed in order to avoid spurious bank
1036 desc
->chip
->unmask(irq
);
1040 static void gpio_irq_shutdown(unsigned int irq
)
1042 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1043 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1045 _reset_gpio(bank
, gpio
);
1048 static void gpio_ack_irq(unsigned int irq
)
1050 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1051 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1053 _clear_gpio_irqstatus(bank
, gpio
);
1056 static void gpio_mask_irq(unsigned int irq
)
1058 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1059 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1061 _set_gpio_irqenable(bank
, gpio
, 0);
1064 static void gpio_unmask_irq(unsigned int irq
)
1066 unsigned int gpio
= irq
- IH_GPIO_BASE
;
1067 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1068 unsigned int irq_mask
= 1 << get_gpio_index(gpio
);
1070 /* For level-triggered GPIOs, the clearing must be done after
1071 * the HW source is cleared, thus after the handler has run */
1072 if (bank
->level_mask
& irq_mask
) {
1073 _set_gpio_irqenable(bank
, gpio
, 0);
1074 _clear_gpio_irqstatus(bank
, gpio
);
1077 _set_gpio_irqenable(bank
, gpio
, 1);
1080 static struct irq_chip gpio_irq_chip
= {
1082 .shutdown
= gpio_irq_shutdown
,
1083 .ack
= gpio_ack_irq
,
1084 .mask
= gpio_mask_irq
,
1085 .unmask
= gpio_unmask_irq
,
1086 .set_type
= gpio_irq_type
,
1087 .set_wake
= gpio_wake_enable
,
1090 /*---------------------------------------------------------------------*/
1092 #ifdef CONFIG_ARCH_OMAP1
1094 /* MPUIO uses the always-on 32k clock */
1096 static void mpuio_ack_irq(unsigned int irq
)
1098 /* The ISR is reset automatically, so do nothing here. */
1101 static void mpuio_mask_irq(unsigned int irq
)
1103 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1104 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1106 _set_gpio_irqenable(bank
, gpio
, 0);
1109 static void mpuio_unmask_irq(unsigned int irq
)
1111 unsigned int gpio
= OMAP_MPUIO(irq
- IH_MPUIO_BASE
);
1112 struct gpio_bank
*bank
= get_irq_chip_data(irq
);
1114 _set_gpio_irqenable(bank
, gpio
, 1);
1117 static struct irq_chip mpuio_irq_chip
= {
1119 .ack
= mpuio_ack_irq
,
1120 .mask
= mpuio_mask_irq
,
1121 .unmask
= mpuio_unmask_irq
,
1122 .set_type
= gpio_irq_type
,
1123 #ifdef CONFIG_ARCH_OMAP16XX
1124 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1125 .set_wake
= gpio_wake_enable
,
1130 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1133 #ifdef CONFIG_ARCH_OMAP16XX
1135 #include <linux/platform_device.h>
1137 static int omap_mpuio_suspend_late(struct platform_device
*pdev
, pm_message_t mesg
)
1139 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1140 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1141 unsigned long flags
;
1143 spin_lock_irqsave(&bank
->lock
, flags
);
1144 bank
->saved_wakeup
= __raw_readl(mask_reg
);
1145 __raw_writel(0xffff & ~bank
->suspend_wakeup
, mask_reg
);
1146 spin_unlock_irqrestore(&bank
->lock
, flags
);
1151 static int omap_mpuio_resume_early(struct platform_device
*pdev
)
1153 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1154 void __iomem
*mask_reg
= bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
;
1155 unsigned long flags
;
1157 spin_lock_irqsave(&bank
->lock
, flags
);
1158 __raw_writel(bank
->saved_wakeup
, mask_reg
);
1159 spin_unlock_irqrestore(&bank
->lock
, flags
);
1164 /* use platform_driver for this, now that there's no longer any
1165 * point to sys_device (other than not disturbing old code).
1167 static struct platform_driver omap_mpuio_driver
= {
1168 .suspend_late
= omap_mpuio_suspend_late
,
1169 .resume_early
= omap_mpuio_resume_early
,
1175 static struct platform_device omap_mpuio_device
= {
1179 .driver
= &omap_mpuio_driver
.driver
,
1181 /* could list the /proc/iomem resources */
1184 static inline void mpuio_init(void)
1186 platform_set_drvdata(&omap_mpuio_device
, &gpio_bank_1610
[0]);
1188 if (platform_driver_register(&omap_mpuio_driver
) == 0)
1189 (void) platform_device_register(&omap_mpuio_device
);
1193 static inline void mpuio_init(void) {}
1198 extern struct irq_chip mpuio_irq_chip
;
1200 #define bank_is_mpuio(bank) 0
1201 static inline void mpuio_init(void) {}
1205 /*---------------------------------------------------------------------*/
1207 /* REVISIT these are stupid implementations! replace by ones that
1208 * don't switch on METHOD_* and which mostly avoid spinlocks
1211 static int gpio_input(struct gpio_chip
*chip
, unsigned offset
)
1213 struct gpio_bank
*bank
;
1214 unsigned long flags
;
1216 bank
= container_of(chip
, struct gpio_bank
, chip
);
1217 spin_lock_irqsave(&bank
->lock
, flags
);
1218 _set_gpio_direction(bank
, offset
, 1);
1219 spin_unlock_irqrestore(&bank
->lock
, flags
);
1223 static int gpio_get(struct gpio_chip
*chip
, unsigned offset
)
1225 return __omap_get_gpio_datain(chip
->base
+ offset
);
1228 static int gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
1230 struct gpio_bank
*bank
;
1231 unsigned long flags
;
1233 bank
= container_of(chip
, struct gpio_bank
, chip
);
1234 spin_lock_irqsave(&bank
->lock
, flags
);
1235 _set_gpio_dataout(bank
, offset
, value
);
1236 _set_gpio_direction(bank
, offset
, 0);
1237 spin_unlock_irqrestore(&bank
->lock
, flags
);
1241 static void gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1243 struct gpio_bank
*bank
;
1244 unsigned long flags
;
1246 bank
= container_of(chip
, struct gpio_bank
, chip
);
1247 spin_lock_irqsave(&bank
->lock
, flags
);
1248 _set_gpio_dataout(bank
, offset
, value
);
1249 spin_unlock_irqrestore(&bank
->lock
, flags
);
1252 static int gpio_2irq(struct gpio_chip
*chip
, unsigned offset
)
1254 struct gpio_bank
*bank
;
1256 bank
= container_of(chip
, struct gpio_bank
, chip
);
1257 return bank
->virtual_irq_start
+ offset
;
1260 /*---------------------------------------------------------------------*/
1262 static int initialized
;
1263 #if !defined(CONFIG_ARCH_OMAP3)
1264 static struct clk
* gpio_ick
;
1267 #if defined(CONFIG_ARCH_OMAP2)
1268 static struct clk
* gpio_fck
;
1271 #if defined(CONFIG_ARCH_OMAP2430)
1272 static struct clk
* gpio5_ick
;
1273 static struct clk
* gpio5_fck
;
1276 #if defined(CONFIG_ARCH_OMAP3)
1277 static struct clk
*gpio_iclks
[OMAP34XX_NR_GPIOS
];
1280 /* This lock class tells lockdep that GPIO irqs are in a different
1281 * category than their parents, so it won't report false recursion.
1283 static struct lock_class_key gpio_lock_class
;
1285 static int __init
_omap_gpio_init(void)
1289 struct gpio_bank
*bank
;
1294 #if defined(CONFIG_ARCH_OMAP1)
1295 if (cpu_is_omap15xx()) {
1296 gpio_ick
= clk_get(NULL
, "arm_gpio_ck");
1297 if (IS_ERR(gpio_ick
))
1298 printk("Could not get arm_gpio_ck\n");
1300 clk_enable(gpio_ick
);
1303 #if defined(CONFIG_ARCH_OMAP2)
1304 if (cpu_class_is_omap2()) {
1305 gpio_ick
= clk_get(NULL
, "gpios_ick");
1306 if (IS_ERR(gpio_ick
))
1307 printk("Could not get gpios_ick\n");
1309 clk_enable(gpio_ick
);
1310 gpio_fck
= clk_get(NULL
, "gpios_fck");
1311 if (IS_ERR(gpio_fck
))
1312 printk("Could not get gpios_fck\n");
1314 clk_enable(gpio_fck
);
1317 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1319 #if defined(CONFIG_ARCH_OMAP2430)
1320 if (cpu_is_omap2430()) {
1321 gpio5_ick
= clk_get(NULL
, "gpio5_ick");
1322 if (IS_ERR(gpio5_ick
))
1323 printk("Could not get gpio5_ick\n");
1325 clk_enable(gpio5_ick
);
1326 gpio5_fck
= clk_get(NULL
, "gpio5_fck");
1327 if (IS_ERR(gpio5_fck
))
1328 printk("Could not get gpio5_fck\n");
1330 clk_enable(gpio5_fck
);
1336 #if defined(CONFIG_ARCH_OMAP3)
1337 if (cpu_is_omap34xx()) {
1338 for (i
= 0; i
< OMAP34XX_NR_GPIOS
; i
++) {
1339 sprintf(clk_name
, "gpio%d_ick", i
+ 1);
1340 gpio_iclks
[i
] = clk_get(NULL
, clk_name
);
1341 if (IS_ERR(gpio_iclks
[i
]))
1342 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1344 clk_enable(gpio_iclks
[i
]);
1350 #ifdef CONFIG_ARCH_OMAP15XX
1351 if (cpu_is_omap15xx()) {
1352 printk(KERN_INFO
"OMAP1510 GPIO hardware\n");
1353 gpio_bank_count
= 2;
1354 gpio_bank
= gpio_bank_1510
;
1357 #if defined(CONFIG_ARCH_OMAP16XX)
1358 if (cpu_is_omap16xx()) {
1361 gpio_bank_count
= 5;
1362 gpio_bank
= gpio_bank_1610
;
1363 rev
= __raw_readw(gpio_bank
[1].base
+ OMAP1610_GPIO_REVISION
);
1364 printk(KERN_INFO
"OMAP GPIO hardware version %d.%d\n",
1365 (rev
>> 4) & 0x0f, rev
& 0x0f);
1368 #ifdef CONFIG_ARCH_OMAP730
1369 if (cpu_is_omap730()) {
1370 printk(KERN_INFO
"OMAP730 GPIO hardware\n");
1371 gpio_bank_count
= 7;
1372 gpio_bank
= gpio_bank_730
;
1376 #ifdef CONFIG_ARCH_OMAP24XX
1377 if (cpu_is_omap242x()) {
1380 gpio_bank_count
= 4;
1381 gpio_bank
= gpio_bank_242x
;
1382 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1383 printk(KERN_INFO
"OMAP242x GPIO hardware version %d.%d\n",
1384 (rev
>> 4) & 0x0f, rev
& 0x0f);
1386 if (cpu_is_omap243x()) {
1389 gpio_bank_count
= 5;
1390 gpio_bank
= gpio_bank_243x
;
1391 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1392 printk(KERN_INFO
"OMAP243x GPIO hardware version %d.%d\n",
1393 (rev
>> 4) & 0x0f, rev
& 0x0f);
1396 #ifdef CONFIG_ARCH_OMAP34XX
1397 if (cpu_is_omap34xx()) {
1400 gpio_bank_count
= OMAP34XX_NR_GPIOS
;
1401 gpio_bank
= gpio_bank_34xx
;
1402 rev
= __raw_readl(gpio_bank
[0].base
+ OMAP24XX_GPIO_REVISION
);
1403 printk(KERN_INFO
"OMAP34xx GPIO hardware version %d.%d\n",
1404 (rev
>> 4) & 0x0f, rev
& 0x0f);
1407 for (i
= 0; i
< gpio_bank_count
; i
++) {
1408 int j
, gpio_count
= 16;
1410 bank
= &gpio_bank
[i
];
1411 spin_lock_init(&bank
->lock
);
1412 if (bank_is_mpuio(bank
))
1413 __raw_writew(0xffff, bank
->base
+ OMAP_MPUIO_GPIO_MASKIT
);
1414 if (cpu_is_omap15xx() && bank
->method
== METHOD_GPIO_1510
) {
1415 __raw_writew(0xffff, bank
->base
+ OMAP1510_GPIO_INT_MASK
);
1416 __raw_writew(0x0000, bank
->base
+ OMAP1510_GPIO_INT_STATUS
);
1418 if (cpu_is_omap16xx() && bank
->method
== METHOD_GPIO_1610
) {
1419 __raw_writew(0x0000, bank
->base
+ OMAP1610_GPIO_IRQENABLE1
);
1420 __raw_writew(0xffff, bank
->base
+ OMAP1610_GPIO_IRQSTATUS1
);
1421 __raw_writew(0x0014, bank
->base
+ OMAP1610_GPIO_SYSCONFIG
);
1423 if (cpu_is_omap730() && bank
->method
== METHOD_GPIO_730
) {
1424 __raw_writel(0xffffffff, bank
->base
+ OMAP730_GPIO_INT_MASK
);
1425 __raw_writel(0x00000000, bank
->base
+ OMAP730_GPIO_INT_STATUS
);
1427 gpio_count
= 32; /* 730 has 32-bit GPIOs */
1430 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1431 if (bank
->method
== METHOD_GPIO_24XX
) {
1432 static const u32 non_wakeup_gpios
[] = {
1433 0xe203ffc0, 0x08700040
1436 __raw_writel(0x00000000, bank
->base
+ OMAP24XX_GPIO_IRQENABLE1
);
1437 __raw_writel(0xffffffff, bank
->base
+ OMAP24XX_GPIO_IRQSTATUS1
);
1438 __raw_writew(0x0015, bank
->base
+ OMAP24XX_GPIO_SYSCONFIG
);
1440 /* Initialize interface clock ungated, module enabled */
1441 __raw_writel(0, bank
->base
+ OMAP24XX_GPIO_CTRL
);
1442 if (i
< ARRAY_SIZE(non_wakeup_gpios
))
1443 bank
->non_wakeup_gpios
= non_wakeup_gpios
[i
];
1448 /* REVISIT eventually switch from OMAP-specific gpio structs
1449 * over to the generic ones
1451 bank
->chip
.request
= omap_gpio_request
;
1452 bank
->chip
.free
= omap_gpio_free
;
1453 bank
->chip
.direction_input
= gpio_input
;
1454 bank
->chip
.get
= gpio_get
;
1455 bank
->chip
.direction_output
= gpio_output
;
1456 bank
->chip
.set
= gpio_set
;
1457 bank
->chip
.to_irq
= gpio_2irq
;
1458 if (bank_is_mpuio(bank
)) {
1459 bank
->chip
.label
= "mpuio";
1460 #ifdef CONFIG_ARCH_OMAP16XX
1461 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1463 bank
->chip
.base
= OMAP_MPUIO(0);
1465 bank
->chip
.label
= "gpio";
1466 bank
->chip
.base
= gpio
;
1469 bank
->chip
.ngpio
= gpio_count
;
1471 gpiochip_add(&bank
->chip
);
1473 for (j
= bank
->virtual_irq_start
;
1474 j
< bank
->virtual_irq_start
+ gpio_count
; j
++) {
1475 lockdep_set_class(&irq_desc
[j
].lock
, &gpio_lock_class
);
1476 set_irq_chip_data(j
, bank
);
1477 if (bank_is_mpuio(bank
))
1478 set_irq_chip(j
, &mpuio_irq_chip
);
1480 set_irq_chip(j
, &gpio_irq_chip
);
1481 set_irq_handler(j
, handle_simple_irq
);
1482 set_irq_flags(j
, IRQF_VALID
);
1484 set_irq_chained_handler(bank
->irq
, gpio_irq_handler
);
1485 set_irq_data(bank
->irq
, bank
);
1487 if (cpu_is_omap34xx()) {
1488 sprintf(clk_name
, "gpio%d_dbck", i
+ 1);
1489 bank
->dbck
= clk_get(NULL
, clk_name
);
1490 if (IS_ERR(bank
->dbck
))
1491 printk(KERN_ERR
"Could not get %s\n", clk_name
);
1495 /* Enable system clock for GPIO module.
1496 * The CAM_CLK_CTRL *is* really the right place. */
1497 if (cpu_is_omap16xx())
1498 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL
) | 0x04, ULPD_CAM_CLK_CTRL
);
1500 /* Enable autoidle for the OCP interface */
1501 if (cpu_is_omap24xx())
1502 omap_writel(1 << 0, 0x48019010);
1503 if (cpu_is_omap34xx())
1504 omap_writel(1 << 0, 0x48306814);
1509 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1510 static int omap_gpio_suspend(struct sys_device
*dev
, pm_message_t mesg
)
1514 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1517 for (i
= 0; i
< gpio_bank_count
; i
++) {
1518 struct gpio_bank
*bank
= &gpio_bank
[i
];
1519 void __iomem
*wake_status
;
1520 void __iomem
*wake_clear
;
1521 void __iomem
*wake_set
;
1522 unsigned long flags
;
1524 switch (bank
->method
) {
1525 #ifdef CONFIG_ARCH_OMAP16XX
1526 case METHOD_GPIO_1610
:
1527 wake_status
= bank
->base
+ OMAP1610_GPIO_WAKEUPENABLE
;
1528 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1529 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1532 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1533 case METHOD_GPIO_24XX
:
1534 wake_status
= bank
->base
+ OMAP24XX_GPIO_WAKE_EN
;
1535 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1536 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1543 spin_lock_irqsave(&bank
->lock
, flags
);
1544 bank
->saved_wakeup
= __raw_readl(wake_status
);
1545 __raw_writel(0xffffffff, wake_clear
);
1546 __raw_writel(bank
->suspend_wakeup
, wake_set
);
1547 spin_unlock_irqrestore(&bank
->lock
, flags
);
1553 static int omap_gpio_resume(struct sys_device
*dev
)
1557 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1560 for (i
= 0; i
< gpio_bank_count
; i
++) {
1561 struct gpio_bank
*bank
= &gpio_bank
[i
];
1562 void __iomem
*wake_clear
;
1563 void __iomem
*wake_set
;
1564 unsigned long flags
;
1566 switch (bank
->method
) {
1567 #ifdef CONFIG_ARCH_OMAP16XX
1568 case METHOD_GPIO_1610
:
1569 wake_clear
= bank
->base
+ OMAP1610_GPIO_CLEAR_WAKEUPENA
;
1570 wake_set
= bank
->base
+ OMAP1610_GPIO_SET_WAKEUPENA
;
1573 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1574 case METHOD_GPIO_24XX
:
1575 wake_clear
= bank
->base
+ OMAP24XX_GPIO_CLEARWKUENA
;
1576 wake_set
= bank
->base
+ OMAP24XX_GPIO_SETWKUENA
;
1583 spin_lock_irqsave(&bank
->lock
, flags
);
1584 __raw_writel(0xffffffff, wake_clear
);
1585 __raw_writel(bank
->saved_wakeup
, wake_set
);
1586 spin_unlock_irqrestore(&bank
->lock
, flags
);
1592 static struct sysdev_class omap_gpio_sysclass
= {
1594 .suspend
= omap_gpio_suspend
,
1595 .resume
= omap_gpio_resume
,
1598 static struct sys_device omap_gpio_device
= {
1600 .cls
= &omap_gpio_sysclass
,
1605 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1607 static int workaround_enabled
;
1609 void omap2_gpio_prepare_for_retention(void)
1613 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1614 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1615 for (i
= 0; i
< gpio_bank_count
; i
++) {
1616 struct gpio_bank
*bank
= &gpio_bank
[i
];
1619 if (!(bank
->enabled_non_wakeup_gpios
))
1621 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1622 bank
->saved_datain
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
1623 l1
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1624 l2
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1626 bank
->saved_fallingdetect
= l1
;
1627 bank
->saved_risingdetect
= l2
;
1628 l1
&= ~bank
->enabled_non_wakeup_gpios
;
1629 l2
&= ~bank
->enabled_non_wakeup_gpios
;
1630 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1631 __raw_writel(l1
, bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1632 __raw_writel(l2
, bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1637 workaround_enabled
= 0;
1640 workaround_enabled
= 1;
1643 void omap2_gpio_resume_after_retention(void)
1647 if (!workaround_enabled
)
1649 for (i
= 0; i
< gpio_bank_count
; i
++) {
1650 struct gpio_bank
*bank
= &gpio_bank
[i
];
1653 if (!(bank
->enabled_non_wakeup_gpios
))
1655 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1656 __raw_writel(bank
->saved_fallingdetect
,
1657 bank
->base
+ OMAP24XX_GPIO_FALLINGDETECT
);
1658 __raw_writel(bank
->saved_risingdetect
,
1659 bank
->base
+ OMAP24XX_GPIO_RISINGDETECT
);
1661 /* Check if any of the non-wakeup interrupt GPIOs have changed
1662 * state. If so, generate an IRQ by software. This is
1663 * horribly racy, but it's the best we can do to work around
1664 * this silicon bug. */
1665 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1666 l
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_DATAIN
);
1668 l
^= bank
->saved_datain
;
1669 l
&= bank
->non_wakeup_gpios
;
1672 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1673 old0
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1674 old1
= __raw_readl(bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1675 __raw_writel(old0
| l
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1676 __raw_writel(old1
| l
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1677 __raw_writel(old0
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT0
);
1678 __raw_writel(old1
, bank
->base
+ OMAP24XX_GPIO_LEVELDETECT1
);
1688 * This may get called early from board specific init
1689 * for boards that have interrupts routed via FPGA.
1691 int __init
omap_gpio_init(void)
1694 return _omap_gpio_init();
1699 static int __init
omap_gpio_sysinit(void)
1704 ret
= _omap_gpio_init();
1708 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1709 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1711 ret
= sysdev_class_register(&omap_gpio_sysclass
);
1713 ret
= sysdev_register(&omap_gpio_device
);
1721 arch_initcall(omap_gpio_sysinit
);
1724 #ifdef CONFIG_DEBUG_FS
1726 #include <linux/debugfs.h>
1727 #include <linux/seq_file.h>
1729 static int gpio_is_input(struct gpio_bank
*bank
, int mask
)
1731 void __iomem
*reg
= bank
->base
;
1733 switch (bank
->method
) {
1735 reg
+= OMAP_MPUIO_IO_CNTL
;
1737 case METHOD_GPIO_1510
:
1738 reg
+= OMAP1510_GPIO_DIR_CONTROL
;
1740 case METHOD_GPIO_1610
:
1741 reg
+= OMAP1610_GPIO_DIRECTION
;
1743 case METHOD_GPIO_730
:
1744 reg
+= OMAP730_GPIO_DIR_CONTROL
;
1746 case METHOD_GPIO_24XX
:
1747 reg
+= OMAP24XX_GPIO_OE
;
1750 return __raw_readl(reg
) & mask
;
1754 static int dbg_gpio_show(struct seq_file
*s
, void *unused
)
1756 unsigned i
, j
, gpio
;
1758 for (i
= 0, gpio
= 0; i
< gpio_bank_count
; i
++) {
1759 struct gpio_bank
*bank
= gpio_bank
+ i
;
1760 unsigned bankwidth
= 16;
1763 if (bank_is_mpuio(bank
))
1764 gpio
= OMAP_MPUIO(0);
1765 else if (cpu_class_is_omap2() || cpu_is_omap730())
1768 for (j
= 0; j
< bankwidth
; j
++, gpio
++, mask
<<= 1) {
1769 unsigned irq
, value
, is_in
, irqstat
;
1772 label
= gpiochip_is_requested(&bank
->chip
, j
);
1776 irq
= bank
->virtual_irq_start
+ j
;
1777 value
= gpio_get_value(gpio
);
1778 is_in
= gpio_is_input(bank
, mask
);
1780 if (bank_is_mpuio(bank
))
1781 seq_printf(s
, "MPUIO %2d ", j
);
1783 seq_printf(s
, "GPIO %3d ", gpio
);
1784 seq_printf(s
, "(%-20.20s): %s %s",
1786 is_in
? "in " : "out",
1787 value
? "hi" : "lo");
1789 /* FIXME for at least omap2, show pullup/pulldown state */
1791 irqstat
= irq_desc
[irq
].status
;
1792 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1793 defined(CONFIG_ARCH_OMAP34XX)
1794 if (is_in
&& ((bank
->suspend_wakeup
& mask
)
1795 || irqstat
& IRQ_TYPE_SENSE_MASK
)) {
1796 char *trigger
= NULL
;
1798 switch (irqstat
& IRQ_TYPE_SENSE_MASK
) {
1799 case IRQ_TYPE_EDGE_FALLING
:
1800 trigger
= "falling";
1802 case IRQ_TYPE_EDGE_RISING
:
1805 case IRQ_TYPE_EDGE_BOTH
:
1806 trigger
= "bothedge";
1808 case IRQ_TYPE_LEVEL_LOW
:
1811 case IRQ_TYPE_LEVEL_HIGH
:
1818 seq_printf(s
, ", irq-%d %-8s%s",
1820 (bank
->suspend_wakeup
& mask
)
1824 seq_printf(s
, "\n");
1827 if (bank_is_mpuio(bank
)) {
1828 seq_printf(s
, "\n");
1835 static int dbg_gpio_open(struct inode
*inode
, struct file
*file
)
1837 return single_open(file
, dbg_gpio_show
, &inode
->i_private
);
1840 static const struct file_operations debug_fops
= {
1841 .open
= dbg_gpio_open
,
1843 .llseek
= seq_lseek
,
1844 .release
= single_release
,
1847 static int __init
omap_gpio_debuginit(void)
1849 (void) debugfs_create_file("omap_gpio", S_IRUGO
,
1850 NULL
, NULL
, &debug_fops
);
1853 late_initcall(omap_gpio_debuginit
);