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[ARM] S3C24XX: Movev udc headers to arch/arm/plat-s3c24xx/include/plat
[linux-2.6/openmoko-kernel.git] / drivers / video / sh_mobile_lcdcfb.c
blobefff672fd7b8e580657440f6bb84744ae05ef1bf
1 /*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
14 #include <linux/mm.h>
15 #include <linux/fb.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <video/sh_mobile_lcdc.h>
20
21 #define PALETTE_NR 16
22
23 struct sh_mobile_lcdc_priv;
24 struct sh_mobile_lcdc_chan {
25 struct sh_mobile_lcdc_priv *lcdc;
26 unsigned long *reg_offs;
27 unsigned long ldmt1r_value;
28 unsigned long enabled; /* ME and SE in LDCNT2R */
29 struct sh_mobile_lcdc_chan_cfg cfg;
30 u32 pseudo_palette[PALETTE_NR];
31 struct fb_info info;
32 dma_addr_t dma_handle;
33 };
34
35 struct sh_mobile_lcdc_priv {
36 void __iomem *base;
37 #ifdef CONFIG_HAVE_CLK
38 struct clk *clk;
39 #endif
40 unsigned long lddckr;
41 struct sh_mobile_lcdc_chan ch[2];
42 };
43
44 /* shared registers */
45 #define _LDDCKR 0x410
46 #define _LDDCKSTPR 0x414
47 #define _LDINTR 0x468
48 #define _LDSR 0x46c
49 #define _LDCNT1R 0x470
50 #define _LDCNT2R 0x474
51 #define _LDDDSR 0x47c
52 #define _LDDWD0R 0x800
53 #define _LDDRDR 0x840
54 #define _LDDWAR 0x900
55 #define _LDDRAR 0x904
56
57 /* per-channel registers */
58 enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
59 LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR };
60
61 static unsigned long lcdc_offs_mainlcd[] = {
62 [LDDCKPAT1R] = 0x400,
63 [LDDCKPAT2R] = 0x404,
64 [LDMT1R] = 0x418,
65 [LDMT2R] = 0x41c,
66 [LDMT3R] = 0x420,
67 [LDDFR] = 0x424,
68 [LDSM1R] = 0x428,
69 [LDSA1R] = 0x430,
70 [LDMLSR] = 0x438,
71 [LDHCNR] = 0x448,
72 [LDHSYNR] = 0x44c,
73 [LDVLNR] = 0x450,
74 [LDVSYNR] = 0x454,
75 [LDPMR] = 0x460,
76 };
77
78 static unsigned long lcdc_offs_sublcd[] = {
79 [LDDCKPAT1R] = 0x408,
80 [LDDCKPAT2R] = 0x40c,
81 [LDMT1R] = 0x600,
82 [LDMT2R] = 0x604,
83 [LDMT3R] = 0x608,
84 [LDDFR] = 0x60c,
85 [LDSM1R] = 0x610,
86 [LDSA1R] = 0x618,
87 [LDMLSR] = 0x620,
88 [LDHCNR] = 0x624,
89 [LDHSYNR] = 0x628,
90 [LDVLNR] = 0x62c,
91 [LDVSYNR] = 0x630,
92 [LDPMR] = 0x63c,
93 };
94
95 #define START_LCDC 0x00000001
96 #define LCDC_RESET 0x00000100
97 #define DISPLAY_BEU 0x00000008
98 #define LCDC_ENABLE 0x00000001
99
100 static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
101 int reg_nr, unsigned long data)
102 {
103 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
104 }
105
106 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
107 int reg_nr)
108 {
109 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
110 }
111
112 static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
113 unsigned long reg_offs, unsigned long data)
114 {
115 iowrite32(data, priv->base + reg_offs);
116 }
117
118 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
119 unsigned long reg_offs)
120 {
121 return ioread32(priv->base + reg_offs);
122 }
123
124 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
125 unsigned long reg_offs,
126 unsigned long mask, unsigned long until)
127 {
128 while ((lcdc_read(priv, reg_offs) & mask) != until)
129 cpu_relax();
130 }
131
132 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
133 {
134 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
135 }
136
137 static void lcdc_sys_write_index(void *handle, unsigned long data)
138 {
139 struct sh_mobile_lcdc_chan *ch = handle;
140
141 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
142 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
143 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
144 }
145
146 static void lcdc_sys_write_data(void *handle, unsigned long data)
147 {
148 struct sh_mobile_lcdc_chan *ch = handle;
149
150 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
151 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
152 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
153 }
154
155 static unsigned long lcdc_sys_read_data(void *handle)
156 {
157 struct sh_mobile_lcdc_chan *ch = handle;
158
159 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
160 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
161 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
162 udelay(1);
163
164 return lcdc_read(ch->lcdc, _LDDRDR) & 0xffff;
165 }
166
167 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
168 lcdc_sys_write_index,
169 lcdc_sys_write_data,
170 lcdc_sys_read_data,
171 };
172
173 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
174 int start)
175 {
176 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
177 int k;
178
179 /* start or stop the lcdc */
180 if (start)
181 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
182 else
183 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
184
185 /* wait until power is applied/stopped on all channels */
186 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
187 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
188 while (1) {
189 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
190 if (start && tmp == 3)
191 break;
192 if (!start && tmp == 0)
193 break;
194 cpu_relax();
195 }
196
197 if (!start)
198 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
199 }
200
201 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
202 {
203 struct sh_mobile_lcdc_chan *ch;
204 struct fb_videomode *lcd_cfg;
205 struct sh_mobile_lcdc_board_cfg *board_cfg;
206 unsigned long tmp;
207 int k, m;
208 int ret = 0;
209
210 /* reset */
211 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
212 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
213
214 /* enable LCDC channels */
215 tmp = lcdc_read(priv, _LDCNT2R);
216 tmp |= priv->ch[0].enabled;
217 tmp |= priv->ch[1].enabled;
218 lcdc_write(priv, _LDCNT2R, tmp);
219
220 /* read data from external memory, avoid using the BEU for now */
221 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
222
223 /* stop the lcdc first */
224 sh_mobile_lcdc_start_stop(priv, 0);
225
226 /* configure clocks */
227 tmp = priv->lddckr;
228 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
229 ch = &priv->ch[k];
230
231 if (!priv->ch[k].enabled)
232 continue;
233
234 m = ch->cfg.clock_divider;
235 if (!m)
236 continue;
237
238 if (m == 1)
239 m = 1 << 6;
240 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
241
242 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
243 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
244 }
245
246 lcdc_write(priv, _LDDCKR, tmp);
247
248 /* start dotclock again */
249 lcdc_write(priv, _LDDCKSTPR, 0);
250 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
251
252 /* interrupts are disabled */
253 lcdc_write(priv, _LDINTR, 0);
254
255 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
256 ch = &priv->ch[k];
257 lcd_cfg = &ch->cfg.lcd_cfg;
258
259 if (!ch->enabled)
260 continue;
261
262 tmp = ch->ldmt1r_value;
263 tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
264 tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
265 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
266 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
267 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
268 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
269 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
270 lcdc_write_chan(ch, LDMT1R, tmp);
271
272 /* setup SYS bus */
273 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
274 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
275
276 /* horizontal configuration */
277 tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
278 tmp += lcd_cfg->left_margin;
279 tmp += lcd_cfg->right_margin;
280 tmp /= 8; /* HTCN */
281 tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
282 lcdc_write_chan(ch, LDHCNR, tmp);
283
284 tmp = lcd_cfg->xres;
285 tmp += lcd_cfg->right_margin;
286 tmp /= 8; /* HSYNP */
287 tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
288 lcdc_write_chan(ch, LDHSYNR, tmp);
289
290 /* power supply */
291 lcdc_write_chan(ch, LDPMR, 0);
292
293 /* vertical configuration */
294 tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
295 tmp += lcd_cfg->upper_margin;
296 tmp += lcd_cfg->lower_margin; /* VTLN */
297 tmp |= lcd_cfg->yres << 16; /* VDLN */
298 lcdc_write_chan(ch, LDVLNR, tmp);
299
300 tmp = lcd_cfg->yres;
301 tmp += lcd_cfg->lower_margin; /* VSYNP */
302 tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
303 lcdc_write_chan(ch, LDVSYNR, tmp);
304
305 board_cfg = &ch->cfg.board_cfg;
306 if (board_cfg->setup_sys)
307 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
308 &sh_mobile_lcdc_sys_bus_ops);
309 if (ret)
310 return ret;
311 }
312
313 /* --- display_lcdc_data() --- */
314 lcdc_write(priv, _LDINTR, 0x00000f00);
315
316 /* word and long word swap */
317 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
318
319 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
320 ch = &priv->ch[k];
321
322 if (!priv->ch[k].enabled)
323 continue;
324
325 /* set bpp format in PKF[4:0] */
326 tmp = lcdc_read_chan(ch, LDDFR);
327 tmp &= ~(0x0001001f);
328 tmp |= (priv->ch[k].info.var.bits_per_pixel == 16) ? 3 : 0;
329 lcdc_write_chan(ch, LDDFR, tmp);
330
331 /* point out our frame buffer */
332 lcdc_write_chan(ch, LDSA1R, ch->info.fix.smem_start);
333
334 /* set line size */
335 lcdc_write_chan(ch, LDMLSR, ch->info.fix.line_length);
336
337 /* continuous read mode */
338 lcdc_write_chan(ch, LDSM1R, 0);
339 }
340
341 /* display output */
342 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
343
344 /* start the lcdc */
345 sh_mobile_lcdc_start_stop(priv, 1);
346
347 /* tell the board code to enable the panel */
348 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
349 ch = &priv->ch[k];
350 board_cfg = &ch->cfg.board_cfg;
351 if (board_cfg->display_on)
352 board_cfg->display_on(board_cfg->board_data);
353 }
354
355 return 0;
356 }
357
358 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
359 {
360 struct sh_mobile_lcdc_chan *ch;
361 struct sh_mobile_lcdc_board_cfg *board_cfg;
362 int k;
363
364 /* tell the board code to disable the panel */
365 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
366 ch = &priv->ch[k];
367 board_cfg = &ch->cfg.board_cfg;
368 if (board_cfg->display_off)
369 board_cfg->display_off(board_cfg->board_data);
370 }
371
372 /* stop the lcdc */
373 sh_mobile_lcdc_start_stop(priv, 0);
374 }
375
376 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
377 {
378 int ifm, miftyp;
379
380 switch (ch->cfg.interface_type) {
381 case RGB8: ifm = 0; miftyp = 0; break;
382 case RGB9: ifm = 0; miftyp = 4; break;
383 case RGB12A: ifm = 0; miftyp = 5; break;
384 case RGB12B: ifm = 0; miftyp = 6; break;
385 case RGB16: ifm = 0; miftyp = 7; break;
386 case RGB18: ifm = 0; miftyp = 10; break;
387 case RGB24: ifm = 0; miftyp = 11; break;
388 case SYS8A: ifm = 1; miftyp = 0; break;
389 case SYS8B: ifm = 1; miftyp = 1; break;
390 case SYS8C: ifm = 1; miftyp = 2; break;
391 case SYS8D: ifm = 1; miftyp = 3; break;
392 case SYS9: ifm = 1; miftyp = 4; break;
393 case SYS12: ifm = 1; miftyp = 5; break;
394 case SYS16A: ifm = 1; miftyp = 7; break;
395 case SYS16B: ifm = 1; miftyp = 8; break;
396 case SYS16C: ifm = 1; miftyp = 9; break;
397 case SYS18: ifm = 1; miftyp = 10; break;
398 case SYS24: ifm = 1; miftyp = 11; break;
399 default: goto bad;
400 }
401
402 /* SUBLCD only supports SYS interface */
403 if (lcdc_chan_is_sublcd(ch)) {
404 if (ifm == 0)
405 goto bad;
406 else
407 ifm = 0;
408 }
409
410 ch->ldmt1r_value = (ifm << 12) | miftyp;
411 return 0;
412 bad:
413 return -EINVAL;
414 }
415
416 static int sh_mobile_lcdc_setup_clocks(struct device *dev, int clock_source,
417 struct sh_mobile_lcdc_priv *priv)
418 {
419 char *str;
420 int icksel;
421
422 switch (clock_source) {
423 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
424 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
425 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
426 default:
427 return -EINVAL;
428 }
429
430 priv->lddckr = icksel << 16;
431
432 #ifdef CONFIG_HAVE_CLK
433 if (str) {
434 priv->clk = clk_get(dev, str);
435 if (IS_ERR(priv->clk)) {
436 dev_err(dev, "cannot get clock %s\n", str);
437 return PTR_ERR(priv->clk);
438 }
439
440 clk_enable(priv->clk);
441 }
442 #endif
443
444 return 0;
445 }
446
447 static int sh_mobile_lcdc_setcolreg(u_int regno,
448 u_int red, u_int green, u_int blue,
449 u_int transp, struct fb_info *info)
450 {
451 u32 *palette = info->pseudo_palette;
452
453 if (regno >= PALETTE_NR)
454 return -EINVAL;
455
456 /* only FB_VISUAL_TRUECOLOR supported */
457
458 red >>= 16 - info->var.red.length;
459 green >>= 16 - info->var.green.length;
460 blue >>= 16 - info->var.blue.length;
461 transp >>= 16 - info->var.transp.length;
462
463 palette[regno] = (red << info->var.red.offset) |
464 (green << info->var.green.offset) |
465 (blue << info->var.blue.offset) |
466 (transp << info->var.transp.offset);
467
468 return 0;
469 }
470
471 static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
472 .id = "SH Mobile LCDC",
473 .type = FB_TYPE_PACKED_PIXELS,
474 .visual = FB_VISUAL_TRUECOLOR,
475 .accel = FB_ACCEL_NONE,
476 };
477
478 static struct fb_ops sh_mobile_lcdc_ops = {
479 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
480 .fb_fillrect = cfb_fillrect,
481 .fb_copyarea = cfb_copyarea,
482 .fb_imageblit = cfb_imageblit,
483 };
484
485 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
486 {
487 switch (bpp) {
488 case 16: /* PKF[4:0] = 00011 - RGB 565 */
489 var->red.offset = 11;
490 var->red.length = 5;
491 var->green.offset = 5;
492 var->green.length = 6;
493 var->blue.offset = 0;
494 var->blue.length = 5;
495 var->transp.offset = 0;
496 var->transp.length = 0;
497 break;
498
499 case 32: /* PKF[4:0] = 00000 - RGB 888
500 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
501 * this may be because LDDDSR has word swap enabled..
502 */
503 var->red.offset = 0;
504 var->red.length = 8;
505 var->green.offset = 24;
506 var->green.length = 8;
507 var->blue.offset = 16;
508 var->blue.length = 8;
509 var->transp.offset = 0;
510 var->transp.length = 0;
511 break;
512 default:
513 return -EINVAL;
514 }
515 var->bits_per_pixel = bpp;
516 var->red.msb_right = 0;
517 var->green.msb_right = 0;
518 var->blue.msb_right = 0;
519 var->transp.msb_right = 0;
520 return 0;
521 }
522
523 static int sh_mobile_lcdc_remove(struct platform_device *pdev);
524
525 static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
526 {
527 struct fb_info *info;
528 struct sh_mobile_lcdc_priv *priv;
529 struct sh_mobile_lcdc_info *pdata;
530 struct sh_mobile_lcdc_chan_cfg *cfg;
531 struct resource *res;
532 int error;
533 void *buf;
534 int i, j;
535
536 if (!pdev->dev.platform_data) {
537 dev_err(&pdev->dev, "no platform data defined\n");
538 error = -EINVAL;
539 goto err0;
540 }
541
542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
543 if (res == NULL) {
544 dev_err(&pdev->dev, "cannot find IO resource\n");
545 error = -ENOENT;
546 goto err0;
547 }
548
549 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
550 if (!priv) {
551 dev_err(&pdev->dev, "cannot allocate device data\n");
552 error = -ENOMEM;
553 goto err0;
554 }
555
556 platform_set_drvdata(pdev, priv);
557 pdata = pdev->dev.platform_data;
558
559 j = 0;
560 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
561 priv->ch[j].lcdc = priv;
562 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
563
564 error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
565 if (error) {
566 dev_err(&pdev->dev, "unsupported interface type\n");
567 goto err1;
568 }
569
570 switch (pdata->ch[i].chan) {
571 case LCDC_CHAN_MAINLCD:
572 priv->ch[j].enabled = 1 << 1;
573 priv->ch[j].reg_offs = lcdc_offs_mainlcd;
574 j++;
575 break;
576 case LCDC_CHAN_SUBLCD:
577 priv->ch[j].enabled = 1 << 2;
578 priv->ch[j].reg_offs = lcdc_offs_sublcd;
579 j++;
580 break;
581 }
582 }
583
584 if (!j) {
585 dev_err(&pdev->dev, "no channels defined\n");
586 error = -EINVAL;
587 goto err1;
588 }
589
590 error = sh_mobile_lcdc_setup_clocks(&pdev->dev,
591 pdata->clock_source, priv);
592 if (error) {
593 dev_err(&pdev->dev, "unable to setup clocks\n");
594 goto err1;
595 }
596
597 priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
598
599 for (i = 0; i < j; i++) {
600 info = &priv->ch[i].info;
601 cfg = &priv->ch[i].cfg;
602
603 info->fbops = &sh_mobile_lcdc_ops;
604 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
605 info->var.yres = info->var.yres_virtual = cfg->lcd_cfg.yres;
606 info->var.width = cfg->lcd_size_cfg.width;
607 info->var.height = cfg->lcd_size_cfg.height;
608 info->var.activate = FB_ACTIVATE_NOW;
609 error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
610 if (error)
611 break;
612
613 info->fix = sh_mobile_lcdc_fix;
614 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
615 info->fix.smem_len = info->fix.line_length * cfg->lcd_cfg.yres;
616
617 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
618 &priv->ch[i].dma_handle, GFP_KERNEL);
619 if (!buf) {
620 dev_err(&pdev->dev, "unable to allocate buffer\n");
621 error = -ENOMEM;
622 break;
623 }
624
625 info->pseudo_palette = &priv->ch[i].pseudo_palette;
626 info->flags = FBINFO_FLAG_DEFAULT;
627
628 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
629 if (error < 0) {
630 dev_err(&pdev->dev, "unable to allocate cmap\n");
631 dma_free_coherent(&pdev->dev, info->fix.smem_len,
632 buf, priv->ch[i].dma_handle);
633 break;
634 }
635
636 memset(buf, 0, info->fix.smem_len);
637 info->fix.smem_start = priv->ch[i].dma_handle;
638 info->screen_base = buf;
639 info->device = &pdev->dev;
640 }
641
642 if (error)
643 goto err1;
644
645 error = sh_mobile_lcdc_start(priv);
646 if (error) {
647 dev_err(&pdev->dev, "unable to start hardware\n");
648 goto err1;
649 }
650
651 for (i = 0; i < j; i++) {
652 error = register_framebuffer(&priv->ch[i].info);
653 if (error < 0)
654 goto err1;
655 }
656
657 for (i = 0; i < j; i++) {
658 info = &priv->ch[i].info;
659 dev_info(info->dev,
660 "registered %s/%s as %dx%d %dbpp.\n",
661 pdev->name,
662 (priv->ch[i].cfg.chan == LCDC_CHAN_MAINLCD) ?
663 "mainlcd" : "sublcd",
664 (int) priv->ch[i].cfg.lcd_cfg.xres,
665 (int) priv->ch[i].cfg.lcd_cfg.yres,
666 priv->ch[i].cfg.bpp);
667 }
668
669 return 0;
670 err1:
671 sh_mobile_lcdc_remove(pdev);
672 err0:
673 return error;
674 }
675
676 static int sh_mobile_lcdc_remove(struct platform_device *pdev)
677 {
678 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
679 struct fb_info *info;
680 int i;
681
682 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
683 if (priv->ch[i].info.dev)
684 unregister_framebuffer(&priv->ch[i].info);
685
686 sh_mobile_lcdc_stop(priv);
687
688 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
689 info = &priv->ch[i].info;
690
691 if (!info->device)
692 continue;
693
694 dma_free_coherent(&pdev->dev, info->fix.smem_len,
695 info->screen_base, priv->ch[i].dma_handle);
696 fb_dealloc_cmap(&info->cmap);
697 }
698
699 #ifdef CONFIG_HAVE_CLK
700 if (priv->clk) {
701 clk_disable(priv->clk);
702 clk_put(priv->clk);
703 }
704 #endif
705
706 if (priv->base)
707 iounmap(priv->base);
708
709 kfree(priv);
710 return 0;
711 }
712
713 static struct platform_driver sh_mobile_lcdc_driver = {
714 .driver = {
715 .name = "sh_mobile_lcdc_fb",
716 .owner = THIS_MODULE,
717 },
718 .probe = sh_mobile_lcdc_probe,
719 .remove = sh_mobile_lcdc_remove,
720 };
721
722 static int __init sh_mobile_lcdc_init(void)
723 {
724 return platform_driver_register(&sh_mobile_lcdc_driver);
725 }
726
727 static void __exit sh_mobile_lcdc_exit(void)
728 {
729 platform_driver_unregister(&sh_mobile_lcdc_driver);
730 }
731
732 module_init(sh_mobile_lcdc_init);
733 module_exit(sh_mobile_lcdc_exit);
734
735 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
736 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
737 MODULE_LICENSE("GPL v2");
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