2 * SuperH Mobile LCDC Framebuffer
4 * Copyright (c) 2008 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/delay.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/interrupt.h>
20 #include <video/sh_mobile_lcdc.h>
21 #include <asm/atomic.h>
25 struct sh_mobile_lcdc_priv
;
26 struct sh_mobile_lcdc_chan
{
27 struct sh_mobile_lcdc_priv
*lcdc
;
28 unsigned long *reg_offs
;
29 unsigned long ldmt1r_value
;
30 unsigned long enabled
; /* ME and SE in LDCNT2R */
31 struct sh_mobile_lcdc_chan_cfg cfg
;
32 u32 pseudo_palette
[PALETTE_NR
];
34 dma_addr_t dma_handle
;
35 struct fb_deferred_io defio
;
38 struct sh_mobile_lcdc_priv
{
41 #ifdef CONFIG_HAVE_CLK
47 struct sh_mobile_lcdc_chan ch
[2];
50 /* shared registers */
52 #define _LDDCKSTPR 0x414
55 #define _LDCNT1R 0x470
56 #define _LDCNT2R 0x474
58 #define _LDDWD0R 0x800
63 /* per-channel registers */
64 enum { LDDCKPAT1R
, LDDCKPAT2R
, LDMT1R
, LDMT2R
, LDMT3R
, LDDFR
, LDSM1R
,
65 LDSM2R
, LDSA1R
, LDMLSR
, LDHCNR
, LDHSYNR
, LDVLNR
, LDVSYNR
, LDPMR
};
67 static unsigned long lcdc_offs_mainlcd
[] = {
85 static unsigned long lcdc_offs_sublcd
[] = {
103 #define START_LCDC 0x00000001
104 #define LCDC_RESET 0x00000100
105 #define DISPLAY_BEU 0x00000008
106 #define LCDC_ENABLE 0x00000001
107 #define LDINTR_FE 0x00000400
108 #define LDINTR_FS 0x00000004
110 static void lcdc_write_chan(struct sh_mobile_lcdc_chan
*chan
,
111 int reg_nr
, unsigned long data
)
113 iowrite32(data
, chan
->lcdc
->base
+ chan
->reg_offs
[reg_nr
]);
116 static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan
*chan
,
119 return ioread32(chan
->lcdc
->base
+ chan
->reg_offs
[reg_nr
]);
122 static void lcdc_write(struct sh_mobile_lcdc_priv
*priv
,
123 unsigned long reg_offs
, unsigned long data
)
125 iowrite32(data
, priv
->base
+ reg_offs
);
128 static unsigned long lcdc_read(struct sh_mobile_lcdc_priv
*priv
,
129 unsigned long reg_offs
)
131 return ioread32(priv
->base
+ reg_offs
);
134 static void lcdc_wait_bit(struct sh_mobile_lcdc_priv
*priv
,
135 unsigned long reg_offs
,
136 unsigned long mask
, unsigned long until
)
138 while ((lcdc_read(priv
, reg_offs
) & mask
) != until
)
142 static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan
*chan
)
144 return chan
->cfg
.chan
== LCDC_CHAN_SUBLCD
;
147 static void lcdc_sys_write_index(void *handle
, unsigned long data
)
149 struct sh_mobile_lcdc_chan
*ch
= handle
;
151 lcdc_write(ch
->lcdc
, _LDDWD0R
, data
| 0x10000000);
152 lcdc_wait_bit(ch
->lcdc
, _LDSR
, 2, 0);
153 lcdc_write(ch
->lcdc
, _LDDWAR
, 1 | (lcdc_chan_is_sublcd(ch
) ? 2 : 0));
156 static void lcdc_sys_write_data(void *handle
, unsigned long data
)
158 struct sh_mobile_lcdc_chan
*ch
= handle
;
160 lcdc_write(ch
->lcdc
, _LDDWD0R
, data
| 0x11000000);
161 lcdc_wait_bit(ch
->lcdc
, _LDSR
, 2, 0);
162 lcdc_write(ch
->lcdc
, _LDDWAR
, 1 | (lcdc_chan_is_sublcd(ch
) ? 2 : 0));
165 static unsigned long lcdc_sys_read_data(void *handle
)
167 struct sh_mobile_lcdc_chan
*ch
= handle
;
169 lcdc_write(ch
->lcdc
, _LDDRDR
, 0x01000000);
170 lcdc_wait_bit(ch
->lcdc
, _LDSR
, 2, 0);
171 lcdc_write(ch
->lcdc
, _LDDRAR
, 1 | (lcdc_chan_is_sublcd(ch
) ? 2 : 0));
174 return lcdc_read(ch
->lcdc
, _LDDRDR
) & 0xffff;
177 struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops
= {
178 lcdc_sys_write_index
,
183 #ifdef CONFIG_HAVE_CLK
184 static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv
*priv
)
186 if (atomic_inc_and_test(&priv
->clk_usecnt
)) {
187 clk_enable(priv
->clk
);
189 clk_enable(priv
->dot_clk
);
193 static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv
*priv
)
195 if (atomic_sub_return(1, &priv
->clk_usecnt
) == -1) {
197 clk_disable(priv
->dot_clk
);
198 clk_disable(priv
->clk
);
202 static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv
*priv
) {}
203 static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv
*priv
) {}
206 static void sh_mobile_lcdc_deferred_io(struct fb_info
*info
,
207 struct list_head
*pagelist
)
209 struct sh_mobile_lcdc_chan
*ch
= info
->par
;
211 /* enable clocks before accessing hardware */
212 sh_mobile_lcdc_clk_on(ch
->lcdc
);
214 /* trigger panel update */
215 lcdc_write_chan(ch
, LDSM2R
, 1);
218 static void sh_mobile_lcdc_deferred_io_touch(struct fb_info
*info
)
220 struct fb_deferred_io
*fbdefio
= info
->fbdefio
;
223 schedule_delayed_work(&info
->deferred_work
, fbdefio
->delay
);
226 static irqreturn_t
sh_mobile_lcdc_irq(int irq
, void *data
)
228 struct sh_mobile_lcdc_priv
*priv
= data
;
231 /* acknowledge interrupt */
232 tmp
= lcdc_read(priv
, _LDINTR
);
233 tmp
&= 0xffffff00; /* mask in high 24 bits */
234 tmp
|= 0x000000ff ^ LDINTR_FS
; /* status in low 8 */
235 lcdc_write(priv
, _LDINTR
, tmp
);
238 sh_mobile_lcdc_clk_off(priv
);
242 static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv
*priv
,
245 unsigned long tmp
= lcdc_read(priv
, _LDCNT2R
);
248 /* start or stop the lcdc */
250 lcdc_write(priv
, _LDCNT2R
, tmp
| START_LCDC
);
252 lcdc_write(priv
, _LDCNT2R
, tmp
& ~START_LCDC
);
254 /* wait until power is applied/stopped on all channels */
255 for (k
= 0; k
< ARRAY_SIZE(priv
->ch
); k
++)
256 if (lcdc_read(priv
, _LDCNT2R
) & priv
->ch
[k
].enabled
)
258 tmp
= lcdc_read_chan(&priv
->ch
[k
], LDPMR
) & 3;
259 if (start
&& tmp
== 3)
261 if (!start
&& tmp
== 0)
267 lcdc_write(priv
, _LDDCKSTPR
, 1); /* stop dotclock */
270 static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv
*priv
)
272 struct sh_mobile_lcdc_chan
*ch
;
273 struct fb_videomode
*lcd_cfg
;
274 struct sh_mobile_lcdc_board_cfg
*board_cfg
;
279 /* enable clocks before accessing the hardware */
280 for (k
= 0; k
< ARRAY_SIZE(priv
->ch
); k
++)
281 if (priv
->ch
[k
].enabled
)
282 sh_mobile_lcdc_clk_on(priv
);
285 lcdc_write(priv
, _LDCNT2R
, lcdc_read(priv
, _LDCNT2R
) | LCDC_RESET
);
286 lcdc_wait_bit(priv
, _LDCNT2R
, LCDC_RESET
, 0);
288 /* enable LCDC channels */
289 tmp
= lcdc_read(priv
, _LDCNT2R
);
290 tmp
|= priv
->ch
[0].enabled
;
291 tmp
|= priv
->ch
[1].enabled
;
292 lcdc_write(priv
, _LDCNT2R
, tmp
);
294 /* read data from external memory, avoid using the BEU for now */
295 lcdc_write(priv
, _LDCNT2R
, lcdc_read(priv
, _LDCNT2R
) & ~DISPLAY_BEU
);
297 /* stop the lcdc first */
298 sh_mobile_lcdc_start_stop(priv
, 0);
300 /* configure clocks */
302 for (k
= 0; k
< ARRAY_SIZE(priv
->ch
); k
++) {
305 if (!priv
->ch
[k
].enabled
)
308 m
= ch
->cfg
.clock_divider
;
314 tmp
|= m
<< (lcdc_chan_is_sublcd(ch
) ? 8 : 0);
316 lcdc_write_chan(ch
, LDDCKPAT1R
, 0x00000000);
317 lcdc_write_chan(ch
, LDDCKPAT2R
, (1 << (m
/2)) - 1);
320 lcdc_write(priv
, _LDDCKR
, tmp
);
322 /* start dotclock again */
323 lcdc_write(priv
, _LDDCKSTPR
, 0);
324 lcdc_wait_bit(priv
, _LDDCKSTPR
, ~0, 0);
326 /* interrupts are disabled to begin with */
327 lcdc_write(priv
, _LDINTR
, 0);
329 for (k
= 0; k
< ARRAY_SIZE(priv
->ch
); k
++) {
331 lcd_cfg
= &ch
->cfg
.lcd_cfg
;
336 tmp
= ch
->ldmt1r_value
;
337 tmp
|= (lcd_cfg
->sync
& FB_SYNC_VERT_HIGH_ACT
) ? 0 : 1 << 28;
338 tmp
|= (lcd_cfg
->sync
& FB_SYNC_HOR_HIGH_ACT
) ? 0 : 1 << 27;
339 tmp
|= (ch
->cfg
.flags
& LCDC_FLAGS_DWPOL
) ? 1 << 26 : 0;
340 tmp
|= (ch
->cfg
.flags
& LCDC_FLAGS_DIPOL
) ? 1 << 25 : 0;
341 tmp
|= (ch
->cfg
.flags
& LCDC_FLAGS_DAPOL
) ? 1 << 24 : 0;
342 tmp
|= (ch
->cfg
.flags
& LCDC_FLAGS_HSCNT
) ? 1 << 17 : 0;
343 tmp
|= (ch
->cfg
.flags
& LCDC_FLAGS_DWCNT
) ? 1 << 16 : 0;
344 lcdc_write_chan(ch
, LDMT1R
, tmp
);
347 lcdc_write_chan(ch
, LDMT2R
, ch
->cfg
.sys_bus_cfg
.ldmt2r
);
348 lcdc_write_chan(ch
, LDMT3R
, ch
->cfg
.sys_bus_cfg
.ldmt3r
);
350 /* horizontal configuration */
351 tmp
= lcd_cfg
->xres
+ lcd_cfg
->hsync_len
;
352 tmp
+= lcd_cfg
->left_margin
;
353 tmp
+= lcd_cfg
->right_margin
;
355 tmp
|= (lcd_cfg
->xres
/ 8) << 16; /* HDCN */
356 lcdc_write_chan(ch
, LDHCNR
, tmp
);
359 tmp
+= lcd_cfg
->right_margin
;
360 tmp
/= 8; /* HSYNP */
361 tmp
|= (lcd_cfg
->hsync_len
/ 8) << 16; /* HSYNW */
362 lcdc_write_chan(ch
, LDHSYNR
, tmp
);
365 lcdc_write_chan(ch
, LDPMR
, 0);
367 /* vertical configuration */
368 tmp
= lcd_cfg
->yres
+ lcd_cfg
->vsync_len
;
369 tmp
+= lcd_cfg
->upper_margin
;
370 tmp
+= lcd_cfg
->lower_margin
; /* VTLN */
371 tmp
|= lcd_cfg
->yres
<< 16; /* VDLN */
372 lcdc_write_chan(ch
, LDVLNR
, tmp
);
375 tmp
+= lcd_cfg
->lower_margin
; /* VSYNP */
376 tmp
|= lcd_cfg
->vsync_len
<< 16; /* VSYNW */
377 lcdc_write_chan(ch
, LDVSYNR
, tmp
);
379 board_cfg
= &ch
->cfg
.board_cfg
;
380 if (board_cfg
->setup_sys
)
381 ret
= board_cfg
->setup_sys(board_cfg
->board_data
, ch
,
382 &sh_mobile_lcdc_sys_bus_ops
);
387 /* word and long word swap */
388 lcdc_write(priv
, _LDDDSR
, lcdc_read(priv
, _LDDDSR
) | 6);
390 for (k
= 0; k
< ARRAY_SIZE(priv
->ch
); k
++) {
393 if (!priv
->ch
[k
].enabled
)
396 /* set bpp format in PKF[4:0] */
397 tmp
= lcdc_read_chan(ch
, LDDFR
);
398 tmp
&= ~(0x0001001f);
399 tmp
|= (priv
->ch
[k
].info
.var
.bits_per_pixel
== 16) ? 3 : 0;
400 lcdc_write_chan(ch
, LDDFR
, tmp
);
402 /* point out our frame buffer */
403 lcdc_write_chan(ch
, LDSA1R
, ch
->info
.fix
.smem_start
);
406 lcdc_write_chan(ch
, LDMLSR
, ch
->info
.fix
.line_length
);
408 /* setup deferred io if SYS bus */
409 tmp
= ch
->cfg
.sys_bus_cfg
.deferred_io_msec
;
410 if (ch
->ldmt1r_value
& (1 << 12) && tmp
) {
411 ch
->defio
.deferred_io
= sh_mobile_lcdc_deferred_io
;
412 ch
->defio
.delay
= msecs_to_jiffies(tmp
);
413 ch
->info
.fbdefio
= &ch
->defio
;
414 fb_deferred_io_init(&ch
->info
);
417 lcdc_write_chan(ch
, LDSM1R
, 1);
419 /* enable "Frame End Interrupt Enable" bit */
420 lcdc_write(priv
, _LDINTR
, LDINTR_FE
);
423 /* continuous read mode */
424 lcdc_write_chan(ch
, LDSM1R
, 0);
429 lcdc_write(priv
, _LDCNT1R
, LCDC_ENABLE
);
432 sh_mobile_lcdc_start_stop(priv
, 1);
434 /* tell the board code to enable the panel */
435 for (k
= 0; k
< ARRAY_SIZE(priv
->ch
); k
++) {
437 board_cfg
= &ch
->cfg
.board_cfg
;
438 if (board_cfg
->display_on
)
439 board_cfg
->display_on(board_cfg
->board_data
);
445 static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv
*priv
)
447 struct sh_mobile_lcdc_chan
*ch
;
448 struct sh_mobile_lcdc_board_cfg
*board_cfg
;
452 /* tell the board code to disable the panel */
453 for (k
= 0; k
< ARRAY_SIZE(priv
->ch
); k
++) {
455 board_cfg
= &ch
->cfg
.board_cfg
;
456 if (board_cfg
->display_off
)
457 board_cfg
->display_off(board_cfg
->board_data
);
459 /* cleanup deferred io if SYS bus */
460 tmp
= ch
->cfg
.sys_bus_cfg
.deferred_io_msec
;
461 if (ch
->ldmt1r_value
& (1 << 12) && tmp
) {
462 fb_deferred_io_cleanup(&ch
->info
);
463 ch
->info
.fbdefio
= NULL
;
468 sh_mobile_lcdc_start_stop(priv
, 0);
471 for (k
= 0; k
< ARRAY_SIZE(priv
->ch
); k
++)
472 if (priv
->ch
[k
].enabled
)
473 sh_mobile_lcdc_clk_off(priv
);
476 static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan
*ch
)
480 switch (ch
->cfg
.interface_type
) {
481 case RGB8
: ifm
= 0; miftyp
= 0; break;
482 case RGB9
: ifm
= 0; miftyp
= 4; break;
483 case RGB12A
: ifm
= 0; miftyp
= 5; break;
484 case RGB12B
: ifm
= 0; miftyp
= 6; break;
485 case RGB16
: ifm
= 0; miftyp
= 7; break;
486 case RGB18
: ifm
= 0; miftyp
= 10; break;
487 case RGB24
: ifm
= 0; miftyp
= 11; break;
488 case SYS8A
: ifm
= 1; miftyp
= 0; break;
489 case SYS8B
: ifm
= 1; miftyp
= 1; break;
490 case SYS8C
: ifm
= 1; miftyp
= 2; break;
491 case SYS8D
: ifm
= 1; miftyp
= 3; break;
492 case SYS9
: ifm
= 1; miftyp
= 4; break;
493 case SYS12
: ifm
= 1; miftyp
= 5; break;
494 case SYS16A
: ifm
= 1; miftyp
= 7; break;
495 case SYS16B
: ifm
= 1; miftyp
= 8; break;
496 case SYS16C
: ifm
= 1; miftyp
= 9; break;
497 case SYS18
: ifm
= 1; miftyp
= 10; break;
498 case SYS24
: ifm
= 1; miftyp
= 11; break;
502 /* SUBLCD only supports SYS interface */
503 if (lcdc_chan_is_sublcd(ch
)) {
510 ch
->ldmt1r_value
= (ifm
<< 12) | miftyp
;
516 static int sh_mobile_lcdc_setup_clocks(struct platform_device
*pdev
,
518 struct sh_mobile_lcdc_priv
*priv
)
520 #ifdef CONFIG_HAVE_CLK
526 switch (clock_source
) {
527 case LCDC_CLK_BUS
: str
= "bus_clk"; icksel
= 0; break;
528 case LCDC_CLK_PERIPHERAL
: str
= "peripheral_clk"; icksel
= 1; break;
529 case LCDC_CLK_EXTERNAL
: str
= NULL
; icksel
= 2; break;
534 priv
->lddckr
= icksel
<< 16;
536 #ifdef CONFIG_HAVE_CLK
537 atomic_set(&priv
->clk_usecnt
, -1);
538 snprintf(clk_name
, sizeof(clk_name
), "lcdc%d", pdev
->id
);
539 priv
->clk
= clk_get(&pdev
->dev
, clk_name
);
540 if (IS_ERR(priv
->clk
)) {
541 dev_err(&pdev
->dev
, "cannot get clock \"%s\"\n", clk_name
);
542 return PTR_ERR(priv
->clk
);
546 priv
->dot_clk
= clk_get(&pdev
->dev
, str
);
547 if (IS_ERR(priv
->dot_clk
)) {
548 dev_err(&pdev
->dev
, "cannot get dot clock %s\n", str
);
550 return PTR_ERR(priv
->dot_clk
);
558 static int sh_mobile_lcdc_setcolreg(u_int regno
,
559 u_int red
, u_int green
, u_int blue
,
560 u_int transp
, struct fb_info
*info
)
562 u32
*palette
= info
->pseudo_palette
;
564 if (regno
>= PALETTE_NR
)
567 /* only FB_VISUAL_TRUECOLOR supported */
569 red
>>= 16 - info
->var
.red
.length
;
570 green
>>= 16 - info
->var
.green
.length
;
571 blue
>>= 16 - info
->var
.blue
.length
;
572 transp
>>= 16 - info
->var
.transp
.length
;
574 palette
[regno
] = (red
<< info
->var
.red
.offset
) |
575 (green
<< info
->var
.green
.offset
) |
576 (blue
<< info
->var
.blue
.offset
) |
577 (transp
<< info
->var
.transp
.offset
);
582 static struct fb_fix_screeninfo sh_mobile_lcdc_fix
= {
583 .id
= "SH Mobile LCDC",
584 .type
= FB_TYPE_PACKED_PIXELS
,
585 .visual
= FB_VISUAL_TRUECOLOR
,
586 .accel
= FB_ACCEL_NONE
,
589 static void sh_mobile_lcdc_fillrect(struct fb_info
*info
,
590 const struct fb_fillrect
*rect
)
592 sys_fillrect(info
, rect
);
593 sh_mobile_lcdc_deferred_io_touch(info
);
596 static void sh_mobile_lcdc_copyarea(struct fb_info
*info
,
597 const struct fb_copyarea
*area
)
599 sys_copyarea(info
, area
);
600 sh_mobile_lcdc_deferred_io_touch(info
);
603 static void sh_mobile_lcdc_imageblit(struct fb_info
*info
,
604 const struct fb_image
*image
)
606 sys_imageblit(info
, image
);
607 sh_mobile_lcdc_deferred_io_touch(info
);
610 static struct fb_ops sh_mobile_lcdc_ops
= {
611 .fb_setcolreg
= sh_mobile_lcdc_setcolreg
,
612 .fb_read
= fb_sys_read
,
613 .fb_write
= fb_sys_write
,
614 .fb_fillrect
= sh_mobile_lcdc_fillrect
,
615 .fb_copyarea
= sh_mobile_lcdc_copyarea
,
616 .fb_imageblit
= sh_mobile_lcdc_imageblit
,
619 static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo
*var
, int bpp
)
622 case 16: /* PKF[4:0] = 00011 - RGB 565 */
623 var
->red
.offset
= 11;
625 var
->green
.offset
= 5;
626 var
->green
.length
= 6;
627 var
->blue
.offset
= 0;
628 var
->blue
.length
= 5;
629 var
->transp
.offset
= 0;
630 var
->transp
.length
= 0;
633 case 32: /* PKF[4:0] = 00000 - RGB 888
634 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
635 * this may be because LDDDSR has word swap enabled..
639 var
->green
.offset
= 24;
640 var
->green
.length
= 8;
641 var
->blue
.offset
= 16;
642 var
->blue
.length
= 8;
643 var
->transp
.offset
= 0;
644 var
->transp
.length
= 0;
649 var
->bits_per_pixel
= bpp
;
650 var
->red
.msb_right
= 0;
651 var
->green
.msb_right
= 0;
652 var
->blue
.msb_right
= 0;
653 var
->transp
.msb_right
= 0;
657 static int sh_mobile_lcdc_remove(struct platform_device
*pdev
);
659 static int __init
sh_mobile_lcdc_probe(struct platform_device
*pdev
)
661 struct fb_info
*info
;
662 struct sh_mobile_lcdc_priv
*priv
;
663 struct sh_mobile_lcdc_info
*pdata
;
664 struct sh_mobile_lcdc_chan_cfg
*cfg
;
665 struct resource
*res
;
670 if (!pdev
->dev
.platform_data
) {
671 dev_err(&pdev
->dev
, "no platform data defined\n");
676 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
677 i
= platform_get_irq(pdev
, 0);
679 dev_err(&pdev
->dev
, "cannot get platform resources\n");
684 priv
= kzalloc(sizeof(*priv
), GFP_KERNEL
);
686 dev_err(&pdev
->dev
, "cannot allocate device data\n");
691 error
= request_irq(i
, sh_mobile_lcdc_irq
, IRQF_DISABLED
,
692 pdev
->dev
.bus_id
, priv
);
694 dev_err(&pdev
->dev
, "unable to request irq\n");
699 platform_set_drvdata(pdev
, priv
);
700 pdata
= pdev
->dev
.platform_data
;
703 for (i
= 0; i
< ARRAY_SIZE(pdata
->ch
); i
++) {
704 priv
->ch
[j
].lcdc
= priv
;
705 memcpy(&priv
->ch
[j
].cfg
, &pdata
->ch
[i
], sizeof(pdata
->ch
[i
]));
707 error
= sh_mobile_lcdc_check_interface(&priv
->ch
[i
]);
709 dev_err(&pdev
->dev
, "unsupported interface type\n");
713 switch (pdata
->ch
[i
].chan
) {
714 case LCDC_CHAN_MAINLCD
:
715 priv
->ch
[j
].enabled
= 1 << 1;
716 priv
->ch
[j
].reg_offs
= lcdc_offs_mainlcd
;
719 case LCDC_CHAN_SUBLCD
:
720 priv
->ch
[j
].enabled
= 1 << 2;
721 priv
->ch
[j
].reg_offs
= lcdc_offs_sublcd
;
728 dev_err(&pdev
->dev
, "no channels defined\n");
733 error
= sh_mobile_lcdc_setup_clocks(pdev
, pdata
->clock_source
, priv
);
735 dev_err(&pdev
->dev
, "unable to setup clocks\n");
739 priv
->base
= ioremap_nocache(res
->start
, (res
->end
- res
->start
) + 1);
741 for (i
= 0; i
< j
; i
++) {
742 info
= &priv
->ch
[i
].info
;
743 cfg
= &priv
->ch
[i
].cfg
;
745 info
->fbops
= &sh_mobile_lcdc_ops
;
746 info
->var
.xres
= info
->var
.xres_virtual
= cfg
->lcd_cfg
.xres
;
747 info
->var
.yres
= info
->var
.yres_virtual
= cfg
->lcd_cfg
.yres
;
748 info
->var
.width
= cfg
->lcd_size_cfg
.width
;
749 info
->var
.height
= cfg
->lcd_size_cfg
.height
;
750 info
->var
.activate
= FB_ACTIVATE_NOW
;
751 error
= sh_mobile_lcdc_set_bpp(&info
->var
, cfg
->bpp
);
755 info
->fix
= sh_mobile_lcdc_fix
;
756 info
->fix
.line_length
= cfg
->lcd_cfg
.xres
* (cfg
->bpp
/ 8);
757 info
->fix
.smem_len
= info
->fix
.line_length
* cfg
->lcd_cfg
.yres
;
759 buf
= dma_alloc_coherent(&pdev
->dev
, info
->fix
.smem_len
,
760 &priv
->ch
[i
].dma_handle
, GFP_KERNEL
);
762 dev_err(&pdev
->dev
, "unable to allocate buffer\n");
767 info
->pseudo_palette
= &priv
->ch
[i
].pseudo_palette
;
768 info
->flags
= FBINFO_FLAG_DEFAULT
;
770 error
= fb_alloc_cmap(&info
->cmap
, PALETTE_NR
, 0);
772 dev_err(&pdev
->dev
, "unable to allocate cmap\n");
773 dma_free_coherent(&pdev
->dev
, info
->fix
.smem_len
,
774 buf
, priv
->ch
[i
].dma_handle
);
778 memset(buf
, 0, info
->fix
.smem_len
);
779 info
->fix
.smem_start
= priv
->ch
[i
].dma_handle
;
780 info
->screen_base
= buf
;
781 info
->device
= &pdev
->dev
;
782 info
->par
= &priv
->ch
[i
];
788 error
= sh_mobile_lcdc_start(priv
);
790 dev_err(&pdev
->dev
, "unable to start hardware\n");
794 for (i
= 0; i
< j
; i
++) {
795 error
= register_framebuffer(&priv
->ch
[i
].info
);
800 for (i
= 0; i
< j
; i
++) {
801 info
= &priv
->ch
[i
].info
;
803 "registered %s/%s as %dx%d %dbpp.\n",
805 (priv
->ch
[i
].cfg
.chan
== LCDC_CHAN_MAINLCD
) ?
806 "mainlcd" : "sublcd",
807 (int) priv
->ch
[i
].cfg
.lcd_cfg
.xres
,
808 (int) priv
->ch
[i
].cfg
.lcd_cfg
.yres
,
809 priv
->ch
[i
].cfg
.bpp
);
811 /* deferred io mode: disable clock to save power */
813 sh_mobile_lcdc_clk_off(priv
);
818 sh_mobile_lcdc_remove(pdev
);
823 static int sh_mobile_lcdc_remove(struct platform_device
*pdev
)
825 struct sh_mobile_lcdc_priv
*priv
= platform_get_drvdata(pdev
);
826 struct fb_info
*info
;
829 for (i
= 0; i
< ARRAY_SIZE(priv
->ch
); i
++)
830 if (priv
->ch
[i
].info
.dev
)
831 unregister_framebuffer(&priv
->ch
[i
].info
);
833 sh_mobile_lcdc_stop(priv
);
835 for (i
= 0; i
< ARRAY_SIZE(priv
->ch
); i
++) {
836 info
= &priv
->ch
[i
].info
;
841 dma_free_coherent(&pdev
->dev
, info
->fix
.smem_len
,
842 info
->screen_base
, priv
->ch
[i
].dma_handle
);
843 fb_dealloc_cmap(&info
->cmap
);
846 #ifdef CONFIG_HAVE_CLK
848 clk_put(priv
->dot_clk
);
856 free_irq(priv
->irq
, priv
);
861 static struct platform_driver sh_mobile_lcdc_driver
= {
863 .name
= "sh_mobile_lcdc_fb",
864 .owner
= THIS_MODULE
,
866 .probe
= sh_mobile_lcdc_probe
,
867 .remove
= sh_mobile_lcdc_remove
,
870 static int __init
sh_mobile_lcdc_init(void)
872 return platform_driver_register(&sh_mobile_lcdc_driver
);
875 static void __exit
sh_mobile_lcdc_exit(void)
877 platform_driver_unregister(&sh_mobile_lcdc_driver
);
880 module_init(sh_mobile_lcdc_init
);
881 module_exit(sh_mobile_lcdc_exit
);
883 MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
884 MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
885 MODULE_LICENSE("GPL v2");