2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
16 #include <asm/processor.h>
17 #include <asm/tlbflush.h>
18 #include <asm/sections.h>
19 #include <asm/uaccess.h>
20 #include <asm/pgalloc.h>
21 #include <asm/proto.h>
25 * The current flushing context - we pass it instead of 5 arguments:
34 unsigned force_split
: 1;
39 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
40 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
41 * entries change the page attribute in parallel to some other cpu
42 * splitting a large page entry along with changing the attribute.
44 static DEFINE_SPINLOCK(cpa_lock
);
46 #define CPA_FLUSHTLB 1
50 static unsigned long direct_pages_count
[PG_LEVEL_NUM
];
52 void update_page_count(int level
, unsigned long pages
)
56 /* Protect against CPA */
57 spin_lock_irqsave(&pgd_lock
, flags
);
58 direct_pages_count
[level
] += pages
;
59 spin_unlock_irqrestore(&pgd_lock
, flags
);
62 static void split_page_count(int level
)
64 direct_pages_count
[level
]--;
65 direct_pages_count
[level
- 1] += PTRS_PER_PTE
;
68 void arch_report_meminfo(struct seq_file
*m
)
70 seq_printf(m
, "DirectMap4k: %8lu kB\n",
71 direct_pages_count
[PG_LEVEL_4K
] << 2);
72 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
73 seq_printf(m
, "DirectMap2M: %8lu kB\n",
74 direct_pages_count
[PG_LEVEL_2M
] << 11);
76 seq_printf(m
, "DirectMap4M: %8lu kB\n",
77 direct_pages_count
[PG_LEVEL_2M
] << 12);
81 seq_printf(m
, "DirectMap1G: %8lu kB\n",
82 direct_pages_count
[PG_LEVEL_1G
] << 20);
86 static inline void split_page_count(int level
) { }
91 static inline unsigned long highmap_start_pfn(void)
93 return __pa(_text
) >> PAGE_SHIFT
;
96 static inline unsigned long highmap_end_pfn(void)
98 return __pa(roundup((unsigned long)_end
, PMD_SIZE
)) >> PAGE_SHIFT
;
103 #ifdef CONFIG_DEBUG_PAGEALLOC
104 # define debug_pagealloc 1
106 # define debug_pagealloc 0
110 within(unsigned long addr
, unsigned long start
, unsigned long end
)
112 return addr
>= start
&& addr
< end
;
120 * clflush_cache_range - flush a cache range with clflush
121 * @addr: virtual start address
122 * @size: number of bytes to flush
124 * clflush is an unordered instruction which needs fencing with mfence
125 * to avoid ordering issues.
127 void clflush_cache_range(void *vaddr
, unsigned int size
)
129 void *vend
= vaddr
+ size
- 1;
133 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
136 * Flush any possible final partial cacheline:
143 static void __cpa_flush_all(void *arg
)
145 unsigned long cache
= (unsigned long)arg
;
148 * Flush all to work around Errata in early athlons regarding
149 * large page flushing.
153 if (cache
&& boot_cpu_data
.x86_model
>= 4)
157 static void cpa_flush_all(unsigned long cache
)
159 BUG_ON(irqs_disabled());
161 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1);
164 static void __cpa_flush_range(void *arg
)
167 * We could optimize that further and do individual per page
168 * tlb invalidates for a low number of pages. Caveat: we must
169 * flush the high aliases on 64bit as well.
174 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
176 unsigned int i
, level
;
179 BUG_ON(irqs_disabled());
180 WARN_ON(PAGE_ALIGN(start
) != start
);
182 on_each_cpu(__cpa_flush_range
, NULL
, 1);
188 * We only need to flush on one CPU,
189 * clflush is a MESI-coherent instruction that
190 * will cause all other CPUs to flush the same
193 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
194 pte_t
*pte
= lookup_address(addr
, &level
);
197 * Only flush present addresses:
199 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
200 clflush_cache_range((void *) addr
, PAGE_SIZE
);
204 static void cpa_flush_array(unsigned long *start
, int numpages
, int cache
)
206 unsigned int i
, level
;
209 BUG_ON(irqs_disabled());
211 on_each_cpu(__cpa_flush_range
, NULL
, 1);
217 if (numpages
>= 1024) {
218 if (boot_cpu_data
.x86_model
>= 4)
223 * We only need to flush on one CPU,
224 * clflush is a MESI-coherent instruction that
225 * will cause all other CPUs to flush the same
228 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
++) {
229 pte_t
*pte
= lookup_address(*addr
, &level
);
232 * Only flush present addresses:
234 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
235 clflush_cache_range((void *) *addr
, PAGE_SIZE
);
240 * Certain areas of memory on x86 require very specific protection flags,
241 * for example the BIOS area or kernel text. Callers don't always get this
242 * right (again, ioremap() on BIOS memory is not uncommon) so this function
243 * checks and fixes these known static required protection bits.
245 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
,
248 pgprot_t forbidden
= __pgprot(0);
251 * The BIOS area between 640k and 1Mb needs to be executable for
252 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
254 if (within(pfn
, BIOS_BEGIN
>> PAGE_SHIFT
, BIOS_END
>> PAGE_SHIFT
))
255 pgprot_val(forbidden
) |= _PAGE_NX
;
258 * The kernel text needs to be executable for obvious reasons
259 * Does not cover __inittext since that is gone later on. On
260 * 64bit we do not enforce !NX on the low mapping
262 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
263 pgprot_val(forbidden
) |= _PAGE_NX
;
266 * The .rodata section needs to be read-only. Using the pfn
267 * catches all aliases.
269 if (within(pfn
, __pa((unsigned long)__start_rodata
) >> PAGE_SHIFT
,
270 __pa((unsigned long)__end_rodata
) >> PAGE_SHIFT
))
271 pgprot_val(forbidden
) |= _PAGE_RW
;
273 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
279 * Lookup the page table entry for a virtual address. Return a pointer
280 * to the entry and the level of the mapping.
282 * Note: We return pud and pmd either when the entry is marked large
283 * or when the present bit is not set. Otherwise we would return a
284 * pointer to a nonexisting mapping.
286 pte_t
*lookup_address(unsigned long address
, unsigned int *level
)
288 pgd_t
*pgd
= pgd_offset_k(address
);
292 *level
= PG_LEVEL_NONE
;
297 pud
= pud_offset(pgd
, address
);
301 *level
= PG_LEVEL_1G
;
302 if (pud_large(*pud
) || !pud_present(*pud
))
305 pmd
= pmd_offset(pud
, address
);
309 *level
= PG_LEVEL_2M
;
310 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
313 *level
= PG_LEVEL_4K
;
315 return pte_offset_kernel(pmd
, address
);
317 EXPORT_SYMBOL_GPL(lookup_address
);
320 * Set the new pmd in all the pgds we know about:
322 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
325 set_pte_atomic(kpte
, pte
);
327 if (!SHARED_KERNEL_PMD
) {
330 list_for_each_entry(page
, &pgd_list
, lru
) {
335 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
336 pud
= pud_offset(pgd
, address
);
337 pmd
= pmd_offset(pud
, address
);
338 set_pte_atomic((pte_t
*)pmd
, pte
);
345 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
346 struct cpa_data
*cpa
)
348 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
, addr
, pfn
;
349 pte_t new_pte
, old_pte
, *tmp
;
350 pgprot_t old_prot
, new_prot
;
354 if (cpa
->force_split
)
357 spin_lock_irqsave(&pgd_lock
, flags
);
359 * Check for races, another CPU might have split this page
362 tmp
= lookup_address(address
, &level
);
368 psize
= PMD_PAGE_SIZE
;
369 pmask
= PMD_PAGE_MASK
;
373 psize
= PUD_PAGE_SIZE
;
374 pmask
= PUD_PAGE_MASK
;
383 * Calculate the number of pages, which fit into this large
384 * page starting at address:
386 nextpage_addr
= (address
+ psize
) & pmask
;
387 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
388 if (numpages
< cpa
->numpages
)
389 cpa
->numpages
= numpages
;
392 * We are safe now. Check whether the new pgprot is the same:
395 old_prot
= new_prot
= pte_pgprot(old_pte
);
397 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
398 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
401 * old_pte points to the large page base address. So we need
402 * to add the offset of the virtual address:
404 pfn
= pte_pfn(old_pte
) + ((address
& (psize
- 1)) >> PAGE_SHIFT
);
407 new_prot
= static_protections(new_prot
, address
, pfn
);
410 * We need to check the full range, whether
411 * static_protection() requires a different pgprot for one of
412 * the pages in the range we try to preserve:
414 addr
= address
+ PAGE_SIZE
;
416 for (i
= 1; i
< cpa
->numpages
; i
++, addr
+= PAGE_SIZE
, pfn
++) {
417 pgprot_t chk_prot
= static_protections(new_prot
, addr
, pfn
);
419 if (pgprot_val(chk_prot
) != pgprot_val(new_prot
))
424 * If there are no changes, return. maxpages has been updated
427 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
433 * We need to change the attributes. Check, whether we can
434 * change the large page in one go. We request a split, when
435 * the address is not aligned and the number of pages is
436 * smaller than the number of pages in the large page. Note
437 * that we limited the number of possible pages already to
438 * the number of pages in the large page.
440 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
442 * The address is aligned and the number of pages
443 * covers the full page.
445 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
446 __set_pmd_pte(kpte
, address
, new_pte
);
447 cpa
->flags
|= CPA_FLUSHTLB
;
452 spin_unlock_irqrestore(&pgd_lock
, flags
);
457 static int split_large_page(pte_t
*kpte
, unsigned long address
)
459 unsigned long flags
, pfn
, pfninc
= 1;
460 unsigned int i
, level
;
465 if (!debug_pagealloc
)
466 spin_unlock(&cpa_lock
);
467 base
= alloc_pages(GFP_KERNEL
, 0);
468 if (!debug_pagealloc
)
469 spin_lock(&cpa_lock
);
473 spin_lock_irqsave(&pgd_lock
, flags
);
475 * Check for races, another CPU might have split this page
478 tmp
= lookup_address(address
, &level
);
482 pbase
= (pte_t
*)page_address(base
);
483 paravirt_alloc_pte(&init_mm
, page_to_pfn(base
));
484 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
486 * If we ever want to utilize the PAT bit, we need to
487 * update this function to make sure it's converted from
488 * bit 12 to bit 7 when we cross from the 2MB level to
491 WARN_ON_ONCE(pgprot_val(ref_prot
) & _PAGE_PAT_LARGE
);
494 if (level
== PG_LEVEL_1G
) {
495 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
496 pgprot_val(ref_prot
) |= _PAGE_PSE
;
501 * Get the target pfn from the original entry:
503 pfn
= pte_pfn(*kpte
);
504 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
505 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
507 if (address
>= (unsigned long)__va(0) &&
508 address
< (unsigned long)__va(max_low_pfn_mapped
<< PAGE_SHIFT
))
509 split_page_count(level
);
512 if (address
>= (unsigned long)__va(1UL<<32) &&
513 address
< (unsigned long)__va(max_pfn_mapped
<< PAGE_SHIFT
))
514 split_page_count(level
);
518 * Install the new, split up pagetable.
520 * We use the standard kernel pagetable protections for the new
521 * pagetable protections, the actual ptes set above control the
522 * primary protection behavior:
524 __set_pmd_pte(kpte
, address
, mk_pte(base
, __pgprot(_KERNPG_TABLE
)));
527 * Intel Atom errata AAH41 workaround.
529 * The real fix should be in hw or in a microcode update, but
530 * we also probabilistically try to reduce the window of having
531 * a large TLB mixed with 4K TLBs while instruction fetches are
540 * If we dropped out via the lookup_address check under
541 * pgd_lock then stick the page back into the pool:
545 spin_unlock_irqrestore(&pgd_lock
, flags
);
550 static int __cpa_process_fault(struct cpa_data
*cpa
, unsigned long vaddr
,
554 * Ignore all non primary paths.
560 * Ignore the NULL PTE for kernel identity mapping, as it is expected
562 * Also set numpages to '1' indicating that we processed cpa req for
563 * one virtual address page and its pfn. TBD: numpages can be set based
564 * on the initial value and the level returned by lookup_address().
566 if (within(vaddr
, PAGE_OFFSET
,
567 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
))) {
569 cpa
->pfn
= __pa(vaddr
) >> PAGE_SHIFT
;
572 WARN(1, KERN_WARNING
"CPA: called for zero pte. "
573 "vaddr = %lx cpa->vaddr = %lx\n", vaddr
,
580 static int __change_page_attr(struct cpa_data
*cpa
, int primary
)
582 unsigned long address
;
585 pte_t
*kpte
, old_pte
;
587 if (cpa
->flags
& CPA_ARRAY
)
588 address
= cpa
->vaddr
[cpa
->curpage
];
590 address
= *cpa
->vaddr
;
592 kpte
= lookup_address(address
, &level
);
594 return __cpa_process_fault(cpa
, address
, primary
);
597 if (!pte_val(old_pte
))
598 return __cpa_process_fault(cpa
, address
, primary
);
600 if (level
== PG_LEVEL_4K
) {
602 pgprot_t new_prot
= pte_pgprot(old_pte
);
603 unsigned long pfn
= pte_pfn(old_pte
);
605 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
606 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
608 new_prot
= static_protections(new_prot
, address
, pfn
);
611 * We need to keep the pfn from the existing PTE,
612 * after all we're only going to change it's attributes
613 * not the memory it points to
615 new_pte
= pfn_pte(pfn
, canon_pgprot(new_prot
));
618 * Do we really change anything ?
620 if (pte_val(old_pte
) != pte_val(new_pte
)) {
621 set_pte_atomic(kpte
, new_pte
);
622 cpa
->flags
|= CPA_FLUSHTLB
;
629 * Check, whether we can keep the large page intact
630 * and just change the pte:
632 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
634 * When the range fits into the existing large page,
635 * return. cp->numpages and cpa->tlbflush have been updated in
642 * We have to split the large page:
644 err
= split_large_page(kpte
, address
);
647 * Do a global flush tlb after splitting the large page
648 * and before we do the actual change page attribute in the PTE.
650 * With out this, we violate the TLB application note, that says
651 * "The TLBs may contain both ordinary and large-page
652 * translations for a 4-KByte range of linear addresses. This
653 * may occur if software modifies the paging structures so that
654 * the page size used for the address range changes. If the two
655 * translations differ with respect to page frame or attributes
656 * (e.g., permissions), processor behavior is undefined and may
657 * be implementation-specific."
659 * We do this global tlb flush inside the cpa_lock, so that we
660 * don't allow any other cpu, with stale tlb entries change the
661 * page attribute in parallel, that also falls into the
662 * just split large page entry.
671 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
);
673 static int cpa_process_alias(struct cpa_data
*cpa
)
675 struct cpa_data alias_cpa
;
677 unsigned long temp_cpa_vaddr
, vaddr
;
679 if (cpa
->pfn
>= max_pfn_mapped
)
683 if (cpa
->pfn
>= max_low_pfn_mapped
&& cpa
->pfn
< (1UL<<(32-PAGE_SHIFT
)))
687 * No need to redo, when the primary call touched the direct
690 if (cpa
->flags
& CPA_ARRAY
)
691 vaddr
= cpa
->vaddr
[cpa
->curpage
];
695 if (!(within(vaddr
, PAGE_OFFSET
,
696 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
)))) {
699 temp_cpa_vaddr
= (unsigned long) __va(cpa
->pfn
<< PAGE_SHIFT
);
700 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
701 alias_cpa
.flags
&= ~CPA_ARRAY
;
704 ret
= __change_page_attr_set_clr(&alias_cpa
, 0);
711 * No need to redo, when the primary call touched the high
714 if (within(vaddr
, (unsigned long) _text
, (unsigned long) _end
))
718 * If the physical address is inside the kernel map, we need
719 * to touch the high mapped kernel as well:
721 if (!within(cpa
->pfn
, highmap_start_pfn(), highmap_end_pfn()))
725 temp_cpa_vaddr
= (cpa
->pfn
<< PAGE_SHIFT
) + __START_KERNEL_map
- phys_base
;
726 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
727 alias_cpa
.flags
&= ~CPA_ARRAY
;
730 * The high mapping range is imprecise, so ignore the return value.
732 __change_page_attr_set_clr(&alias_cpa
, 0);
737 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
)
739 int ret
, numpages
= cpa
->numpages
;
743 * Store the remaining nr of pages for the large page
744 * preservation check.
746 cpa
->numpages
= numpages
;
747 /* for array changes, we can't use large page */
748 if (cpa
->flags
& CPA_ARRAY
)
751 if (!debug_pagealloc
)
752 spin_lock(&cpa_lock
);
753 ret
= __change_page_attr(cpa
, checkalias
);
754 if (!debug_pagealloc
)
755 spin_unlock(&cpa_lock
);
760 ret
= cpa_process_alias(cpa
);
766 * Adjust the number of pages with the result of the
767 * CPA operation. Either a large page has been
768 * preserved or a single page update happened.
770 BUG_ON(cpa
->numpages
> numpages
);
771 numpages
-= cpa
->numpages
;
772 if (cpa
->flags
& CPA_ARRAY
)
775 *cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
781 static inline int cache_attr(pgprot_t attr
)
783 return pgprot_val(attr
) &
784 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
787 static int change_page_attr_set_clr(unsigned long *addr
, int numpages
,
788 pgprot_t mask_set
, pgprot_t mask_clr
,
789 int force_split
, int array
)
792 int ret
, cache
, checkalias
;
795 * Check, if we are requested to change a not supported
798 mask_set
= canon_pgprot(mask_set
);
799 mask_clr
= canon_pgprot(mask_clr
);
800 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
) && !force_split
)
803 /* Ensure we are PAGE_SIZE aligned */
805 if (*addr
& ~PAGE_MASK
) {
808 * People should not be passing in unaligned addresses:
814 for (i
= 0; i
< numpages
; i
++) {
815 if (addr
[i
] & ~PAGE_MASK
) {
816 addr
[i
] &= PAGE_MASK
;
822 /* Must avoid aliasing mappings in the highmem code */
828 * If we're called with lazy mmu updates enabled, the
829 * in-memory pte state may be stale. Flush pending updates to
830 * bring them up to date.
832 arch_flush_lazy_mmu_mode();
835 cpa
.numpages
= numpages
;
836 cpa
.mask_set
= mask_set
;
837 cpa
.mask_clr
= mask_clr
;
840 cpa
.force_split
= force_split
;
843 cpa
.flags
|= CPA_ARRAY
;
845 /* No alias checking for _NX bit modifications */
846 checkalias
= (pgprot_val(mask_set
) | pgprot_val(mask_clr
)) != _PAGE_NX
;
848 ret
= __change_page_attr_set_clr(&cpa
, checkalias
);
851 * Check whether we really changed something:
853 if (!(cpa
.flags
& CPA_FLUSHTLB
))
857 * No need to flush, when we did not set any of the caching
860 cache
= cache_attr(mask_set
);
863 * On success we use clflush, when the CPU supports it to
864 * avoid the wbindv. If the CPU does not support it and in the
865 * error case we fall back to cpa_flush_all (which uses
868 if (!ret
&& cpu_has_clflush
) {
869 if (cpa
.flags
& CPA_ARRAY
)
870 cpa_flush_array(addr
, numpages
, cache
);
872 cpa_flush_range(*addr
, numpages
, cache
);
874 cpa_flush_all(cache
);
877 * If we've been called with lazy mmu updates enabled, then
878 * make sure that everything gets flushed out before we
881 arch_flush_lazy_mmu_mode();
887 static inline int change_page_attr_set(unsigned long *addr
, int numpages
,
888 pgprot_t mask
, int array
)
890 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0), 0,
894 static inline int change_page_attr_clear(unsigned long *addr
, int numpages
,
895 pgprot_t mask
, int array
)
897 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
, 0,
901 int _set_memory_uc(unsigned long addr
, int numpages
)
904 * for now UC MINUS. see comments in ioremap_nocache()
906 return change_page_attr_set(&addr
, numpages
,
907 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
910 int set_memory_uc(unsigned long addr
, int numpages
)
913 * for now UC MINUS. see comments in ioremap_nocache()
915 if (reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
916 _PAGE_CACHE_UC_MINUS
, NULL
))
919 return _set_memory_uc(addr
, numpages
);
921 EXPORT_SYMBOL(set_memory_uc
);
923 int set_memory_array_uc(unsigned long *addr
, int addrinarray
)
929 * for now UC MINUS. see comments in ioremap_nocache()
931 for (i
= 0; i
< addrinarray
; i
++) {
932 start
= __pa(addr
[i
]);
933 for (end
= start
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
934 if (end
!= __pa(addr
[i
+ 1]))
938 if (reserve_memtype(start
, end
, _PAGE_CACHE_UC_MINUS
, NULL
))
942 return change_page_attr_set(addr
, addrinarray
,
943 __pgprot(_PAGE_CACHE_UC_MINUS
), 1);
945 for (i
= 0; i
< addrinarray
; i
++) {
946 unsigned long tmp
= __pa(addr
[i
]);
950 for (end
= tmp
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
951 if (end
!= __pa(addr
[i
+ 1]))
955 free_memtype(tmp
, end
);
959 EXPORT_SYMBOL(set_memory_array_uc
);
961 int _set_memory_wc(unsigned long addr
, int numpages
)
963 return change_page_attr_set(&addr
, numpages
,
964 __pgprot(_PAGE_CACHE_WC
), 0);
967 int set_memory_wc(unsigned long addr
, int numpages
)
970 return set_memory_uc(addr
, numpages
);
972 if (reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
973 _PAGE_CACHE_WC
, NULL
))
976 return _set_memory_wc(addr
, numpages
);
978 EXPORT_SYMBOL(set_memory_wc
);
980 int _set_memory_wb(unsigned long addr
, int numpages
)
982 return change_page_attr_clear(&addr
, numpages
,
983 __pgprot(_PAGE_CACHE_MASK
), 0);
986 int set_memory_wb(unsigned long addr
, int numpages
)
988 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
990 return _set_memory_wb(addr
, numpages
);
992 EXPORT_SYMBOL(set_memory_wb
);
994 int set_memory_array_wb(unsigned long *addr
, int addrinarray
)
998 for (i
= 0; i
< addrinarray
; i
++) {
999 unsigned long start
= __pa(addr
[i
]);
1002 for (end
= start
+ PAGE_SIZE
; i
< addrinarray
- 1; end
+= PAGE_SIZE
) {
1003 if (end
!= __pa(addr
[i
+ 1]))
1007 free_memtype(start
, end
);
1009 return change_page_attr_clear(addr
, addrinarray
,
1010 __pgprot(_PAGE_CACHE_MASK
), 1);
1012 EXPORT_SYMBOL(set_memory_array_wb
);
1014 int set_memory_x(unsigned long addr
, int numpages
)
1016 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1018 EXPORT_SYMBOL(set_memory_x
);
1020 int set_memory_nx(unsigned long addr
, int numpages
)
1022 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1024 EXPORT_SYMBOL(set_memory_nx
);
1026 int set_memory_ro(unsigned long addr
, int numpages
)
1028 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1030 EXPORT_SYMBOL_GPL(set_memory_ro
);
1032 int set_memory_rw(unsigned long addr
, int numpages
)
1034 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1036 EXPORT_SYMBOL_GPL(set_memory_rw
);
1038 int set_memory_np(unsigned long addr
, int numpages
)
1040 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_PRESENT
), 0);
1043 int set_memory_4k(unsigned long addr
, int numpages
)
1045 return change_page_attr_set_clr(&addr
, numpages
, __pgprot(0),
1049 int set_pages_uc(struct page
*page
, int numpages
)
1051 unsigned long addr
= (unsigned long)page_address(page
);
1053 return set_memory_uc(addr
, numpages
);
1055 EXPORT_SYMBOL(set_pages_uc
);
1057 int set_pages_wb(struct page
*page
, int numpages
)
1059 unsigned long addr
= (unsigned long)page_address(page
);
1061 return set_memory_wb(addr
, numpages
);
1063 EXPORT_SYMBOL(set_pages_wb
);
1065 int set_pages_x(struct page
*page
, int numpages
)
1067 unsigned long addr
= (unsigned long)page_address(page
);
1069 return set_memory_x(addr
, numpages
);
1071 EXPORT_SYMBOL(set_pages_x
);
1073 int set_pages_nx(struct page
*page
, int numpages
)
1075 unsigned long addr
= (unsigned long)page_address(page
);
1077 return set_memory_nx(addr
, numpages
);
1079 EXPORT_SYMBOL(set_pages_nx
);
1081 int set_pages_ro(struct page
*page
, int numpages
)
1083 unsigned long addr
= (unsigned long)page_address(page
);
1085 return set_memory_ro(addr
, numpages
);
1088 int set_pages_rw(struct page
*page
, int numpages
)
1090 unsigned long addr
= (unsigned long)page_address(page
);
1092 return set_memory_rw(addr
, numpages
);
1095 #ifdef CONFIG_DEBUG_PAGEALLOC
1097 static int __set_pages_p(struct page
*page
, int numpages
)
1099 unsigned long tempaddr
= (unsigned long) page_address(page
);
1100 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1101 .numpages
= numpages
,
1102 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1103 .mask_clr
= __pgprot(0),
1107 * No alias checking needed for setting present flag. otherwise,
1108 * we may need to break large pages for 64-bit kernel text
1109 * mappings (this adds to complexity if we want to do this from
1110 * atomic context especially). Let's keep it simple!
1112 return __change_page_attr_set_clr(&cpa
, 0);
1115 static int __set_pages_np(struct page
*page
, int numpages
)
1117 unsigned long tempaddr
= (unsigned long) page_address(page
);
1118 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1119 .numpages
= numpages
,
1120 .mask_set
= __pgprot(0),
1121 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1125 * No alias checking needed for setting not present flag. otherwise,
1126 * we may need to break large pages for 64-bit kernel text
1127 * mappings (this adds to complexity if we want to do this from
1128 * atomic context especially). Let's keep it simple!
1130 return __change_page_attr_set_clr(&cpa
, 0);
1133 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1135 if (PageHighMem(page
))
1138 debug_check_no_locks_freed(page_address(page
),
1139 numpages
* PAGE_SIZE
);
1143 * If page allocator is not up yet then do not call c_p_a():
1145 if (!debug_pagealloc_enabled
)
1149 * The return value is ignored as the calls cannot fail.
1150 * Large pages for identity mappings are not used at boot time
1151 * and hence no memory allocations during large page split.
1154 __set_pages_p(page
, numpages
);
1156 __set_pages_np(page
, numpages
);
1159 * We should perform an IPI and flush all tlbs,
1160 * but that can deadlock->flush only current cpu:
1165 #ifdef CONFIG_HIBERNATION
1167 bool kernel_page_present(struct page
*page
)
1172 if (PageHighMem(page
))
1175 pte
= lookup_address((unsigned long)page_address(page
), &level
);
1176 return (pte_val(*pte
) & _PAGE_PRESENT
);
1179 #endif /* CONFIG_HIBERNATION */
1181 #endif /* CONFIG_DEBUG_PAGEALLOC */
1184 * The testcases use internal knowledge of the implementation that shouldn't
1185 * be exposed to the rest of the kernel. Include these directly here.
1187 #ifdef CONFIG_CPA_DEBUG
1188 #include "pageattr-test.c"