2 * Copyright 2002 Andi Kleen, SuSE Labs.
3 * Thanks to Ben LaHaise for precious feedback.
5 #include <linux/highmem.h>
6 #include <linux/bootmem.h>
7 #include <linux/module.h>
8 #include <linux/sched.h>
9 #include <linux/slab.h>
11 #include <linux/interrupt.h>
12 #include <linux/seq_file.h>
13 #include <linux/debugfs.h>
16 #include <asm/processor.h>
17 #include <asm/tlbflush.h>
18 #include <asm/sections.h>
19 #include <asm/setup.h>
20 #include <asm/uaccess.h>
21 #include <asm/pgalloc.h>
22 #include <asm/proto.h>
26 * The current flushing context - we pass it instead of 5 arguments:
35 unsigned force_split
: 1;
41 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
42 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
43 * entries change the page attribute in parallel to some other cpu
44 * splitting a large page entry along with changing the attribute.
46 static DEFINE_SPINLOCK(cpa_lock
);
48 #define CPA_FLUSHTLB 1
50 #define CPA_PAGES_ARRAY 4
53 static unsigned long direct_pages_count
[PG_LEVEL_NUM
];
55 void update_page_count(int level
, unsigned long pages
)
59 /* Protect against CPA */
60 spin_lock_irqsave(&pgd_lock
, flags
);
61 direct_pages_count
[level
] += pages
;
62 spin_unlock_irqrestore(&pgd_lock
, flags
);
65 static void split_page_count(int level
)
67 direct_pages_count
[level
]--;
68 direct_pages_count
[level
- 1] += PTRS_PER_PTE
;
71 void arch_report_meminfo(struct seq_file
*m
)
73 seq_printf(m
, "DirectMap4k: %8lu kB\n",
74 direct_pages_count
[PG_LEVEL_4K
] << 2);
75 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
76 seq_printf(m
, "DirectMap2M: %8lu kB\n",
77 direct_pages_count
[PG_LEVEL_2M
] << 11);
79 seq_printf(m
, "DirectMap4M: %8lu kB\n",
80 direct_pages_count
[PG_LEVEL_2M
] << 12);
84 seq_printf(m
, "DirectMap1G: %8lu kB\n",
85 direct_pages_count
[PG_LEVEL_1G
] << 20);
89 static inline void split_page_count(int level
) { }
94 static inline unsigned long highmap_start_pfn(void)
96 return __pa(_text
) >> PAGE_SHIFT
;
99 static inline unsigned long highmap_end_pfn(void)
101 return __pa(roundup(_brk_end
, PMD_SIZE
)) >> PAGE_SHIFT
;
106 #ifdef CONFIG_DEBUG_PAGEALLOC
107 # define debug_pagealloc 1
109 # define debug_pagealloc 0
113 within(unsigned long addr
, unsigned long start
, unsigned long end
)
115 return addr
>= start
&& addr
< end
;
123 * clflush_cache_range - flush a cache range with clflush
124 * @addr: virtual start address
125 * @size: number of bytes to flush
127 * clflush is an unordered instruction which needs fencing with mfence
128 * to avoid ordering issues.
130 void clflush_cache_range(void *vaddr
, unsigned int size
)
132 void *vend
= vaddr
+ size
- 1;
136 for (; vaddr
< vend
; vaddr
+= boot_cpu_data
.x86_clflush_size
)
139 * Flush any possible final partial cacheline:
146 static void __cpa_flush_all(void *arg
)
148 unsigned long cache
= (unsigned long)arg
;
151 * Flush all to work around Errata in early athlons regarding
152 * large page flushing.
156 if (cache
&& boot_cpu_data
.x86_model
>= 4)
160 static void cpa_flush_all(unsigned long cache
)
162 BUG_ON(irqs_disabled());
164 on_each_cpu(__cpa_flush_all
, (void *) cache
, 1);
167 static void __cpa_flush_range(void *arg
)
170 * We could optimize that further and do individual per page
171 * tlb invalidates for a low number of pages. Caveat: we must
172 * flush the high aliases on 64bit as well.
177 static void cpa_flush_range(unsigned long start
, int numpages
, int cache
)
179 unsigned int i
, level
;
182 BUG_ON(irqs_disabled());
183 WARN_ON(PAGE_ALIGN(start
) != start
);
185 on_each_cpu(__cpa_flush_range
, NULL
, 1);
191 * We only need to flush on one CPU,
192 * clflush is a MESI-coherent instruction that
193 * will cause all other CPUs to flush the same
196 for (i
= 0, addr
= start
; i
< numpages
; i
++, addr
+= PAGE_SIZE
) {
197 pte_t
*pte
= lookup_address(addr
, &level
);
200 * Only flush present addresses:
202 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
203 clflush_cache_range((void *) addr
, PAGE_SIZE
);
207 static void cpa_flush_array(unsigned long *start
, int numpages
, int cache
,
208 int in_flags
, struct page
**pages
)
210 unsigned int i
, level
;
212 BUG_ON(irqs_disabled());
214 on_each_cpu(__cpa_flush_range
, NULL
, 1);
220 if (numpages
>= 1024) {
221 if (boot_cpu_data
.x86_model
>= 4)
226 * We only need to flush on one CPU,
227 * clflush is a MESI-coherent instruction that
228 * will cause all other CPUs to flush the same
231 for (i
= 0; i
< numpages
; i
++) {
235 if (in_flags
& CPA_PAGES_ARRAY
)
236 addr
= (unsigned long)page_address(pages
[i
]);
240 pte
= lookup_address(addr
, &level
);
243 * Only flush present addresses:
245 if (pte
&& (pte_val(*pte
) & _PAGE_PRESENT
))
246 clflush_cache_range((void *)addr
, PAGE_SIZE
);
251 * Certain areas of memory on x86 require very specific protection flags,
252 * for example the BIOS area or kernel text. Callers don't always get this
253 * right (again, ioremap() on BIOS memory is not uncommon) so this function
254 * checks and fixes these known static required protection bits.
256 static inline pgprot_t
static_protections(pgprot_t prot
, unsigned long address
,
259 pgprot_t forbidden
= __pgprot(0);
262 * The BIOS area between 640k and 1Mb needs to be executable for
263 * PCI BIOS based config access (CONFIG_PCI_GOBIOS) support.
265 if (within(pfn
, BIOS_BEGIN
>> PAGE_SHIFT
, BIOS_END
>> PAGE_SHIFT
))
266 pgprot_val(forbidden
) |= _PAGE_NX
;
269 * The kernel text needs to be executable for obvious reasons
270 * Does not cover __inittext since that is gone later on. On
271 * 64bit we do not enforce !NX on the low mapping
273 if (within(address
, (unsigned long)_text
, (unsigned long)_etext
))
274 pgprot_val(forbidden
) |= _PAGE_NX
;
277 * The .rodata section needs to be read-only. Using the pfn
278 * catches all aliases.
280 if (within(pfn
, __pa((unsigned long)__start_rodata
) >> PAGE_SHIFT
,
281 __pa((unsigned long)__end_rodata
) >> PAGE_SHIFT
))
282 pgprot_val(forbidden
) |= _PAGE_RW
;
284 prot
= __pgprot(pgprot_val(prot
) & ~pgprot_val(forbidden
));
290 * Lookup the page table entry for a virtual address. Return a pointer
291 * to the entry and the level of the mapping.
293 * Note: We return pud and pmd either when the entry is marked large
294 * or when the present bit is not set. Otherwise we would return a
295 * pointer to a nonexisting mapping.
297 pte_t
*lookup_address(unsigned long address
, unsigned int *level
)
299 pgd_t
*pgd
= pgd_offset_k(address
);
303 *level
= PG_LEVEL_NONE
;
308 pud
= pud_offset(pgd
, address
);
312 *level
= PG_LEVEL_1G
;
313 if (pud_large(*pud
) || !pud_present(*pud
))
316 pmd
= pmd_offset(pud
, address
);
320 *level
= PG_LEVEL_2M
;
321 if (pmd_large(*pmd
) || !pmd_present(*pmd
))
324 *level
= PG_LEVEL_4K
;
326 return pte_offset_kernel(pmd
, address
);
328 EXPORT_SYMBOL_GPL(lookup_address
);
331 * Set the new pmd in all the pgds we know about:
333 static void __set_pmd_pte(pte_t
*kpte
, unsigned long address
, pte_t pte
)
336 set_pte_atomic(kpte
, pte
);
338 if (!SHARED_KERNEL_PMD
) {
341 list_for_each_entry(page
, &pgd_list
, lru
) {
346 pgd
= (pgd_t
*)page_address(page
) + pgd_index(address
);
347 pud
= pud_offset(pgd
, address
);
348 pmd
= pmd_offset(pud
, address
);
349 set_pte_atomic((pte_t
*)pmd
, pte
);
356 try_preserve_large_page(pte_t
*kpte
, unsigned long address
,
357 struct cpa_data
*cpa
)
359 unsigned long nextpage_addr
, numpages
, pmask
, psize
, flags
, addr
, pfn
;
360 pte_t new_pte
, old_pte
, *tmp
;
361 pgprot_t old_prot
, new_prot
;
365 if (cpa
->force_split
)
368 spin_lock_irqsave(&pgd_lock
, flags
);
370 * Check for races, another CPU might have split this page
373 tmp
= lookup_address(address
, &level
);
379 psize
= PMD_PAGE_SIZE
;
380 pmask
= PMD_PAGE_MASK
;
384 psize
= PUD_PAGE_SIZE
;
385 pmask
= PUD_PAGE_MASK
;
394 * Calculate the number of pages, which fit into this large
395 * page starting at address:
397 nextpage_addr
= (address
+ psize
) & pmask
;
398 numpages
= (nextpage_addr
- address
) >> PAGE_SHIFT
;
399 if (numpages
< cpa
->numpages
)
400 cpa
->numpages
= numpages
;
403 * We are safe now. Check whether the new pgprot is the same:
406 old_prot
= new_prot
= pte_pgprot(old_pte
);
408 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
409 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
412 * old_pte points to the large page base address. So we need
413 * to add the offset of the virtual address:
415 pfn
= pte_pfn(old_pte
) + ((address
& (psize
- 1)) >> PAGE_SHIFT
);
418 new_prot
= static_protections(new_prot
, address
, pfn
);
421 * We need to check the full range, whether
422 * static_protection() requires a different pgprot for one of
423 * the pages in the range we try to preserve:
425 addr
= address
+ PAGE_SIZE
;
427 for (i
= 1; i
< cpa
->numpages
; i
++, addr
+= PAGE_SIZE
, pfn
++) {
428 pgprot_t chk_prot
= static_protections(new_prot
, addr
, pfn
);
430 if (pgprot_val(chk_prot
) != pgprot_val(new_prot
))
435 * If there are no changes, return. maxpages has been updated
438 if (pgprot_val(new_prot
) == pgprot_val(old_prot
)) {
444 * We need to change the attributes. Check, whether we can
445 * change the large page in one go. We request a split, when
446 * the address is not aligned and the number of pages is
447 * smaller than the number of pages in the large page. Note
448 * that we limited the number of possible pages already to
449 * the number of pages in the large page.
451 if (address
== (nextpage_addr
- psize
) && cpa
->numpages
== numpages
) {
453 * The address is aligned and the number of pages
454 * covers the full page.
456 new_pte
= pfn_pte(pte_pfn(old_pte
), canon_pgprot(new_prot
));
457 __set_pmd_pte(kpte
, address
, new_pte
);
458 cpa
->flags
|= CPA_FLUSHTLB
;
463 spin_unlock_irqrestore(&pgd_lock
, flags
);
468 static int split_large_page(pte_t
*kpte
, unsigned long address
)
470 unsigned long flags
, pfn
, pfninc
= 1;
471 unsigned int i
, level
;
476 if (!debug_pagealloc
)
477 spin_unlock(&cpa_lock
);
478 base
= alloc_pages(GFP_KERNEL
, 0);
479 if (!debug_pagealloc
)
480 spin_lock(&cpa_lock
);
484 spin_lock_irqsave(&pgd_lock
, flags
);
486 * Check for races, another CPU might have split this page
489 tmp
= lookup_address(address
, &level
);
493 pbase
= (pte_t
*)page_address(base
);
494 paravirt_alloc_pte(&init_mm
, page_to_pfn(base
));
495 ref_prot
= pte_pgprot(pte_clrhuge(*kpte
));
497 * If we ever want to utilize the PAT bit, we need to
498 * update this function to make sure it's converted from
499 * bit 12 to bit 7 when we cross from the 2MB level to
502 WARN_ON_ONCE(pgprot_val(ref_prot
) & _PAGE_PAT_LARGE
);
505 if (level
== PG_LEVEL_1G
) {
506 pfninc
= PMD_PAGE_SIZE
>> PAGE_SHIFT
;
507 pgprot_val(ref_prot
) |= _PAGE_PSE
;
512 * Get the target pfn from the original entry:
514 pfn
= pte_pfn(*kpte
);
515 for (i
= 0; i
< PTRS_PER_PTE
; i
++, pfn
+= pfninc
)
516 set_pte(&pbase
[i
], pfn_pte(pfn
, ref_prot
));
518 if (address
>= (unsigned long)__va(0) &&
519 address
< (unsigned long)__va(max_low_pfn_mapped
<< PAGE_SHIFT
))
520 split_page_count(level
);
523 if (address
>= (unsigned long)__va(1UL<<32) &&
524 address
< (unsigned long)__va(max_pfn_mapped
<< PAGE_SHIFT
))
525 split_page_count(level
);
529 * Install the new, split up pagetable.
531 * We use the standard kernel pagetable protections for the new
532 * pagetable protections, the actual ptes set above control the
533 * primary protection behavior:
535 __set_pmd_pte(kpte
, address
, mk_pte(base
, __pgprot(_KERNPG_TABLE
)));
538 * Intel Atom errata AAH41 workaround.
540 * The real fix should be in hw or in a microcode update, but
541 * we also probabilistically try to reduce the window of having
542 * a large TLB mixed with 4K TLBs while instruction fetches are
551 * If we dropped out via the lookup_address check under
552 * pgd_lock then stick the page back into the pool:
556 spin_unlock_irqrestore(&pgd_lock
, flags
);
561 static int __cpa_process_fault(struct cpa_data
*cpa
, unsigned long vaddr
,
565 * Ignore all non primary paths.
571 * Ignore the NULL PTE for kernel identity mapping, as it is expected
573 * Also set numpages to '1' indicating that we processed cpa req for
574 * one virtual address page and its pfn. TBD: numpages can be set based
575 * on the initial value and the level returned by lookup_address().
577 if (within(vaddr
, PAGE_OFFSET
,
578 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
))) {
580 cpa
->pfn
= __pa(vaddr
) >> PAGE_SHIFT
;
583 WARN(1, KERN_WARNING
"CPA: called for zero pte. "
584 "vaddr = %lx cpa->vaddr = %lx\n", vaddr
,
591 static int __change_page_attr(struct cpa_data
*cpa
, int primary
)
593 unsigned long address
;
596 pte_t
*kpte
, old_pte
;
598 if (cpa
->flags
& CPA_PAGES_ARRAY
)
599 address
= (unsigned long)page_address(cpa
->pages
[cpa
->curpage
]);
600 else if (cpa
->flags
& CPA_ARRAY
)
601 address
= cpa
->vaddr
[cpa
->curpage
];
603 address
= *cpa
->vaddr
;
605 kpte
= lookup_address(address
, &level
);
607 return __cpa_process_fault(cpa
, address
, primary
);
610 if (!pte_val(old_pte
))
611 return __cpa_process_fault(cpa
, address
, primary
);
613 if (level
== PG_LEVEL_4K
) {
615 pgprot_t new_prot
= pte_pgprot(old_pte
);
616 unsigned long pfn
= pte_pfn(old_pte
);
618 pgprot_val(new_prot
) &= ~pgprot_val(cpa
->mask_clr
);
619 pgprot_val(new_prot
) |= pgprot_val(cpa
->mask_set
);
621 new_prot
= static_protections(new_prot
, address
, pfn
);
624 * We need to keep the pfn from the existing PTE,
625 * after all we're only going to change it's attributes
626 * not the memory it points to
628 new_pte
= pfn_pte(pfn
, canon_pgprot(new_prot
));
631 * Do we really change anything ?
633 if (pte_val(old_pte
) != pte_val(new_pte
)) {
634 set_pte_atomic(kpte
, new_pte
);
635 cpa
->flags
|= CPA_FLUSHTLB
;
642 * Check, whether we can keep the large page intact
643 * and just change the pte:
645 do_split
= try_preserve_large_page(kpte
, address
, cpa
);
647 * When the range fits into the existing large page,
648 * return. cp->numpages and cpa->tlbflush have been updated in
655 * We have to split the large page:
657 err
= split_large_page(kpte
, address
);
660 * Do a global flush tlb after splitting the large page
661 * and before we do the actual change page attribute in the PTE.
663 * With out this, we violate the TLB application note, that says
664 * "The TLBs may contain both ordinary and large-page
665 * translations for a 4-KByte range of linear addresses. This
666 * may occur if software modifies the paging structures so that
667 * the page size used for the address range changes. If the two
668 * translations differ with respect to page frame or attributes
669 * (e.g., permissions), processor behavior is undefined and may
670 * be implementation-specific."
672 * We do this global tlb flush inside the cpa_lock, so that we
673 * don't allow any other cpu, with stale tlb entries change the
674 * page attribute in parallel, that also falls into the
675 * just split large page entry.
684 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
);
686 static int cpa_process_alias(struct cpa_data
*cpa
)
688 struct cpa_data alias_cpa
;
690 unsigned long temp_cpa_vaddr
, vaddr
;
692 if (cpa
->pfn
>= max_pfn_mapped
)
696 if (cpa
->pfn
>= max_low_pfn_mapped
&& cpa
->pfn
< (1UL<<(32-PAGE_SHIFT
)))
700 * No need to redo, when the primary call touched the direct
703 if (cpa
->flags
& CPA_PAGES_ARRAY
)
704 vaddr
= (unsigned long)page_address(cpa
->pages
[cpa
->curpage
]);
705 else if (cpa
->flags
& CPA_ARRAY
)
706 vaddr
= cpa
->vaddr
[cpa
->curpage
];
710 if (!(within(vaddr
, PAGE_OFFSET
,
711 PAGE_OFFSET
+ (max_pfn_mapped
<< PAGE_SHIFT
)))) {
714 temp_cpa_vaddr
= (unsigned long) __va(cpa
->pfn
<< PAGE_SHIFT
);
715 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
716 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
719 ret
= __change_page_attr_set_clr(&alias_cpa
, 0);
726 * No need to redo, when the primary call touched the high
729 if (within(vaddr
, (unsigned long) _text
, _brk_end
))
733 * If the physical address is inside the kernel map, we need
734 * to touch the high mapped kernel as well:
736 if (!within(cpa
->pfn
, highmap_start_pfn(), highmap_end_pfn()))
740 temp_cpa_vaddr
= (cpa
->pfn
<< PAGE_SHIFT
) + __START_KERNEL_map
- phys_base
;
741 alias_cpa
.vaddr
= &temp_cpa_vaddr
;
742 alias_cpa
.flags
&= ~(CPA_PAGES_ARRAY
| CPA_ARRAY
);
745 * The high mapping range is imprecise, so ignore the return value.
747 __change_page_attr_set_clr(&alias_cpa
, 0);
752 static int __change_page_attr_set_clr(struct cpa_data
*cpa
, int checkalias
)
754 int ret
, numpages
= cpa
->numpages
;
758 * Store the remaining nr of pages for the large page
759 * preservation check.
761 cpa
->numpages
= numpages
;
762 /* for array changes, we can't use large page */
763 if (cpa
->flags
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
766 if (!debug_pagealloc
)
767 spin_lock(&cpa_lock
);
768 ret
= __change_page_attr(cpa
, checkalias
);
769 if (!debug_pagealloc
)
770 spin_unlock(&cpa_lock
);
775 ret
= cpa_process_alias(cpa
);
781 * Adjust the number of pages with the result of the
782 * CPA operation. Either a large page has been
783 * preserved or a single page update happened.
785 BUG_ON(cpa
->numpages
> numpages
);
786 numpages
-= cpa
->numpages
;
787 if (cpa
->flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
))
790 *cpa
->vaddr
+= cpa
->numpages
* PAGE_SIZE
;
796 static inline int cache_attr(pgprot_t attr
)
798 return pgprot_val(attr
) &
799 (_PAGE_PAT
| _PAGE_PAT_LARGE
| _PAGE_PWT
| _PAGE_PCD
);
802 static int change_page_attr_set_clr(unsigned long *addr
, int numpages
,
803 pgprot_t mask_set
, pgprot_t mask_clr
,
804 int force_split
, int in_flag
,
808 int ret
, cache
, checkalias
;
811 * Check, if we are requested to change a not supported
814 mask_set
= canon_pgprot(mask_set
);
815 mask_clr
= canon_pgprot(mask_clr
);
816 if (!pgprot_val(mask_set
) && !pgprot_val(mask_clr
) && !force_split
)
819 /* Ensure we are PAGE_SIZE aligned */
820 if (in_flag
& CPA_ARRAY
) {
822 for (i
= 0; i
< numpages
; i
++) {
823 if (addr
[i
] & ~PAGE_MASK
) {
824 addr
[i
] &= PAGE_MASK
;
828 } else if (!(in_flag
& CPA_PAGES_ARRAY
)) {
830 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
831 * No need to cehck in that case
833 if (*addr
& ~PAGE_MASK
) {
836 * People should not be passing in unaligned addresses:
842 /* Must avoid aliasing mappings in the highmem code */
848 * If we're called with lazy mmu updates enabled, the
849 * in-memory pte state may be stale. Flush pending updates to
850 * bring them up to date.
852 arch_flush_lazy_mmu_mode();
856 cpa
.numpages
= numpages
;
857 cpa
.mask_set
= mask_set
;
858 cpa
.mask_clr
= mask_clr
;
861 cpa
.force_split
= force_split
;
863 if (in_flag
& (CPA_ARRAY
| CPA_PAGES_ARRAY
))
864 cpa
.flags
|= in_flag
;
866 /* No alias checking for _NX bit modifications */
867 checkalias
= (pgprot_val(mask_set
) | pgprot_val(mask_clr
)) != _PAGE_NX
;
869 ret
= __change_page_attr_set_clr(&cpa
, checkalias
);
872 * Check whether we really changed something:
874 if (!(cpa
.flags
& CPA_FLUSHTLB
))
878 * No need to flush, when we did not set any of the caching
881 cache
= cache_attr(mask_set
);
884 * On success we use clflush, when the CPU supports it to
885 * avoid the wbindv. If the CPU does not support it and in the
886 * error case we fall back to cpa_flush_all (which uses
889 if (!ret
&& cpu_has_clflush
) {
890 if (cpa
.flags
& (CPA_PAGES_ARRAY
| CPA_ARRAY
)) {
891 cpa_flush_array(addr
, numpages
, cache
,
894 cpa_flush_range(*addr
, numpages
, cache
);
896 cpa_flush_all(cache
);
899 * If we've been called with lazy mmu updates enabled, then
900 * make sure that everything gets flushed out before we
903 arch_flush_lazy_mmu_mode();
909 static inline int change_page_attr_set(unsigned long *addr
, int numpages
,
910 pgprot_t mask
, int array
)
912 return change_page_attr_set_clr(addr
, numpages
, mask
, __pgprot(0), 0,
913 (array
? CPA_ARRAY
: 0), NULL
);
916 static inline int change_page_attr_clear(unsigned long *addr
, int numpages
,
917 pgprot_t mask
, int array
)
919 return change_page_attr_set_clr(addr
, numpages
, __pgprot(0), mask
, 0,
920 (array
? CPA_ARRAY
: 0), NULL
);
923 static inline int cpa_set_pages_array(struct page
**pages
, int numpages
,
926 return change_page_attr_set_clr(NULL
, numpages
, mask
, __pgprot(0), 0,
927 CPA_PAGES_ARRAY
, pages
);
930 static inline int cpa_clear_pages_array(struct page
**pages
, int numpages
,
933 return change_page_attr_set_clr(NULL
, numpages
, __pgprot(0), mask
, 0,
934 CPA_PAGES_ARRAY
, pages
);
937 int _set_memory_uc(unsigned long addr
, int numpages
)
940 * for now UC MINUS. see comments in ioremap_nocache()
942 return change_page_attr_set(&addr
, numpages
,
943 __pgprot(_PAGE_CACHE_UC_MINUS
), 0);
946 int set_memory_uc(unsigned long addr
, int numpages
)
951 * for now UC MINUS. see comments in ioremap_nocache()
953 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
954 _PAGE_CACHE_UC_MINUS
, NULL
);
958 ret
= _set_memory_uc(addr
, numpages
);
965 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
969 EXPORT_SYMBOL(set_memory_uc
);
971 int set_memory_array_uc(unsigned long *addr
, int addrinarray
)
977 * for now UC MINUS. see comments in ioremap_nocache()
979 for (i
= 0; i
< addrinarray
; i
++) {
980 ret
= reserve_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
,
981 _PAGE_CACHE_UC_MINUS
, NULL
);
986 ret
= change_page_attr_set(addr
, addrinarray
,
987 __pgprot(_PAGE_CACHE_UC_MINUS
), 1);
994 for (j
= 0; j
< i
; j
++)
995 free_memtype(__pa(addr
[j
]), __pa(addr
[j
]) + PAGE_SIZE
);
999 EXPORT_SYMBOL(set_memory_array_uc
);
1001 int _set_memory_wc(unsigned long addr
, int numpages
)
1003 return change_page_attr_set(&addr
, numpages
,
1004 __pgprot(_PAGE_CACHE_WC
), 0);
1007 int set_memory_wc(unsigned long addr
, int numpages
)
1012 return set_memory_uc(addr
, numpages
);
1014 ret
= reserve_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
,
1015 _PAGE_CACHE_WC
, NULL
);
1019 ret
= _set_memory_wc(addr
, numpages
);
1026 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1030 EXPORT_SYMBOL(set_memory_wc
);
1032 int _set_memory_wb(unsigned long addr
, int numpages
)
1034 return change_page_attr_clear(&addr
, numpages
,
1035 __pgprot(_PAGE_CACHE_MASK
), 0);
1038 int set_memory_wb(unsigned long addr
, int numpages
)
1042 ret
= _set_memory_wb(addr
, numpages
);
1046 free_memtype(__pa(addr
), __pa(addr
) + numpages
* PAGE_SIZE
);
1049 EXPORT_SYMBOL(set_memory_wb
);
1051 int set_memory_array_wb(unsigned long *addr
, int addrinarray
)
1056 ret
= change_page_attr_clear(addr
, addrinarray
,
1057 __pgprot(_PAGE_CACHE_MASK
), 1);
1061 for (i
= 0; i
< addrinarray
; i
++)
1062 free_memtype(__pa(addr
[i
]), __pa(addr
[i
]) + PAGE_SIZE
);
1066 EXPORT_SYMBOL(set_memory_array_wb
);
1068 int set_memory_x(unsigned long addr
, int numpages
)
1070 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1072 EXPORT_SYMBOL(set_memory_x
);
1074 int set_memory_nx(unsigned long addr
, int numpages
)
1076 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_NX
), 0);
1078 EXPORT_SYMBOL(set_memory_nx
);
1080 int set_memory_ro(unsigned long addr
, int numpages
)
1082 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1084 EXPORT_SYMBOL_GPL(set_memory_ro
);
1086 int set_memory_rw(unsigned long addr
, int numpages
)
1088 return change_page_attr_set(&addr
, numpages
, __pgprot(_PAGE_RW
), 0);
1090 EXPORT_SYMBOL_GPL(set_memory_rw
);
1092 int set_memory_np(unsigned long addr
, int numpages
)
1094 return change_page_attr_clear(&addr
, numpages
, __pgprot(_PAGE_PRESENT
), 0);
1097 int set_memory_4k(unsigned long addr
, int numpages
)
1099 return change_page_attr_set_clr(&addr
, numpages
, __pgprot(0),
1100 __pgprot(0), 1, 0, NULL
);
1103 int set_pages_uc(struct page
*page
, int numpages
)
1105 unsigned long addr
= (unsigned long)page_address(page
);
1107 return set_memory_uc(addr
, numpages
);
1109 EXPORT_SYMBOL(set_pages_uc
);
1111 int set_pages_array_uc(struct page
**pages
, int addrinarray
)
1113 unsigned long start
;
1118 for (i
= 0; i
< addrinarray
; i
++) {
1119 start
= (unsigned long)page_address(pages
[i
]);
1120 end
= start
+ PAGE_SIZE
;
1121 if (reserve_memtype(start
, end
, _PAGE_CACHE_UC_MINUS
, NULL
))
1125 if (cpa_set_pages_array(pages
, addrinarray
,
1126 __pgprot(_PAGE_CACHE_UC_MINUS
)) == 0) {
1127 return 0; /* Success */
1131 for (i
= 0; i
< free_idx
; i
++) {
1132 start
= (unsigned long)page_address(pages
[i
]);
1133 end
= start
+ PAGE_SIZE
;
1134 free_memtype(start
, end
);
1138 EXPORT_SYMBOL(set_pages_array_uc
);
1140 int set_pages_wb(struct page
*page
, int numpages
)
1142 unsigned long addr
= (unsigned long)page_address(page
);
1144 return set_memory_wb(addr
, numpages
);
1146 EXPORT_SYMBOL(set_pages_wb
);
1148 int set_pages_array_wb(struct page
**pages
, int addrinarray
)
1151 unsigned long start
;
1155 retval
= cpa_clear_pages_array(pages
, addrinarray
,
1156 __pgprot(_PAGE_CACHE_MASK
));
1160 for (i
= 0; i
< addrinarray
; i
++) {
1161 start
= (unsigned long)page_address(pages
[i
]);
1162 end
= start
+ PAGE_SIZE
;
1163 free_memtype(start
, end
);
1168 EXPORT_SYMBOL(set_pages_array_wb
);
1170 int set_pages_x(struct page
*page
, int numpages
)
1172 unsigned long addr
= (unsigned long)page_address(page
);
1174 return set_memory_x(addr
, numpages
);
1176 EXPORT_SYMBOL(set_pages_x
);
1178 int set_pages_nx(struct page
*page
, int numpages
)
1180 unsigned long addr
= (unsigned long)page_address(page
);
1182 return set_memory_nx(addr
, numpages
);
1184 EXPORT_SYMBOL(set_pages_nx
);
1186 int set_pages_ro(struct page
*page
, int numpages
)
1188 unsigned long addr
= (unsigned long)page_address(page
);
1190 return set_memory_ro(addr
, numpages
);
1193 int set_pages_rw(struct page
*page
, int numpages
)
1195 unsigned long addr
= (unsigned long)page_address(page
);
1197 return set_memory_rw(addr
, numpages
);
1200 #ifdef CONFIG_DEBUG_PAGEALLOC
1202 static int __set_pages_p(struct page
*page
, int numpages
)
1204 unsigned long tempaddr
= (unsigned long) page_address(page
);
1205 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1206 .numpages
= numpages
,
1207 .mask_set
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1208 .mask_clr
= __pgprot(0),
1212 * No alias checking needed for setting present flag. otherwise,
1213 * we may need to break large pages for 64-bit kernel text
1214 * mappings (this adds to complexity if we want to do this from
1215 * atomic context especially). Let's keep it simple!
1217 return __change_page_attr_set_clr(&cpa
, 0);
1220 static int __set_pages_np(struct page
*page
, int numpages
)
1222 unsigned long tempaddr
= (unsigned long) page_address(page
);
1223 struct cpa_data cpa
= { .vaddr
= &tempaddr
,
1224 .numpages
= numpages
,
1225 .mask_set
= __pgprot(0),
1226 .mask_clr
= __pgprot(_PAGE_PRESENT
| _PAGE_RW
),
1230 * No alias checking needed for setting not present flag. otherwise,
1231 * we may need to break large pages for 64-bit kernel text
1232 * mappings (this adds to complexity if we want to do this from
1233 * atomic context especially). Let's keep it simple!
1235 return __change_page_attr_set_clr(&cpa
, 0);
1238 void kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1240 if (PageHighMem(page
))
1243 debug_check_no_locks_freed(page_address(page
),
1244 numpages
* PAGE_SIZE
);
1248 * If page allocator is not up yet then do not call c_p_a():
1250 if (!debug_pagealloc_enabled
)
1254 * The return value is ignored as the calls cannot fail.
1255 * Large pages for identity mappings are not used at boot time
1256 * and hence no memory allocations during large page split.
1259 __set_pages_p(page
, numpages
);
1261 __set_pages_np(page
, numpages
);
1264 * We should perform an IPI and flush all tlbs,
1265 * but that can deadlock->flush only current cpu:
1270 #ifdef CONFIG_HIBERNATION
1272 bool kernel_page_present(struct page
*page
)
1277 if (PageHighMem(page
))
1280 pte
= lookup_address((unsigned long)page_address(page
), &level
);
1281 return (pte_val(*pte
) & _PAGE_PRESENT
);
1284 #endif /* CONFIG_HIBERNATION */
1286 #endif /* CONFIG_DEBUG_PAGEALLOC */
1289 * The testcases use internal knowledge of the implementation that shouldn't
1290 * be exposed to the rest of the kernel. Include these directly here.
1292 #ifdef CONFIG_CPA_DEBUG
1293 #include "pageattr-test.c"