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Serial: Allow port type to be specified when calling serial8250_register_port.
[linux-2.6/mini2440.git] / drivers / serial / 8250.c
blob3ae497422db577e0d09c167dad39172146319df8
1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
20
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_reg.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/nmi.h>
40 #include <linux/mutex.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 /*
68 * Debugging.
69 */
70 #if 0
71 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
72 #else
73 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
74 #endif
75
76 #if 0
77 #define DEBUG_INTR(fmt...) printk(fmt)
78 #else
79 #define DEBUG_INTR(fmt...) do { } while (0)
80 #endif
81
82 #define PASS_LIMIT 256
83
84 /*
85 * We default to IRQ0 for the "no irq" hack. Some
86 * machine types want others as well - they're free
87 * to redefine this in their header file.
88 */
89 #define is_real_interrupt(irq) ((irq) != 0)
90
91 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92 #define CONFIG_SERIAL_DETECT_IRQ 1
93 #endif
94 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
95 #define CONFIG_SERIAL_MANY_PORTS 1
96 #endif
97
98 /*
99 * HUB6 is always on. This will be removed once the header
100 * files have been cleaned.
101 */
102 #define CONFIG_HUB6 1
103
104 #include <asm/serial.h>
105 /*
106 * SERIAL_PORT_DFNS tells us about built-in ports that have no
107 * standard enumeration mechanism. Platforms that can find all
108 * serial ports via mechanisms like ACPI or PCI need not supply it.
109 */
110 #ifndef SERIAL_PORT_DFNS
111 #define SERIAL_PORT_DFNS
112 #endif
113
114 static const struct old_serial_port old_serial_port[] = {
115 SERIAL_PORT_DFNS /* defined in asm/serial.h */
116 };
117
118 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
119
120 #ifdef CONFIG_SERIAL_8250_RSA
121
122 #define PORT_RSA_MAX 4
123 static unsigned long probe_rsa[PORT_RSA_MAX];
124 static unsigned int probe_rsa_count;
125 #endif /* CONFIG_SERIAL_8250_RSA */
126
127 struct uart_8250_port {
128 struct uart_port port;
129 struct timer_list timer; /* "no irq" timer */
130 struct list_head list; /* ports on this IRQ */
131 unsigned short capabilities; /* port capabilities */
132 unsigned short bugs; /* port bugs */
133 unsigned int tx_loadsz; /* transmit fifo load size */
134 unsigned char acr;
135 unsigned char ier;
136 unsigned char lcr;
137 unsigned char mcr;
138 unsigned char mcr_mask; /* mask of user bits */
139 unsigned char mcr_force; /* mask of forced bits */
140
141 /*
142 * Some bits in registers are cleared on a read, so they must
143 * be saved whenever the register is read but the bits will not
144 * be immediately processed.
145 */
146 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
147 unsigned char lsr_saved_flags;
148 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
149 unsigned char msr_saved_flags;
150
151 /*
152 * We provide a per-port pm hook.
153 */
154 void (*pm)(struct uart_port *port,
155 unsigned int state, unsigned int old);
156 };
157
158 struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163 };
164
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169 /*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172 static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO,
238 },
239 [PORT_16654] = {
240 .name = "ST16654",
241 .fifo_size = 64,
242 .tx_loadsz = 32,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
244 UART_FCR_T_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
246 },
247 [PORT_16850] = {
248 .name = "XR16850",
249 .fifo_size = 128,
250 .tx_loadsz = 128,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
253 },
254 [PORT_RSA] = {
255 .name = "RSA",
256 .fifo_size = 2048,
257 .tx_loadsz = 2048,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
259 .flags = UART_CAP_FIFO,
260 },
261 [PORT_NS16550A] = {
262 .name = "NS16550A",
263 .fifo_size = 16,
264 .tx_loadsz = 16,
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
266 .flags = UART_CAP_FIFO | UART_NATSEMI,
267 },
268 [PORT_XSCALE] = {
269 .name = "XScale",
270 .fifo_size = 32,
271 .tx_loadsz = 32,
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .flags = UART_CAP_FIFO | UART_CAP_UUE,
274 },
275 [PORT_RM9000] = {
276 .name = "RM9000",
277 .fifo_size = 16,
278 .tx_loadsz = 16,
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 .flags = UART_CAP_FIFO,
281 },
282 };
283
284 #if defined (CONFIG_SERIAL_8250_AU1X00)
285
286 /* Au1x00 UART hardware has a weird register layout */
287 static const u8 au_io_in_map[] = {
288 [UART_RX] = 0,
289 [UART_IER] = 2,
290 [UART_IIR] = 3,
291 [UART_LCR] = 5,
292 [UART_MCR] = 6,
293 [UART_LSR] = 7,
294 [UART_MSR] = 8,
295 };
296
297 static const u8 au_io_out_map[] = {
298 [UART_TX] = 1,
299 [UART_IER] = 2,
300 [UART_FCR] = 4,
301 [UART_LCR] = 5,
302 [UART_MCR] = 6,
303 };
304
305 /* sane hardware needs no mapping */
306 static inline int map_8250_in_reg(struct uart_port *p, int offset)
307 {
308 if (p->iotype != UPIO_AU)
309 return offset;
310 return au_io_in_map[offset];
311 }
312
313 static inline int map_8250_out_reg(struct uart_port *p, int offset)
314 {
315 if (p->iotype != UPIO_AU)
316 return offset;
317 return au_io_out_map[offset];
318 }
319
320 #elif defined(CONFIG_SERIAL_8250_RM9K)
321
322 static const u8
323 regmap_in[8] = {
324 [UART_RX] = 0x00,
325 [UART_IER] = 0x0c,
326 [UART_IIR] = 0x14,
327 [UART_LCR] = 0x1c,
328 [UART_MCR] = 0x20,
329 [UART_LSR] = 0x24,
330 [UART_MSR] = 0x28,
331 [UART_SCR] = 0x2c
332 },
333 regmap_out[8] = {
334 [UART_TX] = 0x04,
335 [UART_IER] = 0x0c,
336 [UART_FCR] = 0x18,
337 [UART_LCR] = 0x1c,
338 [UART_MCR] = 0x20,
339 [UART_LSR] = 0x24,
340 [UART_MSR] = 0x28,
341 [UART_SCR] = 0x2c
342 };
343
344 static inline int map_8250_in_reg(struct uart_port *p, int offset)
345 {
346 if (p->iotype != UPIO_RM9000)
347 return offset;
348 return regmap_in[offset];
349 }
350
351 static inline int map_8250_out_reg(struct uart_port *p, int offset)
352 {
353 if (p->iotype != UPIO_RM9000)
354 return offset;
355 return regmap_out[offset];
356 }
357
358 #else
359
360 /* sane hardware needs no mapping */
361 #define map_8250_in_reg(up, offset) (offset)
362 #define map_8250_out_reg(up, offset) (offset)
363
364 #endif
365
366 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
367 {
368 offset = map_8250_in_reg(p, offset) << p->regshift;
369 outb(p->hub6 - 1 + offset, p->iobase);
370 return inb(p->iobase + 1);
371 }
372
373 static void hub6_serial_out(struct uart_port *p, int offset, int value)
374 {
375 offset = map_8250_out_reg(p, offset) << p->regshift;
376 outb(p->hub6 - 1 + offset, p->iobase);
377 outb(value, p->iobase + 1);
378 }
379
380 static unsigned int mem_serial_in(struct uart_port *p, int offset)
381 {
382 offset = map_8250_in_reg(p, offset) << p->regshift;
383 return readb(p->membase + offset);
384 }
385
386 static void mem_serial_out(struct uart_port *p, int offset, int value)
387 {
388 offset = map_8250_out_reg(p, offset) << p->regshift;
389 writeb(value, p->membase + offset);
390 }
391
392 static void mem32_serial_out(struct uart_port *p, int offset, int value)
393 {
394 offset = map_8250_out_reg(p, offset) << p->regshift;
395 writel(value, p->membase + offset);
396 }
397
398 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
399 {
400 offset = map_8250_in_reg(p, offset) << p->regshift;
401 return readl(p->membase + offset);
402 }
403
404 #ifdef CONFIG_SERIAL_8250_AU1X00
405 static unsigned int au_serial_in(struct uart_port *p, int offset)
406 {
407 offset = map_8250_in_reg(p, offset) << p->regshift;
408 return __raw_readl(p->membase + offset);
409 }
410
411 static void au_serial_out(struct uart_port *p, int offset, int value)
412 {
413 offset = map_8250_out_reg(p, offset) << p->regshift;
414 __raw_writel(value, p->membase + offset);
415 }
416 #endif
417
418 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
419 {
420 unsigned int tmp;
421 offset = map_8250_in_reg(p, offset) << p->regshift;
422 if (offset == UART_IIR) {
423 tmp = readl(p->membase + (UART_IIR & ~3));
424 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
425 } else
426 return readb(p->membase + offset);
427 }
428
429 static void tsi_serial_out(struct uart_port *p, int offset, int value)
430 {
431 offset = map_8250_out_reg(p, offset) << p->regshift;
432 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
433 writeb(value, p->membase + offset);
434 }
435
436 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
437 {
438 int save_offset = offset;
439 offset = map_8250_out_reg(p, offset) << p->regshift;
440 /* Save the LCR value so it can be re-written when a
441 * Busy Detect interrupt occurs. */
442 if (save_offset == UART_LCR) {
443 struct uart_8250_port *up = (struct uart_8250_port *)p;
444 up->lcr = value;
445 }
446 writeb(value, p->membase + offset);
447 /* Read the IER to ensure any interrupt is cleared before
448 * returning from ISR. */
449 if (save_offset == UART_TX || save_offset == UART_IER)
450 value = p->serial_in(p, UART_IER);
451 }
452
453 static unsigned int io_serial_in(struct uart_port *p, int offset)
454 {
455 offset = map_8250_in_reg(p, offset) << p->regshift;
456 return inb(p->iobase + offset);
457 }
458
459 static void io_serial_out(struct uart_port *p, int offset, int value)
460 {
461 offset = map_8250_out_reg(p, offset) << p->regshift;
462 outb(value, p->iobase + offset);
463 }
464
465 static void set_io_from_upio(struct uart_port *p)
466 {
467 switch (p->iotype) {
468 case UPIO_HUB6:
469 p->serial_in = hub6_serial_in;
470 p->serial_out = hub6_serial_out;
471 break;
472
473 case UPIO_MEM:
474 p->serial_in = mem_serial_in;
475 p->serial_out = mem_serial_out;
476 break;
477
478 case UPIO_RM9000:
479 case UPIO_MEM32:
480 p->serial_in = mem32_serial_in;
481 p->serial_out = mem32_serial_out;
482 break;
483
484 #ifdef CONFIG_SERIAL_8250_AU1X00
485 case UPIO_AU:
486 p->serial_in = au_serial_in;
487 p->serial_out = au_serial_out;
488 break;
489 #endif
490 case UPIO_TSI:
491 p->serial_in = tsi_serial_in;
492 p->serial_out = tsi_serial_out;
493 break;
494
495 case UPIO_DWAPB:
496 p->serial_in = mem_serial_in;
497 p->serial_out = dwapb_serial_out;
498 break;
499
500 default:
501 p->serial_in = io_serial_in;
502 p->serial_out = io_serial_out;
503 break;
504 }
505 }
506
507 static void
508 serial_out_sync(struct uart_8250_port *up, int offset, int value)
509 {
510 struct uart_port *p = &up->port;
511 switch (p->iotype) {
512 case UPIO_MEM:
513 case UPIO_MEM32:
514 #ifdef CONFIG_SERIAL_8250_AU1X00
515 case UPIO_AU:
516 #endif
517 case UPIO_DWAPB:
518 p->serial_out(p, offset, value);
519 p->serial_in(p, UART_LCR); /* safe, no side-effects */
520 break;
521 default:
522 p->serial_out(p, offset, value);
523 }
524 }
525
526 #define serial_in(up, offset) \
527 (up->port.serial_in(&(up)->port, (offset)))
528 #define serial_out(up, offset, value) \
529 (up->port.serial_out(&(up)->port, (offset), (value)))
530 /*
531 * We used to support using pause I/O for certain machines. We
532 * haven't supported this for a while, but just in case it's badly
533 * needed for certain old 386 machines, I've left these #define's
534 * in....
535 */
536 #define serial_inp(up, offset) serial_in(up, offset)
537 #define serial_outp(up, offset, value) serial_out(up, offset, value)
538
539 /* Uart divisor latch read */
540 static inline int _serial_dl_read(struct uart_8250_port *up)
541 {
542 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
543 }
544
545 /* Uart divisor latch write */
546 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
547 {
548 serial_outp(up, UART_DLL, value & 0xff);
549 serial_outp(up, UART_DLM, value >> 8 & 0xff);
550 }
551
552 #if defined(CONFIG_SERIAL_8250_AU1X00)
553 /* Au1x00 haven't got a standard divisor latch */
554 static int serial_dl_read(struct uart_8250_port *up)
555 {
556 if (up->port.iotype == UPIO_AU)
557 return __raw_readl(up->port.membase + 0x28);
558 else
559 return _serial_dl_read(up);
560 }
561
562 static void serial_dl_write(struct uart_8250_port *up, int value)
563 {
564 if (up->port.iotype == UPIO_AU)
565 __raw_writel(value, up->port.membase + 0x28);
566 else
567 _serial_dl_write(up, value);
568 }
569 #elif defined(CONFIG_SERIAL_8250_RM9K)
570 static int serial_dl_read(struct uart_8250_port *up)
571 {
572 return (up->port.iotype == UPIO_RM9000) ?
573 (((__raw_readl(up->port.membase + 0x10) << 8) |
574 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
575 _serial_dl_read(up);
576 }
577
578 static void serial_dl_write(struct uart_8250_port *up, int value)
579 {
580 if (up->port.iotype == UPIO_RM9000) {
581 __raw_writel(value, up->port.membase + 0x08);
582 __raw_writel(value >> 8, up->port.membase + 0x10);
583 } else {
584 _serial_dl_write(up, value);
585 }
586 }
587 #else
588 #define serial_dl_read(up) _serial_dl_read(up)
589 #define serial_dl_write(up, value) _serial_dl_write(up, value)
590 #endif
591
592 /*
593 * For the 16C950
594 */
595 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
596 {
597 serial_out(up, UART_SCR, offset);
598 serial_out(up, UART_ICR, value);
599 }
600
601 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
602 {
603 unsigned int value;
604
605 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
606 serial_out(up, UART_SCR, offset);
607 value = serial_in(up, UART_ICR);
608 serial_icr_write(up, UART_ACR, up->acr);
609
610 return value;
611 }
612
613 /*
614 * FIFO support.
615 */
616 static void serial8250_clear_fifos(struct uart_8250_port *p)
617 {
618 if (p->capabilities & UART_CAP_FIFO) {
619 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
620 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
621 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
622 serial_outp(p, UART_FCR, 0);
623 }
624 }
625
626 /*
627 * IER sleep support. UARTs which have EFRs need the "extended
628 * capability" bit enabled. Note that on XR16C850s, we need to
629 * reset LCR to write to IER.
630 */
631 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
632 {
633 if (p->capabilities & UART_CAP_SLEEP) {
634 if (p->capabilities & UART_CAP_EFR) {
635 serial_outp(p, UART_LCR, 0xBF);
636 serial_outp(p, UART_EFR, UART_EFR_ECB);
637 serial_outp(p, UART_LCR, 0);
638 }
639 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
640 if (p->capabilities & UART_CAP_EFR) {
641 serial_outp(p, UART_LCR, 0xBF);
642 serial_outp(p, UART_EFR, 0);
643 serial_outp(p, UART_LCR, 0);
644 }
645 }
646 }
647
648 #ifdef CONFIG_SERIAL_8250_RSA
649 /*
650 * Attempts to turn on the RSA FIFO. Returns zero on failure.
651 * We set the port uart clock rate if we succeed.
652 */
653 static int __enable_rsa(struct uart_8250_port *up)
654 {
655 unsigned char mode;
656 int result;
657
658 mode = serial_inp(up, UART_RSA_MSR);
659 result = mode & UART_RSA_MSR_FIFO;
660
661 if (!result) {
662 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
663 mode = serial_inp(up, UART_RSA_MSR);
664 result = mode & UART_RSA_MSR_FIFO;
665 }
666
667 if (result)
668 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
669
670 return result;
671 }
672
673 static void enable_rsa(struct uart_8250_port *up)
674 {
675 if (up->port.type == PORT_RSA) {
676 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
677 spin_lock_irq(&up->port.lock);
678 __enable_rsa(up);
679 spin_unlock_irq(&up->port.lock);
680 }
681 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
682 serial_outp(up, UART_RSA_FRR, 0);
683 }
684 }
685
686 /*
687 * Attempts to turn off the RSA FIFO. Returns zero on failure.
688 * It is unknown why interrupts were disabled in here. However,
689 * the caller is expected to preserve this behaviour by grabbing
690 * the spinlock before calling this function.
691 */
692 static void disable_rsa(struct uart_8250_port *up)
693 {
694 unsigned char mode;
695 int result;
696
697 if (up->port.type == PORT_RSA &&
698 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
699 spin_lock_irq(&up->port.lock);
700
701 mode = serial_inp(up, UART_RSA_MSR);
702 result = !(mode & UART_RSA_MSR_FIFO);
703
704 if (!result) {
705 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
706 mode = serial_inp(up, UART_RSA_MSR);
707 result = !(mode & UART_RSA_MSR_FIFO);
708 }
709
710 if (result)
711 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
712 spin_unlock_irq(&up->port.lock);
713 }
714 }
715 #endif /* CONFIG_SERIAL_8250_RSA */
716
717 /*
718 * This is a quickie test to see how big the FIFO is.
719 * It doesn't work at all the time, more's the pity.
720 */
721 static int size_fifo(struct uart_8250_port *up)
722 {
723 unsigned char old_fcr, old_mcr, old_lcr;
724 unsigned short old_dl;
725 int count;
726
727 old_lcr = serial_inp(up, UART_LCR);
728 serial_outp(up, UART_LCR, 0);
729 old_fcr = serial_inp(up, UART_FCR);
730 old_mcr = serial_inp(up, UART_MCR);
731 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
732 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
733 serial_outp(up, UART_MCR, UART_MCR_LOOP);
734 serial_outp(up, UART_LCR, UART_LCR_DLAB);
735 old_dl = serial_dl_read(up);
736 serial_dl_write(up, 0x0001);
737 serial_outp(up, UART_LCR, 0x03);
738 for (count = 0; count < 256; count++)
739 serial_outp(up, UART_TX, count);
740 mdelay(20);/* FIXME - schedule_timeout */
741 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
742 (count < 256); count++)
743 serial_inp(up, UART_RX);
744 serial_outp(up, UART_FCR, old_fcr);
745 serial_outp(up, UART_MCR, old_mcr);
746 serial_outp(up, UART_LCR, UART_LCR_DLAB);
747 serial_dl_write(up, old_dl);
748 serial_outp(up, UART_LCR, old_lcr);
749
750 return count;
751 }
752
753 /*
754 * Read UART ID using the divisor method - set DLL and DLM to zero
755 * and the revision will be in DLL and device type in DLM. We
756 * preserve the device state across this.
757 */
758 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
759 {
760 unsigned char old_dll, old_dlm, old_lcr;
761 unsigned int id;
762
763 old_lcr = serial_inp(p, UART_LCR);
764 serial_outp(p, UART_LCR, UART_LCR_DLAB);
765
766 old_dll = serial_inp(p, UART_DLL);
767 old_dlm = serial_inp(p, UART_DLM);
768
769 serial_outp(p, UART_DLL, 0);
770 serial_outp(p, UART_DLM, 0);
771
772 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
773
774 serial_outp(p, UART_DLL, old_dll);
775 serial_outp(p, UART_DLM, old_dlm);
776 serial_outp(p, UART_LCR, old_lcr);
777
778 return id;
779 }
780
781 /*
782 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
783 * When this function is called we know it is at least a StarTech
784 * 16650 V2, but it might be one of several StarTech UARTs, or one of
785 * its clones. (We treat the broken original StarTech 16650 V1 as a
786 * 16550, and why not? Startech doesn't seem to even acknowledge its
787 * existence.)
788 *
789 * What evil have men's minds wrought...
790 */
791 static void autoconfig_has_efr(struct uart_8250_port *up)
792 {
793 unsigned int id1, id2, id3, rev;
794
795 /*
796 * Everything with an EFR has SLEEP
797 */
798 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
799
800 /*
801 * First we check to see if it's an Oxford Semiconductor UART.
802 *
803 * If we have to do this here because some non-National
804 * Semiconductor clone chips lock up if you try writing to the
805 * LSR register (which serial_icr_read does)
806 */
807
808 /*
809 * Check for Oxford Semiconductor 16C950.
810 *
811 * EFR [4] must be set else this test fails.
812 *
813 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
814 * claims that it's needed for 952 dual UART's (which are not
815 * recommended for new designs).
816 */
817 up->acr = 0;
818 serial_out(up, UART_LCR, 0xBF);
819 serial_out(up, UART_EFR, UART_EFR_ECB);
820 serial_out(up, UART_LCR, 0x00);
821 id1 = serial_icr_read(up, UART_ID1);
822 id2 = serial_icr_read(up, UART_ID2);
823 id3 = serial_icr_read(up, UART_ID3);
824 rev = serial_icr_read(up, UART_REV);
825
826 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
827
828 if (id1 == 0x16 && id2 == 0xC9 &&
829 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
830 up->port.type = PORT_16C950;
831
832 /*
833 * Enable work around for the Oxford Semiconductor 952 rev B
834 * chip which causes it to seriously miscalculate baud rates
835 * when DLL is 0.
836 */
837 if (id3 == 0x52 && rev == 0x01)
838 up->bugs |= UART_BUG_QUOT;
839 return;
840 }
841
842 /*
843 * We check for a XR16C850 by setting DLL and DLM to 0, and then
844 * reading back DLL and DLM. The chip type depends on the DLM
845 * value read back:
846 * 0x10 - XR16C850 and the DLL contains the chip revision.
847 * 0x12 - XR16C2850.
848 * 0x14 - XR16C854.
849 */
850 id1 = autoconfig_read_divisor_id(up);
851 DEBUG_AUTOCONF("850id=%04x ", id1);
852
853 id2 = id1 >> 8;
854 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
855 up->port.type = PORT_16850;
856 return;
857 }
858
859 /*
860 * It wasn't an XR16C850.
861 *
862 * We distinguish between the '654 and the '650 by counting
863 * how many bytes are in the FIFO. I'm using this for now,
864 * since that's the technique that was sent to me in the
865 * serial driver update, but I'm not convinced this works.
866 * I've had problems doing this in the past. -TYT
867 */
868 if (size_fifo(up) == 64)
869 up->port.type = PORT_16654;
870 else
871 up->port.type = PORT_16650V2;
872 }
873
874 /*
875 * We detected a chip without a FIFO. Only two fall into
876 * this category - the original 8250 and the 16450. The
877 * 16450 has a scratch register (accessible with LCR=0)
878 */
879 static void autoconfig_8250(struct uart_8250_port *up)
880 {
881 unsigned char scratch, status1, status2;
882
883 up->port.type = PORT_8250;
884
885 scratch = serial_in(up, UART_SCR);
886 serial_outp(up, UART_SCR, 0xa5);
887 status1 = serial_in(up, UART_SCR);
888 serial_outp(up, UART_SCR, 0x5a);
889 status2 = serial_in(up, UART_SCR);
890 serial_outp(up, UART_SCR, scratch);
891
892 if (status1 == 0xa5 && status2 == 0x5a)
893 up->port.type = PORT_16450;
894 }
895
896 static int broken_efr(struct uart_8250_port *up)
897 {
898 /*
899 * Exar ST16C2550 "A2" devices incorrectly detect as
900 * having an EFR, and report an ID of 0x0201. See
901 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
902 */
903 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
904 return 1;
905
906 return 0;
907 }
908
909 /*
910 * We know that the chip has FIFOs. Does it have an EFR? The
911 * EFR is located in the same register position as the IIR and
912 * we know the top two bits of the IIR are currently set. The
913 * EFR should contain zero. Try to read the EFR.
914 */
915 static void autoconfig_16550a(struct uart_8250_port *up)
916 {
917 unsigned char status1, status2;
918 unsigned int iersave;
919
920 up->port.type = PORT_16550A;
921 up->capabilities |= UART_CAP_FIFO;
922
923 /*
924 * Check for presence of the EFR when DLAB is set.
925 * Only ST16C650V1 UARTs pass this test.
926 */
927 serial_outp(up, UART_LCR, UART_LCR_DLAB);
928 if (serial_in(up, UART_EFR) == 0) {
929 serial_outp(up, UART_EFR, 0xA8);
930 if (serial_in(up, UART_EFR) != 0) {
931 DEBUG_AUTOCONF("EFRv1 ");
932 up->port.type = PORT_16650;
933 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
934 } else {
935 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
936 }
937 serial_outp(up, UART_EFR, 0);
938 return;
939 }
940
941 /*
942 * Maybe it requires 0xbf to be written to the LCR.
943 * (other ST16C650V2 UARTs, TI16C752A, etc)
944 */
945 serial_outp(up, UART_LCR, 0xBF);
946 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
947 DEBUG_AUTOCONF("EFRv2 ");
948 autoconfig_has_efr(up);
949 return;
950 }
951
952 /*
953 * Check for a National Semiconductor SuperIO chip.
954 * Attempt to switch to bank 2, read the value of the LOOP bit
955 * from EXCR1. Switch back to bank 0, change it in MCR. Then
956 * switch back to bank 2, read it from EXCR1 again and check
957 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
958 */
959 serial_outp(up, UART_LCR, 0);
960 status1 = serial_in(up, UART_MCR);
961 serial_outp(up, UART_LCR, 0xE0);
962 status2 = serial_in(up, 0x02); /* EXCR1 */
963
964 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
965 serial_outp(up, UART_LCR, 0);
966 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
967 serial_outp(up, UART_LCR, 0xE0);
968 status2 = serial_in(up, 0x02); /* EXCR1 */
969 serial_outp(up, UART_LCR, 0);
970 serial_outp(up, UART_MCR, status1);
971
972 if ((status2 ^ status1) & UART_MCR_LOOP) {
973 unsigned short quot;
974
975 serial_outp(up, UART_LCR, 0xE0);
976
977 quot = serial_dl_read(up);
978 quot <<= 3;
979
980 status1 = serial_in(up, 0x04); /* EXCR2 */
981 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
982 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
983 serial_outp(up, 0x04, status1);
984
985 serial_dl_write(up, quot);
986
987 serial_outp(up, UART_LCR, 0);
988
989 up->port.uartclk = 921600*16;
990 up->port.type = PORT_NS16550A;
991 up->capabilities |= UART_NATSEMI;
992 return;
993 }
994 }
995
996 /*
997 * No EFR. Try to detect a TI16750, which only sets bit 5 of
998 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
999 * Try setting it with and without DLAB set. Cheap clones
1000 * set bit 5 without DLAB set.
1001 */
1002 serial_outp(up, UART_LCR, 0);
1003 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1004 status1 = serial_in(up, UART_IIR) >> 5;
1005 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1006 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1007 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1008 status2 = serial_in(up, UART_IIR) >> 5;
1009 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1010 serial_outp(up, UART_LCR, 0);
1011
1012 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1013
1014 if (status1 == 6 && status2 == 7) {
1015 up->port.type = PORT_16750;
1016 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1017 return;
1018 }
1019
1020 /*
1021 * Try writing and reading the UART_IER_UUE bit (b6).
1022 * If it works, this is probably one of the Xscale platform's
1023 * internal UARTs.
1024 * We're going to explicitly set the UUE bit to 0 before
1025 * trying to write and read a 1 just to make sure it's not
1026 * already a 1 and maybe locked there before we even start start.
1027 */
1028 iersave = serial_in(up, UART_IER);
1029 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1030 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1031 /*
1032 * OK it's in a known zero state, try writing and reading
1033 * without disturbing the current state of the other bits.
1034 */
1035 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1036 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1037 /*
1038 * It's an Xscale.
1039 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1040 */
1041 DEBUG_AUTOCONF("Xscale ");
1042 up->port.type = PORT_XSCALE;
1043 up->capabilities |= UART_CAP_UUE;
1044 return;
1045 }
1046 } else {
1047 /*
1048 * If we got here we couldn't force the IER_UUE bit to 0.
1049 * Log it and continue.
1050 */
1051 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1052 }
1053 serial_outp(up, UART_IER, iersave);
1054 }
1055
1056 /*
1057 * This routine is called by rs_init() to initialize a specific serial
1058 * port. It determines what type of UART chip this serial port is
1059 * using: 8250, 16450, 16550, 16550A. The important question is
1060 * whether or not this UART is a 16550A or not, since this will
1061 * determine whether or not we can use its FIFO features or not.
1062 */
1063 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1064 {
1065 unsigned char status1, scratch, scratch2, scratch3;
1066 unsigned char save_lcr, save_mcr;
1067 unsigned long flags;
1068
1069 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1070 return;
1071
1072 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
1073 serial_index(&up->port), up->port.iobase, up->port.membase);
1074
1075 /*
1076 * We really do need global IRQs disabled here - we're going to
1077 * be frobbing the chips IRQ enable register to see if it exists.
1078 */
1079 spin_lock_irqsave(&up->port.lock, flags);
1080
1081 up->capabilities = 0;
1082 up->bugs = 0;
1083
1084 if (!(up->port.flags & UPF_BUGGY_UART)) {
1085 /*
1086 * Do a simple existence test first; if we fail this,
1087 * there's no point trying anything else.
1088 *
1089 * 0x80 is used as a nonsense port to prevent against
1090 * false positives due to ISA bus float. The
1091 * assumption is that 0x80 is a non-existent port;
1092 * which should be safe since include/asm/io.h also
1093 * makes this assumption.
1094 *
1095 * Note: this is safe as long as MCR bit 4 is clear
1096 * and the device is in "PC" mode.
1097 */
1098 scratch = serial_inp(up, UART_IER);
1099 serial_outp(up, UART_IER, 0);
1100 #ifdef __i386__
1101 outb(0xff, 0x080);
1102 #endif
1103 /*
1104 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1105 * 16C754B) allow only to modify them if an EFR bit is set.
1106 */
1107 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1108 serial_outp(up, UART_IER, 0x0F);
1109 #ifdef __i386__
1110 outb(0, 0x080);
1111 #endif
1112 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1113 serial_outp(up, UART_IER, scratch);
1114 if (scratch2 != 0 || scratch3 != 0x0F) {
1115 /*
1116 * We failed; there's nothing here
1117 */
1118 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1119 scratch2, scratch3);
1120 goto out;
1121 }
1122 }
1123
1124 save_mcr = serial_in(up, UART_MCR);
1125 save_lcr = serial_in(up, UART_LCR);
1126
1127 /*
1128 * Check to see if a UART is really there. Certain broken
1129 * internal modems based on the Rockwell chipset fail this
1130 * test, because they apparently don't implement the loopback
1131 * test mode. So this test is skipped on the COM 1 through
1132 * COM 4 ports. This *should* be safe, since no board
1133 * manufacturer would be stupid enough to design a board
1134 * that conflicts with COM 1-4 --- we hope!
1135 */
1136 if (!(up->port.flags & UPF_SKIP_TEST)) {
1137 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1138 status1 = serial_inp(up, UART_MSR) & 0xF0;
1139 serial_outp(up, UART_MCR, save_mcr);
1140 if (status1 != 0x90) {
1141 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1142 status1);
1143 goto out;
1144 }
1145 }
1146
1147 /*
1148 * We're pretty sure there's a port here. Lets find out what
1149 * type of port it is. The IIR top two bits allows us to find
1150 * out if it's 8250 or 16450, 16550, 16550A or later. This
1151 * determines what we test for next.
1152 *
1153 * We also initialise the EFR (if any) to zero for later. The
1154 * EFR occupies the same register location as the FCR and IIR.
1155 */
1156 serial_outp(up, UART_LCR, 0xBF);
1157 serial_outp(up, UART_EFR, 0);
1158 serial_outp(up, UART_LCR, 0);
1159
1160 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1161 scratch = serial_in(up, UART_IIR) >> 6;
1162
1163 DEBUG_AUTOCONF("iir=%d ", scratch);
1164
1165 switch (scratch) {
1166 case 0:
1167 autoconfig_8250(up);
1168 break;
1169 case 1:
1170 up->port.type = PORT_UNKNOWN;
1171 break;
1172 case 2:
1173 up->port.type = PORT_16550;
1174 break;
1175 case 3:
1176 autoconfig_16550a(up);
1177 break;
1178 }
1179
1180 #ifdef CONFIG_SERIAL_8250_RSA
1181 /*
1182 * Only probe for RSA ports if we got the region.
1183 */
1184 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1185 int i;
1186
1187 for (i = 0 ; i < probe_rsa_count; ++i) {
1188 if (probe_rsa[i] == up->port.iobase &&
1189 __enable_rsa(up)) {
1190 up->port.type = PORT_RSA;
1191 break;
1192 }
1193 }
1194 }
1195 #endif
1196
1197 #ifdef CONFIG_SERIAL_8250_AU1X00
1198 /* if access method is AU, it is a 16550 with a quirk */
1199 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1200 up->bugs |= UART_BUG_NOMSR;
1201 #endif
1202
1203 serial_outp(up, UART_LCR, save_lcr);
1204
1205 if (up->capabilities != uart_config[up->port.type].flags) {
1206 printk(KERN_WARNING
1207 "ttyS%d: detected caps %08x should be %08x\n",
1208 serial_index(&up->port), up->capabilities,
1209 uart_config[up->port.type].flags);
1210 }
1211
1212 up->port.fifosize = uart_config[up->port.type].fifo_size;
1213 up->capabilities = uart_config[up->port.type].flags;
1214 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1215
1216 if (up->port.type == PORT_UNKNOWN)
1217 goto out;
1218
1219 /*
1220 * Reset the UART.
1221 */
1222 #ifdef CONFIG_SERIAL_8250_RSA
1223 if (up->port.type == PORT_RSA)
1224 serial_outp(up, UART_RSA_FRR, 0);
1225 #endif
1226 serial_outp(up, UART_MCR, save_mcr);
1227 serial8250_clear_fifos(up);
1228 serial_in(up, UART_RX);
1229 if (up->capabilities & UART_CAP_UUE)
1230 serial_outp(up, UART_IER, UART_IER_UUE);
1231 else
1232 serial_outp(up, UART_IER, 0);
1233
1234 out:
1235 spin_unlock_irqrestore(&up->port.lock, flags);
1236 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1237 }
1238
1239 static void autoconfig_irq(struct uart_8250_port *up)
1240 {
1241 unsigned char save_mcr, save_ier;
1242 unsigned char save_ICP = 0;
1243 unsigned int ICP = 0;
1244 unsigned long irqs;
1245 int irq;
1246
1247 if (up->port.flags & UPF_FOURPORT) {
1248 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1249 save_ICP = inb_p(ICP);
1250 outb_p(0x80, ICP);
1251 (void) inb_p(ICP);
1252 }
1253
1254 /* forget possible initially masked and pending IRQ */
1255 probe_irq_off(probe_irq_on());
1256 save_mcr = serial_inp(up, UART_MCR);
1257 save_ier = serial_inp(up, UART_IER);
1258 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1259
1260 irqs = probe_irq_on();
1261 serial_outp(up, UART_MCR, 0);
1262 udelay(10);
1263 if (up->port.flags & UPF_FOURPORT) {
1264 serial_outp(up, UART_MCR,
1265 UART_MCR_DTR | UART_MCR_RTS);
1266 } else {
1267 serial_outp(up, UART_MCR,
1268 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1269 }
1270 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1271 (void)serial_inp(up, UART_LSR);
1272 (void)serial_inp(up, UART_RX);
1273 (void)serial_inp(up, UART_IIR);
1274 (void)serial_inp(up, UART_MSR);
1275 serial_outp(up, UART_TX, 0xFF);
1276 udelay(20);
1277 irq = probe_irq_off(irqs);
1278
1279 serial_outp(up, UART_MCR, save_mcr);
1280 serial_outp(up, UART_IER, save_ier);
1281
1282 if (up->port.flags & UPF_FOURPORT)
1283 outb_p(save_ICP, ICP);
1284
1285 up->port.irq = (irq > 0) ? irq : 0;
1286 }
1287
1288 static inline void __stop_tx(struct uart_8250_port *p)
1289 {
1290 if (p->ier & UART_IER_THRI) {
1291 p->ier &= ~UART_IER_THRI;
1292 serial_out(p, UART_IER, p->ier);
1293 }
1294 }
1295
1296 static void serial8250_stop_tx(struct uart_port *port)
1297 {
1298 struct uart_8250_port *up = (struct uart_8250_port *)port;
1299
1300 __stop_tx(up);
1301
1302 /*
1303 * We really want to stop the transmitter from sending.
1304 */
1305 if (up->port.type == PORT_16C950) {
1306 up->acr |= UART_ACR_TXDIS;
1307 serial_icr_write(up, UART_ACR, up->acr);
1308 }
1309 }
1310
1311 static void transmit_chars(struct uart_8250_port *up);
1312
1313 static void serial8250_start_tx(struct uart_port *port)
1314 {
1315 struct uart_8250_port *up = (struct uart_8250_port *)port;
1316
1317 if (!(up->ier & UART_IER_THRI)) {
1318 up->ier |= UART_IER_THRI;
1319 serial_out(up, UART_IER, up->ier);
1320
1321 if (up->bugs & UART_BUG_TXEN) {
1322 unsigned char lsr, iir;
1323 lsr = serial_in(up, UART_LSR);
1324 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1325 iir = serial_in(up, UART_IIR) & 0x0f;
1326 if ((up->port.type == PORT_RM9000) ?
1327 (lsr & UART_LSR_THRE &&
1328 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1329 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1330 transmit_chars(up);
1331 }
1332 }
1333
1334 /*
1335 * Re-enable the transmitter if we disabled it.
1336 */
1337 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1338 up->acr &= ~UART_ACR_TXDIS;
1339 serial_icr_write(up, UART_ACR, up->acr);
1340 }
1341 }
1342
1343 static void serial8250_stop_rx(struct uart_port *port)
1344 {
1345 struct uart_8250_port *up = (struct uart_8250_port *)port;
1346
1347 up->ier &= ~UART_IER_RLSI;
1348 up->port.read_status_mask &= ~UART_LSR_DR;
1349 serial_out(up, UART_IER, up->ier);
1350 }
1351
1352 static void serial8250_enable_ms(struct uart_port *port)
1353 {
1354 struct uart_8250_port *up = (struct uart_8250_port *)port;
1355
1356 /* no MSR capabilities */
1357 if (up->bugs & UART_BUG_NOMSR)
1358 return;
1359
1360 up->ier |= UART_IER_MSI;
1361 serial_out(up, UART_IER, up->ier);
1362 }
1363
1364 static void
1365 receive_chars(struct uart_8250_port *up, unsigned int *status)
1366 {
1367 struct tty_struct *tty = up->port.info->port.tty;
1368 unsigned char ch, lsr = *status;
1369 int max_count = 256;
1370 char flag;
1371
1372 do {
1373 if (likely(lsr & UART_LSR_DR))
1374 ch = serial_inp(up, UART_RX);
1375 else
1376 /*
1377 * Intel 82571 has a Serial Over Lan device that will
1378 * set UART_LSR_BI without setting UART_LSR_DR when
1379 * it receives a break. To avoid reading from the
1380 * receive buffer without UART_LSR_DR bit set, we
1381 * just force the read character to be 0
1382 */
1383 ch = 0;
1384
1385 flag = TTY_NORMAL;
1386 up->port.icount.rx++;
1387
1388 lsr |= up->lsr_saved_flags;
1389 up->lsr_saved_flags = 0;
1390
1391 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1392 /*
1393 * For statistics only
1394 */
1395 if (lsr & UART_LSR_BI) {
1396 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1397 up->port.icount.brk++;
1398 /*
1399 * We do the SysRQ and SAK checking
1400 * here because otherwise the break
1401 * may get masked by ignore_status_mask
1402 * or read_status_mask.
1403 */
1404 if (uart_handle_break(&up->port))
1405 goto ignore_char;
1406 } else if (lsr & UART_LSR_PE)
1407 up->port.icount.parity++;
1408 else if (lsr & UART_LSR_FE)
1409 up->port.icount.frame++;
1410 if (lsr & UART_LSR_OE)
1411 up->port.icount.overrun++;
1412
1413 /*
1414 * Mask off conditions which should be ignored.
1415 */
1416 lsr &= up->port.read_status_mask;
1417
1418 if (lsr & UART_LSR_BI) {
1419 DEBUG_INTR("handling break....");
1420 flag = TTY_BREAK;
1421 } else if (lsr & UART_LSR_PE)
1422 flag = TTY_PARITY;
1423 else if (lsr & UART_LSR_FE)
1424 flag = TTY_FRAME;
1425 }
1426 if (uart_handle_sysrq_char(&up->port, ch))
1427 goto ignore_char;
1428
1429 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1430
1431 ignore_char:
1432 lsr = serial_inp(up, UART_LSR);
1433 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1434 spin_unlock(&up->port.lock);
1435 tty_flip_buffer_push(tty);
1436 spin_lock(&up->port.lock);
1437 *status = lsr;
1438 }
1439
1440 static void transmit_chars(struct uart_8250_port *up)
1441 {
1442 struct circ_buf *xmit = &up->port.info->xmit;
1443 int count;
1444
1445 if (up->port.x_char) {
1446 serial_outp(up, UART_TX, up->port.x_char);
1447 up->port.icount.tx++;
1448 up->port.x_char = 0;
1449 return;
1450 }
1451 if (uart_tx_stopped(&up->port)) {
1452 serial8250_stop_tx(&up->port);
1453 return;
1454 }
1455 if (uart_circ_empty(xmit)) {
1456 __stop_tx(up);
1457 return;
1458 }
1459
1460 count = up->tx_loadsz;
1461 do {
1462 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1463 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1464 up->port.icount.tx++;
1465 if (uart_circ_empty(xmit))
1466 break;
1467 } while (--count > 0);
1468
1469 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1470 uart_write_wakeup(&up->port);
1471
1472 DEBUG_INTR("THRE...");
1473
1474 if (uart_circ_empty(xmit))
1475 __stop_tx(up);
1476 }
1477
1478 static unsigned int check_modem_status(struct uart_8250_port *up)
1479 {
1480 unsigned int status = serial_in(up, UART_MSR);
1481
1482 status |= up->msr_saved_flags;
1483 up->msr_saved_flags = 0;
1484 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1485 up->port.info != NULL) {
1486 if (status & UART_MSR_TERI)
1487 up->port.icount.rng++;
1488 if (status & UART_MSR_DDSR)
1489 up->port.icount.dsr++;
1490 if (status & UART_MSR_DDCD)
1491 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1492 if (status & UART_MSR_DCTS)
1493 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1494
1495 wake_up_interruptible(&up->port.info->delta_msr_wait);
1496 }
1497
1498 return status;
1499 }
1500
1501 /*
1502 * This handles the interrupt from one port.
1503 */
1504 static void serial8250_handle_port(struct uart_8250_port *up)
1505 {
1506 unsigned int status;
1507 unsigned long flags;
1508
1509 spin_lock_irqsave(&up->port.lock, flags);
1510
1511 status = serial_inp(up, UART_LSR);
1512
1513 DEBUG_INTR("status = %x...", status);
1514
1515 if (status & (UART_LSR_DR | UART_LSR_BI))
1516 receive_chars(up, &status);
1517 check_modem_status(up);
1518 if (status & UART_LSR_THRE)
1519 transmit_chars(up);
1520
1521 spin_unlock_irqrestore(&up->port.lock, flags);
1522 }
1523
1524 /*
1525 * This is the serial driver's interrupt routine.
1526 *
1527 * Arjan thinks the old way was overly complex, so it got simplified.
1528 * Alan disagrees, saying that need the complexity to handle the weird
1529 * nature of ISA shared interrupts. (This is a special exception.)
1530 *
1531 * In order to handle ISA shared interrupts properly, we need to check
1532 * that all ports have been serviced, and therefore the ISA interrupt
1533 * line has been de-asserted.
1534 *
1535 * This means we need to loop through all ports. checking that they
1536 * don't have an interrupt pending.
1537 */
1538 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1539 {
1540 struct irq_info *i = dev_id;
1541 struct list_head *l, *end = NULL;
1542 int pass_counter = 0, handled = 0;
1543
1544 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1545
1546 spin_lock(&i->lock);
1547
1548 l = i->head;
1549 do {
1550 struct uart_8250_port *up;
1551 unsigned int iir;
1552
1553 up = list_entry(l, struct uart_8250_port, list);
1554
1555 iir = serial_in(up, UART_IIR);
1556 if (!(iir & UART_IIR_NO_INT)) {
1557 serial8250_handle_port(up);
1558
1559 handled = 1;
1560
1561 end = NULL;
1562 } else if (up->port.iotype == UPIO_DWAPB &&
1563 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1564 /* The DesignWare APB UART has an Busy Detect (0x07)
1565 * interrupt meaning an LCR write attempt occured while the
1566 * UART was busy. The interrupt must be cleared by reading
1567 * the UART status register (USR) and the LCR re-written. */
1568 unsigned int status;
1569 status = *(volatile u32 *)up->port.private_data;
1570 serial_out(up, UART_LCR, up->lcr);
1571
1572 handled = 1;
1573
1574 end = NULL;
1575 } else if (end == NULL)
1576 end = l;
1577
1578 l = l->next;
1579
1580 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1581 /* If we hit this, we're dead. */
1582 printk(KERN_ERR "serial8250: too much work for "
1583 "irq%d\n", irq);
1584 break;
1585 }
1586 } while (l != end);
1587
1588 spin_unlock(&i->lock);
1589
1590 DEBUG_INTR("end.\n");
1591
1592 return IRQ_RETVAL(handled);
1593 }
1594
1595 /*
1596 * To support ISA shared interrupts, we need to have one interrupt
1597 * handler that ensures that the IRQ line has been deasserted
1598 * before returning. Failing to do this will result in the IRQ
1599 * line being stuck active, and, since ISA irqs are edge triggered,
1600 * no more IRQs will be seen.
1601 */
1602 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1603 {
1604 spin_lock_irq(&i->lock);
1605
1606 if (!list_empty(i->head)) {
1607 if (i->head == &up->list)
1608 i->head = i->head->next;
1609 list_del(&up->list);
1610 } else {
1611 BUG_ON(i->head != &up->list);
1612 i->head = NULL;
1613 }
1614 spin_unlock_irq(&i->lock);
1615 /* List empty so throw away the hash node */
1616 if (i->head == NULL) {
1617 hlist_del(&i->node);
1618 kfree(i);
1619 }
1620 }
1621
1622 static int serial_link_irq_chain(struct uart_8250_port *up)
1623 {
1624 struct hlist_head *h;
1625 struct hlist_node *n;
1626 struct irq_info *i;
1627 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1628
1629 mutex_lock(&hash_mutex);
1630
1631 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1632
1633 hlist_for_each(n, h) {
1634 i = hlist_entry(n, struct irq_info, node);
1635 if (i->irq == up->port.irq)
1636 break;
1637 }
1638
1639 if (n == NULL) {
1640 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1641 if (i == NULL) {
1642 mutex_unlock(&hash_mutex);
1643 return -ENOMEM;
1644 }
1645 spin_lock_init(&i->lock);
1646 i->irq = up->port.irq;
1647 hlist_add_head(&i->node, h);
1648 }
1649 mutex_unlock(&hash_mutex);
1650
1651 spin_lock_irq(&i->lock);
1652
1653 if (i->head) {
1654 list_add(&up->list, i->head);
1655 spin_unlock_irq(&i->lock);
1656
1657 ret = 0;
1658 } else {
1659 INIT_LIST_HEAD(&up->list);
1660 i->head = &up->list;
1661 spin_unlock_irq(&i->lock);
1662
1663 ret = request_irq(up->port.irq, serial8250_interrupt,
1664 irq_flags, "serial", i);
1665 if (ret < 0)
1666 serial_do_unlink(i, up);
1667 }
1668
1669 return ret;
1670 }
1671
1672 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1673 {
1674 struct irq_info *i;
1675 struct hlist_node *n;
1676 struct hlist_head *h;
1677
1678 mutex_lock(&hash_mutex);
1679
1680 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1681
1682 hlist_for_each(n, h) {
1683 i = hlist_entry(n, struct irq_info, node);
1684 if (i->irq == up->port.irq)
1685 break;
1686 }
1687
1688 BUG_ON(n == NULL);
1689 BUG_ON(i->head == NULL);
1690
1691 if (list_empty(i->head))
1692 free_irq(up->port.irq, i);
1693
1694 serial_do_unlink(i, up);
1695 mutex_unlock(&hash_mutex);
1696 }
1697
1698 /* Base timer interval for polling */
1699 static inline int poll_timeout(int timeout)
1700 {
1701 return timeout > 6 ? (timeout / 2 - 2) : 1;
1702 }
1703
1704 /*
1705 * This function is used to handle ports that do not have an
1706 * interrupt. This doesn't work very well for 16450's, but gives
1707 * barely passable results for a 16550A. (Although at the expense
1708 * of much CPU overhead).
1709 */
1710 static void serial8250_timeout(unsigned long data)
1711 {
1712 struct uart_8250_port *up = (struct uart_8250_port *)data;
1713 unsigned int iir;
1714
1715 iir = serial_in(up, UART_IIR);
1716 if (!(iir & UART_IIR_NO_INT))
1717 serial8250_handle_port(up);
1718 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1719 }
1720
1721 static void serial8250_backup_timeout(unsigned long data)
1722 {
1723 struct uart_8250_port *up = (struct uart_8250_port *)data;
1724 unsigned int iir, ier = 0, lsr;
1725 unsigned long flags;
1726
1727 /*
1728 * Must disable interrupts or else we risk racing with the interrupt
1729 * based handler.
1730 */
1731 if (is_real_interrupt(up->port.irq)) {
1732 ier = serial_in(up, UART_IER);
1733 serial_out(up, UART_IER, 0);
1734 }
1735
1736 iir = serial_in(up, UART_IIR);
1737
1738 /*
1739 * This should be a safe test for anyone who doesn't trust the
1740 * IIR bits on their UART, but it's specifically designed for
1741 * the "Diva" UART used on the management processor on many HP
1742 * ia64 and parisc boxes.
1743 */
1744 spin_lock_irqsave(&up->port.lock, flags);
1745 lsr = serial_in(up, UART_LSR);
1746 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1747 spin_unlock_irqrestore(&up->port.lock, flags);
1748 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1749 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1750 (lsr & UART_LSR_THRE)) {
1751 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1752 iir |= UART_IIR_THRI;
1753 }
1754
1755 if (!(iir & UART_IIR_NO_INT))
1756 serial8250_handle_port(up);
1757
1758 if (is_real_interrupt(up->port.irq))
1759 serial_out(up, UART_IER, ier);
1760
1761 /* Standard timer interval plus 0.2s to keep the port running */
1762 mod_timer(&up->timer,
1763 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1764 }
1765
1766 static unsigned int serial8250_tx_empty(struct uart_port *port)
1767 {
1768 struct uart_8250_port *up = (struct uart_8250_port *)port;
1769 unsigned long flags;
1770 unsigned int lsr;
1771
1772 spin_lock_irqsave(&up->port.lock, flags);
1773 lsr = serial_in(up, UART_LSR);
1774 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1775 spin_unlock_irqrestore(&up->port.lock, flags);
1776
1777 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1778 }
1779
1780 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1781 {
1782 struct uart_8250_port *up = (struct uart_8250_port *)port;
1783 unsigned int status;
1784 unsigned int ret;
1785
1786 status = check_modem_status(up);
1787
1788 ret = 0;
1789 if (status & UART_MSR_DCD)
1790 ret |= TIOCM_CAR;
1791 if (status & UART_MSR_RI)
1792 ret |= TIOCM_RNG;
1793 if (status & UART_MSR_DSR)
1794 ret |= TIOCM_DSR;
1795 if (status & UART_MSR_CTS)
1796 ret |= TIOCM_CTS;
1797 return ret;
1798 }
1799
1800 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1801 {
1802 struct uart_8250_port *up = (struct uart_8250_port *)port;
1803 unsigned char mcr = 0;
1804
1805 if (mctrl & TIOCM_RTS)
1806 mcr |= UART_MCR_RTS;
1807 if (mctrl & TIOCM_DTR)
1808 mcr |= UART_MCR_DTR;
1809 if (mctrl & TIOCM_OUT1)
1810 mcr |= UART_MCR_OUT1;
1811 if (mctrl & TIOCM_OUT2)
1812 mcr |= UART_MCR_OUT2;
1813 if (mctrl & TIOCM_LOOP)
1814 mcr |= UART_MCR_LOOP;
1815
1816 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1817
1818 serial_out(up, UART_MCR, mcr);
1819 }
1820
1821 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1822 {
1823 struct uart_8250_port *up = (struct uart_8250_port *)port;
1824 unsigned long flags;
1825
1826 spin_lock_irqsave(&up->port.lock, flags);
1827 if (break_state == -1)
1828 up->lcr |= UART_LCR_SBC;
1829 else
1830 up->lcr &= ~UART_LCR_SBC;
1831 serial_out(up, UART_LCR, up->lcr);
1832 spin_unlock_irqrestore(&up->port.lock, flags);
1833 }
1834
1835 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1836
1837 /*
1838 * Wait for transmitter & holding register to empty
1839 */
1840 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1841 {
1842 unsigned int status, tmout = 10000;
1843
1844 /* Wait up to 10ms for the character(s) to be sent. */
1845 do {
1846 status = serial_in(up, UART_LSR);
1847
1848 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1849
1850 if (--tmout == 0)
1851 break;
1852 udelay(1);
1853 } while ((status & bits) != bits);
1854
1855 /* Wait up to 1s for flow control if necessary */
1856 if (up->port.flags & UPF_CONS_FLOW) {
1857 unsigned int tmout;
1858 for (tmout = 1000000; tmout; tmout--) {
1859 unsigned int msr = serial_in(up, UART_MSR);
1860 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1861 if (msr & UART_MSR_CTS)
1862 break;
1863 udelay(1);
1864 touch_nmi_watchdog();
1865 }
1866 }
1867 }
1868
1869 #ifdef CONFIG_CONSOLE_POLL
1870 /*
1871 * Console polling routines for writing and reading from the uart while
1872 * in an interrupt or debug context.
1873 */
1874
1875 static int serial8250_get_poll_char(struct uart_port *port)
1876 {
1877 struct uart_8250_port *up = (struct uart_8250_port *)port;
1878 unsigned char lsr = serial_inp(up, UART_LSR);
1879
1880 while (!(lsr & UART_LSR_DR))
1881 lsr = serial_inp(up, UART_LSR);
1882
1883 return serial_inp(up, UART_RX);
1884 }
1885
1886
1887 static void serial8250_put_poll_char(struct uart_port *port,
1888 unsigned char c)
1889 {
1890 unsigned int ier;
1891 struct uart_8250_port *up = (struct uart_8250_port *)port;
1892
1893 /*
1894 * First save the IER then disable the interrupts
1895 */
1896 ier = serial_in(up, UART_IER);
1897 if (up->capabilities & UART_CAP_UUE)
1898 serial_out(up, UART_IER, UART_IER_UUE);
1899 else
1900 serial_out(up, UART_IER, 0);
1901
1902 wait_for_xmitr(up, BOTH_EMPTY);
1903 /*
1904 * Send the character out.
1905 * If a LF, also do CR...
1906 */
1907 serial_out(up, UART_TX, c);
1908 if (c == 10) {
1909 wait_for_xmitr(up, BOTH_EMPTY);
1910 serial_out(up, UART_TX, 13);
1911 }
1912
1913 /*
1914 * Finally, wait for transmitter to become empty
1915 * and restore the IER
1916 */
1917 wait_for_xmitr(up, BOTH_EMPTY);
1918 serial_out(up, UART_IER, ier);
1919 }
1920
1921 #endif /* CONFIG_CONSOLE_POLL */
1922
1923 static int serial8250_startup(struct uart_port *port)
1924 {
1925 struct uart_8250_port *up = (struct uart_8250_port *)port;
1926 unsigned long flags;
1927 unsigned char lsr, iir;
1928 int retval;
1929
1930 up->capabilities = uart_config[up->port.type].flags;
1931 up->mcr = 0;
1932
1933 if (up->port.type == PORT_16C950) {
1934 /* Wake up and initialize UART */
1935 up->acr = 0;
1936 serial_outp(up, UART_LCR, 0xBF);
1937 serial_outp(up, UART_EFR, UART_EFR_ECB);
1938 serial_outp(up, UART_IER, 0);
1939 serial_outp(up, UART_LCR, 0);
1940 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1941 serial_outp(up, UART_LCR, 0xBF);
1942 serial_outp(up, UART_EFR, UART_EFR_ECB);
1943 serial_outp(up, UART_LCR, 0);
1944 }
1945
1946 #ifdef CONFIG_SERIAL_8250_RSA
1947 /*
1948 * If this is an RSA port, see if we can kick it up to the
1949 * higher speed clock.
1950 */
1951 enable_rsa(up);
1952 #endif
1953
1954 /*
1955 * Clear the FIFO buffers and disable them.
1956 * (they will be reenabled in set_termios())
1957 */
1958 serial8250_clear_fifos(up);
1959
1960 /*
1961 * Clear the interrupt registers.
1962 */
1963 (void) serial_inp(up, UART_LSR);
1964 (void) serial_inp(up, UART_RX);
1965 (void) serial_inp(up, UART_IIR);
1966 (void) serial_inp(up, UART_MSR);
1967
1968 /*
1969 * At this point, there's no way the LSR could still be 0xff;
1970 * if it is, then bail out, because there's likely no UART
1971 * here.
1972 */
1973 if (!(up->port.flags & UPF_BUGGY_UART) &&
1974 (serial_inp(up, UART_LSR) == 0xff)) {
1975 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1976 serial_index(&up->port));
1977 return -ENODEV;
1978 }
1979
1980 /*
1981 * For a XR16C850, we need to set the trigger levels
1982 */
1983 if (up->port.type == PORT_16850) {
1984 unsigned char fctr;
1985
1986 serial_outp(up, UART_LCR, 0xbf);
1987
1988 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1989 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1990 serial_outp(up, UART_TRG, UART_TRG_96);
1991 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1992 serial_outp(up, UART_TRG, UART_TRG_96);
1993
1994 serial_outp(up, UART_LCR, 0);
1995 }
1996
1997 if (is_real_interrupt(up->port.irq)) {
1998 unsigned char iir1;
1999 /*
2000 * Test for UARTs that do not reassert THRE when the
2001 * transmitter is idle and the interrupt has already
2002 * been cleared. Real 16550s should always reassert
2003 * this interrupt whenever the transmitter is idle and
2004 * the interrupt is enabled. Delays are necessary to
2005 * allow register changes to become visible.
2006 */
2007 spin_lock_irqsave(&up->port.lock, flags);
2008 if (up->port.flags & UPF_SHARE_IRQ)
2009 disable_irq_nosync(up->port.irq);
2010
2011 wait_for_xmitr(up, UART_LSR_THRE);
2012 serial_out_sync(up, UART_IER, UART_IER_THRI);
2013 udelay(1); /* allow THRE to set */
2014 iir1 = serial_in(up, UART_IIR);
2015 serial_out(up, UART_IER, 0);
2016 serial_out_sync(up, UART_IER, UART_IER_THRI);
2017 udelay(1); /* allow a working UART time to re-assert THRE */
2018 iir = serial_in(up, UART_IIR);
2019 serial_out(up, UART_IER, 0);
2020
2021 if (up->port.flags & UPF_SHARE_IRQ)
2022 enable_irq(up->port.irq);
2023 spin_unlock_irqrestore(&up->port.lock, flags);
2024
2025 /*
2026 * If the interrupt is not reasserted, setup a timer to
2027 * kick the UART on a regular basis.
2028 */
2029 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2030 up->bugs |= UART_BUG_THRE;
2031 pr_debug("ttyS%d - using backup timer\n",
2032 serial_index(port));
2033 }
2034 }
2035
2036 /*
2037 * The above check will only give an accurate result the first time
2038 * the port is opened so this value needs to be preserved.
2039 */
2040 if (up->bugs & UART_BUG_THRE) {
2041 up->timer.function = serial8250_backup_timeout;
2042 up->timer.data = (unsigned long)up;
2043 mod_timer(&up->timer, jiffies +
2044 poll_timeout(up->port.timeout) + HZ / 5);
2045 }
2046
2047 /*
2048 * If the "interrupt" for this port doesn't correspond with any
2049 * hardware interrupt, we use a timer-based system. The original
2050 * driver used to do this with IRQ0.
2051 */
2052 if (!is_real_interrupt(up->port.irq)) {
2053 up->timer.data = (unsigned long)up;
2054 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2055 } else {
2056 retval = serial_link_irq_chain(up);
2057 if (retval)
2058 return retval;
2059 }
2060
2061 /*
2062 * Now, initialize the UART
2063 */
2064 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2065
2066 spin_lock_irqsave(&up->port.lock, flags);
2067 if (up->port.flags & UPF_FOURPORT) {
2068 if (!is_real_interrupt(up->port.irq))
2069 up->port.mctrl |= TIOCM_OUT1;
2070 } else
2071 /*
2072 * Most PC uarts need OUT2 raised to enable interrupts.
2073 */
2074 if (is_real_interrupt(up->port.irq))
2075 up->port.mctrl |= TIOCM_OUT2;
2076
2077 serial8250_set_mctrl(&up->port, up->port.mctrl);
2078
2079 /*
2080 * Do a quick test to see if we receive an
2081 * interrupt when we enable the TX irq.
2082 */
2083 serial_outp(up, UART_IER, UART_IER_THRI);
2084 lsr = serial_in(up, UART_LSR);
2085 iir = serial_in(up, UART_IIR);
2086 serial_outp(up, UART_IER, 0);
2087
2088 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2089 if (!(up->bugs & UART_BUG_TXEN)) {
2090 up->bugs |= UART_BUG_TXEN;
2091 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2092 serial_index(port));
2093 }
2094 } else {
2095 up->bugs &= ~UART_BUG_TXEN;
2096 }
2097
2098 spin_unlock_irqrestore(&up->port.lock, flags);
2099
2100 /*
2101 * Clear the interrupt registers again for luck, and clear the
2102 * saved flags to avoid getting false values from polling
2103 * routines or the previous session.
2104 */
2105 serial_inp(up, UART_LSR);
2106 serial_inp(up, UART_RX);
2107 serial_inp(up, UART_IIR);
2108 serial_inp(up, UART_MSR);
2109 up->lsr_saved_flags = 0;
2110 up->msr_saved_flags = 0;
2111
2112 /*
2113 * Finally, enable interrupts. Note: Modem status interrupts
2114 * are set via set_termios(), which will be occurring imminently
2115 * anyway, so we don't enable them here.
2116 */
2117 up->ier = UART_IER_RLSI | UART_IER_RDI;
2118 serial_outp(up, UART_IER, up->ier);
2119
2120 if (up->port.flags & UPF_FOURPORT) {
2121 unsigned int icp;
2122 /*
2123 * Enable interrupts on the AST Fourport board
2124 */
2125 icp = (up->port.iobase & 0xfe0) | 0x01f;
2126 outb_p(0x80, icp);
2127 (void) inb_p(icp);
2128 }
2129
2130 return 0;
2131 }
2132
2133 static void serial8250_shutdown(struct uart_port *port)
2134 {
2135 struct uart_8250_port *up = (struct uart_8250_port *)port;
2136 unsigned long flags;
2137
2138 /*
2139 * Disable interrupts from this port
2140 */
2141 up->ier = 0;
2142 serial_outp(up, UART_IER, 0);
2143
2144 spin_lock_irqsave(&up->port.lock, flags);
2145 if (up->port.flags & UPF_FOURPORT) {
2146 /* reset interrupts on the AST Fourport board */
2147 inb((up->port.iobase & 0xfe0) | 0x1f);
2148 up->port.mctrl |= TIOCM_OUT1;
2149 } else
2150 up->port.mctrl &= ~TIOCM_OUT2;
2151
2152 serial8250_set_mctrl(&up->port, up->port.mctrl);
2153 spin_unlock_irqrestore(&up->port.lock, flags);
2154
2155 /*
2156 * Disable break condition and FIFOs
2157 */
2158 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2159 serial8250_clear_fifos(up);
2160
2161 #ifdef CONFIG_SERIAL_8250_RSA
2162 /*
2163 * Reset the RSA board back to 115kbps compat mode.
2164 */
2165 disable_rsa(up);
2166 #endif
2167
2168 /*
2169 * Read data port to reset things, and then unlink from
2170 * the IRQ chain.
2171 */
2172 (void) serial_in(up, UART_RX);
2173
2174 del_timer_sync(&up->timer);
2175 up->timer.function = serial8250_timeout;
2176 if (is_real_interrupt(up->port.irq))
2177 serial_unlink_irq_chain(up);
2178 }
2179
2180 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2181 {
2182 unsigned int quot;
2183
2184 /*
2185 * Handle magic divisors for baud rates above baud_base on
2186 * SMSC SuperIO chips.
2187 */
2188 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2189 baud == (port->uartclk/4))
2190 quot = 0x8001;
2191 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2192 baud == (port->uartclk/8))
2193 quot = 0x8002;
2194 else
2195 quot = uart_get_divisor(port, baud);
2196
2197 return quot;
2198 }
2199
2200 static void
2201 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2202 struct ktermios *old)
2203 {
2204 struct uart_8250_port *up = (struct uart_8250_port *)port;
2205 unsigned char cval, fcr = 0;
2206 unsigned long flags;
2207 unsigned int baud, quot;
2208
2209 switch (termios->c_cflag & CSIZE) {
2210 case CS5:
2211 cval = UART_LCR_WLEN5;
2212 break;
2213 case CS6:
2214 cval = UART_LCR_WLEN6;
2215 break;
2216 case CS7:
2217 cval = UART_LCR_WLEN7;
2218 break;
2219 default:
2220 case CS8:
2221 cval = UART_LCR_WLEN8;
2222 break;
2223 }
2224
2225 if (termios->c_cflag & CSTOPB)
2226 cval |= UART_LCR_STOP;
2227 if (termios->c_cflag & PARENB)
2228 cval |= UART_LCR_PARITY;
2229 if (!(termios->c_cflag & PARODD))
2230 cval |= UART_LCR_EPAR;
2231 #ifdef CMSPAR
2232 if (termios->c_cflag & CMSPAR)
2233 cval |= UART_LCR_SPAR;
2234 #endif
2235
2236 /*
2237 * Ask the core to calculate the divisor for us.
2238 */
2239 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2240 quot = serial8250_get_divisor(port, baud);
2241
2242 /*
2243 * Oxford Semi 952 rev B workaround
2244 */
2245 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2246 quot++;
2247
2248 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2249 if (baud < 2400)
2250 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2251 else
2252 fcr = uart_config[up->port.type].fcr;
2253 }
2254
2255 /*
2256 * MCR-based auto flow control. When AFE is enabled, RTS will be
2257 * deasserted when the receive FIFO contains more characters than
2258 * the trigger, or the MCR RTS bit is cleared. In the case where
2259 * the remote UART is not using CTS auto flow control, we must
2260 * have sufficient FIFO entries for the latency of the remote
2261 * UART to respond. IOW, at least 32 bytes of FIFO.
2262 */
2263 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2264 up->mcr &= ~UART_MCR_AFE;
2265 if (termios->c_cflag & CRTSCTS)
2266 up->mcr |= UART_MCR_AFE;
2267 }
2268
2269 /*
2270 * Ok, we're now changing the port state. Do it with
2271 * interrupts disabled.
2272 */
2273 spin_lock_irqsave(&up->port.lock, flags);
2274
2275 /*
2276 * Update the per-port timeout.
2277 */
2278 uart_update_timeout(port, termios->c_cflag, baud);
2279
2280 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2281 if (termios->c_iflag & INPCK)
2282 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2283 if (termios->c_iflag & (BRKINT | PARMRK))
2284 up->port.read_status_mask |= UART_LSR_BI;
2285
2286 /*
2287 * Characteres to ignore
2288 */
2289 up->port.ignore_status_mask = 0;
2290 if (termios->c_iflag & IGNPAR)
2291 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2292 if (termios->c_iflag & IGNBRK) {
2293 up->port.ignore_status_mask |= UART_LSR_BI;
2294 /*
2295 * If we're ignoring parity and break indicators,
2296 * ignore overruns too (for real raw support).
2297 */
2298 if (termios->c_iflag & IGNPAR)
2299 up->port.ignore_status_mask |= UART_LSR_OE;
2300 }
2301
2302 /*
2303 * ignore all characters if CREAD is not set
2304 */
2305 if ((termios->c_cflag & CREAD) == 0)
2306 up->port.ignore_status_mask |= UART_LSR_DR;
2307
2308 /*
2309 * CTS flow control flag and modem status interrupts
2310 */
2311 up->ier &= ~UART_IER_MSI;
2312 if (!(up->bugs & UART_BUG_NOMSR) &&
2313 UART_ENABLE_MS(&up->port, termios->c_cflag))
2314 up->ier |= UART_IER_MSI;
2315 if (up->capabilities & UART_CAP_UUE)
2316 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2317
2318 serial_out(up, UART_IER, up->ier);
2319
2320 if (up->capabilities & UART_CAP_EFR) {
2321 unsigned char efr = 0;
2322 /*
2323 * TI16C752/Startech hardware flow control. FIXME:
2324 * - TI16C752 requires control thresholds to be set.
2325 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2326 */
2327 if (termios->c_cflag & CRTSCTS)
2328 efr |= UART_EFR_CTS;
2329
2330 serial_outp(up, UART_LCR, 0xBF);
2331 serial_outp(up, UART_EFR, efr);
2332 }
2333
2334 #ifdef CONFIG_ARCH_OMAP
2335 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2336 if (cpu_is_omap1510() && is_omap_port(up)) {
2337 if (baud == 115200) {
2338 quot = 1;
2339 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2340 } else
2341 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2342 }
2343 #endif
2344
2345 if (up->capabilities & UART_NATSEMI) {
2346 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2347 serial_outp(up, UART_LCR, 0xe0);
2348 } else {
2349 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2350 }
2351
2352 serial_dl_write(up, quot);
2353
2354 /*
2355 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2356 * is written without DLAB set, this mode will be disabled.
2357 */
2358 if (up->port.type == PORT_16750)
2359 serial_outp(up, UART_FCR, fcr);
2360
2361 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2362 up->lcr = cval; /* Save LCR */
2363 if (up->port.type != PORT_16750) {
2364 if (fcr & UART_FCR_ENABLE_FIFO) {
2365 /* emulated UARTs (Lucent Venus 167x) need two steps */
2366 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2367 }
2368 serial_outp(up, UART_FCR, fcr); /* set fcr */
2369 }
2370 serial8250_set_mctrl(&up->port, up->port.mctrl);
2371 spin_unlock_irqrestore(&up->port.lock, flags);
2372 /* Don't rewrite B0 */
2373 if (tty_termios_baud_rate(termios))
2374 tty_termios_encode_baud_rate(termios, baud, baud);
2375 }
2376
2377 static void
2378 serial8250_pm(struct uart_port *port, unsigned int state,
2379 unsigned int oldstate)
2380 {
2381 struct uart_8250_port *p = (struct uart_8250_port *)port;
2382
2383 serial8250_set_sleep(p, state != 0);
2384
2385 if (p->pm)
2386 p->pm(port, state, oldstate);
2387 }
2388
2389 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2390 {
2391 if (pt->port.iotype == UPIO_AU)
2392 return 0x100000;
2393 #ifdef CONFIG_ARCH_OMAP
2394 if (is_omap_port(pt))
2395 return 0x16 << pt->port.regshift;
2396 #endif
2397 return 8 << pt->port.regshift;
2398 }
2399
2400 /*
2401 * Resource handling.
2402 */
2403 static int serial8250_request_std_resource(struct uart_8250_port *up)
2404 {
2405 unsigned int size = serial8250_port_size(up);
2406 int ret = 0;
2407
2408 switch (up->port.iotype) {
2409 case UPIO_AU:
2410 case UPIO_TSI:
2411 case UPIO_MEM32:
2412 case UPIO_MEM:
2413 case UPIO_DWAPB:
2414 if (!up->port.mapbase)
2415 break;
2416
2417 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2418 ret = -EBUSY;
2419 break;
2420 }
2421
2422 if (up->port.flags & UPF_IOREMAP) {
2423 up->port.membase = ioremap_nocache(up->port.mapbase,
2424 size);
2425 if (!up->port.membase) {
2426 release_mem_region(up->port.mapbase, size);
2427 ret = -ENOMEM;
2428 }
2429 }
2430 break;
2431
2432 case UPIO_HUB6:
2433 case UPIO_PORT:
2434 if (!request_region(up->port.iobase, size, "serial"))
2435 ret = -EBUSY;
2436 break;
2437 }
2438 return ret;
2439 }
2440
2441 static void serial8250_release_std_resource(struct uart_8250_port *up)
2442 {
2443 unsigned int size = serial8250_port_size(up);
2444
2445 switch (up->port.iotype) {
2446 case UPIO_AU:
2447 case UPIO_TSI:
2448 case UPIO_MEM32:
2449 case UPIO_MEM:
2450 case UPIO_DWAPB:
2451 if (!up->port.mapbase)
2452 break;
2453
2454 if (up->port.flags & UPF_IOREMAP) {
2455 iounmap(up->port.membase);
2456 up->port.membase = NULL;
2457 }
2458
2459 release_mem_region(up->port.mapbase, size);
2460 break;
2461
2462 case UPIO_HUB6:
2463 case UPIO_PORT:
2464 release_region(up->port.iobase, size);
2465 break;
2466 }
2467 }
2468
2469 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2470 {
2471 unsigned long start = UART_RSA_BASE << up->port.regshift;
2472 unsigned int size = 8 << up->port.regshift;
2473 int ret = -EINVAL;
2474
2475 switch (up->port.iotype) {
2476 case UPIO_HUB6:
2477 case UPIO_PORT:
2478 start += up->port.iobase;
2479 if (request_region(start, size, "serial-rsa"))
2480 ret = 0;
2481 else
2482 ret = -EBUSY;
2483 break;
2484 }
2485
2486 return ret;
2487 }
2488
2489 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2490 {
2491 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2492 unsigned int size = 8 << up->port.regshift;
2493
2494 switch (up->port.iotype) {
2495 case UPIO_HUB6:
2496 case UPIO_PORT:
2497 release_region(up->port.iobase + offset, size);
2498 break;
2499 }
2500 }
2501
2502 static void serial8250_release_port(struct uart_port *port)
2503 {
2504 struct uart_8250_port *up = (struct uart_8250_port *)port;
2505
2506 serial8250_release_std_resource(up);
2507 if (up->port.type == PORT_RSA)
2508 serial8250_release_rsa_resource(up);
2509 }
2510
2511 static int serial8250_request_port(struct uart_port *port)
2512 {
2513 struct uart_8250_port *up = (struct uart_8250_port *)port;
2514 int ret = 0;
2515
2516 ret = serial8250_request_std_resource(up);
2517 if (ret == 0 && up->port.type == PORT_RSA) {
2518 ret = serial8250_request_rsa_resource(up);
2519 if (ret < 0)
2520 serial8250_release_std_resource(up);
2521 }
2522
2523 return ret;
2524 }
2525
2526 static void serial8250_config_port(struct uart_port *port, int flags)
2527 {
2528 struct uart_8250_port *up = (struct uart_8250_port *)port;
2529 int probeflags = PROBE_ANY;
2530 int ret;
2531
2532 /*
2533 * Find the region that we can probe for. This in turn
2534 * tells us whether we can probe for the type of port.
2535 */
2536 ret = serial8250_request_std_resource(up);
2537 if (ret < 0)
2538 return;
2539
2540 ret = serial8250_request_rsa_resource(up);
2541 if (ret < 0)
2542 probeflags &= ~PROBE_RSA;
2543
2544 if (flags & UART_CONFIG_TYPE)
2545 autoconfig(up, probeflags);
2546 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2547 autoconfig_irq(up);
2548
2549 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2550 serial8250_release_rsa_resource(up);
2551 if (up->port.type == PORT_UNKNOWN)
2552 serial8250_release_std_resource(up);
2553 }
2554
2555 static int
2556 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2557 {
2558 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2559 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2560 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2561 ser->type == PORT_STARTECH)
2562 return -EINVAL;
2563 return 0;
2564 }
2565
2566 static const char *
2567 serial8250_type(struct uart_port *port)
2568 {
2569 int type = port->type;
2570
2571 if (type >= ARRAY_SIZE(uart_config))
2572 type = 0;
2573 return uart_config[type].name;
2574 }
2575
2576 static struct uart_ops serial8250_pops = {
2577 .tx_empty = serial8250_tx_empty,
2578 .set_mctrl = serial8250_set_mctrl,
2579 .get_mctrl = serial8250_get_mctrl,
2580 .stop_tx = serial8250_stop_tx,
2581 .start_tx = serial8250_start_tx,
2582 .stop_rx = serial8250_stop_rx,
2583 .enable_ms = serial8250_enable_ms,
2584 .break_ctl = serial8250_break_ctl,
2585 .startup = serial8250_startup,
2586 .shutdown = serial8250_shutdown,
2587 .set_termios = serial8250_set_termios,
2588 .pm = serial8250_pm,
2589 .type = serial8250_type,
2590 .release_port = serial8250_release_port,
2591 .request_port = serial8250_request_port,
2592 .config_port = serial8250_config_port,
2593 .verify_port = serial8250_verify_port,
2594 #ifdef CONFIG_CONSOLE_POLL
2595 .poll_get_char = serial8250_get_poll_char,
2596 .poll_put_char = serial8250_put_poll_char,
2597 #endif
2598 };
2599
2600 static struct uart_8250_port serial8250_ports[UART_NR];
2601
2602 static void __init serial8250_isa_init_ports(void)
2603 {
2604 struct uart_8250_port *up;
2605 static int first = 1;
2606 int i;
2607
2608 if (!first)
2609 return;
2610 first = 0;
2611
2612 for (i = 0; i < nr_uarts; i++) {
2613 struct uart_8250_port *up = &serial8250_ports[i];
2614
2615 up->port.line = i;
2616 spin_lock_init(&up->port.lock);
2617
2618 init_timer(&up->timer);
2619 up->timer.function = serial8250_timeout;
2620
2621 /*
2622 * ALPHA_KLUDGE_MCR needs to be killed.
2623 */
2624 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2625 up->mcr_force = ALPHA_KLUDGE_MCR;
2626
2627 up->port.ops = &serial8250_pops;
2628 }
2629
2630 for (i = 0, up = serial8250_ports;
2631 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2632 i++, up++) {
2633 up->port.iobase = old_serial_port[i].port;
2634 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2635 up->port.uartclk = old_serial_port[i].baud_base * 16;
2636 up->port.flags = old_serial_port[i].flags;
2637 up->port.hub6 = old_serial_port[i].hub6;
2638 up->port.membase = old_serial_port[i].iomem_base;
2639 up->port.iotype = old_serial_port[i].io_type;
2640 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2641 set_io_from_upio(&up->port);
2642 if (share_irqs)
2643 up->port.flags |= UPF_SHARE_IRQ;
2644 }
2645 }
2646
2647 static void __init
2648 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2649 {
2650 int i;
2651
2652 serial8250_isa_init_ports();
2653
2654 for (i = 0; i < nr_uarts; i++) {
2655 struct uart_8250_port *up = &serial8250_ports[i];
2656
2657 up->port.dev = dev;
2658 uart_add_one_port(drv, &up->port);
2659 }
2660 }
2661
2662 #ifdef CONFIG_SERIAL_8250_CONSOLE
2663
2664 static void serial8250_console_putchar(struct uart_port *port, int ch)
2665 {
2666 struct uart_8250_port *up = (struct uart_8250_port *)port;
2667
2668 wait_for_xmitr(up, UART_LSR_THRE);
2669 serial_out(up, UART_TX, ch);
2670 }
2671
2672 /*
2673 * Print a string to the serial port trying not to disturb
2674 * any possible real use of the port...
2675 *
2676 * The console_lock must be held when we get here.
2677 */
2678 static void
2679 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2680 {
2681 struct uart_8250_port *up = &serial8250_ports[co->index];
2682 unsigned long flags;
2683 unsigned int ier;
2684 int locked = 1;
2685
2686 touch_nmi_watchdog();
2687
2688 local_irq_save(flags);
2689 if (up->port.sysrq) {
2690 /* serial8250_handle_port() already took the lock */
2691 locked = 0;
2692 } else if (oops_in_progress) {
2693 locked = spin_trylock(&up->port.lock);
2694 } else
2695 spin_lock(&up->port.lock);
2696
2697 /*
2698 * First save the IER then disable the interrupts
2699 */
2700 ier = serial_in(up, UART_IER);
2701
2702 if (up->capabilities & UART_CAP_UUE)
2703 serial_out(up, UART_IER, UART_IER_UUE);
2704 else
2705 serial_out(up, UART_IER, 0);
2706
2707 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2708
2709 /*
2710 * Finally, wait for transmitter to become empty
2711 * and restore the IER
2712 */
2713 wait_for_xmitr(up, BOTH_EMPTY);
2714 serial_out(up, UART_IER, ier);
2715
2716 /*
2717 * The receive handling will happen properly because the
2718 * receive ready bit will still be set; it is not cleared
2719 * on read. However, modem control will not, we must
2720 * call it if we have saved something in the saved flags
2721 * while processing with interrupts off.
2722 */
2723 if (up->msr_saved_flags)
2724 check_modem_status(up);
2725
2726 if (locked)
2727 spin_unlock(&up->port.lock);
2728 local_irq_restore(flags);
2729 }
2730
2731 static int __init serial8250_console_setup(struct console *co, char *options)
2732 {
2733 struct uart_port *port;
2734 int baud = 9600;
2735 int bits = 8;
2736 int parity = 'n';
2737 int flow = 'n';
2738
2739 /*
2740 * Check whether an invalid uart number has been specified, and
2741 * if so, search for the first available port that does have
2742 * console support.
2743 */
2744 if (co->index >= nr_uarts)
2745 co->index = 0;
2746 port = &serial8250_ports[co->index].port;
2747 if (!port->iobase && !port->membase)
2748 return -ENODEV;
2749
2750 if (options)
2751 uart_parse_options(options, &baud, &parity, &bits, &flow);
2752
2753 return uart_set_options(port, co, baud, parity, bits, flow);
2754 }
2755
2756 static int serial8250_console_early_setup(void)
2757 {
2758 return serial8250_find_port_for_earlycon();
2759 }
2760
2761 static struct console serial8250_console = {
2762 .name = "ttyS",
2763 .write = serial8250_console_write,
2764 .device = uart_console_device,
2765 .setup = serial8250_console_setup,
2766 .early_setup = serial8250_console_early_setup,
2767 .flags = CON_PRINTBUFFER,
2768 .index = -1,
2769 .data = &serial8250_reg,
2770 };
2771
2772 static int __init serial8250_console_init(void)
2773 {
2774 if (nr_uarts > UART_NR)
2775 nr_uarts = UART_NR;
2776
2777 serial8250_isa_init_ports();
2778 register_console(&serial8250_console);
2779 return 0;
2780 }
2781 console_initcall(serial8250_console_init);
2782
2783 int serial8250_find_port(struct uart_port *p)
2784 {
2785 int line;
2786 struct uart_port *port;
2787
2788 for (line = 0; line < nr_uarts; line++) {
2789 port = &serial8250_ports[line].port;
2790 if (uart_match_port(p, port))
2791 return line;
2792 }
2793 return -ENODEV;
2794 }
2795
2796 #define SERIAL8250_CONSOLE &serial8250_console
2797 #else
2798 #define SERIAL8250_CONSOLE NULL
2799 #endif
2800
2801 static struct uart_driver serial8250_reg = {
2802 .owner = THIS_MODULE,
2803 .driver_name = "serial",
2804 .dev_name = "ttyS",
2805 .major = TTY_MAJOR,
2806 .minor = 64,
2807 .cons = SERIAL8250_CONSOLE,
2808 };
2809
2810 /*
2811 * early_serial_setup - early registration for 8250 ports
2812 *
2813 * Setup an 8250 port structure prior to console initialisation. Use
2814 * after console initialisation will cause undefined behaviour.
2815 */
2816 int __init early_serial_setup(struct uart_port *port)
2817 {
2818 struct uart_port *p;
2819
2820 if (port->line >= ARRAY_SIZE(serial8250_ports))
2821 return -ENODEV;
2822
2823 serial8250_isa_init_ports();
2824 p = &serial8250_ports[port->line].port;
2825 p->iobase = port->iobase;
2826 p->membase = port->membase;
2827 p->irq = port->irq;
2828 p->uartclk = port->uartclk;
2829 p->fifosize = port->fifosize;
2830 p->regshift = port->regshift;
2831 p->iotype = port->iotype;
2832 p->flags = port->flags;
2833 p->mapbase = port->mapbase;
2834 p->private_data = port->private_data;
2835
2836 set_io_from_upio(p);
2837 if (port->serial_in)
2838 p->serial_in = port->serial_in;
2839 if (port->serial_out)
2840 p->serial_out = port->serial_out;
2841
2842 return 0;
2843 }
2844
2845 /**
2846 * serial8250_suspend_port - suspend one serial port
2847 * @line: serial line number
2848 *
2849 * Suspend one serial port.
2850 */
2851 void serial8250_suspend_port(int line)
2852 {
2853 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2854 }
2855
2856 /**
2857 * serial8250_resume_port - resume one serial port
2858 * @line: serial line number
2859 *
2860 * Resume one serial port.
2861 */
2862 void serial8250_resume_port(int line)
2863 {
2864 struct uart_8250_port *up = &serial8250_ports[line];
2865
2866 if (up->capabilities & UART_NATSEMI) {
2867 unsigned char tmp;
2868
2869 /* Ensure it's still in high speed mode */
2870 serial_outp(up, UART_LCR, 0xE0);
2871
2872 tmp = serial_in(up, 0x04); /* EXCR2 */
2873 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2874 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2875 serial_outp(up, 0x04, tmp);
2876
2877 serial_outp(up, UART_LCR, 0);
2878 }
2879 uart_resume_port(&serial8250_reg, &up->port);
2880 }
2881
2882 /*
2883 * Register a set of serial devices attached to a platform device. The
2884 * list is terminated with a zero flags entry, which means we expect
2885 * all entries to have at least UPF_BOOT_AUTOCONF set.
2886 */
2887 static int __devinit serial8250_probe(struct platform_device *dev)
2888 {
2889 struct plat_serial8250_port *p = dev->dev.platform_data;
2890 struct uart_port port;
2891 int ret, i;
2892
2893 memset(&port, 0, sizeof(struct uart_port));
2894
2895 for (i = 0; p && p->flags != 0; p++, i++) {
2896 port.iobase = p->iobase;
2897 port.membase = p->membase;
2898 port.irq = p->irq;
2899 port.uartclk = p->uartclk;
2900 port.regshift = p->regshift;
2901 port.iotype = p->iotype;
2902 port.flags = p->flags;
2903 port.mapbase = p->mapbase;
2904 port.hub6 = p->hub6;
2905 port.private_data = p->private_data;
2906 port.type = p->type;
2907 port.serial_in = p->serial_in;
2908 port.serial_out = p->serial_out;
2909 port.dev = &dev->dev;
2910 if (share_irqs)
2911 port.flags |= UPF_SHARE_IRQ;
2912 ret = serial8250_register_port(&port);
2913 if (ret < 0) {
2914 dev_err(&dev->dev, "unable to register port at index %d "
2915 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2916 p->iobase, (unsigned long long)p->mapbase,
2917 p->irq, ret);
2918 }
2919 }
2920 return 0;
2921 }
2922
2923 /*
2924 * Remove serial ports registered against a platform device.
2925 */
2926 static int __devexit serial8250_remove(struct platform_device *dev)
2927 {
2928 int i;
2929
2930 for (i = 0; i < nr_uarts; i++) {
2931 struct uart_8250_port *up = &serial8250_ports[i];
2932
2933 if (up->port.dev == &dev->dev)
2934 serial8250_unregister_port(i);
2935 }
2936 return 0;
2937 }
2938
2939 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2940 {
2941 int i;
2942
2943 for (i = 0; i < UART_NR; i++) {
2944 struct uart_8250_port *up = &serial8250_ports[i];
2945
2946 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2947 uart_suspend_port(&serial8250_reg, &up->port);
2948 }
2949
2950 return 0;
2951 }
2952
2953 static int serial8250_resume(struct platform_device *dev)
2954 {
2955 int i;
2956
2957 for (i = 0; i < UART_NR; i++) {
2958 struct uart_8250_port *up = &serial8250_ports[i];
2959
2960 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2961 serial8250_resume_port(i);
2962 }
2963
2964 return 0;
2965 }
2966
2967 static struct platform_driver serial8250_isa_driver = {
2968 .probe = serial8250_probe,
2969 .remove = __devexit_p(serial8250_remove),
2970 .suspend = serial8250_suspend,
2971 .resume = serial8250_resume,
2972 .driver = {
2973 .name = "serial8250",
2974 .owner = THIS_MODULE,
2975 },
2976 };
2977
2978 /*
2979 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2980 * in the table in include/asm/serial.h
2981 */
2982 static struct platform_device *serial8250_isa_devs;
2983
2984 /*
2985 * serial8250_register_port and serial8250_unregister_port allows for
2986 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2987 * modems and PCI multiport cards.
2988 */
2989 static DEFINE_MUTEX(serial_mutex);
2990
2991 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2992 {
2993 int i;
2994
2995 /*
2996 * First, find a port entry which matches.
2997 */
2998 for (i = 0; i < nr_uarts; i++)
2999 if (uart_match_port(&serial8250_ports[i].port, port))
3000 return &serial8250_ports[i];
3001
3002 /*
3003 * We didn't find a matching entry, so look for the first
3004 * free entry. We look for one which hasn't been previously
3005 * used (indicated by zero iobase).
3006 */
3007 for (i = 0; i < nr_uarts; i++)
3008 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3009 serial8250_ports[i].port.iobase == 0)
3010 return &serial8250_ports[i];
3011
3012 /*
3013 * That also failed. Last resort is to find any entry which
3014 * doesn't have a real port associated with it.
3015 */
3016 for (i = 0; i < nr_uarts; i++)
3017 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3018 return &serial8250_ports[i];
3019
3020 return NULL;
3021 }
3022
3023 /**
3024 * serial8250_register_port - register a serial port
3025 * @port: serial port template
3026 *
3027 * Configure the serial port specified by the request. If the
3028 * port exists and is in use, it is hung up and unregistered
3029 * first.
3030 *
3031 * The port is then probed and if necessary the IRQ is autodetected
3032 * If this fails an error is returned.
3033 *
3034 * On success the port is ready to use and the line number is returned.
3035 */
3036 int serial8250_register_port(struct uart_port *port)
3037 {
3038 struct uart_8250_port *uart;
3039 int ret = -ENOSPC;
3040
3041 if (port->uartclk == 0)
3042 return -EINVAL;
3043
3044 mutex_lock(&serial_mutex);
3045
3046 uart = serial8250_find_match_or_unused(port);
3047 if (uart) {
3048 uart_remove_one_port(&serial8250_reg, &uart->port);
3049
3050 uart->port.iobase = port->iobase;
3051 uart->port.membase = port->membase;
3052 uart->port.irq = port->irq;
3053 uart->port.uartclk = port->uartclk;
3054 uart->port.fifosize = port->fifosize;
3055 uart->port.regshift = port->regshift;
3056 uart->port.iotype = port->iotype;
3057 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3058 uart->port.mapbase = port->mapbase;
3059 uart->port.private_data = port->private_data;
3060 if (port->dev)
3061 uart->port.dev = port->dev;
3062
3063 if (port->flags & UPF_FIXED_TYPE) {
3064 uart->port.type = port->type;
3065 uart->port.fifosize = uart_config[port->type].fifo_size;
3066 uart->capabilities = uart_config[port->type].flags;
3067 uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3068 }
3069
3070 set_io_from_upio(&uart->port);
3071 /* Possibly override default I/O functions. */
3072 if (port->serial_in)
3073 uart->port.serial_in = port->serial_in;
3074 if (port->serial_out)
3075 uart->port.serial_out = port->serial_out;
3076
3077 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3078 if (ret == 0)
3079 ret = uart->port.line;
3080 }
3081 mutex_unlock(&serial_mutex);
3082
3083 return ret;
3084 }
3085 EXPORT_SYMBOL(serial8250_register_port);
3086
3087 /**
3088 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3089 * @line: serial line number
3090 *
3091 * Remove one serial port. This may not be called from interrupt
3092 * context. We hand the port back to the our control.
3093 */
3094 void serial8250_unregister_port(int line)
3095 {
3096 struct uart_8250_port *uart = &serial8250_ports[line];
3097
3098 mutex_lock(&serial_mutex);
3099 uart_remove_one_port(&serial8250_reg, &uart->port);
3100 if (serial8250_isa_devs) {
3101 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3102 uart->port.type = PORT_UNKNOWN;
3103 uart->port.dev = &serial8250_isa_devs->dev;
3104 uart_add_one_port(&serial8250_reg, &uart->port);
3105 } else {
3106 uart->port.dev = NULL;
3107 }
3108 mutex_unlock(&serial_mutex);
3109 }
3110 EXPORT_SYMBOL(serial8250_unregister_port);
3111
3112 static int __init serial8250_init(void)
3113 {
3114 int ret;
3115
3116 if (nr_uarts > UART_NR)
3117 nr_uarts = UART_NR;
3118
3119 printk(KERN_INFO "Serial: 8250/16550 driver"
3120 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3121 share_irqs ? "en" : "dis");
3122
3123 #ifdef CONFIG_SPARC
3124 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3125 #else
3126 serial8250_reg.nr = UART_NR;
3127 ret = uart_register_driver(&serial8250_reg);
3128 #endif
3129 if (ret)
3130 goto out;
3131
3132 serial8250_isa_devs = platform_device_alloc("serial8250",
3133 PLAT8250_DEV_LEGACY);
3134 if (!serial8250_isa_devs) {
3135 ret = -ENOMEM;
3136 goto unreg_uart_drv;
3137 }
3138
3139 ret = platform_device_add(serial8250_isa_devs);
3140 if (ret)
3141 goto put_dev;
3142
3143 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3144
3145 ret = platform_driver_register(&serial8250_isa_driver);
3146 if (ret == 0)
3147 goto out;
3148
3149 platform_device_del(serial8250_isa_devs);
3150 put_dev:
3151 platform_device_put(serial8250_isa_devs);
3152 unreg_uart_drv:
3153 #ifdef CONFIG_SPARC
3154 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3155 #else
3156 uart_unregister_driver(&serial8250_reg);
3157 #endif
3158 out:
3159 return ret;
3160 }
3161
3162 static void __exit serial8250_exit(void)
3163 {
3164 struct platform_device *isa_dev = serial8250_isa_devs;
3165
3166 /*
3167 * This tells serial8250_unregister_port() not to re-register
3168 * the ports (thereby making serial8250_isa_driver permanently
3169 * in use.)
3170 */
3171 serial8250_isa_devs = NULL;
3172
3173 platform_driver_unregister(&serial8250_isa_driver);
3174 platform_device_unregister(isa_dev);
3175
3176 #ifdef CONFIG_SPARC
3177 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3178 #else
3179 uart_unregister_driver(&serial8250_reg);
3180 #endif
3181 }
3182
3183 module_init(serial8250_init);
3184 module_exit(serial8250_exit);
3185
3186 EXPORT_SYMBOL(serial8250_suspend_port);
3187 EXPORT_SYMBOL(serial8250_resume_port);
3188
3189 MODULE_LICENSE("GPL");
3190 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3191
3192 module_param(share_irqs, uint, 0644);
3193 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3194 " (unsafe)");
3195
3196 module_param(nr_uarts, uint, 0644);
3197 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3198
3199 #ifdef CONFIG_SERIAL_8250_RSA
3200 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3201 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3202 #endif
3203 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Support for the Chinese Samsung S3C2440 based development boards