1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/init.h>
4 #include <linux/module.h>
5 #include <linux/timer.h>
6 #include <linux/acpi_pmtmr.h>
7 #include <linux/cpufreq.h>
9 #include <linux/delay.h>
10 #include <linux/clocksource.h>
11 #include <linux/percpu.h>
14 #include <asm/timer.h>
15 #include <asm/vgtod.h>
17 #include <asm/delay.h>
18 #include <asm/hypervisor.h>
20 unsigned int cpu_khz
; /* TSC clocks / usec, not used here */
21 EXPORT_SYMBOL(cpu_khz
);
23 EXPORT_SYMBOL(tsc_khz
);
26 * TSC can be unstable due to cpufreq or due to unsynced TSCs
28 static int tsc_unstable
;
30 /* native_sched_clock() is called before tsc_init(), so
31 we must start with the TSC soft disabled to prevent
32 erroneous rdtsc usage on !cpu_has_tsc processors */
33 static int tsc_disabled
= -1;
36 * Scheduler clock - returns current time in nanosec units.
38 u64
native_sched_clock(void)
43 * Fall back to jiffies if there's no TSC available:
44 * ( But note that we still use it if the TSC is marked
45 * unstable. We do this because unlike Time Of Day,
46 * the scheduler clock tolerates small errors and it's
47 * very important for it to be as fast as the platform
50 if (unlikely(tsc_disabled
)) {
51 /* No locking but a rare wrong value is not a big deal: */
52 return (jiffies_64
- INITIAL_JIFFIES
) * (1000000000 / HZ
);
55 /* read the Time Stamp Counter: */
58 /* return the value in ns */
59 return cycles_2_ns(this_offset
);
62 /* We need to define a real function for sched_clock, to override the
63 weak default version */
64 #ifdef CONFIG_PARAVIRT
65 unsigned long long sched_clock(void)
67 return paravirt_sched_clock();
71 sched_clock(void) __attribute__((alias("native_sched_clock")));
74 int check_tsc_unstable(void)
78 EXPORT_SYMBOL_GPL(check_tsc_unstable
);
81 int __init
notsc_setup(char *str
)
83 printk(KERN_WARNING
"notsc: Kernel compiled with CONFIG_X86_TSC, "
84 "cannot disable TSC completely.\n");
90 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
93 int __init
notsc_setup(char *str
)
95 setup_clear_cpu_cap(X86_FEATURE_TSC
);
100 __setup("notsc", notsc_setup
);
102 #define MAX_RETRIES 5
103 #define SMI_TRESHOLD 50000
106 * Read TSC and the reference counters. Take care of SMI disturbance
108 static u64
tsc_read_refs(u64
*p
, int hpet
)
113 for (i
= 0; i
< MAX_RETRIES
; i
++) {
116 *p
= hpet_readl(HPET_COUNTER
) & 0xFFFFFFFF;
118 *p
= acpi_pm_read_early();
120 if ((t2
- t1
) < SMI_TRESHOLD
)
127 * Calculate the TSC frequency from HPET reference
129 static unsigned long calc_hpet_ref(u64 deltatsc
, u64 hpet1
, u64 hpet2
)
134 hpet2
+= 0x100000000ULL
;
136 tmp
= ((u64
)hpet2
* hpet_readl(HPET_PERIOD
));
137 do_div(tmp
, 1000000);
138 do_div(deltatsc
, tmp
);
140 return (unsigned long) deltatsc
;
144 * Calculate the TSC frequency from PMTimer reference
146 static unsigned long calc_pmtimer_ref(u64 deltatsc
, u64 pm1
, u64 pm2
)
154 pm2
+= (u64
)ACPI_PM_OVRRUN
;
156 tmp
= pm2
* 1000000000LL;
157 do_div(tmp
, PMTMR_TICKS_PER_SEC
);
158 do_div(deltatsc
, tmp
);
160 return (unsigned long) deltatsc
;
164 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
165 #define CAL_PIT_LOOPS 1000
168 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
169 #define CAL2_PIT_LOOPS 5000
173 * Try to calibrate the TSC against the Programmable
174 * Interrupt Timer and return the frequency of the TSC
177 * Return ULONG_MAX on failure to calibrate.
179 static unsigned long pit_calibrate_tsc(u32 latch
, unsigned long ms
, int loopmin
)
181 u64 tsc
, t1
, t2
, delta
;
182 unsigned long tscmin
, tscmax
;
185 /* Set the Gate high, disable speaker */
186 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
189 * Setup CTC channel 2* for mode 0, (interrupt on terminal
190 * count mode), binary count. Set the latch register to 50ms
191 * (LSB then MSB) to begin countdown.
194 outb(latch
& 0xff, 0x42);
195 outb(latch
>> 8, 0x42);
197 tsc
= t1
= t2
= get_cycles();
202 while ((inb(0x61) & 0x20) == 0) {
206 if ((unsigned long) delta
< tscmin
)
207 tscmin
= (unsigned int) delta
;
208 if ((unsigned long) delta
> tscmax
)
209 tscmax
= (unsigned int) delta
;
216 * If we were not able to read the PIT more than loopmin
217 * times, then we have been hit by a massive SMI
219 * If the maximum is 10 times larger than the minimum,
220 * then we got hit by an SMI as well.
222 if (pitcnt
< loopmin
|| tscmax
> 10 * tscmin
)
225 /* Calculate the PIT value */
232 * This reads the current MSB of the PIT counter, and
233 * checks if we are running on sufficiently fast and
234 * non-virtualized hardware.
236 * Our expectations are:
238 * - the PIT is running at roughly 1.19MHz
240 * - each IO is going to take about 1us on real hardware,
241 * but we allow it to be much faster (by a factor of 10) or
242 * _slightly_ slower (ie we allow up to a 2us read+counter
243 * update - anything else implies a unacceptably slow CPU
244 * or PIT for the fast calibration to work.
246 * - with 256 PIT ticks to read the value, we have 214us to
247 * see the same MSB (and overhead like doing a single TSC
248 * read per MSB value etc).
250 * - We're doing 2 reads per loop (LSB, MSB), and we expect
251 * them each to take about a microsecond on real hardware.
252 * So we expect a count value of around 100. But we'll be
253 * generous, and accept anything over 50.
255 * - if the PIT is stuck, and we see *many* more reads, we
256 * return early (and the next caller of pit_expect_msb()
257 * then consider it a failure when they don't see the
258 * next expected value).
260 * These expectations mean that we know that we have seen the
261 * transition from one expected value to another with a fairly
262 * high accuracy, and we didn't miss any events. We can thus
263 * use the TSC value at the transitions to calculate a pretty
264 * good value for the TSC frequencty.
266 static inline int pit_expect_msb(unsigned char val
)
270 for (count
= 0; count
< 50000; count
++) {
273 if (inb(0x42) != val
)
280 * How many MSB values do we want to see? We aim for a
281 * 15ms calibration, which assuming a 2us counter read
282 * error should give us roughly 150 ppm precision for
285 #define QUICK_PIT_MS 15
286 #define QUICK_PIT_ITERATIONS (QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
288 static unsigned long quick_pit_calibrate(void)
290 /* Set the Gate high, disable speaker */
291 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
294 * Counter 2, mode 0 (one-shot), binary count
296 * NOTE! Mode 2 decrements by two (and then the
297 * output is flipped each time, giving the same
298 * final output frequency as a decrement-by-one),
299 * so mode 0 is much better when looking at the
304 /* Start at 0xffff */
308 if (pit_expect_msb(0xff)) {
311 unsigned char expect
= 0xfe;
314 for (i
= 0; i
< QUICK_PIT_ITERATIONS
; i
++, expect
--) {
315 if (!pit_expect_msb(expect
))
321 * Make sure we can rely on the second TSC timestamp:
323 if (!pit_expect_msb(expect
))
327 * Ok, if we get here, then we've seen the
328 * MSB of the PIT decrement QUICK_PIT_ITERATIONS
329 * times, and each MSB had many hits, so we never
330 * had any sudden jumps.
332 * As a result, we can depend on there not being
333 * any odd delays anywhere, and the TSC reads are
336 * kHz = ticks / time-in-seconds / 1000;
337 * kHz = (t2 - t1) / (QPI * 256 / PIT_TICK_RATE) / 1000
338 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (QPI * 256 * 1000)
340 delta
= (t2
- t1
)*PIT_TICK_RATE
;
341 do_div(delta
, QUICK_PIT_ITERATIONS
*256*1000);
342 printk("Fast TSC calibration using PIT\n");
350 * native_calibrate_tsc - calibrate the tsc on boot
352 unsigned long native_calibrate_tsc(void)
354 u64 tsc1
, tsc2
, delta
, ref1
, ref2
;
355 unsigned long tsc_pit_min
= ULONG_MAX
, tsc_ref_min
= ULONG_MAX
;
356 unsigned long flags
, latch
, ms
, fast_calibrate
, tsc_khz
;
357 int hpet
= is_hpet_enabled(), i
, loopmin
;
359 tsc_khz
= get_hypervisor_tsc_freq();
361 printk(KERN_INFO
"TSC: Frequency read from the hypervisor\n");
365 local_irq_save(flags
);
366 fast_calibrate
= quick_pit_calibrate();
367 local_irq_restore(flags
);
369 return fast_calibrate
;
372 * Run 5 calibration loops to get the lowest frequency value
373 * (the best estimate). We use two different calibration modes
376 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
377 * load a timeout of 50ms. We read the time right after we
378 * started the timer and wait until the PIT count down reaches
379 * zero. In each wait loop iteration we read the TSC and check
380 * the delta to the previous read. We keep track of the min
381 * and max values of that delta. The delta is mostly defined
382 * by the IO time of the PIT access, so we can detect when a
383 * SMI/SMM disturbance happend between the two reads. If the
384 * maximum time is significantly larger than the minimum time,
385 * then we discard the result and have another try.
387 * 2) Reference counter. If available we use the HPET or the
388 * PMTIMER as a reference to check the sanity of that value.
389 * We use separate TSC readouts and check inside of the
390 * reference read for a SMI/SMM disturbance. We dicard
391 * disturbed values here as well. We do that around the PIT
392 * calibration delay loop as we have to wait for a certain
393 * amount of time anyway.
396 /* Preset PIT loop values */
399 loopmin
= CAL_PIT_LOOPS
;
401 for (i
= 0; i
< 3; i
++) {
402 unsigned long tsc_pit_khz
;
405 * Read the start value and the reference count of
406 * hpet/pmtimer when available. Then do the PIT
407 * calibration, which will take at least 50ms, and
408 * read the end value.
410 local_irq_save(flags
);
411 tsc1
= tsc_read_refs(&ref1
, hpet
);
412 tsc_pit_khz
= pit_calibrate_tsc(latch
, ms
, loopmin
);
413 tsc2
= tsc_read_refs(&ref2
, hpet
);
414 local_irq_restore(flags
);
416 /* Pick the lowest PIT TSC calibration so far */
417 tsc_pit_min
= min(tsc_pit_min
, tsc_pit_khz
);
419 /* hpet or pmtimer available ? */
420 if (!hpet
&& !ref1
&& !ref2
)
423 /* Check, whether the sampling was disturbed by an SMI */
424 if (tsc1
== ULLONG_MAX
|| tsc2
== ULLONG_MAX
)
427 tsc2
= (tsc2
- tsc1
) * 1000000LL;
429 tsc2
= calc_hpet_ref(tsc2
, ref1
, ref2
);
431 tsc2
= calc_pmtimer_ref(tsc2
, ref1
, ref2
);
433 tsc_ref_min
= min(tsc_ref_min
, (unsigned long) tsc2
);
435 /* Check the reference deviation */
436 delta
= ((u64
) tsc_pit_min
) * 100;
437 do_div(delta
, tsc_ref_min
);
440 * If both calibration results are inside a 10% window
441 * then we can be sure, that the calibration
442 * succeeded. We break out of the loop right away. We
443 * use the reference value, as it is more precise.
445 if (delta
>= 90 && delta
<= 110) {
447 "TSC: PIT calibration matches %s. %d loops\n",
448 hpet
? "HPET" : "PMTIMER", i
+ 1);
453 * Check whether PIT failed more than once. This
454 * happens in virtualized environments. We need to
455 * give the virtual PC a slightly longer timeframe for
456 * the HPET/PMTIMER to make the result precise.
458 if (i
== 1 && tsc_pit_min
== ULONG_MAX
) {
461 loopmin
= CAL2_PIT_LOOPS
;
466 * Now check the results.
468 if (tsc_pit_min
== ULONG_MAX
) {
469 /* PIT gave no useful value */
470 printk(KERN_WARNING
"TSC: Unable to calibrate against PIT\n");
472 /* We don't have an alternative source, disable TSC */
473 if (!hpet
&& !ref1
&& !ref2
) {
474 printk("TSC: No reference (HPET/PMTIMER) available\n");
478 /* The alternative source failed as well, disable TSC */
479 if (tsc_ref_min
== ULONG_MAX
) {
480 printk(KERN_WARNING
"TSC: HPET/PMTIMER calibration "
485 /* Use the alternative source */
486 printk(KERN_INFO
"TSC: using %s reference calibration\n",
487 hpet
? "HPET" : "PMTIMER");
492 /* We don't have an alternative source, use the PIT calibration value */
493 if (!hpet
&& !ref1
&& !ref2
) {
494 printk(KERN_INFO
"TSC: Using PIT calibration value\n");
498 /* The alternative source failed, use the PIT calibration value */
499 if (tsc_ref_min
== ULONG_MAX
) {
500 printk(KERN_WARNING
"TSC: HPET/PMTIMER calibration failed. "
501 "Using PIT calibration\n");
506 * The calibration values differ too much. In doubt, we use
507 * the PIT value as we know that there are PMTIMERs around
508 * running at double speed. At least we let the user know:
510 printk(KERN_WARNING
"TSC: PIT calibration deviates from %s: %lu %lu.\n",
511 hpet
? "HPET" : "PMTIMER", tsc_pit_min
, tsc_ref_min
);
512 printk(KERN_INFO
"TSC: Using PIT calibration value\n");
517 /* Only called from the Powernow K7 cpu freq driver */
518 int recalibrate_cpu_khz(void)
521 unsigned long cpu_khz_old
= cpu_khz
;
524 tsc_khz
= calibrate_tsc();
526 cpu_data(0).loops_per_jiffy
=
527 cpufreq_scale(cpu_data(0).loops_per_jiffy
,
528 cpu_khz_old
, cpu_khz
);
537 EXPORT_SYMBOL(recalibrate_cpu_khz
);
539 #endif /* CONFIG_X86_32 */
541 /* Accelerators for sched_clock()
542 * convert from cycles(64bits) => nanoseconds (64bits)
544 * ns = cycles / (freq / ns_per_sec)
545 * ns = cycles * (ns_per_sec / freq)
546 * ns = cycles * (10^9 / (cpu_khz * 10^3))
547 * ns = cycles * (10^6 / cpu_khz)
549 * Then we use scaling math (suggested by george@mvista.com) to get:
550 * ns = cycles * (10^6 * SC / cpu_khz) / SC
551 * ns = cycles * cyc2ns_scale / SC
553 * And since SC is a constant power of two, we can convert the div
556 * We can use khz divisor instead of mhz to keep a better precision, since
557 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
558 * (mathieu.desnoyers@polymtl.ca)
560 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
563 DEFINE_PER_CPU(unsigned long, cyc2ns
);
565 static void set_cyc2ns_scale(unsigned long cpu_khz
, int cpu
)
567 unsigned long long tsc_now
, ns_now
;
568 unsigned long flags
, *scale
;
570 local_irq_save(flags
);
571 sched_clock_idle_sleep_event();
573 scale
= &per_cpu(cyc2ns
, cpu
);
576 ns_now
= __cycles_2_ns(tsc_now
);
579 *scale
= (NSEC_PER_MSEC
<< CYC2NS_SCALE_FACTOR
)/cpu_khz
;
581 sched_clock_idle_wakeup_event(0);
582 local_irq_restore(flags
);
585 #ifdef CONFIG_CPU_FREQ
587 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
590 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
591 * not that important because current Opteron setups do not support
592 * scaling on SMP anyroads.
594 * Should fix up last_tsc too. Currently gettimeofday in the
595 * first tick after the change will be slightly wrong.
598 static unsigned int ref_freq
;
599 static unsigned long loops_per_jiffy_ref
;
600 static unsigned long tsc_khz_ref
;
602 static int time_cpufreq_notifier(struct notifier_block
*nb
, unsigned long val
,
605 struct cpufreq_freqs
*freq
= data
;
606 unsigned long *lpj
, dummy
;
608 if (cpu_has(&cpu_data(freq
->cpu
), X86_FEATURE_CONSTANT_TSC
))
612 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
614 lpj
= &cpu_data(freq
->cpu
).loops_per_jiffy
;
616 lpj
= &boot_cpu_data
.loops_per_jiffy
;
620 ref_freq
= freq
->old
;
621 loops_per_jiffy_ref
= *lpj
;
622 tsc_khz_ref
= tsc_khz
;
624 if ((val
== CPUFREQ_PRECHANGE
&& freq
->old
< freq
->new) ||
625 (val
== CPUFREQ_POSTCHANGE
&& freq
->old
> freq
->new) ||
626 (val
== CPUFREQ_RESUMECHANGE
)) {
627 *lpj
= cpufreq_scale(loops_per_jiffy_ref
, ref_freq
, freq
->new);
629 tsc_khz
= cpufreq_scale(tsc_khz_ref
, ref_freq
, freq
->new);
630 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
631 mark_tsc_unstable("cpufreq changes");
634 set_cyc2ns_scale(tsc_khz
, freq
->cpu
);
639 static struct notifier_block time_cpufreq_notifier_block
= {
640 .notifier_call
= time_cpufreq_notifier
643 static int __init
cpufreq_tsc(void)
647 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
649 cpufreq_register_notifier(&time_cpufreq_notifier_block
,
650 CPUFREQ_TRANSITION_NOTIFIER
);
654 core_initcall(cpufreq_tsc
);
656 #endif /* CONFIG_CPU_FREQ */
658 /* clocksource code */
660 static struct clocksource clocksource_tsc
;
663 * We compare the TSC to the cycle_last value in the clocksource
664 * structure to avoid a nasty time-warp. This can be observed in a
665 * very small window right after one CPU updated cycle_last under
666 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
667 * is smaller than the cycle_last reference value due to a TSC which
668 * is slighty behind. This delta is nowhere else observable, but in
669 * that case it results in a forward time jump in the range of hours
670 * due to the unsigned delta calculation of the time keeping core
671 * code, which is necessary to support wrapping clocksources like pm
674 static cycle_t
read_tsc(void)
676 cycle_t ret
= (cycle_t
)get_cycles();
678 return ret
>= clocksource_tsc
.cycle_last
?
679 ret
: clocksource_tsc
.cycle_last
;
683 static cycle_t __vsyscall_fn
vread_tsc(void)
685 cycle_t ret
= (cycle_t
)vget_cycles();
687 return ret
>= __vsyscall_gtod_data
.clock
.cycle_last
?
688 ret
: __vsyscall_gtod_data
.clock
.cycle_last
;
692 static struct clocksource clocksource_tsc
= {
696 .mask
= CLOCKSOURCE_MASK(64),
698 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
|
699 CLOCK_SOURCE_MUST_VERIFY
,
705 void mark_tsc_unstable(char *reason
)
709 printk("Marking TSC unstable due to %s\n", reason
);
710 /* Change only the rating, when not registered */
711 if (clocksource_tsc
.mult
)
712 clocksource_change_rating(&clocksource_tsc
, 0);
714 clocksource_tsc
.rating
= 0;
718 EXPORT_SYMBOL_GPL(mark_tsc_unstable
);
720 static int __init
dmi_mark_tsc_unstable(const struct dmi_system_id
*d
)
722 printk(KERN_NOTICE
"%s detected: marking TSC unstable.\n",
728 /* List of systems that have known TSC problems */
729 static struct dmi_system_id __initdata bad_tsc_dmi_table
[] = {
731 .callback
= dmi_mark_tsc_unstable
,
732 .ident
= "IBM Thinkpad 380XD",
734 DMI_MATCH(DMI_BOARD_VENDOR
, "IBM"),
735 DMI_MATCH(DMI_BOARD_NAME
, "2635FA0"),
742 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC
744 #ifdef CONFIG_MGEODE_LX
745 /* RTSC counts during suspend */
746 #define RTSC_SUSP 0x100
748 static void __init
check_geode_tsc_reliable(void)
750 unsigned long res_low
, res_high
;
752 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0
, &res_low
, &res_high
);
753 if (res_low
& RTSC_SUSP
)
754 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_MUST_VERIFY
;
757 static inline void check_geode_tsc_reliable(void) { }
761 * Make an educated guess if the TSC is trustworthy and synchronized
764 __cpuinit
int unsynchronized_tsc(void)
766 if (!cpu_has_tsc
|| tsc_unstable
)
769 #ifdef CONFIG_X86_SMP
770 if (apic_is_clustered_box())
774 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC
))
777 * Intel systems are normally all synchronized.
778 * Exceptions must mark TSC as unstable:
780 if (boot_cpu_data
.x86_vendor
!= X86_VENDOR_INTEL
) {
781 /* assume multi socket systems are not synchronized: */
782 if (num_possible_cpus() > 1)
789 static void __init
init_tsc_clocksource(void)
791 clocksource_tsc
.mult
= clocksource_khz2mult(tsc_khz
,
792 clocksource_tsc
.shift
);
793 /* lower the rating if we already know its unstable: */
794 if (check_tsc_unstable()) {
795 clocksource_tsc
.rating
= 0;
796 clocksource_tsc
.flags
&= ~CLOCK_SOURCE_IS_CONTINUOUS
;
798 clocksource_register(&clocksource_tsc
);
801 void __init
tsc_init(void)
809 tsc_khz
= calibrate_tsc();
813 mark_tsc_unstable("could not calculate TSC khz");
818 if (cpu_has(&boot_cpu_data
, X86_FEATURE_CONSTANT_TSC
) &&
819 (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
))
820 cpu_khz
= calibrate_cpu();
823 lpj
= ((u64
)tsc_khz
* 1000);
827 printk("Detected %lu.%03lu MHz processor.\n",
828 (unsigned long)cpu_khz
/ 1000,
829 (unsigned long)cpu_khz
% 1000);
832 * Secondary CPUs do not run through tsc_init(), so set up
833 * all the scale factors for all CPUs, assuming the same
834 * speed as the bootup CPU. (cpufreq notifiers will fix this
835 * up if their speed diverges)
837 for_each_possible_cpu(cpu
)
838 set_cyc2ns_scale(cpu_khz
, cpu
);
840 if (tsc_disabled
> 0)
843 /* now allow native_sched_clock() to use rdtsc */
847 /* Check and install the TSC clocksource */
848 dmi_check_system(bad_tsc_dmi_table
);
850 if (unsynchronized_tsc())
851 mark_tsc_unstable("TSCs unsynchronized");
853 check_geode_tsc_reliable();
854 init_tsc_clocksource();