?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: check range in reserve_early()
[linux-2.6/mini2440.git] / drivers / serial / 8250.c
blob0d934bfbdd9b2ded293260968927a7de5e776f88
1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
20
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_reg.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/nmi.h>
40 #include <linux/mutex.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 /*
68 * Debugging.
69 */
70 #if 0
71 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
72 #else
73 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
74 #endif
75
76 #if 0
77 #define DEBUG_INTR(fmt...) printk(fmt)
78 #else
79 #define DEBUG_INTR(fmt...) do { } while (0)
80 #endif
81
82 #define PASS_LIMIT 256
83
84 /*
85 * We default to IRQ0 for the "no irq" hack. Some
86 * machine types want others as well - they're free
87 * to redefine this in their header file.
88 */
89 #define is_real_interrupt(irq) ((irq) != 0)
90
91 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92 #define CONFIG_SERIAL_DETECT_IRQ 1
93 #endif
94 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
95 #define CONFIG_SERIAL_MANY_PORTS 1
96 #endif
97
98 /*
99 * HUB6 is always on. This will be removed once the header
100 * files have been cleaned.
101 */
102 #define CONFIG_HUB6 1
103
104 #include <asm/serial.h>
105 /*
106 * SERIAL_PORT_DFNS tells us about built-in ports that have no
107 * standard enumeration mechanism. Platforms that can find all
108 * serial ports via mechanisms like ACPI or PCI need not supply it.
109 */
110 #ifndef SERIAL_PORT_DFNS
111 #define SERIAL_PORT_DFNS
112 #endif
113
114 static const struct old_serial_port old_serial_port[] = {
115 SERIAL_PORT_DFNS /* defined in asm/serial.h */
116 };
117
118 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
119
120 #ifdef CONFIG_SERIAL_8250_RSA
121
122 #define PORT_RSA_MAX 4
123 static unsigned long probe_rsa[PORT_RSA_MAX];
124 static unsigned int probe_rsa_count;
125 #endif /* CONFIG_SERIAL_8250_RSA */
126
127 struct uart_8250_port {
128 struct uart_port port;
129 struct timer_list timer; /* "no irq" timer */
130 struct list_head list; /* ports on this IRQ */
131 unsigned short capabilities; /* port capabilities */
132 unsigned short bugs; /* port bugs */
133 unsigned int tx_loadsz; /* transmit fifo load size */
134 unsigned char acr;
135 unsigned char ier;
136 unsigned char lcr;
137 unsigned char mcr;
138 unsigned char mcr_mask; /* mask of user bits */
139 unsigned char mcr_force; /* mask of forced bits */
140
141 /*
142 * Some bits in registers are cleared on a read, so they must
143 * be saved whenever the register is read but the bits will not
144 * be immediately processed.
145 */
146 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
147 unsigned char lsr_saved_flags;
148 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
149 unsigned char msr_saved_flags;
150
151 /*
152 * We provide a per-port pm hook.
153 */
154 void (*pm)(struct uart_port *port,
155 unsigned int state, unsigned int old);
156 };
157
158 struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163 };
164
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169 /*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172 static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO,
238 },
239 [PORT_16654] = {
240 .name = "ST16654",
241 .fifo_size = 64,
242 .tx_loadsz = 32,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
244 UART_FCR_T_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
246 },
247 [PORT_16850] = {
248 .name = "XR16850",
249 .fifo_size = 128,
250 .tx_loadsz = 128,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
253 },
254 [PORT_RSA] = {
255 .name = "RSA",
256 .fifo_size = 2048,
257 .tx_loadsz = 2048,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
259 .flags = UART_CAP_FIFO,
260 },
261 [PORT_NS16550A] = {
262 .name = "NS16550A",
263 .fifo_size = 16,
264 .tx_loadsz = 16,
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
266 .flags = UART_CAP_FIFO | UART_NATSEMI,
267 },
268 [PORT_XSCALE] = {
269 .name = "XScale",
270 .fifo_size = 32,
271 .tx_loadsz = 32,
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .flags = UART_CAP_FIFO | UART_CAP_UUE,
274 },
275 [PORT_RM9000] = {
276 .name = "RM9000",
277 .fifo_size = 16,
278 .tx_loadsz = 16,
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 .flags = UART_CAP_FIFO,
281 },
282 [PORT_OCTEON] = {
283 .name = "OCTEON",
284 .fifo_size = 64,
285 .tx_loadsz = 64,
286 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
287 .flags = UART_CAP_FIFO,
288 },
289 };
290
291 #if defined (CONFIG_SERIAL_8250_AU1X00)
292
293 /* Au1x00 UART hardware has a weird register layout */
294 static const u8 au_io_in_map[] = {
295 [UART_RX] = 0,
296 [UART_IER] = 2,
297 [UART_IIR] = 3,
298 [UART_LCR] = 5,
299 [UART_MCR] = 6,
300 [UART_LSR] = 7,
301 [UART_MSR] = 8,
302 };
303
304 static const u8 au_io_out_map[] = {
305 [UART_TX] = 1,
306 [UART_IER] = 2,
307 [UART_FCR] = 4,
308 [UART_LCR] = 5,
309 [UART_MCR] = 6,
310 };
311
312 /* sane hardware needs no mapping */
313 static inline int map_8250_in_reg(struct uart_port *p, int offset)
314 {
315 if (p->iotype != UPIO_AU)
316 return offset;
317 return au_io_in_map[offset];
318 }
319
320 static inline int map_8250_out_reg(struct uart_port *p, int offset)
321 {
322 if (p->iotype != UPIO_AU)
323 return offset;
324 return au_io_out_map[offset];
325 }
326
327 #elif defined(CONFIG_SERIAL_8250_RM9K)
328
329 static const u8
330 regmap_in[8] = {
331 [UART_RX] = 0x00,
332 [UART_IER] = 0x0c,
333 [UART_IIR] = 0x14,
334 [UART_LCR] = 0x1c,
335 [UART_MCR] = 0x20,
336 [UART_LSR] = 0x24,
337 [UART_MSR] = 0x28,
338 [UART_SCR] = 0x2c
339 },
340 regmap_out[8] = {
341 [UART_TX] = 0x04,
342 [UART_IER] = 0x0c,
343 [UART_FCR] = 0x18,
344 [UART_LCR] = 0x1c,
345 [UART_MCR] = 0x20,
346 [UART_LSR] = 0x24,
347 [UART_MSR] = 0x28,
348 [UART_SCR] = 0x2c
349 };
350
351 static inline int map_8250_in_reg(struct uart_port *p, int offset)
352 {
353 if (p->iotype != UPIO_RM9000)
354 return offset;
355 return regmap_in[offset];
356 }
357
358 static inline int map_8250_out_reg(struct uart_port *p, int offset)
359 {
360 if (p->iotype != UPIO_RM9000)
361 return offset;
362 return regmap_out[offset];
363 }
364
365 #else
366
367 /* sane hardware needs no mapping */
368 #define map_8250_in_reg(up, offset) (offset)
369 #define map_8250_out_reg(up, offset) (offset)
370
371 #endif
372
373 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
374 {
375 offset = map_8250_in_reg(p, offset) << p->regshift;
376 outb(p->hub6 - 1 + offset, p->iobase);
377 return inb(p->iobase + 1);
378 }
379
380 static void hub6_serial_out(struct uart_port *p, int offset, int value)
381 {
382 offset = map_8250_out_reg(p, offset) << p->regshift;
383 outb(p->hub6 - 1 + offset, p->iobase);
384 outb(value, p->iobase + 1);
385 }
386
387 static unsigned int mem_serial_in(struct uart_port *p, int offset)
388 {
389 offset = map_8250_in_reg(p, offset) << p->regshift;
390 return readb(p->membase + offset);
391 }
392
393 static void mem_serial_out(struct uart_port *p, int offset, int value)
394 {
395 offset = map_8250_out_reg(p, offset) << p->regshift;
396 writeb(value, p->membase + offset);
397 }
398
399 static void mem32_serial_out(struct uart_port *p, int offset, int value)
400 {
401 offset = map_8250_out_reg(p, offset) << p->regshift;
402 writel(value, p->membase + offset);
403 }
404
405 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
406 {
407 offset = map_8250_in_reg(p, offset) << p->regshift;
408 return readl(p->membase + offset);
409 }
410
411 #ifdef CONFIG_SERIAL_8250_AU1X00
412 static unsigned int au_serial_in(struct uart_port *p, int offset)
413 {
414 offset = map_8250_in_reg(p, offset) << p->regshift;
415 return __raw_readl(p->membase + offset);
416 }
417
418 static void au_serial_out(struct uart_port *p, int offset, int value)
419 {
420 offset = map_8250_out_reg(p, offset) << p->regshift;
421 __raw_writel(value, p->membase + offset);
422 }
423 #endif
424
425 static unsigned int tsi_serial_in(struct uart_port *p, int offset)
426 {
427 unsigned int tmp;
428 offset = map_8250_in_reg(p, offset) << p->regshift;
429 if (offset == UART_IIR) {
430 tmp = readl(p->membase + (UART_IIR & ~3));
431 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
432 } else
433 return readb(p->membase + offset);
434 }
435
436 static void tsi_serial_out(struct uart_port *p, int offset, int value)
437 {
438 offset = map_8250_out_reg(p, offset) << p->regshift;
439 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
440 writeb(value, p->membase + offset);
441 }
442
443 static void dwapb_serial_out(struct uart_port *p, int offset, int value)
444 {
445 int save_offset = offset;
446 offset = map_8250_out_reg(p, offset) << p->regshift;
447 /* Save the LCR value so it can be re-written when a
448 * Busy Detect interrupt occurs. */
449 if (save_offset == UART_LCR) {
450 struct uart_8250_port *up = (struct uart_8250_port *)p;
451 up->lcr = value;
452 }
453 writeb(value, p->membase + offset);
454 /* Read the IER to ensure any interrupt is cleared before
455 * returning from ISR. */
456 if (save_offset == UART_TX || save_offset == UART_IER)
457 value = p->serial_in(p, UART_IER);
458 }
459
460 static unsigned int io_serial_in(struct uart_port *p, int offset)
461 {
462 offset = map_8250_in_reg(p, offset) << p->regshift;
463 return inb(p->iobase + offset);
464 }
465
466 static void io_serial_out(struct uart_port *p, int offset, int value)
467 {
468 offset = map_8250_out_reg(p, offset) << p->regshift;
469 outb(value, p->iobase + offset);
470 }
471
472 static void set_io_from_upio(struct uart_port *p)
473 {
474 switch (p->iotype) {
475 case UPIO_HUB6:
476 p->serial_in = hub6_serial_in;
477 p->serial_out = hub6_serial_out;
478 break;
479
480 case UPIO_MEM:
481 p->serial_in = mem_serial_in;
482 p->serial_out = mem_serial_out;
483 break;
484
485 case UPIO_RM9000:
486 case UPIO_MEM32:
487 p->serial_in = mem32_serial_in;
488 p->serial_out = mem32_serial_out;
489 break;
490
491 #ifdef CONFIG_SERIAL_8250_AU1X00
492 case UPIO_AU:
493 p->serial_in = au_serial_in;
494 p->serial_out = au_serial_out;
495 break;
496 #endif
497 case UPIO_TSI:
498 p->serial_in = tsi_serial_in;
499 p->serial_out = tsi_serial_out;
500 break;
501
502 case UPIO_DWAPB:
503 p->serial_in = mem_serial_in;
504 p->serial_out = dwapb_serial_out;
505 break;
506
507 default:
508 p->serial_in = io_serial_in;
509 p->serial_out = io_serial_out;
510 break;
511 }
512 }
513
514 static void
515 serial_out_sync(struct uart_8250_port *up, int offset, int value)
516 {
517 struct uart_port *p = &up->port;
518 switch (p->iotype) {
519 case UPIO_MEM:
520 case UPIO_MEM32:
521 #ifdef CONFIG_SERIAL_8250_AU1X00
522 case UPIO_AU:
523 #endif
524 case UPIO_DWAPB:
525 p->serial_out(p, offset, value);
526 p->serial_in(p, UART_LCR); /* safe, no side-effects */
527 break;
528 default:
529 p->serial_out(p, offset, value);
530 }
531 }
532
533 #define serial_in(up, offset) \
534 (up->port.serial_in(&(up)->port, (offset)))
535 #define serial_out(up, offset, value) \
536 (up->port.serial_out(&(up)->port, (offset), (value)))
537 /*
538 * We used to support using pause I/O for certain machines. We
539 * haven't supported this for a while, but just in case it's badly
540 * needed for certain old 386 machines, I've left these #define's
541 * in....
542 */
543 #define serial_inp(up, offset) serial_in(up, offset)
544 #define serial_outp(up, offset, value) serial_out(up, offset, value)
545
546 /* Uart divisor latch read */
547 static inline int _serial_dl_read(struct uart_8250_port *up)
548 {
549 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
550 }
551
552 /* Uart divisor latch write */
553 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
554 {
555 serial_outp(up, UART_DLL, value & 0xff);
556 serial_outp(up, UART_DLM, value >> 8 & 0xff);
557 }
558
559 #if defined(CONFIG_SERIAL_8250_AU1X00)
560 /* Au1x00 haven't got a standard divisor latch */
561 static int serial_dl_read(struct uart_8250_port *up)
562 {
563 if (up->port.iotype == UPIO_AU)
564 return __raw_readl(up->port.membase + 0x28);
565 else
566 return _serial_dl_read(up);
567 }
568
569 static void serial_dl_write(struct uart_8250_port *up, int value)
570 {
571 if (up->port.iotype == UPIO_AU)
572 __raw_writel(value, up->port.membase + 0x28);
573 else
574 _serial_dl_write(up, value);
575 }
576 #elif defined(CONFIG_SERIAL_8250_RM9K)
577 static int serial_dl_read(struct uart_8250_port *up)
578 {
579 return (up->port.iotype == UPIO_RM9000) ?
580 (((__raw_readl(up->port.membase + 0x10) << 8) |
581 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
582 _serial_dl_read(up);
583 }
584
585 static void serial_dl_write(struct uart_8250_port *up, int value)
586 {
587 if (up->port.iotype == UPIO_RM9000) {
588 __raw_writel(value, up->port.membase + 0x08);
589 __raw_writel(value >> 8, up->port.membase + 0x10);
590 } else {
591 _serial_dl_write(up, value);
592 }
593 }
594 #else
595 #define serial_dl_read(up) _serial_dl_read(up)
596 #define serial_dl_write(up, value) _serial_dl_write(up, value)
597 #endif
598
599 /*
600 * For the 16C950
601 */
602 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
603 {
604 serial_out(up, UART_SCR, offset);
605 serial_out(up, UART_ICR, value);
606 }
607
608 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
609 {
610 unsigned int value;
611
612 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
613 serial_out(up, UART_SCR, offset);
614 value = serial_in(up, UART_ICR);
615 serial_icr_write(up, UART_ACR, up->acr);
616
617 return value;
618 }
619
620 /*
621 * FIFO support.
622 */
623 static void serial8250_clear_fifos(struct uart_8250_port *p)
624 {
625 if (p->capabilities & UART_CAP_FIFO) {
626 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
627 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
628 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
629 serial_outp(p, UART_FCR, 0);
630 }
631 }
632
633 /*
634 * IER sleep support. UARTs which have EFRs need the "extended
635 * capability" bit enabled. Note that on XR16C850s, we need to
636 * reset LCR to write to IER.
637 */
638 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
639 {
640 if (p->capabilities & UART_CAP_SLEEP) {
641 if (p->capabilities & UART_CAP_EFR) {
642 serial_outp(p, UART_LCR, 0xBF);
643 serial_outp(p, UART_EFR, UART_EFR_ECB);
644 serial_outp(p, UART_LCR, 0);
645 }
646 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
647 if (p->capabilities & UART_CAP_EFR) {
648 serial_outp(p, UART_LCR, 0xBF);
649 serial_outp(p, UART_EFR, 0);
650 serial_outp(p, UART_LCR, 0);
651 }
652 }
653 }
654
655 #ifdef CONFIG_SERIAL_8250_RSA
656 /*
657 * Attempts to turn on the RSA FIFO. Returns zero on failure.
658 * We set the port uart clock rate if we succeed.
659 */
660 static int __enable_rsa(struct uart_8250_port *up)
661 {
662 unsigned char mode;
663 int result;
664
665 mode = serial_inp(up, UART_RSA_MSR);
666 result = mode & UART_RSA_MSR_FIFO;
667
668 if (!result) {
669 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
670 mode = serial_inp(up, UART_RSA_MSR);
671 result = mode & UART_RSA_MSR_FIFO;
672 }
673
674 if (result)
675 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
676
677 return result;
678 }
679
680 static void enable_rsa(struct uart_8250_port *up)
681 {
682 if (up->port.type == PORT_RSA) {
683 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
684 spin_lock_irq(&up->port.lock);
685 __enable_rsa(up);
686 spin_unlock_irq(&up->port.lock);
687 }
688 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
689 serial_outp(up, UART_RSA_FRR, 0);
690 }
691 }
692
693 /*
694 * Attempts to turn off the RSA FIFO. Returns zero on failure.
695 * It is unknown why interrupts were disabled in here. However,
696 * the caller is expected to preserve this behaviour by grabbing
697 * the spinlock before calling this function.
698 */
699 static void disable_rsa(struct uart_8250_port *up)
700 {
701 unsigned char mode;
702 int result;
703
704 if (up->port.type == PORT_RSA &&
705 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
706 spin_lock_irq(&up->port.lock);
707
708 mode = serial_inp(up, UART_RSA_MSR);
709 result = !(mode & UART_RSA_MSR_FIFO);
710
711 if (!result) {
712 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
713 mode = serial_inp(up, UART_RSA_MSR);
714 result = !(mode & UART_RSA_MSR_FIFO);
715 }
716
717 if (result)
718 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
719 spin_unlock_irq(&up->port.lock);
720 }
721 }
722 #endif /* CONFIG_SERIAL_8250_RSA */
723
724 /*
725 * This is a quickie test to see how big the FIFO is.
726 * It doesn't work at all the time, more's the pity.
727 */
728 static int size_fifo(struct uart_8250_port *up)
729 {
730 unsigned char old_fcr, old_mcr, old_lcr;
731 unsigned short old_dl;
732 int count;
733
734 old_lcr = serial_inp(up, UART_LCR);
735 serial_outp(up, UART_LCR, 0);
736 old_fcr = serial_inp(up, UART_FCR);
737 old_mcr = serial_inp(up, UART_MCR);
738 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
739 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
740 serial_outp(up, UART_MCR, UART_MCR_LOOP);
741 serial_outp(up, UART_LCR, UART_LCR_DLAB);
742 old_dl = serial_dl_read(up);
743 serial_dl_write(up, 0x0001);
744 serial_outp(up, UART_LCR, 0x03);
745 for (count = 0; count < 256; count++)
746 serial_outp(up, UART_TX, count);
747 mdelay(20);/* FIXME - schedule_timeout */
748 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
749 (count < 256); count++)
750 serial_inp(up, UART_RX);
751 serial_outp(up, UART_FCR, old_fcr);
752 serial_outp(up, UART_MCR, old_mcr);
753 serial_outp(up, UART_LCR, UART_LCR_DLAB);
754 serial_dl_write(up, old_dl);
755 serial_outp(up, UART_LCR, old_lcr);
756
757 return count;
758 }
759
760 /*
761 * Read UART ID using the divisor method - set DLL and DLM to zero
762 * and the revision will be in DLL and device type in DLM. We
763 * preserve the device state across this.
764 */
765 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
766 {
767 unsigned char old_dll, old_dlm, old_lcr;
768 unsigned int id;
769
770 old_lcr = serial_inp(p, UART_LCR);
771 serial_outp(p, UART_LCR, UART_LCR_DLAB);
772
773 old_dll = serial_inp(p, UART_DLL);
774 old_dlm = serial_inp(p, UART_DLM);
775
776 serial_outp(p, UART_DLL, 0);
777 serial_outp(p, UART_DLM, 0);
778
779 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
780
781 serial_outp(p, UART_DLL, old_dll);
782 serial_outp(p, UART_DLM, old_dlm);
783 serial_outp(p, UART_LCR, old_lcr);
784
785 return id;
786 }
787
788 /*
789 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
790 * When this function is called we know it is at least a StarTech
791 * 16650 V2, but it might be one of several StarTech UARTs, or one of
792 * its clones. (We treat the broken original StarTech 16650 V1 as a
793 * 16550, and why not? Startech doesn't seem to even acknowledge its
794 * existence.)
795 *
796 * What evil have men's minds wrought...
797 */
798 static void autoconfig_has_efr(struct uart_8250_port *up)
799 {
800 unsigned int id1, id2, id3, rev;
801
802 /*
803 * Everything with an EFR has SLEEP
804 */
805 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
806
807 /*
808 * First we check to see if it's an Oxford Semiconductor UART.
809 *
810 * If we have to do this here because some non-National
811 * Semiconductor clone chips lock up if you try writing to the
812 * LSR register (which serial_icr_read does)
813 */
814
815 /*
816 * Check for Oxford Semiconductor 16C950.
817 *
818 * EFR [4] must be set else this test fails.
819 *
820 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
821 * claims that it's needed for 952 dual UART's (which are not
822 * recommended for new designs).
823 */
824 up->acr = 0;
825 serial_out(up, UART_LCR, 0xBF);
826 serial_out(up, UART_EFR, UART_EFR_ECB);
827 serial_out(up, UART_LCR, 0x00);
828 id1 = serial_icr_read(up, UART_ID1);
829 id2 = serial_icr_read(up, UART_ID2);
830 id3 = serial_icr_read(up, UART_ID3);
831 rev = serial_icr_read(up, UART_REV);
832
833 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
834
835 if (id1 == 0x16 && id2 == 0xC9 &&
836 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
837 up->port.type = PORT_16C950;
838
839 /*
840 * Enable work around for the Oxford Semiconductor 952 rev B
841 * chip which causes it to seriously miscalculate baud rates
842 * when DLL is 0.
843 */
844 if (id3 == 0x52 && rev == 0x01)
845 up->bugs |= UART_BUG_QUOT;
846 return;
847 }
848
849 /*
850 * We check for a XR16C850 by setting DLL and DLM to 0, and then
851 * reading back DLL and DLM. The chip type depends on the DLM
852 * value read back:
853 * 0x10 - XR16C850 and the DLL contains the chip revision.
854 * 0x12 - XR16C2850.
855 * 0x14 - XR16C854.
856 */
857 id1 = autoconfig_read_divisor_id(up);
858 DEBUG_AUTOCONF("850id=%04x ", id1);
859
860 id2 = id1 >> 8;
861 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
862 up->port.type = PORT_16850;
863 return;
864 }
865
866 /*
867 * It wasn't an XR16C850.
868 *
869 * We distinguish between the '654 and the '650 by counting
870 * how many bytes are in the FIFO. I'm using this for now,
871 * since that's the technique that was sent to me in the
872 * serial driver update, but I'm not convinced this works.
873 * I've had problems doing this in the past. -TYT
874 */
875 if (size_fifo(up) == 64)
876 up->port.type = PORT_16654;
877 else
878 up->port.type = PORT_16650V2;
879 }
880
881 /*
882 * We detected a chip without a FIFO. Only two fall into
883 * this category - the original 8250 and the 16450. The
884 * 16450 has a scratch register (accessible with LCR=0)
885 */
886 static void autoconfig_8250(struct uart_8250_port *up)
887 {
888 unsigned char scratch, status1, status2;
889
890 up->port.type = PORT_8250;
891
892 scratch = serial_in(up, UART_SCR);
893 serial_outp(up, UART_SCR, 0xa5);
894 status1 = serial_in(up, UART_SCR);
895 serial_outp(up, UART_SCR, 0x5a);
896 status2 = serial_in(up, UART_SCR);
897 serial_outp(up, UART_SCR, scratch);
898
899 if (status1 == 0xa5 && status2 == 0x5a)
900 up->port.type = PORT_16450;
901 }
902
903 static int broken_efr(struct uart_8250_port *up)
904 {
905 /*
906 * Exar ST16C2550 "A2" devices incorrectly detect as
907 * having an EFR, and report an ID of 0x0201. See
908 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
909 */
910 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
911 return 1;
912
913 return 0;
914 }
915
916 /*
917 * We know that the chip has FIFOs. Does it have an EFR? The
918 * EFR is located in the same register position as the IIR and
919 * we know the top two bits of the IIR are currently set. The
920 * EFR should contain zero. Try to read the EFR.
921 */
922 static void autoconfig_16550a(struct uart_8250_port *up)
923 {
924 unsigned char status1, status2;
925 unsigned int iersave;
926
927 up->port.type = PORT_16550A;
928 up->capabilities |= UART_CAP_FIFO;
929
930 /*
931 * Check for presence of the EFR when DLAB is set.
932 * Only ST16C650V1 UARTs pass this test.
933 */
934 serial_outp(up, UART_LCR, UART_LCR_DLAB);
935 if (serial_in(up, UART_EFR) == 0) {
936 serial_outp(up, UART_EFR, 0xA8);
937 if (serial_in(up, UART_EFR) != 0) {
938 DEBUG_AUTOCONF("EFRv1 ");
939 up->port.type = PORT_16650;
940 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
941 } else {
942 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
943 }
944 serial_outp(up, UART_EFR, 0);
945 return;
946 }
947
948 /*
949 * Maybe it requires 0xbf to be written to the LCR.
950 * (other ST16C650V2 UARTs, TI16C752A, etc)
951 */
952 serial_outp(up, UART_LCR, 0xBF);
953 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
954 DEBUG_AUTOCONF("EFRv2 ");
955 autoconfig_has_efr(up);
956 return;
957 }
958
959 /*
960 * Check for a National Semiconductor SuperIO chip.
961 * Attempt to switch to bank 2, read the value of the LOOP bit
962 * from EXCR1. Switch back to bank 0, change it in MCR. Then
963 * switch back to bank 2, read it from EXCR1 again and check
964 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
965 */
966 serial_outp(up, UART_LCR, 0);
967 status1 = serial_in(up, UART_MCR);
968 serial_outp(up, UART_LCR, 0xE0);
969 status2 = serial_in(up, 0x02); /* EXCR1 */
970
971 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
972 serial_outp(up, UART_LCR, 0);
973 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
974 serial_outp(up, UART_LCR, 0xE0);
975 status2 = serial_in(up, 0x02); /* EXCR1 */
976 serial_outp(up, UART_LCR, 0);
977 serial_outp(up, UART_MCR, status1);
978
979 if ((status2 ^ status1) & UART_MCR_LOOP) {
980 unsigned short quot;
981
982 serial_outp(up, UART_LCR, 0xE0);
983
984 quot = serial_dl_read(up);
985 quot <<= 3;
986
987 status1 = serial_in(up, 0x04); /* EXCR2 */
988 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
989 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
990 serial_outp(up, 0x04, status1);
991
992 serial_dl_write(up, quot);
993
994 serial_outp(up, UART_LCR, 0);
995
996 up->port.uartclk = 921600*16;
997 up->port.type = PORT_NS16550A;
998 up->capabilities |= UART_NATSEMI;
999 return;
1000 }
1001 }
1002
1003 /*
1004 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1005 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1006 * Try setting it with and without DLAB set. Cheap clones
1007 * set bit 5 without DLAB set.
1008 */
1009 serial_outp(up, UART_LCR, 0);
1010 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1011 status1 = serial_in(up, UART_IIR) >> 5;
1012 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1013 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1014 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1015 status2 = serial_in(up, UART_IIR) >> 5;
1016 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1017 serial_outp(up, UART_LCR, 0);
1018
1019 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1020
1021 if (status1 == 6 && status2 == 7) {
1022 up->port.type = PORT_16750;
1023 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1024 return;
1025 }
1026
1027 /*
1028 * Try writing and reading the UART_IER_UUE bit (b6).
1029 * If it works, this is probably one of the Xscale platform's
1030 * internal UARTs.
1031 * We're going to explicitly set the UUE bit to 0 before
1032 * trying to write and read a 1 just to make sure it's not
1033 * already a 1 and maybe locked there before we even start start.
1034 */
1035 iersave = serial_in(up, UART_IER);
1036 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1037 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1038 /*
1039 * OK it's in a known zero state, try writing and reading
1040 * without disturbing the current state of the other bits.
1041 */
1042 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1043 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1044 /*
1045 * It's an Xscale.
1046 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1047 */
1048 DEBUG_AUTOCONF("Xscale ");
1049 up->port.type = PORT_XSCALE;
1050 up->capabilities |= UART_CAP_UUE;
1051 return;
1052 }
1053 } else {
1054 /*
1055 * If we got here we couldn't force the IER_UUE bit to 0.
1056 * Log it and continue.
1057 */
1058 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1059 }
1060 serial_outp(up, UART_IER, iersave);
1061 }
1062
1063 /*
1064 * This routine is called by rs_init() to initialize a specific serial
1065 * port. It determines what type of UART chip this serial port is
1066 * using: 8250, 16450, 16550, 16550A. The important question is
1067 * whether or not this UART is a 16550A or not, since this will
1068 * determine whether or not we can use its FIFO features or not.
1069 */
1070 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1071 {
1072 unsigned char status1, scratch, scratch2, scratch3;
1073 unsigned char save_lcr, save_mcr;
1074 unsigned long flags;
1075
1076 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1077 return;
1078
1079 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
1080 serial_index(&up->port), up->port.iobase, up->port.membase);
1081
1082 /*
1083 * We really do need global IRQs disabled here - we're going to
1084 * be frobbing the chips IRQ enable register to see if it exists.
1085 */
1086 spin_lock_irqsave(&up->port.lock, flags);
1087
1088 up->capabilities = 0;
1089 up->bugs = 0;
1090
1091 if (!(up->port.flags & UPF_BUGGY_UART)) {
1092 /*
1093 * Do a simple existence test first; if we fail this,
1094 * there's no point trying anything else.
1095 *
1096 * 0x80 is used as a nonsense port to prevent against
1097 * false positives due to ISA bus float. The
1098 * assumption is that 0x80 is a non-existent port;
1099 * which should be safe since include/asm/io.h also
1100 * makes this assumption.
1101 *
1102 * Note: this is safe as long as MCR bit 4 is clear
1103 * and the device is in "PC" mode.
1104 */
1105 scratch = serial_inp(up, UART_IER);
1106 serial_outp(up, UART_IER, 0);
1107 #ifdef __i386__
1108 outb(0xff, 0x080);
1109 #endif
1110 /*
1111 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1112 * 16C754B) allow only to modify them if an EFR bit is set.
1113 */
1114 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1115 serial_outp(up, UART_IER, 0x0F);
1116 #ifdef __i386__
1117 outb(0, 0x080);
1118 #endif
1119 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1120 serial_outp(up, UART_IER, scratch);
1121 if (scratch2 != 0 || scratch3 != 0x0F) {
1122 /*
1123 * We failed; there's nothing here
1124 */
1125 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1126 scratch2, scratch3);
1127 goto out;
1128 }
1129 }
1130
1131 save_mcr = serial_in(up, UART_MCR);
1132 save_lcr = serial_in(up, UART_LCR);
1133
1134 /*
1135 * Check to see if a UART is really there. Certain broken
1136 * internal modems based on the Rockwell chipset fail this
1137 * test, because they apparently don't implement the loopback
1138 * test mode. So this test is skipped on the COM 1 through
1139 * COM 4 ports. This *should* be safe, since no board
1140 * manufacturer would be stupid enough to design a board
1141 * that conflicts with COM 1-4 --- we hope!
1142 */
1143 if (!(up->port.flags & UPF_SKIP_TEST)) {
1144 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1145 status1 = serial_inp(up, UART_MSR) & 0xF0;
1146 serial_outp(up, UART_MCR, save_mcr);
1147 if (status1 != 0x90) {
1148 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1149 status1);
1150 goto out;
1151 }
1152 }
1153
1154 /*
1155 * We're pretty sure there's a port here. Lets find out what
1156 * type of port it is. The IIR top two bits allows us to find
1157 * out if it's 8250 or 16450, 16550, 16550A or later. This
1158 * determines what we test for next.
1159 *
1160 * We also initialise the EFR (if any) to zero for later. The
1161 * EFR occupies the same register location as the FCR and IIR.
1162 */
1163 serial_outp(up, UART_LCR, 0xBF);
1164 serial_outp(up, UART_EFR, 0);
1165 serial_outp(up, UART_LCR, 0);
1166
1167 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1168 scratch = serial_in(up, UART_IIR) >> 6;
1169
1170 DEBUG_AUTOCONF("iir=%d ", scratch);
1171
1172 switch (scratch) {
1173 case 0:
1174 autoconfig_8250(up);
1175 break;
1176 case 1:
1177 up->port.type = PORT_UNKNOWN;
1178 break;
1179 case 2:
1180 up->port.type = PORT_16550;
1181 break;
1182 case 3:
1183 autoconfig_16550a(up);
1184 break;
1185 }
1186
1187 #ifdef CONFIG_SERIAL_8250_RSA
1188 /*
1189 * Only probe for RSA ports if we got the region.
1190 */
1191 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1192 int i;
1193
1194 for (i = 0 ; i < probe_rsa_count; ++i) {
1195 if (probe_rsa[i] == up->port.iobase &&
1196 __enable_rsa(up)) {
1197 up->port.type = PORT_RSA;
1198 break;
1199 }
1200 }
1201 }
1202 #endif
1203
1204 #ifdef CONFIG_SERIAL_8250_AU1X00
1205 /* if access method is AU, it is a 16550 with a quirk */
1206 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1207 up->bugs |= UART_BUG_NOMSR;
1208 #endif
1209
1210 serial_outp(up, UART_LCR, save_lcr);
1211
1212 if (up->capabilities != uart_config[up->port.type].flags) {
1213 printk(KERN_WARNING
1214 "ttyS%d: detected caps %08x should be %08x\n",
1215 serial_index(&up->port), up->capabilities,
1216 uart_config[up->port.type].flags);
1217 }
1218
1219 up->port.fifosize = uart_config[up->port.type].fifo_size;
1220 up->capabilities = uart_config[up->port.type].flags;
1221 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1222
1223 if (up->port.type == PORT_UNKNOWN)
1224 goto out;
1225
1226 /*
1227 * Reset the UART.
1228 */
1229 #ifdef CONFIG_SERIAL_8250_RSA
1230 if (up->port.type == PORT_RSA)
1231 serial_outp(up, UART_RSA_FRR, 0);
1232 #endif
1233 serial_outp(up, UART_MCR, save_mcr);
1234 serial8250_clear_fifos(up);
1235 serial_in(up, UART_RX);
1236 if (up->capabilities & UART_CAP_UUE)
1237 serial_outp(up, UART_IER, UART_IER_UUE);
1238 else
1239 serial_outp(up, UART_IER, 0);
1240
1241 out:
1242 spin_unlock_irqrestore(&up->port.lock, flags);
1243 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1244 }
1245
1246 static void autoconfig_irq(struct uart_8250_port *up)
1247 {
1248 unsigned char save_mcr, save_ier;
1249 unsigned char save_ICP = 0;
1250 unsigned int ICP = 0;
1251 unsigned long irqs;
1252 int irq;
1253
1254 if (up->port.flags & UPF_FOURPORT) {
1255 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1256 save_ICP = inb_p(ICP);
1257 outb_p(0x80, ICP);
1258 (void) inb_p(ICP);
1259 }
1260
1261 /* forget possible initially masked and pending IRQ */
1262 probe_irq_off(probe_irq_on());
1263 save_mcr = serial_inp(up, UART_MCR);
1264 save_ier = serial_inp(up, UART_IER);
1265 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1266
1267 irqs = probe_irq_on();
1268 serial_outp(up, UART_MCR, 0);
1269 udelay(10);
1270 if (up->port.flags & UPF_FOURPORT) {
1271 serial_outp(up, UART_MCR,
1272 UART_MCR_DTR | UART_MCR_RTS);
1273 } else {
1274 serial_outp(up, UART_MCR,
1275 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1276 }
1277 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1278 (void)serial_inp(up, UART_LSR);
1279 (void)serial_inp(up, UART_RX);
1280 (void)serial_inp(up, UART_IIR);
1281 (void)serial_inp(up, UART_MSR);
1282 serial_outp(up, UART_TX, 0xFF);
1283 udelay(20);
1284 irq = probe_irq_off(irqs);
1285
1286 serial_outp(up, UART_MCR, save_mcr);
1287 serial_outp(up, UART_IER, save_ier);
1288
1289 if (up->port.flags & UPF_FOURPORT)
1290 outb_p(save_ICP, ICP);
1291
1292 up->port.irq = (irq > 0) ? irq : 0;
1293 }
1294
1295 static inline void __stop_tx(struct uart_8250_port *p)
1296 {
1297 if (p->ier & UART_IER_THRI) {
1298 p->ier &= ~UART_IER_THRI;
1299 serial_out(p, UART_IER, p->ier);
1300 }
1301 }
1302
1303 static void serial8250_stop_tx(struct uart_port *port)
1304 {
1305 struct uart_8250_port *up = (struct uart_8250_port *)port;
1306
1307 __stop_tx(up);
1308
1309 /*
1310 * We really want to stop the transmitter from sending.
1311 */
1312 if (up->port.type == PORT_16C950) {
1313 up->acr |= UART_ACR_TXDIS;
1314 serial_icr_write(up, UART_ACR, up->acr);
1315 }
1316 }
1317
1318 static void transmit_chars(struct uart_8250_port *up);
1319
1320 static void serial8250_start_tx(struct uart_port *port)
1321 {
1322 struct uart_8250_port *up = (struct uart_8250_port *)port;
1323
1324 if (!(up->ier & UART_IER_THRI)) {
1325 up->ier |= UART_IER_THRI;
1326 serial_out(up, UART_IER, up->ier);
1327
1328 if (up->bugs & UART_BUG_TXEN) {
1329 unsigned char lsr, iir;
1330 lsr = serial_in(up, UART_LSR);
1331 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1332 iir = serial_in(up, UART_IIR) & 0x0f;
1333 if ((up->port.type == PORT_RM9000) ?
1334 (lsr & UART_LSR_THRE &&
1335 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1336 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1337 transmit_chars(up);
1338 }
1339 }
1340
1341 /*
1342 * Re-enable the transmitter if we disabled it.
1343 */
1344 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1345 up->acr &= ~UART_ACR_TXDIS;
1346 serial_icr_write(up, UART_ACR, up->acr);
1347 }
1348 }
1349
1350 static void serial8250_stop_rx(struct uart_port *port)
1351 {
1352 struct uart_8250_port *up = (struct uart_8250_port *)port;
1353
1354 up->ier &= ~UART_IER_RLSI;
1355 up->port.read_status_mask &= ~UART_LSR_DR;
1356 serial_out(up, UART_IER, up->ier);
1357 }
1358
1359 static void serial8250_enable_ms(struct uart_port *port)
1360 {
1361 struct uart_8250_port *up = (struct uart_8250_port *)port;
1362
1363 /* no MSR capabilities */
1364 if (up->bugs & UART_BUG_NOMSR)
1365 return;
1366
1367 up->ier |= UART_IER_MSI;
1368 serial_out(up, UART_IER, up->ier);
1369 }
1370
1371 static void
1372 receive_chars(struct uart_8250_port *up, unsigned int *status)
1373 {
1374 struct tty_struct *tty = up->port.info->port.tty;
1375 unsigned char ch, lsr = *status;
1376 int max_count = 256;
1377 char flag;
1378
1379 do {
1380 if (likely(lsr & UART_LSR_DR))
1381 ch = serial_inp(up, UART_RX);
1382 else
1383 /*
1384 * Intel 82571 has a Serial Over Lan device that will
1385 * set UART_LSR_BI without setting UART_LSR_DR when
1386 * it receives a break. To avoid reading from the
1387 * receive buffer without UART_LSR_DR bit set, we
1388 * just force the read character to be 0
1389 */
1390 ch = 0;
1391
1392 flag = TTY_NORMAL;
1393 up->port.icount.rx++;
1394
1395 lsr |= up->lsr_saved_flags;
1396 up->lsr_saved_flags = 0;
1397
1398 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1399 /*
1400 * For statistics only
1401 */
1402 if (lsr & UART_LSR_BI) {
1403 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1404 up->port.icount.brk++;
1405 /*
1406 * We do the SysRQ and SAK checking
1407 * here because otherwise the break
1408 * may get masked by ignore_status_mask
1409 * or read_status_mask.
1410 */
1411 if (uart_handle_break(&up->port))
1412 goto ignore_char;
1413 } else if (lsr & UART_LSR_PE)
1414 up->port.icount.parity++;
1415 else if (lsr & UART_LSR_FE)
1416 up->port.icount.frame++;
1417 if (lsr & UART_LSR_OE)
1418 up->port.icount.overrun++;
1419
1420 /*
1421 * Mask off conditions which should be ignored.
1422 */
1423 lsr &= up->port.read_status_mask;
1424
1425 if (lsr & UART_LSR_BI) {
1426 DEBUG_INTR("handling break....");
1427 flag = TTY_BREAK;
1428 } else if (lsr & UART_LSR_PE)
1429 flag = TTY_PARITY;
1430 else if (lsr & UART_LSR_FE)
1431 flag = TTY_FRAME;
1432 }
1433 if (uart_handle_sysrq_char(&up->port, ch))
1434 goto ignore_char;
1435
1436 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1437
1438 ignore_char:
1439 lsr = serial_inp(up, UART_LSR);
1440 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1441 spin_unlock(&up->port.lock);
1442 tty_flip_buffer_push(tty);
1443 spin_lock(&up->port.lock);
1444 *status = lsr;
1445 }
1446
1447 static void transmit_chars(struct uart_8250_port *up)
1448 {
1449 struct circ_buf *xmit = &up->port.info->xmit;
1450 int count;
1451
1452 if (up->port.x_char) {
1453 serial_outp(up, UART_TX, up->port.x_char);
1454 up->port.icount.tx++;
1455 up->port.x_char = 0;
1456 return;
1457 }
1458 if (uart_tx_stopped(&up->port)) {
1459 serial8250_stop_tx(&up->port);
1460 return;
1461 }
1462 if (uart_circ_empty(xmit)) {
1463 __stop_tx(up);
1464 return;
1465 }
1466
1467 count = up->tx_loadsz;
1468 do {
1469 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1470 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1471 up->port.icount.tx++;
1472 if (uart_circ_empty(xmit))
1473 break;
1474 } while (--count > 0);
1475
1476 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1477 uart_write_wakeup(&up->port);
1478
1479 DEBUG_INTR("THRE...");
1480
1481 if (uart_circ_empty(xmit))
1482 __stop_tx(up);
1483 }
1484
1485 static unsigned int check_modem_status(struct uart_8250_port *up)
1486 {
1487 unsigned int status = serial_in(up, UART_MSR);
1488
1489 status |= up->msr_saved_flags;
1490 up->msr_saved_flags = 0;
1491 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1492 up->port.info != NULL) {
1493 if (status & UART_MSR_TERI)
1494 up->port.icount.rng++;
1495 if (status & UART_MSR_DDSR)
1496 up->port.icount.dsr++;
1497 if (status & UART_MSR_DDCD)
1498 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1499 if (status & UART_MSR_DCTS)
1500 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1501
1502 wake_up_interruptible(&up->port.info->delta_msr_wait);
1503 }
1504
1505 return status;
1506 }
1507
1508 /*
1509 * This handles the interrupt from one port.
1510 */
1511 static void serial8250_handle_port(struct uart_8250_port *up)
1512 {
1513 unsigned int status;
1514 unsigned long flags;
1515
1516 spin_lock_irqsave(&up->port.lock, flags);
1517
1518 status = serial_inp(up, UART_LSR);
1519
1520 DEBUG_INTR("status = %x...", status);
1521
1522 if (status & (UART_LSR_DR | UART_LSR_BI))
1523 receive_chars(up, &status);
1524 check_modem_status(up);
1525 if (status & UART_LSR_THRE)
1526 transmit_chars(up);
1527
1528 spin_unlock_irqrestore(&up->port.lock, flags);
1529 }
1530
1531 /*
1532 * This is the serial driver's interrupt routine.
1533 *
1534 * Arjan thinks the old way was overly complex, so it got simplified.
1535 * Alan disagrees, saying that need the complexity to handle the weird
1536 * nature of ISA shared interrupts. (This is a special exception.)
1537 *
1538 * In order to handle ISA shared interrupts properly, we need to check
1539 * that all ports have been serviced, and therefore the ISA interrupt
1540 * line has been de-asserted.
1541 *
1542 * This means we need to loop through all ports. checking that they
1543 * don't have an interrupt pending.
1544 */
1545 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1546 {
1547 struct irq_info *i = dev_id;
1548 struct list_head *l, *end = NULL;
1549 int pass_counter = 0, handled = 0;
1550
1551 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1552
1553 spin_lock(&i->lock);
1554
1555 l = i->head;
1556 do {
1557 struct uart_8250_port *up;
1558 unsigned int iir;
1559
1560 up = list_entry(l, struct uart_8250_port, list);
1561
1562 iir = serial_in(up, UART_IIR);
1563 if (!(iir & UART_IIR_NO_INT)) {
1564 serial8250_handle_port(up);
1565
1566 handled = 1;
1567
1568 end = NULL;
1569 } else if (up->port.iotype == UPIO_DWAPB &&
1570 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1571 /* The DesignWare APB UART has an Busy Detect (0x07)
1572 * interrupt meaning an LCR write attempt occured while the
1573 * UART was busy. The interrupt must be cleared by reading
1574 * the UART status register (USR) and the LCR re-written. */
1575 unsigned int status;
1576 status = *(volatile u32 *)up->port.private_data;
1577 serial_out(up, UART_LCR, up->lcr);
1578
1579 handled = 1;
1580
1581 end = NULL;
1582 } else if (end == NULL)
1583 end = l;
1584
1585 l = l->next;
1586
1587 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1588 /* If we hit this, we're dead. */
1589 printk(KERN_ERR "serial8250: too much work for "
1590 "irq%d\n", irq);
1591 break;
1592 }
1593 } while (l != end);
1594
1595 spin_unlock(&i->lock);
1596
1597 DEBUG_INTR("end.\n");
1598
1599 return IRQ_RETVAL(handled);
1600 }
1601
1602 /*
1603 * To support ISA shared interrupts, we need to have one interrupt
1604 * handler that ensures that the IRQ line has been deasserted
1605 * before returning. Failing to do this will result in the IRQ
1606 * line being stuck active, and, since ISA irqs are edge triggered,
1607 * no more IRQs will be seen.
1608 */
1609 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1610 {
1611 spin_lock_irq(&i->lock);
1612
1613 if (!list_empty(i->head)) {
1614 if (i->head == &up->list)
1615 i->head = i->head->next;
1616 list_del(&up->list);
1617 } else {
1618 BUG_ON(i->head != &up->list);
1619 i->head = NULL;
1620 }
1621 spin_unlock_irq(&i->lock);
1622 /* List empty so throw away the hash node */
1623 if (i->head == NULL) {
1624 hlist_del(&i->node);
1625 kfree(i);
1626 }
1627 }
1628
1629 static int serial_link_irq_chain(struct uart_8250_port *up)
1630 {
1631 struct hlist_head *h;
1632 struct hlist_node *n;
1633 struct irq_info *i;
1634 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1635
1636 mutex_lock(&hash_mutex);
1637
1638 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1639
1640 hlist_for_each(n, h) {
1641 i = hlist_entry(n, struct irq_info, node);
1642 if (i->irq == up->port.irq)
1643 break;
1644 }
1645
1646 if (n == NULL) {
1647 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1648 if (i == NULL) {
1649 mutex_unlock(&hash_mutex);
1650 return -ENOMEM;
1651 }
1652 spin_lock_init(&i->lock);
1653 i->irq = up->port.irq;
1654 hlist_add_head(&i->node, h);
1655 }
1656 mutex_unlock(&hash_mutex);
1657
1658 spin_lock_irq(&i->lock);
1659
1660 if (i->head) {
1661 list_add(&up->list, i->head);
1662 spin_unlock_irq(&i->lock);
1663
1664 ret = 0;
1665 } else {
1666 INIT_LIST_HEAD(&up->list);
1667 i->head = &up->list;
1668 spin_unlock_irq(&i->lock);
1669
1670 ret = request_irq(up->port.irq, serial8250_interrupt,
1671 irq_flags, "serial", i);
1672 if (ret < 0)
1673 serial_do_unlink(i, up);
1674 }
1675
1676 return ret;
1677 }
1678
1679 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1680 {
1681 struct irq_info *i;
1682 struct hlist_node *n;
1683 struct hlist_head *h;
1684
1685 mutex_lock(&hash_mutex);
1686
1687 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1688
1689 hlist_for_each(n, h) {
1690 i = hlist_entry(n, struct irq_info, node);
1691 if (i->irq == up->port.irq)
1692 break;
1693 }
1694
1695 BUG_ON(n == NULL);
1696 BUG_ON(i->head == NULL);
1697
1698 if (list_empty(i->head))
1699 free_irq(up->port.irq, i);
1700
1701 serial_do_unlink(i, up);
1702 mutex_unlock(&hash_mutex);
1703 }
1704
1705 /* Base timer interval for polling */
1706 static inline int poll_timeout(int timeout)
1707 {
1708 return timeout > 6 ? (timeout / 2 - 2) : 1;
1709 }
1710
1711 /*
1712 * This function is used to handle ports that do not have an
1713 * interrupt. This doesn't work very well for 16450's, but gives
1714 * barely passable results for a 16550A. (Although at the expense
1715 * of much CPU overhead).
1716 */
1717 static void serial8250_timeout(unsigned long data)
1718 {
1719 struct uart_8250_port *up = (struct uart_8250_port *)data;
1720 unsigned int iir;
1721
1722 iir = serial_in(up, UART_IIR);
1723 if (!(iir & UART_IIR_NO_INT))
1724 serial8250_handle_port(up);
1725 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1726 }
1727
1728 static void serial8250_backup_timeout(unsigned long data)
1729 {
1730 struct uart_8250_port *up = (struct uart_8250_port *)data;
1731 unsigned int iir, ier = 0, lsr;
1732 unsigned long flags;
1733
1734 /*
1735 * Must disable interrupts or else we risk racing with the interrupt
1736 * based handler.
1737 */
1738 if (is_real_interrupt(up->port.irq)) {
1739 ier = serial_in(up, UART_IER);
1740 serial_out(up, UART_IER, 0);
1741 }
1742
1743 iir = serial_in(up, UART_IIR);
1744
1745 /*
1746 * This should be a safe test for anyone who doesn't trust the
1747 * IIR bits on their UART, but it's specifically designed for
1748 * the "Diva" UART used on the management processor on many HP
1749 * ia64 and parisc boxes.
1750 */
1751 spin_lock_irqsave(&up->port.lock, flags);
1752 lsr = serial_in(up, UART_LSR);
1753 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1754 spin_unlock_irqrestore(&up->port.lock, flags);
1755 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1756 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1757 (lsr & UART_LSR_THRE)) {
1758 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1759 iir |= UART_IIR_THRI;
1760 }
1761
1762 if (!(iir & UART_IIR_NO_INT))
1763 serial8250_handle_port(up);
1764
1765 if (is_real_interrupt(up->port.irq))
1766 serial_out(up, UART_IER, ier);
1767
1768 /* Standard timer interval plus 0.2s to keep the port running */
1769 mod_timer(&up->timer,
1770 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1771 }
1772
1773 static unsigned int serial8250_tx_empty(struct uart_port *port)
1774 {
1775 struct uart_8250_port *up = (struct uart_8250_port *)port;
1776 unsigned long flags;
1777 unsigned int lsr;
1778
1779 spin_lock_irqsave(&up->port.lock, flags);
1780 lsr = serial_in(up, UART_LSR);
1781 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1782 spin_unlock_irqrestore(&up->port.lock, flags);
1783
1784 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1785 }
1786
1787 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1788 {
1789 struct uart_8250_port *up = (struct uart_8250_port *)port;
1790 unsigned int status;
1791 unsigned int ret;
1792
1793 status = check_modem_status(up);
1794
1795 ret = 0;
1796 if (status & UART_MSR_DCD)
1797 ret |= TIOCM_CAR;
1798 if (status & UART_MSR_RI)
1799 ret |= TIOCM_RNG;
1800 if (status & UART_MSR_DSR)
1801 ret |= TIOCM_DSR;
1802 if (status & UART_MSR_CTS)
1803 ret |= TIOCM_CTS;
1804 return ret;
1805 }
1806
1807 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1808 {
1809 struct uart_8250_port *up = (struct uart_8250_port *)port;
1810 unsigned char mcr = 0;
1811
1812 if (mctrl & TIOCM_RTS)
1813 mcr |= UART_MCR_RTS;
1814 if (mctrl & TIOCM_DTR)
1815 mcr |= UART_MCR_DTR;
1816 if (mctrl & TIOCM_OUT1)
1817 mcr |= UART_MCR_OUT1;
1818 if (mctrl & TIOCM_OUT2)
1819 mcr |= UART_MCR_OUT2;
1820 if (mctrl & TIOCM_LOOP)
1821 mcr |= UART_MCR_LOOP;
1822
1823 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1824
1825 serial_out(up, UART_MCR, mcr);
1826 }
1827
1828 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1829 {
1830 struct uart_8250_port *up = (struct uart_8250_port *)port;
1831 unsigned long flags;
1832
1833 spin_lock_irqsave(&up->port.lock, flags);
1834 if (break_state == -1)
1835 up->lcr |= UART_LCR_SBC;
1836 else
1837 up->lcr &= ~UART_LCR_SBC;
1838 serial_out(up, UART_LCR, up->lcr);
1839 spin_unlock_irqrestore(&up->port.lock, flags);
1840 }
1841
1842 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1843
1844 /*
1845 * Wait for transmitter & holding register to empty
1846 */
1847 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1848 {
1849 unsigned int status, tmout = 10000;
1850
1851 /* Wait up to 10ms for the character(s) to be sent. */
1852 do {
1853 status = serial_in(up, UART_LSR);
1854
1855 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1856
1857 if (--tmout == 0)
1858 break;
1859 udelay(1);
1860 } while ((status & bits) != bits);
1861
1862 /* Wait up to 1s for flow control if necessary */
1863 if (up->port.flags & UPF_CONS_FLOW) {
1864 unsigned int tmout;
1865 for (tmout = 1000000; tmout; tmout--) {
1866 unsigned int msr = serial_in(up, UART_MSR);
1867 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1868 if (msr & UART_MSR_CTS)
1869 break;
1870 udelay(1);
1871 touch_nmi_watchdog();
1872 }
1873 }
1874 }
1875
1876 #ifdef CONFIG_CONSOLE_POLL
1877 /*
1878 * Console polling routines for writing and reading from the uart while
1879 * in an interrupt or debug context.
1880 */
1881
1882 static int serial8250_get_poll_char(struct uart_port *port)
1883 {
1884 struct uart_8250_port *up = (struct uart_8250_port *)port;
1885 unsigned char lsr = serial_inp(up, UART_LSR);
1886
1887 while (!(lsr & UART_LSR_DR))
1888 lsr = serial_inp(up, UART_LSR);
1889
1890 return serial_inp(up, UART_RX);
1891 }
1892
1893
1894 static void serial8250_put_poll_char(struct uart_port *port,
1895 unsigned char c)
1896 {
1897 unsigned int ier;
1898 struct uart_8250_port *up = (struct uart_8250_port *)port;
1899
1900 /*
1901 * First save the IER then disable the interrupts
1902 */
1903 ier = serial_in(up, UART_IER);
1904 if (up->capabilities & UART_CAP_UUE)
1905 serial_out(up, UART_IER, UART_IER_UUE);
1906 else
1907 serial_out(up, UART_IER, 0);
1908
1909 wait_for_xmitr(up, BOTH_EMPTY);
1910 /*
1911 * Send the character out.
1912 * If a LF, also do CR...
1913 */
1914 serial_out(up, UART_TX, c);
1915 if (c == 10) {
1916 wait_for_xmitr(up, BOTH_EMPTY);
1917 serial_out(up, UART_TX, 13);
1918 }
1919
1920 /*
1921 * Finally, wait for transmitter to become empty
1922 * and restore the IER
1923 */
1924 wait_for_xmitr(up, BOTH_EMPTY);
1925 serial_out(up, UART_IER, ier);
1926 }
1927
1928 #endif /* CONFIG_CONSOLE_POLL */
1929
1930 static int serial8250_startup(struct uart_port *port)
1931 {
1932 struct uart_8250_port *up = (struct uart_8250_port *)port;
1933 unsigned long flags;
1934 unsigned char lsr, iir;
1935 int retval;
1936
1937 up->capabilities = uart_config[up->port.type].flags;
1938 up->mcr = 0;
1939
1940 if (up->port.type == PORT_16C950) {
1941 /* Wake up and initialize UART */
1942 up->acr = 0;
1943 serial_outp(up, UART_LCR, 0xBF);
1944 serial_outp(up, UART_EFR, UART_EFR_ECB);
1945 serial_outp(up, UART_IER, 0);
1946 serial_outp(up, UART_LCR, 0);
1947 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1948 serial_outp(up, UART_LCR, 0xBF);
1949 serial_outp(up, UART_EFR, UART_EFR_ECB);
1950 serial_outp(up, UART_LCR, 0);
1951 }
1952
1953 #ifdef CONFIG_SERIAL_8250_RSA
1954 /*
1955 * If this is an RSA port, see if we can kick it up to the
1956 * higher speed clock.
1957 */
1958 enable_rsa(up);
1959 #endif
1960
1961 /*
1962 * Clear the FIFO buffers and disable them.
1963 * (they will be reenabled in set_termios())
1964 */
1965 serial8250_clear_fifos(up);
1966
1967 /*
1968 * Clear the interrupt registers.
1969 */
1970 (void) serial_inp(up, UART_LSR);
1971 (void) serial_inp(up, UART_RX);
1972 (void) serial_inp(up, UART_IIR);
1973 (void) serial_inp(up, UART_MSR);
1974
1975 /*
1976 * At this point, there's no way the LSR could still be 0xff;
1977 * if it is, then bail out, because there's likely no UART
1978 * here.
1979 */
1980 if (!(up->port.flags & UPF_BUGGY_UART) &&
1981 (serial_inp(up, UART_LSR) == 0xff)) {
1982 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1983 serial_index(&up->port));
1984 return -ENODEV;
1985 }
1986
1987 /*
1988 * For a XR16C850, we need to set the trigger levels
1989 */
1990 if (up->port.type == PORT_16850) {
1991 unsigned char fctr;
1992
1993 serial_outp(up, UART_LCR, 0xbf);
1994
1995 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1996 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1997 serial_outp(up, UART_TRG, UART_TRG_96);
1998 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1999 serial_outp(up, UART_TRG, UART_TRG_96);
2000
2001 serial_outp(up, UART_LCR, 0);
2002 }
2003
2004 if (is_real_interrupt(up->port.irq)) {
2005 unsigned char iir1;
2006 /*
2007 * Test for UARTs that do not reassert THRE when the
2008 * transmitter is idle and the interrupt has already
2009 * been cleared. Real 16550s should always reassert
2010 * this interrupt whenever the transmitter is idle and
2011 * the interrupt is enabled. Delays are necessary to
2012 * allow register changes to become visible.
2013 */
2014 spin_lock_irqsave(&up->port.lock, flags);
2015 if (up->port.flags & UPF_SHARE_IRQ)
2016 disable_irq_nosync(up->port.irq);
2017
2018 wait_for_xmitr(up, UART_LSR_THRE);
2019 serial_out_sync(up, UART_IER, UART_IER_THRI);
2020 udelay(1); /* allow THRE to set */
2021 iir1 = serial_in(up, UART_IIR);
2022 serial_out(up, UART_IER, 0);
2023 serial_out_sync(up, UART_IER, UART_IER_THRI);
2024 udelay(1); /* allow a working UART time to re-assert THRE */
2025 iir = serial_in(up, UART_IIR);
2026 serial_out(up, UART_IER, 0);
2027
2028 if (up->port.flags & UPF_SHARE_IRQ)
2029 enable_irq(up->port.irq);
2030 spin_unlock_irqrestore(&up->port.lock, flags);
2031
2032 /*
2033 * If the interrupt is not reasserted, setup a timer to
2034 * kick the UART on a regular basis.
2035 */
2036 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2037 up->bugs |= UART_BUG_THRE;
2038 pr_debug("ttyS%d - using backup timer\n",
2039 serial_index(port));
2040 }
2041 }
2042
2043 /*
2044 * The above check will only give an accurate result the first time
2045 * the port is opened so this value needs to be preserved.
2046 */
2047 if (up->bugs & UART_BUG_THRE) {
2048 up->timer.function = serial8250_backup_timeout;
2049 up->timer.data = (unsigned long)up;
2050 mod_timer(&up->timer, jiffies +
2051 poll_timeout(up->port.timeout) + HZ / 5);
2052 }
2053
2054 /*
2055 * If the "interrupt" for this port doesn't correspond with any
2056 * hardware interrupt, we use a timer-based system. The original
2057 * driver used to do this with IRQ0.
2058 */
2059 if (!is_real_interrupt(up->port.irq)) {
2060 up->timer.data = (unsigned long)up;
2061 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
2062 } else {
2063 retval = serial_link_irq_chain(up);
2064 if (retval)
2065 return retval;
2066 }
2067
2068 /*
2069 * Now, initialize the UART
2070 */
2071 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2072
2073 spin_lock_irqsave(&up->port.lock, flags);
2074 if (up->port.flags & UPF_FOURPORT) {
2075 if (!is_real_interrupt(up->port.irq))
2076 up->port.mctrl |= TIOCM_OUT1;
2077 } else
2078 /*
2079 * Most PC uarts need OUT2 raised to enable interrupts.
2080 */
2081 if (is_real_interrupt(up->port.irq))
2082 up->port.mctrl |= TIOCM_OUT2;
2083
2084 serial8250_set_mctrl(&up->port, up->port.mctrl);
2085
2086 /*
2087 * Do a quick test to see if we receive an
2088 * interrupt when we enable the TX irq.
2089 */
2090 serial_outp(up, UART_IER, UART_IER_THRI);
2091 lsr = serial_in(up, UART_LSR);
2092 iir = serial_in(up, UART_IIR);
2093 serial_outp(up, UART_IER, 0);
2094
2095 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2096 if (!(up->bugs & UART_BUG_TXEN)) {
2097 up->bugs |= UART_BUG_TXEN;
2098 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2099 serial_index(port));
2100 }
2101 } else {
2102 up->bugs &= ~UART_BUG_TXEN;
2103 }
2104
2105 spin_unlock_irqrestore(&up->port.lock, flags);
2106
2107 /*
2108 * Clear the interrupt registers again for luck, and clear the
2109 * saved flags to avoid getting false values from polling
2110 * routines or the previous session.
2111 */
2112 serial_inp(up, UART_LSR);
2113 serial_inp(up, UART_RX);
2114 serial_inp(up, UART_IIR);
2115 serial_inp(up, UART_MSR);
2116 up->lsr_saved_flags = 0;
2117 up->msr_saved_flags = 0;
2118
2119 /*
2120 * Finally, enable interrupts. Note: Modem status interrupts
2121 * are set via set_termios(), which will be occurring imminently
2122 * anyway, so we don't enable them here.
2123 */
2124 up->ier = UART_IER_RLSI | UART_IER_RDI;
2125 serial_outp(up, UART_IER, up->ier);
2126
2127 if (up->port.flags & UPF_FOURPORT) {
2128 unsigned int icp;
2129 /*
2130 * Enable interrupts on the AST Fourport board
2131 */
2132 icp = (up->port.iobase & 0xfe0) | 0x01f;
2133 outb_p(0x80, icp);
2134 (void) inb_p(icp);
2135 }
2136
2137 return 0;
2138 }
2139
2140 static void serial8250_shutdown(struct uart_port *port)
2141 {
2142 struct uart_8250_port *up = (struct uart_8250_port *)port;
2143 unsigned long flags;
2144
2145 /*
2146 * Disable interrupts from this port
2147 */
2148 up->ier = 0;
2149 serial_outp(up, UART_IER, 0);
2150
2151 spin_lock_irqsave(&up->port.lock, flags);
2152 if (up->port.flags & UPF_FOURPORT) {
2153 /* reset interrupts on the AST Fourport board */
2154 inb((up->port.iobase & 0xfe0) | 0x1f);
2155 up->port.mctrl |= TIOCM_OUT1;
2156 } else
2157 up->port.mctrl &= ~TIOCM_OUT2;
2158
2159 serial8250_set_mctrl(&up->port, up->port.mctrl);
2160 spin_unlock_irqrestore(&up->port.lock, flags);
2161
2162 /*
2163 * Disable break condition and FIFOs
2164 */
2165 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2166 serial8250_clear_fifos(up);
2167
2168 #ifdef CONFIG_SERIAL_8250_RSA
2169 /*
2170 * Reset the RSA board back to 115kbps compat mode.
2171 */
2172 disable_rsa(up);
2173 #endif
2174
2175 /*
2176 * Read data port to reset things, and then unlink from
2177 * the IRQ chain.
2178 */
2179 (void) serial_in(up, UART_RX);
2180
2181 del_timer_sync(&up->timer);
2182 up->timer.function = serial8250_timeout;
2183 if (is_real_interrupt(up->port.irq))
2184 serial_unlink_irq_chain(up);
2185 }
2186
2187 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2188 {
2189 unsigned int quot;
2190
2191 /*
2192 * Handle magic divisors for baud rates above baud_base on
2193 * SMSC SuperIO chips.
2194 */
2195 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2196 baud == (port->uartclk/4))
2197 quot = 0x8001;
2198 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2199 baud == (port->uartclk/8))
2200 quot = 0x8002;
2201 else
2202 quot = uart_get_divisor(port, baud);
2203
2204 return quot;
2205 }
2206
2207 static void
2208 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2209 struct ktermios *old)
2210 {
2211 struct uart_8250_port *up = (struct uart_8250_port *)port;
2212 unsigned char cval, fcr = 0;
2213 unsigned long flags;
2214 unsigned int baud, quot;
2215
2216 switch (termios->c_cflag & CSIZE) {
2217 case CS5:
2218 cval = UART_LCR_WLEN5;
2219 break;
2220 case CS6:
2221 cval = UART_LCR_WLEN6;
2222 break;
2223 case CS7:
2224 cval = UART_LCR_WLEN7;
2225 break;
2226 default:
2227 case CS8:
2228 cval = UART_LCR_WLEN8;
2229 break;
2230 }
2231
2232 if (termios->c_cflag & CSTOPB)
2233 cval |= UART_LCR_STOP;
2234 if (termios->c_cflag & PARENB)
2235 cval |= UART_LCR_PARITY;
2236 if (!(termios->c_cflag & PARODD))
2237 cval |= UART_LCR_EPAR;
2238 #ifdef CMSPAR
2239 if (termios->c_cflag & CMSPAR)
2240 cval |= UART_LCR_SPAR;
2241 #endif
2242
2243 /*
2244 * Ask the core to calculate the divisor for us.
2245 */
2246 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2247 quot = serial8250_get_divisor(port, baud);
2248
2249 /*
2250 * Oxford Semi 952 rev B workaround
2251 */
2252 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2253 quot++;
2254
2255 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2256 if (baud < 2400)
2257 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2258 else
2259 fcr = uart_config[up->port.type].fcr;
2260 }
2261
2262 /*
2263 * MCR-based auto flow control. When AFE is enabled, RTS will be
2264 * deasserted when the receive FIFO contains more characters than
2265 * the trigger, or the MCR RTS bit is cleared. In the case where
2266 * the remote UART is not using CTS auto flow control, we must
2267 * have sufficient FIFO entries for the latency of the remote
2268 * UART to respond. IOW, at least 32 bytes of FIFO.
2269 */
2270 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2271 up->mcr &= ~UART_MCR_AFE;
2272 if (termios->c_cflag & CRTSCTS)
2273 up->mcr |= UART_MCR_AFE;
2274 }
2275
2276 /*
2277 * Ok, we're now changing the port state. Do it with
2278 * interrupts disabled.
2279 */
2280 spin_lock_irqsave(&up->port.lock, flags);
2281
2282 /*
2283 * Update the per-port timeout.
2284 */
2285 uart_update_timeout(port, termios->c_cflag, baud);
2286
2287 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2288 if (termios->c_iflag & INPCK)
2289 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2290 if (termios->c_iflag & (BRKINT | PARMRK))
2291 up->port.read_status_mask |= UART_LSR_BI;
2292
2293 /*
2294 * Characteres to ignore
2295 */
2296 up->port.ignore_status_mask = 0;
2297 if (termios->c_iflag & IGNPAR)
2298 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2299 if (termios->c_iflag & IGNBRK) {
2300 up->port.ignore_status_mask |= UART_LSR_BI;
2301 /*
2302 * If we're ignoring parity and break indicators,
2303 * ignore overruns too (for real raw support).
2304 */
2305 if (termios->c_iflag & IGNPAR)
2306 up->port.ignore_status_mask |= UART_LSR_OE;
2307 }
2308
2309 /*
2310 * ignore all characters if CREAD is not set
2311 */
2312 if ((termios->c_cflag & CREAD) == 0)
2313 up->port.ignore_status_mask |= UART_LSR_DR;
2314
2315 /*
2316 * CTS flow control flag and modem status interrupts
2317 */
2318 up->ier &= ~UART_IER_MSI;
2319 if (!(up->bugs & UART_BUG_NOMSR) &&
2320 UART_ENABLE_MS(&up->port, termios->c_cflag))
2321 up->ier |= UART_IER_MSI;
2322 if (up->capabilities & UART_CAP_UUE)
2323 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2324
2325 serial_out(up, UART_IER, up->ier);
2326
2327 if (up->capabilities & UART_CAP_EFR) {
2328 unsigned char efr = 0;
2329 /*
2330 * TI16C752/Startech hardware flow control. FIXME:
2331 * - TI16C752 requires control thresholds to be set.
2332 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2333 */
2334 if (termios->c_cflag & CRTSCTS)
2335 efr |= UART_EFR_CTS;
2336
2337 serial_outp(up, UART_LCR, 0xBF);
2338 serial_outp(up, UART_EFR, efr);
2339 }
2340
2341 #ifdef CONFIG_ARCH_OMAP
2342 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2343 if (cpu_is_omap1510() && is_omap_port(up)) {
2344 if (baud == 115200) {
2345 quot = 1;
2346 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2347 } else
2348 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2349 }
2350 #endif
2351
2352 if (up->capabilities & UART_NATSEMI) {
2353 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2354 serial_outp(up, UART_LCR, 0xe0);
2355 } else {
2356 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2357 }
2358
2359 serial_dl_write(up, quot);
2360
2361 /*
2362 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2363 * is written without DLAB set, this mode will be disabled.
2364 */
2365 if (up->port.type == PORT_16750)
2366 serial_outp(up, UART_FCR, fcr);
2367
2368 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2369 up->lcr = cval; /* Save LCR */
2370 if (up->port.type != PORT_16750) {
2371 if (fcr & UART_FCR_ENABLE_FIFO) {
2372 /* emulated UARTs (Lucent Venus 167x) need two steps */
2373 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2374 }
2375 serial_outp(up, UART_FCR, fcr); /* set fcr */
2376 }
2377 serial8250_set_mctrl(&up->port, up->port.mctrl);
2378 spin_unlock_irqrestore(&up->port.lock, flags);
2379 /* Don't rewrite B0 */
2380 if (tty_termios_baud_rate(termios))
2381 tty_termios_encode_baud_rate(termios, baud, baud);
2382 }
2383
2384 static void
2385 serial8250_pm(struct uart_port *port, unsigned int state,
2386 unsigned int oldstate)
2387 {
2388 struct uart_8250_port *p = (struct uart_8250_port *)port;
2389
2390 serial8250_set_sleep(p, state != 0);
2391
2392 if (p->pm)
2393 p->pm(port, state, oldstate);
2394 }
2395
2396 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2397 {
2398 if (pt->port.iotype == UPIO_AU)
2399 return 0x100000;
2400 #ifdef CONFIG_ARCH_OMAP
2401 if (is_omap_port(pt))
2402 return 0x16 << pt->port.regshift;
2403 #endif
2404 return 8 << pt->port.regshift;
2405 }
2406
2407 /*
2408 * Resource handling.
2409 */
2410 static int serial8250_request_std_resource(struct uart_8250_port *up)
2411 {
2412 unsigned int size = serial8250_port_size(up);
2413 int ret = 0;
2414
2415 switch (up->port.iotype) {
2416 case UPIO_AU:
2417 case UPIO_TSI:
2418 case UPIO_MEM32:
2419 case UPIO_MEM:
2420 case UPIO_DWAPB:
2421 if (!up->port.mapbase)
2422 break;
2423
2424 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2425 ret = -EBUSY;
2426 break;
2427 }
2428
2429 if (up->port.flags & UPF_IOREMAP) {
2430 up->port.membase = ioremap_nocache(up->port.mapbase,
2431 size);
2432 if (!up->port.membase) {
2433 release_mem_region(up->port.mapbase, size);
2434 ret = -ENOMEM;
2435 }
2436 }
2437 break;
2438
2439 case UPIO_HUB6:
2440 case UPIO_PORT:
2441 if (!request_region(up->port.iobase, size, "serial"))
2442 ret = -EBUSY;
2443 break;
2444 }
2445 return ret;
2446 }
2447
2448 static void serial8250_release_std_resource(struct uart_8250_port *up)
2449 {
2450 unsigned int size = serial8250_port_size(up);
2451
2452 switch (up->port.iotype) {
2453 case UPIO_AU:
2454 case UPIO_TSI:
2455 case UPIO_MEM32:
2456 case UPIO_MEM:
2457 case UPIO_DWAPB:
2458 if (!up->port.mapbase)
2459 break;
2460
2461 if (up->port.flags & UPF_IOREMAP) {
2462 iounmap(up->port.membase);
2463 up->port.membase = NULL;
2464 }
2465
2466 release_mem_region(up->port.mapbase, size);
2467 break;
2468
2469 case UPIO_HUB6:
2470 case UPIO_PORT:
2471 release_region(up->port.iobase, size);
2472 break;
2473 }
2474 }
2475
2476 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2477 {
2478 unsigned long start = UART_RSA_BASE << up->port.regshift;
2479 unsigned int size = 8 << up->port.regshift;
2480 int ret = -EINVAL;
2481
2482 switch (up->port.iotype) {
2483 case UPIO_HUB6:
2484 case UPIO_PORT:
2485 start += up->port.iobase;
2486 if (request_region(start, size, "serial-rsa"))
2487 ret = 0;
2488 else
2489 ret = -EBUSY;
2490 break;
2491 }
2492
2493 return ret;
2494 }
2495
2496 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2497 {
2498 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2499 unsigned int size = 8 << up->port.regshift;
2500
2501 switch (up->port.iotype) {
2502 case UPIO_HUB6:
2503 case UPIO_PORT:
2504 release_region(up->port.iobase + offset, size);
2505 break;
2506 }
2507 }
2508
2509 static void serial8250_release_port(struct uart_port *port)
2510 {
2511 struct uart_8250_port *up = (struct uart_8250_port *)port;
2512
2513 serial8250_release_std_resource(up);
2514 if (up->port.type == PORT_RSA)
2515 serial8250_release_rsa_resource(up);
2516 }
2517
2518 static int serial8250_request_port(struct uart_port *port)
2519 {
2520 struct uart_8250_port *up = (struct uart_8250_port *)port;
2521 int ret = 0;
2522
2523 ret = serial8250_request_std_resource(up);
2524 if (ret == 0 && up->port.type == PORT_RSA) {
2525 ret = serial8250_request_rsa_resource(up);
2526 if (ret < 0)
2527 serial8250_release_std_resource(up);
2528 }
2529
2530 return ret;
2531 }
2532
2533 static void serial8250_config_port(struct uart_port *port, int flags)
2534 {
2535 struct uart_8250_port *up = (struct uart_8250_port *)port;
2536 int probeflags = PROBE_ANY;
2537 int ret;
2538
2539 /*
2540 * Find the region that we can probe for. This in turn
2541 * tells us whether we can probe for the type of port.
2542 */
2543 ret = serial8250_request_std_resource(up);
2544 if (ret < 0)
2545 return;
2546
2547 ret = serial8250_request_rsa_resource(up);
2548 if (ret < 0)
2549 probeflags &= ~PROBE_RSA;
2550
2551 if (flags & UART_CONFIG_TYPE)
2552 autoconfig(up, probeflags);
2553 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2554 autoconfig_irq(up);
2555
2556 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2557 serial8250_release_rsa_resource(up);
2558 if (up->port.type == PORT_UNKNOWN)
2559 serial8250_release_std_resource(up);
2560 }
2561
2562 static int
2563 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2564 {
2565 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2566 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2567 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2568 ser->type == PORT_STARTECH)
2569 return -EINVAL;
2570 return 0;
2571 }
2572
2573 static const char *
2574 serial8250_type(struct uart_port *port)
2575 {
2576 int type = port->type;
2577
2578 if (type >= ARRAY_SIZE(uart_config))
2579 type = 0;
2580 return uart_config[type].name;
2581 }
2582
2583 static struct uart_ops serial8250_pops = {
2584 .tx_empty = serial8250_tx_empty,
2585 .set_mctrl = serial8250_set_mctrl,
2586 .get_mctrl = serial8250_get_mctrl,
2587 .stop_tx = serial8250_stop_tx,
2588 .start_tx = serial8250_start_tx,
2589 .stop_rx = serial8250_stop_rx,
2590 .enable_ms = serial8250_enable_ms,
2591 .break_ctl = serial8250_break_ctl,
2592 .startup = serial8250_startup,
2593 .shutdown = serial8250_shutdown,
2594 .set_termios = serial8250_set_termios,
2595 .pm = serial8250_pm,
2596 .type = serial8250_type,
2597 .release_port = serial8250_release_port,
2598 .request_port = serial8250_request_port,
2599 .config_port = serial8250_config_port,
2600 .verify_port = serial8250_verify_port,
2601 #ifdef CONFIG_CONSOLE_POLL
2602 .poll_get_char = serial8250_get_poll_char,
2603 .poll_put_char = serial8250_put_poll_char,
2604 #endif
2605 };
2606
2607 static struct uart_8250_port serial8250_ports[UART_NR];
2608
2609 static void __init serial8250_isa_init_ports(void)
2610 {
2611 struct uart_8250_port *up;
2612 static int first = 1;
2613 int i;
2614
2615 if (!first)
2616 return;
2617 first = 0;
2618
2619 for (i = 0; i < nr_uarts; i++) {
2620 struct uart_8250_port *up = &serial8250_ports[i];
2621
2622 up->port.line = i;
2623 spin_lock_init(&up->port.lock);
2624
2625 init_timer(&up->timer);
2626 up->timer.function = serial8250_timeout;
2627
2628 /*
2629 * ALPHA_KLUDGE_MCR needs to be killed.
2630 */
2631 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2632 up->mcr_force = ALPHA_KLUDGE_MCR;
2633
2634 up->port.ops = &serial8250_pops;
2635 }
2636
2637 for (i = 0, up = serial8250_ports;
2638 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2639 i++, up++) {
2640 up->port.iobase = old_serial_port[i].port;
2641 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2642 up->port.uartclk = old_serial_port[i].baud_base * 16;
2643 up->port.flags = old_serial_port[i].flags;
2644 up->port.hub6 = old_serial_port[i].hub6;
2645 up->port.membase = old_serial_port[i].iomem_base;
2646 up->port.iotype = old_serial_port[i].io_type;
2647 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2648 set_io_from_upio(&up->port);
2649 if (share_irqs)
2650 up->port.flags |= UPF_SHARE_IRQ;
2651 }
2652 }
2653
2654 static void __init
2655 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2656 {
2657 int i;
2658
2659 serial8250_isa_init_ports();
2660
2661 for (i = 0; i < nr_uarts; i++) {
2662 struct uart_8250_port *up = &serial8250_ports[i];
2663
2664 up->port.dev = dev;
2665 uart_add_one_port(drv, &up->port);
2666 }
2667 }
2668
2669 #ifdef CONFIG_SERIAL_8250_CONSOLE
2670
2671 static void serial8250_console_putchar(struct uart_port *port, int ch)
2672 {
2673 struct uart_8250_port *up = (struct uart_8250_port *)port;
2674
2675 wait_for_xmitr(up, UART_LSR_THRE);
2676 serial_out(up, UART_TX, ch);
2677 }
2678
2679 /*
2680 * Print a string to the serial port trying not to disturb
2681 * any possible real use of the port...
2682 *
2683 * The console_lock must be held when we get here.
2684 */
2685 static void
2686 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2687 {
2688 struct uart_8250_port *up = &serial8250_ports[co->index];
2689 unsigned long flags;
2690 unsigned int ier;
2691 int locked = 1;
2692
2693 touch_nmi_watchdog();
2694
2695 local_irq_save(flags);
2696 if (up->port.sysrq) {
2697 /* serial8250_handle_port() already took the lock */
2698 locked = 0;
2699 } else if (oops_in_progress) {
2700 locked = spin_trylock(&up->port.lock);
2701 } else
2702 spin_lock(&up->port.lock);
2703
2704 /*
2705 * First save the IER then disable the interrupts
2706 */
2707 ier = serial_in(up, UART_IER);
2708
2709 if (up->capabilities & UART_CAP_UUE)
2710 serial_out(up, UART_IER, UART_IER_UUE);
2711 else
2712 serial_out(up, UART_IER, 0);
2713
2714 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2715
2716 /*
2717 * Finally, wait for transmitter to become empty
2718 * and restore the IER
2719 */
2720 wait_for_xmitr(up, BOTH_EMPTY);
2721 serial_out(up, UART_IER, ier);
2722
2723 /*
2724 * The receive handling will happen properly because the
2725 * receive ready bit will still be set; it is not cleared
2726 * on read. However, modem control will not, we must
2727 * call it if we have saved something in the saved flags
2728 * while processing with interrupts off.
2729 */
2730 if (up->msr_saved_flags)
2731 check_modem_status(up);
2732
2733 if (locked)
2734 spin_unlock(&up->port.lock);
2735 local_irq_restore(flags);
2736 }
2737
2738 static int __init serial8250_console_setup(struct console *co, char *options)
2739 {
2740 struct uart_port *port;
2741 int baud = 9600;
2742 int bits = 8;
2743 int parity = 'n';
2744 int flow = 'n';
2745
2746 /*
2747 * Check whether an invalid uart number has been specified, and
2748 * if so, search for the first available port that does have
2749 * console support.
2750 */
2751 if (co->index >= nr_uarts)
2752 co->index = 0;
2753 port = &serial8250_ports[co->index].port;
2754 if (!port->iobase && !port->membase)
2755 return -ENODEV;
2756
2757 if (options)
2758 uart_parse_options(options, &baud, &parity, &bits, &flow);
2759
2760 return uart_set_options(port, co, baud, parity, bits, flow);
2761 }
2762
2763 static int serial8250_console_early_setup(void)
2764 {
2765 return serial8250_find_port_for_earlycon();
2766 }
2767
2768 static struct console serial8250_console = {
2769 .name = "ttyS",
2770 .write = serial8250_console_write,
2771 .device = uart_console_device,
2772 .setup = serial8250_console_setup,
2773 .early_setup = serial8250_console_early_setup,
2774 .flags = CON_PRINTBUFFER,
2775 .index = -1,
2776 .data = &serial8250_reg,
2777 };
2778
2779 static int __init serial8250_console_init(void)
2780 {
2781 if (nr_uarts > UART_NR)
2782 nr_uarts = UART_NR;
2783
2784 serial8250_isa_init_ports();
2785 register_console(&serial8250_console);
2786 return 0;
2787 }
2788 console_initcall(serial8250_console_init);
2789
2790 int serial8250_find_port(struct uart_port *p)
2791 {
2792 int line;
2793 struct uart_port *port;
2794
2795 for (line = 0; line < nr_uarts; line++) {
2796 port = &serial8250_ports[line].port;
2797 if (uart_match_port(p, port))
2798 return line;
2799 }
2800 return -ENODEV;
2801 }
2802
2803 #define SERIAL8250_CONSOLE &serial8250_console
2804 #else
2805 #define SERIAL8250_CONSOLE NULL
2806 #endif
2807
2808 static struct uart_driver serial8250_reg = {
2809 .owner = THIS_MODULE,
2810 .driver_name = "serial",
2811 .dev_name = "ttyS",
2812 .major = TTY_MAJOR,
2813 .minor = 64,
2814 .cons = SERIAL8250_CONSOLE,
2815 };
2816
2817 /*
2818 * early_serial_setup - early registration for 8250 ports
2819 *
2820 * Setup an 8250 port structure prior to console initialisation. Use
2821 * after console initialisation will cause undefined behaviour.
2822 */
2823 int __init early_serial_setup(struct uart_port *port)
2824 {
2825 struct uart_port *p;
2826
2827 if (port->line >= ARRAY_SIZE(serial8250_ports))
2828 return -ENODEV;
2829
2830 serial8250_isa_init_ports();
2831 p = &serial8250_ports[port->line].port;
2832 p->iobase = port->iobase;
2833 p->membase = port->membase;
2834 p->irq = port->irq;
2835 p->uartclk = port->uartclk;
2836 p->fifosize = port->fifosize;
2837 p->regshift = port->regshift;
2838 p->iotype = port->iotype;
2839 p->flags = port->flags;
2840 p->mapbase = port->mapbase;
2841 p->private_data = port->private_data;
2842 p->type = port->type;
2843 p->line = port->line;
2844
2845 set_io_from_upio(p);
2846 if (port->serial_in)
2847 p->serial_in = port->serial_in;
2848 if (port->serial_out)
2849 p->serial_out = port->serial_out;
2850
2851 return 0;
2852 }
2853
2854 /**
2855 * serial8250_suspend_port - suspend one serial port
2856 * @line: serial line number
2857 *
2858 * Suspend one serial port.
2859 */
2860 void serial8250_suspend_port(int line)
2861 {
2862 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2863 }
2864
2865 /**
2866 * serial8250_resume_port - resume one serial port
2867 * @line: serial line number
2868 *
2869 * Resume one serial port.
2870 */
2871 void serial8250_resume_port(int line)
2872 {
2873 struct uart_8250_port *up = &serial8250_ports[line];
2874
2875 if (up->capabilities & UART_NATSEMI) {
2876 unsigned char tmp;
2877
2878 /* Ensure it's still in high speed mode */
2879 serial_outp(up, UART_LCR, 0xE0);
2880
2881 tmp = serial_in(up, 0x04); /* EXCR2 */
2882 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2883 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2884 serial_outp(up, 0x04, tmp);
2885
2886 serial_outp(up, UART_LCR, 0);
2887 }
2888 uart_resume_port(&serial8250_reg, &up->port);
2889 }
2890
2891 /*
2892 * Register a set of serial devices attached to a platform device. The
2893 * list is terminated with a zero flags entry, which means we expect
2894 * all entries to have at least UPF_BOOT_AUTOCONF set.
2895 */
2896 static int __devinit serial8250_probe(struct platform_device *dev)
2897 {
2898 struct plat_serial8250_port *p = dev->dev.platform_data;
2899 struct uart_port port;
2900 int ret, i;
2901
2902 memset(&port, 0, sizeof(struct uart_port));
2903
2904 for (i = 0; p && p->flags != 0; p++, i++) {
2905 port.iobase = p->iobase;
2906 port.membase = p->membase;
2907 port.irq = p->irq;
2908 port.uartclk = p->uartclk;
2909 port.regshift = p->regshift;
2910 port.iotype = p->iotype;
2911 port.flags = p->flags;
2912 port.mapbase = p->mapbase;
2913 port.hub6 = p->hub6;
2914 port.private_data = p->private_data;
2915 port.type = p->type;
2916 port.serial_in = p->serial_in;
2917 port.serial_out = p->serial_out;
2918 port.dev = &dev->dev;
2919 if (share_irqs)
2920 port.flags |= UPF_SHARE_IRQ;
2921 ret = serial8250_register_port(&port);
2922 if (ret < 0) {
2923 dev_err(&dev->dev, "unable to register port at index %d "
2924 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2925 p->iobase, (unsigned long long)p->mapbase,
2926 p->irq, ret);
2927 }
2928 }
2929 return 0;
2930 }
2931
2932 /*
2933 * Remove serial ports registered against a platform device.
2934 */
2935 static int __devexit serial8250_remove(struct platform_device *dev)
2936 {
2937 int i;
2938
2939 for (i = 0; i < nr_uarts; i++) {
2940 struct uart_8250_port *up = &serial8250_ports[i];
2941
2942 if (up->port.dev == &dev->dev)
2943 serial8250_unregister_port(i);
2944 }
2945 return 0;
2946 }
2947
2948 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2949 {
2950 int i;
2951
2952 for (i = 0; i < UART_NR; i++) {
2953 struct uart_8250_port *up = &serial8250_ports[i];
2954
2955 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2956 uart_suspend_port(&serial8250_reg, &up->port);
2957 }
2958
2959 return 0;
2960 }
2961
2962 static int serial8250_resume(struct platform_device *dev)
2963 {
2964 int i;
2965
2966 for (i = 0; i < UART_NR; i++) {
2967 struct uart_8250_port *up = &serial8250_ports[i];
2968
2969 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2970 serial8250_resume_port(i);
2971 }
2972
2973 return 0;
2974 }
2975
2976 static struct platform_driver serial8250_isa_driver = {
2977 .probe = serial8250_probe,
2978 .remove = __devexit_p(serial8250_remove),
2979 .suspend = serial8250_suspend,
2980 .resume = serial8250_resume,
2981 .driver = {
2982 .name = "serial8250",
2983 .owner = THIS_MODULE,
2984 },
2985 };
2986
2987 /*
2988 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2989 * in the table in include/asm/serial.h
2990 */
2991 static struct platform_device *serial8250_isa_devs;
2992
2993 /*
2994 * serial8250_register_port and serial8250_unregister_port allows for
2995 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2996 * modems and PCI multiport cards.
2997 */
2998 static DEFINE_MUTEX(serial_mutex);
2999
3000 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3001 {
3002 int i;
3003
3004 /*
3005 * First, find a port entry which matches.
3006 */
3007 for (i = 0; i < nr_uarts; i++)
3008 if (uart_match_port(&serial8250_ports[i].port, port))
3009 return &serial8250_ports[i];
3010
3011 /*
3012 * We didn't find a matching entry, so look for the first
3013 * free entry. We look for one which hasn't been previously
3014 * used (indicated by zero iobase).
3015 */
3016 for (i = 0; i < nr_uarts; i++)
3017 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3018 serial8250_ports[i].port.iobase == 0)
3019 return &serial8250_ports[i];
3020
3021 /*
3022 * That also failed. Last resort is to find any entry which
3023 * doesn't have a real port associated with it.
3024 */
3025 for (i = 0; i < nr_uarts; i++)
3026 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3027 return &serial8250_ports[i];
3028
3029 return NULL;
3030 }
3031
3032 /**
3033 * serial8250_register_port - register a serial port
3034 * @port: serial port template
3035 *
3036 * Configure the serial port specified by the request. If the
3037 * port exists and is in use, it is hung up and unregistered
3038 * first.
3039 *
3040 * The port is then probed and if necessary the IRQ is autodetected
3041 * If this fails an error is returned.
3042 *
3043 * On success the port is ready to use and the line number is returned.
3044 */
3045 int serial8250_register_port(struct uart_port *port)
3046 {
3047 struct uart_8250_port *uart;
3048 int ret = -ENOSPC;
3049
3050 if (port->uartclk == 0)
3051 return -EINVAL;
3052
3053 mutex_lock(&serial_mutex);
3054
3055 uart = serial8250_find_match_or_unused(port);
3056 if (uart) {
3057 uart_remove_one_port(&serial8250_reg, &uart->port);
3058
3059 uart->port.iobase = port->iobase;
3060 uart->port.membase = port->membase;
3061 uart->port.irq = port->irq;
3062 uart->port.uartclk = port->uartclk;
3063 uart->port.fifosize = port->fifosize;
3064 uart->port.regshift = port->regshift;
3065 uart->port.iotype = port->iotype;
3066 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3067 uart->port.mapbase = port->mapbase;
3068 uart->port.private_data = port->private_data;
3069 if (port->dev)
3070 uart->port.dev = port->dev;
3071
3072 if (port->flags & UPF_FIXED_TYPE) {
3073 uart->port.type = port->type;
3074 uart->port.fifosize = uart_config[port->type].fifo_size;
3075 uart->capabilities = uart_config[port->type].flags;
3076 uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3077 }
3078
3079 set_io_from_upio(&uart->port);
3080 /* Possibly override default I/O functions. */
3081 if (port->serial_in)
3082 uart->port.serial_in = port->serial_in;
3083 if (port->serial_out)
3084 uart->port.serial_out = port->serial_out;
3085
3086 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3087 if (ret == 0)
3088 ret = uart->port.line;
3089 }
3090 mutex_unlock(&serial_mutex);
3091
3092 return ret;
3093 }
3094 EXPORT_SYMBOL(serial8250_register_port);
3095
3096 /**
3097 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3098 * @line: serial line number
3099 *
3100 * Remove one serial port. This may not be called from interrupt
3101 * context. We hand the port back to the our control.
3102 */
3103 void serial8250_unregister_port(int line)
3104 {
3105 struct uart_8250_port *uart = &serial8250_ports[line];
3106
3107 mutex_lock(&serial_mutex);
3108 uart_remove_one_port(&serial8250_reg, &uart->port);
3109 if (serial8250_isa_devs) {
3110 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3111 uart->port.type = PORT_UNKNOWN;
3112 uart->port.dev = &serial8250_isa_devs->dev;
3113 uart_add_one_port(&serial8250_reg, &uart->port);
3114 } else {
3115 uart->port.dev = NULL;
3116 }
3117 mutex_unlock(&serial_mutex);
3118 }
3119 EXPORT_SYMBOL(serial8250_unregister_port);
3120
3121 static int __init serial8250_init(void)
3122 {
3123 int ret;
3124
3125 if (nr_uarts > UART_NR)
3126 nr_uarts = UART_NR;
3127
3128 printk(KERN_INFO "Serial: 8250/16550 driver, "
3129 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3130 share_irqs ? "en" : "dis");
3131
3132 #ifdef CONFIG_SPARC
3133 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3134 #else
3135 serial8250_reg.nr = UART_NR;
3136 ret = uart_register_driver(&serial8250_reg);
3137 #endif
3138 if (ret)
3139 goto out;
3140
3141 serial8250_isa_devs = platform_device_alloc("serial8250",
3142 PLAT8250_DEV_LEGACY);
3143 if (!serial8250_isa_devs) {
3144 ret = -ENOMEM;
3145 goto unreg_uart_drv;
3146 }
3147
3148 ret = platform_device_add(serial8250_isa_devs);
3149 if (ret)
3150 goto put_dev;
3151
3152 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3153
3154 ret = platform_driver_register(&serial8250_isa_driver);
3155 if (ret == 0)
3156 goto out;
3157
3158 platform_device_del(serial8250_isa_devs);
3159 put_dev:
3160 platform_device_put(serial8250_isa_devs);
3161 unreg_uart_drv:
3162 #ifdef CONFIG_SPARC
3163 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3164 #else
3165 uart_unregister_driver(&serial8250_reg);
3166 #endif
3167 out:
3168 return ret;
3169 }
3170
3171 static void __exit serial8250_exit(void)
3172 {
3173 struct platform_device *isa_dev = serial8250_isa_devs;
3174
3175 /*
3176 * This tells serial8250_unregister_port() not to re-register
3177 * the ports (thereby making serial8250_isa_driver permanently
3178 * in use.)
3179 */
3180 serial8250_isa_devs = NULL;
3181
3182 platform_driver_unregister(&serial8250_isa_driver);
3183 platform_device_unregister(isa_dev);
3184
3185 #ifdef CONFIG_SPARC
3186 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3187 #else
3188 uart_unregister_driver(&serial8250_reg);
3189 #endif
3190 }
3191
3192 module_init(serial8250_init);
3193 module_exit(serial8250_exit);
3194
3195 EXPORT_SYMBOL(serial8250_suspend_port);
3196 EXPORT_SYMBOL(serial8250_resume_port);
3197
3198 MODULE_LICENSE("GPL");
3199 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3200
3201 module_param(share_irqs, uint, 0644);
3202 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3203 " (unsafe)");
3204
3205 module_param(nr_uarts, uint, 0644);
3206 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3207
3208 #ifdef CONFIG_SERIAL_8250_RSA
3209 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3210 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3211 #endif
3212 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Support for the Chinese Samsung S3C2440 based development boards