include/asm-mips64/war.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2002 by Ralf Baechle
   7  */
   8 #ifndef _ASM_WAR_H
   9 #define _ASM_WAR_H
  10
  11 #include <linux/config.h>
  12
  13 /*
  14  * Pleassures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
  15  *
  16  *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
  17  *      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
  18  *      executed if there is no other dcache activity. If the dcache is
  19  *      accessed for another instruction immeidately preceding when these
  20  *      cache instructions are executing, it is possible that the dcache
  21  *      tag match outputs used by these cache instructions will be
  22  *      incorrect. These cache instructions should be preceded by at least
  23  *      four instructions that are not any kind of load or store
  24  *      instruction.
  25  *
  26  *      This is not allowed:    lw
  27  *                              nop
  28  *                              nop
  29  *                              nop
  30  *                              cache       Hit_Writeback_Invalidate_D
  31  *
  32  *      This is allowed:        lw
  33  *                              nop
  34  *                              nop
  35  *                              nop
  36  *                              nop
  37  *                              cache       Hit_Writeback_Invalidate_D
  38  *
  39  * #define R4600_V1_HIT_CACHEOP_WAR 1
  40  */
  41
  42
  43 /*
  44  * Writeback and invalidate the primary cache dcache before DMA.
  45  *
  46  * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
  47  * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
  48  * operate correctly if the internal data cache refill buffer is empty.  These
  49  * CACHE instructions should be separated from any potential data cache miss
  50  * by a load instruction to an uncached address to empty the response buffer."
  51  * (Revision 2.0 device errata from IDT available on http://www.idt.com/
  52  * in .pdf format.)
  53  *
  54  * #define R4600_V2_HIT_CACHEOP_WAR 1
  55  */
  56
  57 /*
  58  * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
  59  */
  60 #ifdef CONFIG_SGI_IP22
  61
  62 #define R4600_V1_HIT_CACHEOP_WAR        1
  63 #define R4600_V2_HIT_CACHEOP_WAR        1
  64
  65 #endif
  66
  67 /*
  68  * But the RM200C seems to have been shipped only with V2.0 R4600s
  69  */
  70 #ifdef CONFIG_SNI_RM200_PCI
  71
  72 #define R4600_V2_HIT_CACHEOP_WAR        1
  73
  74 #endif
  75
  76 #ifdef CONFIG_CPU_R5432
  77
  78 /*
  79  * When an interrupt happens on a CP0 register read instruction, CPU may
  80  * lock up or read corrupted values of CP0 registers after it enters
  81  * the exception handler.
  82  *
  83  * This workaround makes sure that we read a "safe" CP0 register as the
  84  * first thing in the exception handler, which breaks one of the
  85  * pre-conditions for this problem.
  86  */
  87 #define R5432_CP0_INTERRUPT_WAR 1
  88
  89 #endif
  90
  91 #if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
  92     defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
  93
  94 /*
  95  * Workaround for the Sibyte M3 errata the text of which can be found at
  96  *
  97  *   http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
  98  *
  99  * This will enable the use of a special TLB refill handler which does a
 100  * consistency check on the information in c0_badvaddr and c0_entryhi and
 101  * will just return and take the exception again if the information was
 102  * found to be inconsistent.
 103  */
 104 #define BCM1250_M3_WAR 1
 105
 106 /*
 107  * This is a DUART workaround related to glitches around register accesses
 108  */
 109 #define SIBYTE_1956_WAR 1
 110
 111 #endif
 112
 113 /*
 114  * Workarounds default to off
 115  */
 116 #ifndef R4600_V1_HIT_CACHEOP_WAR
 117 #define R4600_V1_HIT_CACHEOP_WAR        0
 118 #endif
 119 #ifndef R4600_V2_HIT_CACHEOP_WAR
 120 #define R4600_V2_HIT_CACHEOP_WAR        0
 121 #endif
 122 #ifndef R5432_CP0_INTERRUPT_WAR
 123 #define R5432_CP0_INTERRUPT_WAR         0
 124 #endif
 125 #ifndef BCM1250_M3_WAR
 126 #define BCM1250_M3_WAR                  0
 127 #endif
 128 #ifndef SIBYTE_1956_WAR
 129 #define SIBYTE_1956_WAR                 0
 130 #endif
 131
 132 #endif /* _ASM_WAR_H */