arch/x86/include/asm/perf_event_p4.h

   1 /*
   2  * Netburst Perfomance Events (P4, old Xeon)
   3  */
   4
   5 #ifndef PERF_EVENT_P4_H
   6 #define PERF_EVENT_P4_H
   7
   8 #include <linux/cpu.h>
   9 #include <linux/bitops.h>
  10
  11 /*
  12  * NetBurst has perfomance MSRs shared between
  13  * threads if HT is turned on, ie for both logical
  14  * processors (mem: in turn in Atom with HT support
  15  * perf-MSRs are not shared and every thread has its
  16  * own perf-MSRs set)
  17  */
  18 #define ARCH_P4_TOTAL_ESCR              (46)
  19 #define ARCH_P4_RESERVED_ESCR           (2) /* IQ_ESCR(0,1) not always present */
  20 #define ARCH_P4_MAX_ESCR                (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
  21 #define ARCH_P4_MAX_CCCR                (18)
  22 #define ARCH_P4_MAX_COUNTER             (ARCH_P4_MAX_CCCR / 2)
  23
  24 #define P4_EVNTSEL_EVENT_MASK           0x7e000000U
  25 #define P4_EVNTSEL_EVENT_SHIFT          25
  26 #define P4_EVNTSEL_EVENTMASK_MASK       0x01fffe00U
  27 #define P4_EVNTSEL_EVENTMASK_SHIFT      9
  28 #define P4_EVNTSEL_TAG_MASK             0x000001e0U
  29 #define P4_EVNTSEL_TAG_SHIFT            5
  30 #define P4_EVNTSEL_TAG_ENABLE           0x00000010U
  31 #define P4_EVNTSEL_T0_OS                0x00000008U
  32 #define P4_EVNTSEL_T0_USR               0x00000004U
  33 #define P4_EVNTSEL_T1_OS                0x00000002U
  34 #define P4_EVNTSEL_T1_USR               0x00000001U
  35
  36 /* Non HT mask */
  37 #define P4_EVNTSEL_MASK                         \
  38         (P4_EVNTSEL_EVENT_MASK          |       \
  39         P4_EVNTSEL_EVENTMASK_MASK       |       \
  40         P4_EVNTSEL_TAG_MASK             |       \
  41         P4_EVNTSEL_TAG_ENABLE           |       \
  42         P4_EVNTSEL_T0_OS                |       \
  43         P4_EVNTSEL_T0_USR)
  44
  45 /* HT mask */
  46 #define P4_EVNTSEL_MASK_HT                      \
  47         (P4_EVNTSEL_MASK                |       \
  48         P4_EVNTSEL_T1_OS                |       \
  49         P4_EVNTSEL_T1_USR)
  50
  51 #define P4_CCCR_OVF                     0x80000000U
  52 #define P4_CCCR_CASCADE                 0x40000000U
  53 #define P4_CCCR_OVF_PMI_T0              0x04000000U
  54 #define P4_CCCR_OVF_PMI_T1              0x08000000U
  55 #define P4_CCCR_FORCE_OVF               0x02000000U
  56 #define P4_CCCR_EDGE                    0x01000000U
  57 #define P4_CCCR_THRESHOLD_MASK          0x00f00000U
  58 #define P4_CCCR_THRESHOLD_SHIFT         20
  59 #define P4_CCCR_THRESHOLD(v)            ((v) << P4_CCCR_THRESHOLD_SHIFT)
  60 #define P4_CCCR_COMPLEMENT              0x00080000U
  61 #define P4_CCCR_COMPARE                 0x00040000U
  62 #define P4_CCCR_ESCR_SELECT_MASK        0x0000e000U
  63 #define P4_CCCR_ESCR_SELECT_SHIFT       13
  64 #define P4_CCCR_ENABLE                  0x00001000U
  65 #define P4_CCCR_THREAD_SINGLE           0x00010000U
  66 #define P4_CCCR_THREAD_BOTH             0x00020000U
  67 #define P4_CCCR_THREAD_ANY              0x00030000U
  68 #define P4_CCCR_RESERVED                0x00000fffU
  69
  70 /* Non HT mask */
  71 #define P4_CCCR_MASK                            \
  72         (P4_CCCR_OVF                    |       \
  73         P4_CCCR_CASCADE                 |       \
  74         P4_CCCR_OVF_PMI_T0              |       \
  75         P4_CCCR_FORCE_OVF               |       \
  76         P4_CCCR_EDGE                    |       \
  77         P4_CCCR_THRESHOLD_MASK          |       \
  78         P4_CCCR_COMPLEMENT              |       \
  79         P4_CCCR_COMPARE                 |       \
  80         P4_CCCR_ESCR_SELECT_MASK        |       \
  81         P4_CCCR_ENABLE)
  82
  83 /* HT mask */
  84 #define P4_CCCR_MASK_HT                         \
  85         (P4_CCCR_MASK                   |       \
  86         P4_CCCR_THREAD_ANY)
  87
  88 /*
  89  * format is 32 bit: ee ss aa aa
  90  * where
  91  *      ee - 8 bit event
  92  *      ss - 8 bit selector
  93  *      aa aa - 16 bits reserved for tags/attributes
  94  */
  95 #define P4_EVENT_PACK(event, selector)          (((event) << 24) | ((selector) << 16))
  96 #define P4_EVENT_UNPACK_EVENT(packed)           (((packed) >> 24) & 0xff)
  97 #define P4_EVENT_UNPACK_SELECTOR(packed)        (((packed) >> 16) & 0xff)
  98 #define P4_EVENT_PACK_ATTR(attr)                ((attr))
  99 #define P4_EVENT_UNPACK_ATTR(packed)            ((packed) & 0xffff)
 100 #define P4_MAKE_EVENT_ATTR(class, name, bit)    class##_##name = (1 << bit)
 101 #define P4_EVENT_ATTR(class, name)              class##_##name
 102 #define P4_EVENT_ATTR_STR(class, name)          __stringify(class##_##name)
 103
 104 /*
 105  * config field is 64bit width and consists of
 106  * HT << 63 | ESCR << 32 | CCCR
 107  * where HT is HyperThreading bit (since ESCR
 108  * has it reserved we may use it for own purpose)
 109  *
 110  * note that this is NOT the addresses of respective
 111  * ESCR and CCCR but rather an only packed value should
 112  * be unpacked and written to a proper addresses
 113  *
 114  * the base idea is to pack as much info as
 115  * possible
 116  */
 117 #define p4_config_pack_escr(v)          (((u64)(v)) << 32)
 118 #define p4_config_pack_cccr(v)          (((u64)(v)) & 0xffffffffULL)
 119 #define p4_config_unpack_escr(v)        (((u64)(v)) >> 32)
 120 #define p4_config_unpack_cccr(v)        (((u64)(v)) & 0xfffff000ULL)
 121
 122 #define p4_config_unpack_emask(v)                       \
 123         ({                                              \
 124                 u32 t = p4_config_unpack_escr((v));     \
 125                 t  &= P4_EVNTSEL_EVENTMASK_MASK;        \
 126                 t >>= P4_EVNTSEL_EVENTMASK_SHIFT;       \
 127                 t;                                      \
 128         })
 129
 130 #define p4_config_unpack_key(v)         (((u64)(v)) & P4_CCCR_RESERVED)
 131
 132 #define P4_CONFIG_HT_SHIFT              63
 133 #define P4_CONFIG_HT                    (1ULL << P4_CONFIG_HT_SHIFT)
 134
 135 static inline u32 p4_config_unpack_opcode(u64 config)
 136 {
 137         u32 e, s;
 138
 139         /*
 140          * we don't care about HT presence here since
 141          * event opcode doesn't depend on it
 142          */
 143         e = (p4_config_unpack_escr(config) & P4_EVNTSEL_EVENT_MASK) >> P4_EVNTSEL_EVENT_SHIFT;
 144         s = (p4_config_unpack_cccr(config) & P4_CCCR_ESCR_SELECT_MASK) >> P4_CCCR_ESCR_SELECT_SHIFT;
 145
 146         return P4_EVENT_PACK(e, s);
 147 }
 148
 149 static inline bool p4_is_event_cascaded(u64 config)
 150 {
 151         u32 cccr = p4_config_unpack_cccr(config);
 152         return !!(cccr & P4_CCCR_CASCADE);
 153 }
 154
 155 static inline int p4_ht_config_thread(u64 config)
 156 {
 157         return !!(config & P4_CONFIG_HT);
 158 }
 159
 160 static inline u64 p4_set_ht_bit(u64 config)
 161 {
 162         return config | P4_CONFIG_HT;
 163 }
 164
 165 static inline u64 p4_clear_ht_bit(u64 config)
 166 {
 167         return config & ~P4_CONFIG_HT;
 168 }
 169
 170 static inline int p4_ht_active(void)
 171 {
 172 #ifdef CONFIG_SMP
 173         return smp_num_siblings > 1;
 174 #endif
 175         return 0;
 176 }
 177
 178 static inline int p4_ht_thread(int cpu)
 179 {
 180 #ifdef CONFIG_SMP
 181         if (smp_num_siblings == 2)
 182                 return cpu != cpumask_first(__get_cpu_var(cpu_sibling_map));
 183 #endif
 184         return 0;
 185 }
 186
 187 static inline int p4_should_swap_ts(u64 config, int cpu)
 188 {
 189         return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);
 190 }
 191
 192 static inline u32 p4_default_cccr_conf(int cpu)
 193 {
 194         /*
 195          * Note that P4_CCCR_THREAD_ANY is "required" on
 196          * non-HT machines (on HT machines we count TS events
 197          * regardless the state of second logical processor
 198          */
 199         u32 cccr = P4_CCCR_THREAD_ANY;
 200
 201         if (!p4_ht_thread(cpu))
 202                 cccr |= P4_CCCR_OVF_PMI_T0;
 203         else
 204                 cccr |= P4_CCCR_OVF_PMI_T1;
 205
 206         return cccr;
 207 }
 208
 209 static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
 210 {
 211         u32 escr = 0;
 212
 213         if (!p4_ht_thread(cpu)) {
 214                 if (!exclude_os)
 215                         escr |= P4_EVNTSEL_T0_OS;
 216                 if (!exclude_usr)
 217                         escr |= P4_EVNTSEL_T0_USR;
 218         } else {
 219                 if (!exclude_os)
 220                         escr |= P4_EVNTSEL_T1_OS;
 221                 if (!exclude_usr)
 222                         escr |= P4_EVNTSEL_T1_USR;
 223         }
 224
 225         return escr;
 226 }
 227
 228 /*
 229  * Comments below the event represent ESCR restriction
 230  * for this event and counter index per ESCR
 231  *
 232  * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early
 233  * processor builds (family 0FH, models 01H-02H). These MSRs
 234  * are not available on later versions, so that we don't use
 235  * them completely
 236  *
 237  * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly
 238  * working so that we should not use this CCCR and respective
 239  * counter as result
 240  */
 241 #define P4_TC_DELIVER_MODE              P4_EVENT_PACK(0x01, 0x01)
 242         /*
 243          * MSR_P4_TC_ESCR0:     4, 5
 244          * MSR_P4_TC_ESCR1:     6, 7
 245          */
 246
 247 #define P4_BPU_FETCH_REQUEST            P4_EVENT_PACK(0x03, 0x00)
 248         /*
 249          * MSR_P4_BPU_ESCR0:    0, 1
 250          * MSR_P4_BPU_ESCR1:    2, 3
 251          */
 252
 253 #define P4_ITLB_REFERENCE               P4_EVENT_PACK(0x18, 0x03)
 254         /*
 255          * MSR_P4_ITLB_ESCR0:   0, 1
 256          * MSR_P4_ITLB_ESCR1:   2, 3
 257          */
 258
 259 #define P4_MEMORY_CANCEL                P4_EVENT_PACK(0x02, 0x05)
 260         /*
 261          * MSR_P4_DAC_ESCR0:    8, 9
 262          * MSR_P4_DAC_ESCR1:    10, 11
 263          */
 264
 265 #define P4_MEMORY_COMPLETE              P4_EVENT_PACK(0x08, 0x02)
 266         /*
 267          * MSR_P4_SAAT_ESCR0:   8, 9
 268          * MSR_P4_SAAT_ESCR1:   10, 11
 269          */
 270
 271 #define P4_LOAD_PORT_REPLAY             P4_EVENT_PACK(0x04, 0x02)
 272         /*
 273          * MSR_P4_SAAT_ESCR0:   8, 9
 274          * MSR_P4_SAAT_ESCR1:   10, 11
 275          */
 276
 277 #define P4_STORE_PORT_REPLAY            P4_EVENT_PACK(0x05, 0x02)
 278         /*
 279          * MSR_P4_SAAT_ESCR0:   8, 9
 280          * MSR_P4_SAAT_ESCR1:   10, 11
 281          */
 282
 283 #define P4_MOB_LOAD_REPLAY              P4_EVENT_PACK(0x03, 0x02)
 284         /*
 285          * MSR_P4_MOB_ESCR0:    0, 1
 286          * MSR_P4_MOB_ESCR1:    2, 3
 287          */
 288
 289 #define P4_PAGE_WALK_TYPE               P4_EVENT_PACK(0x01, 0x04)
 290         /*
 291          * MSR_P4_PMH_ESCR0:    0, 1
 292          * MSR_P4_PMH_ESCR1:    2, 3
 293          */
 294
 295 #define P4_BSQ_CACHE_REFERENCE          P4_EVENT_PACK(0x0c, 0x07)
 296         /*
 297          * MSR_P4_BSU_ESCR0:    0, 1
 298          * MSR_P4_BSU_ESCR1:    2, 3
 299          */
 300
 301 #define P4_IOQ_ALLOCATION               P4_EVENT_PACK(0x03, 0x06)
 302         /*
 303          * MSR_P4_FSB_ESCR0:    0, 1
 304          * MSR_P4_FSB_ESCR1:    2, 3
 305          */
 306
 307 #define P4_IOQ_ACTIVE_ENTRIES           P4_EVENT_PACK(0x1a, 0x06)
 308         /*
 309          * MSR_P4_FSB_ESCR1:    2, 3
 310          */
 311
 312 #define P4_FSB_DATA_ACTIVITY            P4_EVENT_PACK(0x17, 0x06)
 313         /*
 314          * MSR_P4_FSB_ESCR0:    0, 1
 315          * MSR_P4_FSB_ESCR1:    2, 3
 316          */
 317
 318 #define P4_BSQ_ALLOCATION               P4_EVENT_PACK(0x05, 0x07)
 319         /*
 320          * MSR_P4_BSU_ESCR0:    0, 1
 321          */
 322
 323 #define P4_BSQ_ACTIVE_ENTRIES           P4_EVENT_PACK(0x06, 0x07)
 324         /*
 325          * NOTE: no ESCR name in docs, it's guessed
 326          * MSR_P4_BSU_ESCR1:    2, 3
 327          */
 328
 329 #define P4_SSE_INPUT_ASSIST             P4_EVENT_PACK(0x34, 0x01)
 330         /*
 331          * MSR_P4_FIRM_ESCR0:   8, 9
 332          * MSR_P4_FIRM_ESCR1:   10, 11
 333          */
 334
 335 #define P4_PACKED_SP_UOP                P4_EVENT_PACK(0x08, 0x01)
 336         /*
 337          * MSR_P4_FIRM_ESCR0:   8, 9
 338          * MSR_P4_FIRM_ESCR1:   10, 11
 339          */
 340
 341 #define P4_PACKED_DP_UOP                P4_EVENT_PACK(0x0c, 0x01)
 342         /*
 343          * MSR_P4_FIRM_ESCR0:   8, 9
 344          * MSR_P4_FIRM_ESCR1:   10, 11
 345          */
 346
 347 #define P4_SCALAR_SP_UOP                P4_EVENT_PACK(0x0a, 0x01)
 348         /*
 349          * MSR_P4_FIRM_ESCR0:   8, 9
 350          * MSR_P4_FIRM_ESCR1:   10, 11
 351          */
 352
 353 #define P4_SCALAR_DP_UOP                P4_EVENT_PACK(0x0e, 0x01)
 354         /*
 355          * MSR_P4_FIRM_ESCR0:   8, 9
 356          * MSR_P4_FIRM_ESCR1:   10, 11
 357          */
 358
 359 #define P4_64BIT_MMX_UOP                P4_EVENT_PACK(0x02, 0x01)
 360         /*
 361          * MSR_P4_FIRM_ESCR0:   8, 9
 362          * MSR_P4_FIRM_ESCR1:   10, 11
 363          */
 364
 365 #define P4_128BIT_MMX_UOP               P4_EVENT_PACK(0x1a, 0x01)
 366         /*
 367          * MSR_P4_FIRM_ESCR0:   8, 9
 368          * MSR_P4_FIRM_ESCR1:   10, 11
 369          */
 370
 371 #define P4_X87_FP_UOP                   P4_EVENT_PACK(0x04, 0x01)
 372         /*
 373          * MSR_P4_FIRM_ESCR0:   8, 9
 374          * MSR_P4_FIRM_ESCR1:   10, 11
 375          */
 376
 377 #define P4_TC_MISC                      P4_EVENT_PACK(0x06, 0x01)
 378         /*
 379          * MSR_P4_TC_ESCR0:     4, 5
 380          * MSR_P4_TC_ESCR1:     6, 7
 381          */
 382
 383 #define P4_GLOBAL_POWER_EVENTS          P4_EVENT_PACK(0x13, 0x06)
 384         /*
 385          * MSR_P4_FSB_ESCR0:    0, 1
 386          * MSR_P4_FSB_ESCR1:    2, 3
 387          */
 388
 389 #define P4_TC_MS_XFER                   P4_EVENT_PACK(0x05, 0x00)
 390         /*
 391          * MSR_P4_MS_ESCR0:     4, 5
 392          * MSR_P4_MS_ESCR1:     6, 7
 393          */
 394
 395 #define P4_UOP_QUEUE_WRITES             P4_EVENT_PACK(0x09, 0x00)
 396         /*
 397          * MSR_P4_MS_ESCR0:     4, 5
 398          * MSR_P4_MS_ESCR1:     6, 7
 399          */
 400
 401 #define P4_RETIRED_MISPRED_BRANCH_TYPE  P4_EVENT_PACK(0x05, 0x02)
 402         /*
 403          * MSR_P4_TBPU_ESCR0:   4, 5
 404          * MSR_P4_TBPU_ESCR0:   6, 7
 405          */
 406
 407 #define P4_RETIRED_BRANCH_TYPE          P4_EVENT_PACK(0x04, 0x02)
 408         /*
 409          * MSR_P4_TBPU_ESCR0:   4, 5
 410          * MSR_P4_TBPU_ESCR0:   6, 7
 411          */
 412
 413 #define P4_RESOURCE_STALL               P4_EVENT_PACK(0x01, 0x01)
 414         /*
 415          * MSR_P4_ALF_ESCR0:    12, 13, 16
 416          * MSR_P4_ALF_ESCR1:    14, 15, 17
 417          */
 418
 419 #define P4_WC_BUFFER                    P4_EVENT_PACK(0x05, 0x05)
 420         /*
 421          * MSR_P4_DAC_ESCR0:    8, 9
 422          * MSR_P4_DAC_ESCR1:    10, 11
 423          */
 424
 425 #define P4_B2B_CYCLES                   P4_EVENT_PACK(0x16, 0x03)
 426         /*
 427          * MSR_P4_FSB_ESCR0:    0, 1
 428          * MSR_P4_FSB_ESCR1:    2, 3
 429          */
 430
 431 #define P4_BNR                          P4_EVENT_PACK(0x08, 0x03)
 432         /*
 433          * MSR_P4_FSB_ESCR0:    0, 1
 434          * MSR_P4_FSB_ESCR1:    2, 3
 435          */
 436
 437 #define P4_SNOOP                        P4_EVENT_PACK(0x06, 0x03)
 438         /*
 439          * MSR_P4_FSB_ESCR0:    0, 1
 440          * MSR_P4_FSB_ESCR1:    2, 3
 441          */
 442
 443 #define P4_RESPONSE                     P4_EVENT_PACK(0x04, 0x03)
 444         /*
 445          * MSR_P4_FSB_ESCR0:    0, 1
 446          * MSR_P4_FSB_ESCR1:    2, 3
 447          */
 448
 449 #define P4_FRONT_END_EVENT              P4_EVENT_PACK(0x08, 0x05)
 450         /*
 451          * MSR_P4_CRU_ESCR2:    12, 13, 16
 452          * MSR_P4_CRU_ESCR3:    14, 15, 17
 453          */
 454
 455 #define P4_EXECUTION_EVENT              P4_EVENT_PACK(0x0c, 0x05)
 456         /*
 457          * MSR_P4_CRU_ESCR2:    12, 13, 16
 458          * MSR_P4_CRU_ESCR3:    14, 15, 17
 459          */
 460
 461 #define P4_REPLAY_EVENT                 P4_EVENT_PACK(0x09, 0x05)
 462         /*
 463          * MSR_P4_CRU_ESCR2:    12, 13, 16
 464          * MSR_P4_CRU_ESCR3:    14, 15, 17
 465          */
 466
 467 #define P4_INSTR_RETIRED                P4_EVENT_PACK(0x02, 0x04)
 468         /*
 469          * MSR_P4_CRU_ESCR0:    12, 13, 16
 470          * MSR_P4_CRU_ESCR1:    14, 15, 17
 471          */
 472
 473 #define P4_UOPS_RETIRED                 P4_EVENT_PACK(0x01, 0x04)
 474         /*
 475          * MSR_P4_CRU_ESCR0:    12, 13, 16
 476          * MSR_P4_CRU_ESCR1:    14, 15, 17
 477          */
 478
 479 #define P4_UOP_TYPE                     P4_EVENT_PACK(0x02, 0x02)
 480         /*
 481          * MSR_P4_RAT_ESCR0:    12, 13, 16
 482          * MSR_P4_RAT_ESCR1:    14, 15, 17
 483          */
 484
 485 #define P4_BRANCH_RETIRED               P4_EVENT_PACK(0x06, 0x05)
 486         /*
 487          * MSR_P4_CRU_ESCR2:    12, 13, 16
 488          * MSR_P4_CRU_ESCR3:    14, 15, 17
 489          */
 490
 491 #define P4_MISPRED_BRANCH_RETIRED       P4_EVENT_PACK(0x03, 0x04)
 492         /*
 493          * MSR_P4_CRU_ESCR0:    12, 13, 16
 494          * MSR_P4_CRU_ESCR1:    14, 15, 17
 495          */
 496
 497 #define P4_X87_ASSIST                   P4_EVENT_PACK(0x03, 0x05)
 498         /*
 499          * MSR_P4_CRU_ESCR2:    12, 13, 16
 500          * MSR_P4_CRU_ESCR3:    14, 15, 17
 501          */
 502
 503 #define P4_MACHINE_CLEAR                P4_EVENT_PACK(0x02, 0x05)
 504         /*
 505          * MSR_P4_CRU_ESCR2:    12, 13, 16
 506          * MSR_P4_CRU_ESCR3:    14, 15, 17
 507          */
 508
 509 #define P4_INSTR_COMPLETED              P4_EVENT_PACK(0x07, 0x04)
 510         /*
 511          * MSR_P4_CRU_ESCR0:    12, 13, 16
 512          * MSR_P4_CRU_ESCR1:    14, 15, 17
 513          */
 514
 515 /*
 516  * a caller should use P4_EVENT_ATTR helper to
 517  * pick the attribute needed, for example
 518  *
 519  *      P4_EVENT_ATTR(P4_TC_DELIVER_MODE, DD)
 520  */
 521 enum P4_EVENTS_ATTR {
 522         P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DD, 0),
 523         P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DB, 1),
 524         P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, DI, 2),
 525         P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BD, 3),
 526         P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BB, 4),
 527         P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, BI, 5),
 528         P4_MAKE_EVENT_ATTR(P4_TC_DELIVER_MODE, ID, 6),
 529
 530         P4_MAKE_EVENT_ATTR(P4_BPU_FETCH_REQUEST, TCMISS, 0),
 531
 532         P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT, 0),
 533         P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, MISS, 1),
 534         P4_MAKE_EVENT_ATTR(P4_ITLB_REFERENCE, HIT_UK, 2),
 535
 536         P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, ST_RB_FULL, 2),
 537         P4_MAKE_EVENT_ATTR(P4_MEMORY_CANCEL, 64K_CONF, 3),
 538
 539         P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, LSC, 0),
 540         P4_MAKE_EVENT_ATTR(P4_MEMORY_COMPLETE, SSC, 1),
 541
 542         P4_MAKE_EVENT_ATTR(P4_LOAD_PORT_REPLAY, SPLIT_LD, 1),
 543
 544         P4_MAKE_EVENT_ATTR(P4_STORE_PORT_REPLAY, SPLIT_ST, 1),
 545
 546         P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STA, 1),
 547         P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, NO_STD, 3),
 548         P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
 549         P4_MAKE_EVENT_ATTR(P4_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
 550
 551         P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, DTMISS, 0),
 552         P4_MAKE_EVENT_ATTR(P4_PAGE_WALK_TYPE, ITMISS, 1),
 553
 554         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
 555         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
 556         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
 557         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
 558         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
 559         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
 560         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
 561         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
 562         P4_MAKE_EVENT_ATTR(P4_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
 563
 564         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, DEFAULT, 0),
 565         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_READ, 5),
 566         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, ALL_WRITE, 6),
 567         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_UC, 7),
 568         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WC, 8),
 569         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WT, 9),
 570         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WP, 10),
 571         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, MEM_WB, 11),
 572         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OWN, 13),
 573         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, OTHER, 14),
 574         P4_MAKE_EVENT_ATTR(P4_IOQ_ALLOCATION, PREFETCH, 15),
 575
 576         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
 577         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
 578         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
 579         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
 580         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
 581         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
 582         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
 583         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
 584         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OWN, 13),
 585         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, OTHER, 14),
 586         P4_MAKE_EVENT_ATTR(P4_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
 587
 588         P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
 589         P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
 590         P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
 591         P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
 592         P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
 593         P4_MAKE_EVENT_ATTR(P4_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
 594
 595         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE0, 0),
 596         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_TYPE1, 1),
 597         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN0, 2),
 598         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LEN1, 3),
 599         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
 600         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
 601         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
 602         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
 603         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
 604         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
 605         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE0, 11),
 606         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE1, 12),
 607         P4_MAKE_EVENT_ATTR(P4_BSQ_ALLOCATION, MEM_TYPE2, 13),
 608
 609         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
 610         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
 611         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
 612         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
 613         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
 614         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
 615         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
 616         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
 617         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
 618         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
 619         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
 620         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
 621         P4_MAKE_EVENT_ATTR(P4_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
 622
 623         P4_MAKE_EVENT_ATTR(P4_SSE_INPUT_ASSIST, ALL, 15),
 624
 625         P4_MAKE_EVENT_ATTR(P4_PACKED_SP_UOP, ALL, 15),
 626
 627         P4_MAKE_EVENT_ATTR(P4_PACKED_DP_UOP, ALL, 15),
 628
 629         P4_MAKE_EVENT_ATTR(P4_SCALAR_SP_UOP, ALL, 15),
 630
 631         P4_MAKE_EVENT_ATTR(P4_SCALAR_DP_UOP, ALL, 15),
 632
 633         P4_MAKE_EVENT_ATTR(P4_64BIT_MMX_UOP, ALL, 15),
 634
 635         P4_MAKE_EVENT_ATTR(P4_128BIT_MMX_UOP, ALL, 15),
 636
 637         P4_MAKE_EVENT_ATTR(P4_X87_FP_UOP, ALL, 15),
 638
 639         P4_MAKE_EVENT_ATTR(P4_TC_MISC, FLUSH, 4),
 640
 641         P4_MAKE_EVENT_ATTR(P4_GLOBAL_POWER_EVENTS, RUNNING, 0),
 642
 643         P4_MAKE_EVENT_ATTR(P4_TC_MS_XFER, CISC, 0),
 644
 645         P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
 646         P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
 647         P4_MAKE_EVENT_ATTR(P4_UOP_QUEUE_WRITES, FROM_ROM, 2),
 648
 649         P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
 650         P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
 651         P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
 652         P4_MAKE_EVENT_ATTR(P4_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
 653
 654         P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
 655         P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, CALL, 2),
 656         P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, RETURN, 3),
 657         P4_MAKE_EVENT_ATTR(P4_RETIRED_BRANCH_TYPE, INDIRECT, 4),
 658
 659         P4_MAKE_EVENT_ATTR(P4_RESOURCE_STALL, SBFULL, 5),
 660
 661         P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_EVICTS, 0),
 662         P4_MAKE_EVENT_ATTR(P4_WC_BUFFER, WCB_FULL_EVICTS, 1),
 663
 664         P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, NBOGUS, 0),
 665         P4_MAKE_EVENT_ATTR(P4_FRONT_END_EVENT, BOGUS, 1),
 666
 667         P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS0, 0),
 668         P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS1, 1),
 669         P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS2, 2),
 670         P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, NBOGUS3, 3),
 671         P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS0, 4),
 672         P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS1, 5),
 673         P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS2, 6),
 674         P4_MAKE_EVENT_ATTR(P4_EXECUTION_EVENT, BOGUS3, 7),
 675
 676         P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, NBOGUS, 0),
 677         P4_MAKE_EVENT_ATTR(P4_REPLAY_EVENT, BOGUS, 1),
 678
 679         P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSNTAG, 0),
 680         P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, NBOGUSTAG, 1),
 681         P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSNTAG, 2),
 682         P4_MAKE_EVENT_ATTR(P4_INSTR_RETIRED, BOGUSTAG, 3),
 683
 684         P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, NBOGUS, 0),
 685         P4_MAKE_EVENT_ATTR(P4_UOPS_RETIRED, BOGUS, 1),
 686
 687         P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGLOADS, 1),
 688         P4_MAKE_EVENT_ATTR(P4_UOP_TYPE, TAGSTORES, 2),
 689
 690         P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNP, 0),
 691         P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMNM, 1),
 692         P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTP, 2),
 693         P4_MAKE_EVENT_ATTR(P4_BRANCH_RETIRED, MMTM, 3),
 694
 695         P4_MAKE_EVENT_ATTR(P4_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
 696
 697         P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSU, 0),
 698         P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, FPSO, 1),
 699         P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAO, 2),
 700         P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, POAU, 3),
 701         P4_MAKE_EVENT_ATTR(P4_X87_ASSIST, PREA, 4),
 702
 703         P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, CLEAR, 0),
 704         P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, MOCLEAR, 1),
 705         P4_MAKE_EVENT_ATTR(P4_MACHINE_CLEAR, SMCLEAR, 2),
 706
 707         P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, NBOGUS, 0),
 708         P4_MAKE_EVENT_ATTR(P4_INSTR_COMPLETED, BOGUS, 1),
 709 };
 710
 711 #endif /* PERF_EVENT_P4_H */