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KVM: VMX: Enable NMI with in-kernel irqchip
[linux-2.6/linux-2.6-openrd.git] / arch / x86 / kvm / vmx.c
blob1bb994657208ce6a34573851010adf90b2083c2e
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "vmx.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29
30 #include <asm/io.h>
31 #include <asm/desc.h>
32
33 #define __ex(x) __kvm_handle_fault_on_reboot(x)
34
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
37
38 static int bypass_guest_pf = 1;
39 module_param(bypass_guest_pf, bool, 0);
40
41 static int enable_vpid = 1;
42 module_param(enable_vpid, bool, 0);
43
44 static int flexpriority_enabled = 1;
45 module_param(flexpriority_enabled, bool, 0);
46
47 static int enable_ept = 1;
48 module_param(enable_ept, bool, 0);
49
50 struct vmcs {
51 u32 revision_id;
52 u32 abort;
53 char data[0];
54 };
55
56 struct vcpu_vmx {
57 struct kvm_vcpu vcpu;
58 struct list_head local_vcpus_link;
59 int launched;
60 u8 fail;
61 u32 idt_vectoring_info;
62 struct kvm_msr_entry *guest_msrs;
63 struct kvm_msr_entry *host_msrs;
64 int nmsrs;
65 int save_nmsrs;
66 int msr_offset_efer;
67 #ifdef CONFIG_X86_64
68 int msr_offset_kernel_gs_base;
69 #endif
70 struct vmcs *vmcs;
71 struct {
72 int loaded;
73 u16 fs_sel, gs_sel, ldt_sel;
74 int gs_ldt_reload_needed;
75 int fs_reload_needed;
76 int guest_efer_loaded;
77 } host_state;
78 struct {
79 struct {
80 bool pending;
81 u8 vector;
82 unsigned rip;
83 } irq;
84 } rmode;
85 int vpid;
86 };
87
88 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
89 {
90 return container_of(vcpu, struct vcpu_vmx, vcpu);
91 }
92
93 static int init_rmode(struct kvm *kvm);
94
95 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
96 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
97 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
98
99 static struct page *vmx_io_bitmap_a;
100 static struct page *vmx_io_bitmap_b;
101 static struct page *vmx_msr_bitmap;
102
103 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
104 static DEFINE_SPINLOCK(vmx_vpid_lock);
105
106 static struct vmcs_config {
107 int size;
108 int order;
109 u32 revision_id;
110 u32 pin_based_exec_ctrl;
111 u32 cpu_based_exec_ctrl;
112 u32 cpu_based_2nd_exec_ctrl;
113 u32 vmexit_ctrl;
114 u32 vmentry_ctrl;
115 } vmcs_config;
116
117 struct vmx_capability {
118 u32 ept;
119 u32 vpid;
120 } vmx_capability;
121
122 #define VMX_SEGMENT_FIELD(seg) \
123 [VCPU_SREG_##seg] = { \
124 .selector = GUEST_##seg##_SELECTOR, \
125 .base = GUEST_##seg##_BASE, \
126 .limit = GUEST_##seg##_LIMIT, \
127 .ar_bytes = GUEST_##seg##_AR_BYTES, \
128 }
129
130 static struct kvm_vmx_segment_field {
131 unsigned selector;
132 unsigned base;
133 unsigned limit;
134 unsigned ar_bytes;
135 } kvm_vmx_segment_fields[] = {
136 VMX_SEGMENT_FIELD(CS),
137 VMX_SEGMENT_FIELD(DS),
138 VMX_SEGMENT_FIELD(ES),
139 VMX_SEGMENT_FIELD(FS),
140 VMX_SEGMENT_FIELD(GS),
141 VMX_SEGMENT_FIELD(SS),
142 VMX_SEGMENT_FIELD(TR),
143 VMX_SEGMENT_FIELD(LDTR),
144 };
145
146 /*
147 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
148 * away by decrementing the array size.
149 */
150 static const u32 vmx_msr_index[] = {
151 #ifdef CONFIG_X86_64
152 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
153 #endif
154 MSR_EFER, MSR_K6_STAR,
155 };
156 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
157
158 static void load_msrs(struct kvm_msr_entry *e, int n)
159 {
160 int i;
161
162 for (i = 0; i < n; ++i)
163 wrmsrl(e[i].index, e[i].data);
164 }
165
166 static void save_msrs(struct kvm_msr_entry *e, int n)
167 {
168 int i;
169
170 for (i = 0; i < n; ++i)
171 rdmsrl(e[i].index, e[i].data);
172 }
173
174 static inline int is_page_fault(u32 intr_info)
175 {
176 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
177 INTR_INFO_VALID_MASK)) ==
178 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
179 }
180
181 static inline int is_no_device(u32 intr_info)
182 {
183 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
184 INTR_INFO_VALID_MASK)) ==
185 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
186 }
187
188 static inline int is_invalid_opcode(u32 intr_info)
189 {
190 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
191 INTR_INFO_VALID_MASK)) ==
192 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
193 }
194
195 static inline int is_external_interrupt(u32 intr_info)
196 {
197 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
198 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
199 }
200
201 static inline int cpu_has_vmx_msr_bitmap(void)
202 {
203 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
204 }
205
206 static inline int cpu_has_vmx_tpr_shadow(void)
207 {
208 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
209 }
210
211 static inline int vm_need_tpr_shadow(struct kvm *kvm)
212 {
213 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
214 }
215
216 static inline int cpu_has_secondary_exec_ctrls(void)
217 {
218 return (vmcs_config.cpu_based_exec_ctrl &
219 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
220 }
221
222 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
223 {
224 return flexpriority_enabled
225 && (vmcs_config.cpu_based_2nd_exec_ctrl &
226 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
227 }
228
229 static inline int cpu_has_vmx_invept_individual_addr(void)
230 {
231 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
232 }
233
234 static inline int cpu_has_vmx_invept_context(void)
235 {
236 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
237 }
238
239 static inline int cpu_has_vmx_invept_global(void)
240 {
241 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
242 }
243
244 static inline int cpu_has_vmx_ept(void)
245 {
246 return (vmcs_config.cpu_based_2nd_exec_ctrl &
247 SECONDARY_EXEC_ENABLE_EPT);
248 }
249
250 static inline int vm_need_ept(void)
251 {
252 return (cpu_has_vmx_ept() && enable_ept);
253 }
254
255 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
256 {
257 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
258 (irqchip_in_kernel(kvm)));
259 }
260
261 static inline int cpu_has_vmx_vpid(void)
262 {
263 return (vmcs_config.cpu_based_2nd_exec_ctrl &
264 SECONDARY_EXEC_ENABLE_VPID);
265 }
266
267 static inline int cpu_has_virtual_nmis(void)
268 {
269 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
270 }
271
272 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
273 {
274 int i;
275
276 for (i = 0; i < vmx->nmsrs; ++i)
277 if (vmx->guest_msrs[i].index == msr)
278 return i;
279 return -1;
280 }
281
282 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
283 {
284 struct {
285 u64 vpid : 16;
286 u64 rsvd : 48;
287 u64 gva;
288 } operand = { vpid, 0, gva };
289
290 asm volatile (__ex(ASM_VMX_INVVPID)
291 /* CF==1 or ZF==1 --> rc = -1 */
292 "; ja 1f ; ud2 ; 1:"
293 : : "a"(&operand), "c"(ext) : "cc", "memory");
294 }
295
296 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
297 {
298 struct {
299 u64 eptp, gpa;
300 } operand = {eptp, gpa};
301
302 asm volatile (__ex(ASM_VMX_INVEPT)
303 /* CF==1 or ZF==1 --> rc = -1 */
304 "; ja 1f ; ud2 ; 1:\n"
305 : : "a" (&operand), "c" (ext) : "cc", "memory");
306 }
307
308 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
309 {
310 int i;
311
312 i = __find_msr_index(vmx, msr);
313 if (i >= 0)
314 return &vmx->guest_msrs[i];
315 return NULL;
316 }
317
318 static void vmcs_clear(struct vmcs *vmcs)
319 {
320 u64 phys_addr = __pa(vmcs);
321 u8 error;
322
323 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
324 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
325 : "cc", "memory");
326 if (error)
327 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
328 vmcs, phys_addr);
329 }
330
331 static void __vcpu_clear(void *arg)
332 {
333 struct vcpu_vmx *vmx = arg;
334 int cpu = raw_smp_processor_id();
335
336 if (vmx->vcpu.cpu == cpu)
337 vmcs_clear(vmx->vmcs);
338 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
339 per_cpu(current_vmcs, cpu) = NULL;
340 rdtscll(vmx->vcpu.arch.host_tsc);
341 list_del(&vmx->local_vcpus_link);
342 vmx->vcpu.cpu = -1;
343 vmx->launched = 0;
344 }
345
346 static void vcpu_clear(struct vcpu_vmx *vmx)
347 {
348 if (vmx->vcpu.cpu == -1)
349 return;
350 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
351 }
352
353 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
354 {
355 if (vmx->vpid == 0)
356 return;
357
358 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
359 }
360
361 static inline void ept_sync_global(void)
362 {
363 if (cpu_has_vmx_invept_global())
364 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
365 }
366
367 static inline void ept_sync_context(u64 eptp)
368 {
369 if (vm_need_ept()) {
370 if (cpu_has_vmx_invept_context())
371 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
372 else
373 ept_sync_global();
374 }
375 }
376
377 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
378 {
379 if (vm_need_ept()) {
380 if (cpu_has_vmx_invept_individual_addr())
381 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
382 eptp, gpa);
383 else
384 ept_sync_context(eptp);
385 }
386 }
387
388 static unsigned long vmcs_readl(unsigned long field)
389 {
390 unsigned long value;
391
392 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
393 : "=a"(value) : "d"(field) : "cc");
394 return value;
395 }
396
397 static u16 vmcs_read16(unsigned long field)
398 {
399 return vmcs_readl(field);
400 }
401
402 static u32 vmcs_read32(unsigned long field)
403 {
404 return vmcs_readl(field);
405 }
406
407 static u64 vmcs_read64(unsigned long field)
408 {
409 #ifdef CONFIG_X86_64
410 return vmcs_readl(field);
411 #else
412 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
413 #endif
414 }
415
416 static noinline void vmwrite_error(unsigned long field, unsigned long value)
417 {
418 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
419 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
420 dump_stack();
421 }
422
423 static void vmcs_writel(unsigned long field, unsigned long value)
424 {
425 u8 error;
426
427 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
428 : "=q"(error) : "a"(value), "d"(field) : "cc");
429 if (unlikely(error))
430 vmwrite_error(field, value);
431 }
432
433 static void vmcs_write16(unsigned long field, u16 value)
434 {
435 vmcs_writel(field, value);
436 }
437
438 static void vmcs_write32(unsigned long field, u32 value)
439 {
440 vmcs_writel(field, value);
441 }
442
443 static void vmcs_write64(unsigned long field, u64 value)
444 {
445 vmcs_writel(field, value);
446 #ifndef CONFIG_X86_64
447 asm volatile ("");
448 vmcs_writel(field+1, value >> 32);
449 #endif
450 }
451
452 static void vmcs_clear_bits(unsigned long field, u32 mask)
453 {
454 vmcs_writel(field, vmcs_readl(field) & ~mask);
455 }
456
457 static void vmcs_set_bits(unsigned long field, u32 mask)
458 {
459 vmcs_writel(field, vmcs_readl(field) | mask);
460 }
461
462 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
463 {
464 u32 eb;
465
466 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
467 if (!vcpu->fpu_active)
468 eb |= 1u << NM_VECTOR;
469 if (vcpu->guest_debug.enabled)
470 eb |= 1u << 1;
471 if (vcpu->arch.rmode.active)
472 eb = ~0;
473 if (vm_need_ept())
474 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
475 vmcs_write32(EXCEPTION_BITMAP, eb);
476 }
477
478 static void reload_tss(void)
479 {
480 /*
481 * VT restores TR but not its size. Useless.
482 */
483 struct descriptor_table gdt;
484 struct desc_struct *descs;
485
486 get_gdt(&gdt);
487 descs = (void *)gdt.base;
488 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
489 load_TR_desc();
490 }
491
492 static void load_transition_efer(struct vcpu_vmx *vmx)
493 {
494 int efer_offset = vmx->msr_offset_efer;
495 u64 host_efer = vmx->host_msrs[efer_offset].data;
496 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
497 u64 ignore_bits;
498
499 if (efer_offset < 0)
500 return;
501 /*
502 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
503 * outside long mode
504 */
505 ignore_bits = EFER_NX | EFER_SCE;
506 #ifdef CONFIG_X86_64
507 ignore_bits |= EFER_LMA | EFER_LME;
508 /* SCE is meaningful only in long mode on Intel */
509 if (guest_efer & EFER_LMA)
510 ignore_bits &= ~(u64)EFER_SCE;
511 #endif
512 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
513 return;
514
515 vmx->host_state.guest_efer_loaded = 1;
516 guest_efer &= ~ignore_bits;
517 guest_efer |= host_efer & ignore_bits;
518 wrmsrl(MSR_EFER, guest_efer);
519 vmx->vcpu.stat.efer_reload++;
520 }
521
522 static void reload_host_efer(struct vcpu_vmx *vmx)
523 {
524 if (vmx->host_state.guest_efer_loaded) {
525 vmx->host_state.guest_efer_loaded = 0;
526 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
527 }
528 }
529
530 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
531 {
532 struct vcpu_vmx *vmx = to_vmx(vcpu);
533
534 if (vmx->host_state.loaded)
535 return;
536
537 vmx->host_state.loaded = 1;
538 /*
539 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
540 * allow segment selectors with cpl > 0 or ti == 1.
541 */
542 vmx->host_state.ldt_sel = read_ldt();
543 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
544 vmx->host_state.fs_sel = read_fs();
545 if (!(vmx->host_state.fs_sel & 7)) {
546 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
547 vmx->host_state.fs_reload_needed = 0;
548 } else {
549 vmcs_write16(HOST_FS_SELECTOR, 0);
550 vmx->host_state.fs_reload_needed = 1;
551 }
552 vmx->host_state.gs_sel = read_gs();
553 if (!(vmx->host_state.gs_sel & 7))
554 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
555 else {
556 vmcs_write16(HOST_GS_SELECTOR, 0);
557 vmx->host_state.gs_ldt_reload_needed = 1;
558 }
559
560 #ifdef CONFIG_X86_64
561 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
562 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
563 #else
564 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
565 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
566 #endif
567
568 #ifdef CONFIG_X86_64
569 if (is_long_mode(&vmx->vcpu))
570 save_msrs(vmx->host_msrs +
571 vmx->msr_offset_kernel_gs_base, 1);
572
573 #endif
574 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
575 load_transition_efer(vmx);
576 }
577
578 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
579 {
580 unsigned long flags;
581
582 if (!vmx->host_state.loaded)
583 return;
584
585 ++vmx->vcpu.stat.host_state_reload;
586 vmx->host_state.loaded = 0;
587 if (vmx->host_state.fs_reload_needed)
588 load_fs(vmx->host_state.fs_sel);
589 if (vmx->host_state.gs_ldt_reload_needed) {
590 load_ldt(vmx->host_state.ldt_sel);
591 /*
592 * If we have to reload gs, we must take care to
593 * preserve our gs base.
594 */
595 local_irq_save(flags);
596 load_gs(vmx->host_state.gs_sel);
597 #ifdef CONFIG_X86_64
598 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
599 #endif
600 local_irq_restore(flags);
601 }
602 reload_tss();
603 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
604 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
605 reload_host_efer(vmx);
606 }
607
608 static void vmx_load_host_state(struct vcpu_vmx *vmx)
609 {
610 preempt_disable();
611 __vmx_load_host_state(vmx);
612 preempt_enable();
613 }
614
615 /*
616 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
617 * vcpu mutex is already taken.
618 */
619 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
620 {
621 struct vcpu_vmx *vmx = to_vmx(vcpu);
622 u64 phys_addr = __pa(vmx->vmcs);
623 u64 tsc_this, delta, new_offset;
624
625 if (vcpu->cpu != cpu) {
626 vcpu_clear(vmx);
627 kvm_migrate_timers(vcpu);
628 vpid_sync_vcpu_all(vmx);
629 local_irq_disable();
630 list_add(&vmx->local_vcpus_link,
631 &per_cpu(vcpus_on_cpu, cpu));
632 local_irq_enable();
633 }
634
635 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
636 u8 error;
637
638 per_cpu(current_vmcs, cpu) = vmx->vmcs;
639 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
640 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
641 : "cc");
642 if (error)
643 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
644 vmx->vmcs, phys_addr);
645 }
646
647 if (vcpu->cpu != cpu) {
648 struct descriptor_table dt;
649 unsigned long sysenter_esp;
650
651 vcpu->cpu = cpu;
652 /*
653 * Linux uses per-cpu TSS and GDT, so set these when switching
654 * processors.
655 */
656 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
657 get_gdt(&dt);
658 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
659
660 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
661 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
662
663 /*
664 * Make sure the time stamp counter is monotonous.
665 */
666 rdtscll(tsc_this);
667 if (tsc_this < vcpu->arch.host_tsc) {
668 delta = vcpu->arch.host_tsc - tsc_this;
669 new_offset = vmcs_read64(TSC_OFFSET) + delta;
670 vmcs_write64(TSC_OFFSET, new_offset);
671 }
672 }
673 }
674
675 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
676 {
677 __vmx_load_host_state(to_vmx(vcpu));
678 }
679
680 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
681 {
682 if (vcpu->fpu_active)
683 return;
684 vcpu->fpu_active = 1;
685 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
686 if (vcpu->arch.cr0 & X86_CR0_TS)
687 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
688 update_exception_bitmap(vcpu);
689 }
690
691 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
692 {
693 if (!vcpu->fpu_active)
694 return;
695 vcpu->fpu_active = 0;
696 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
697 update_exception_bitmap(vcpu);
698 }
699
700 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
701 {
702 return vmcs_readl(GUEST_RFLAGS);
703 }
704
705 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
706 {
707 if (vcpu->arch.rmode.active)
708 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
709 vmcs_writel(GUEST_RFLAGS, rflags);
710 }
711
712 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
713 {
714 unsigned long rip;
715 u32 interruptibility;
716
717 rip = vmcs_readl(GUEST_RIP);
718 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
719 vmcs_writel(GUEST_RIP, rip);
720
721 /*
722 * We emulated an instruction, so temporary interrupt blocking
723 * should be removed, if set.
724 */
725 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
726 if (interruptibility & 3)
727 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
728 interruptibility & ~3);
729 vcpu->arch.interrupt_window_open = 1;
730 }
731
732 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
733 bool has_error_code, u32 error_code)
734 {
735 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
736 nr | INTR_TYPE_EXCEPTION
737 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
738 | INTR_INFO_VALID_MASK);
739 if (has_error_code)
740 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
741 }
742
743 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
744 {
745 struct vcpu_vmx *vmx = to_vmx(vcpu);
746
747 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
748 }
749
750 /*
751 * Swap MSR entry in host/guest MSR entry array.
752 */
753 #ifdef CONFIG_X86_64
754 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
755 {
756 struct kvm_msr_entry tmp;
757
758 tmp = vmx->guest_msrs[to];
759 vmx->guest_msrs[to] = vmx->guest_msrs[from];
760 vmx->guest_msrs[from] = tmp;
761 tmp = vmx->host_msrs[to];
762 vmx->host_msrs[to] = vmx->host_msrs[from];
763 vmx->host_msrs[from] = tmp;
764 }
765 #endif
766
767 /*
768 * Set up the vmcs to automatically save and restore system
769 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
770 * mode, as fiddling with msrs is very expensive.
771 */
772 static void setup_msrs(struct vcpu_vmx *vmx)
773 {
774 int save_nmsrs;
775
776 vmx_load_host_state(vmx);
777 save_nmsrs = 0;
778 #ifdef CONFIG_X86_64
779 if (is_long_mode(&vmx->vcpu)) {
780 int index;
781
782 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
783 if (index >= 0)
784 move_msr_up(vmx, index, save_nmsrs++);
785 index = __find_msr_index(vmx, MSR_LSTAR);
786 if (index >= 0)
787 move_msr_up(vmx, index, save_nmsrs++);
788 index = __find_msr_index(vmx, MSR_CSTAR);
789 if (index >= 0)
790 move_msr_up(vmx, index, save_nmsrs++);
791 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
792 if (index >= 0)
793 move_msr_up(vmx, index, save_nmsrs++);
794 /*
795 * MSR_K6_STAR is only needed on long mode guests, and only
796 * if efer.sce is enabled.
797 */
798 index = __find_msr_index(vmx, MSR_K6_STAR);
799 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
800 move_msr_up(vmx, index, save_nmsrs++);
801 }
802 #endif
803 vmx->save_nmsrs = save_nmsrs;
804
805 #ifdef CONFIG_X86_64
806 vmx->msr_offset_kernel_gs_base =
807 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
808 #endif
809 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
810 }
811
812 /*
813 * reads and returns guest's timestamp counter "register"
814 * guest_tsc = host_tsc + tsc_offset -- 21.3
815 */
816 static u64 guest_read_tsc(void)
817 {
818 u64 host_tsc, tsc_offset;
819
820 rdtscll(host_tsc);
821 tsc_offset = vmcs_read64(TSC_OFFSET);
822 return host_tsc + tsc_offset;
823 }
824
825 /*
826 * writes 'guest_tsc' into guest's timestamp counter "register"
827 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
828 */
829 static void guest_write_tsc(u64 guest_tsc)
830 {
831 u64 host_tsc;
832
833 rdtscll(host_tsc);
834 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
835 }
836
837 /*
838 * Reads an msr value (of 'msr_index') into 'pdata'.
839 * Returns 0 on success, non-0 otherwise.
840 * Assumes vcpu_load() was already called.
841 */
842 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
843 {
844 u64 data;
845 struct kvm_msr_entry *msr;
846
847 if (!pdata) {
848 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
849 return -EINVAL;
850 }
851
852 switch (msr_index) {
853 #ifdef CONFIG_X86_64
854 case MSR_FS_BASE:
855 data = vmcs_readl(GUEST_FS_BASE);
856 break;
857 case MSR_GS_BASE:
858 data = vmcs_readl(GUEST_GS_BASE);
859 break;
860 case MSR_EFER:
861 return kvm_get_msr_common(vcpu, msr_index, pdata);
862 #endif
863 case MSR_IA32_TIME_STAMP_COUNTER:
864 data = guest_read_tsc();
865 break;
866 case MSR_IA32_SYSENTER_CS:
867 data = vmcs_read32(GUEST_SYSENTER_CS);
868 break;
869 case MSR_IA32_SYSENTER_EIP:
870 data = vmcs_readl(GUEST_SYSENTER_EIP);
871 break;
872 case MSR_IA32_SYSENTER_ESP:
873 data = vmcs_readl(GUEST_SYSENTER_ESP);
874 break;
875 default:
876 msr = find_msr_entry(to_vmx(vcpu), msr_index);
877 if (msr) {
878 data = msr->data;
879 break;
880 }
881 return kvm_get_msr_common(vcpu, msr_index, pdata);
882 }
883
884 *pdata = data;
885 return 0;
886 }
887
888 /*
889 * Writes msr value into into the appropriate "register".
890 * Returns 0 on success, non-0 otherwise.
891 * Assumes vcpu_load() was already called.
892 */
893 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
894 {
895 struct vcpu_vmx *vmx = to_vmx(vcpu);
896 struct kvm_msr_entry *msr;
897 int ret = 0;
898
899 switch (msr_index) {
900 #ifdef CONFIG_X86_64
901 case MSR_EFER:
902 vmx_load_host_state(vmx);
903 ret = kvm_set_msr_common(vcpu, msr_index, data);
904 break;
905 case MSR_FS_BASE:
906 vmcs_writel(GUEST_FS_BASE, data);
907 break;
908 case MSR_GS_BASE:
909 vmcs_writel(GUEST_GS_BASE, data);
910 break;
911 #endif
912 case MSR_IA32_SYSENTER_CS:
913 vmcs_write32(GUEST_SYSENTER_CS, data);
914 break;
915 case MSR_IA32_SYSENTER_EIP:
916 vmcs_writel(GUEST_SYSENTER_EIP, data);
917 break;
918 case MSR_IA32_SYSENTER_ESP:
919 vmcs_writel(GUEST_SYSENTER_ESP, data);
920 break;
921 case MSR_IA32_TIME_STAMP_COUNTER:
922 guest_write_tsc(data);
923 break;
924 default:
925 vmx_load_host_state(vmx);
926 msr = find_msr_entry(vmx, msr_index);
927 if (msr) {
928 msr->data = data;
929 break;
930 }
931 ret = kvm_set_msr_common(vcpu, msr_index, data);
932 }
933
934 return ret;
935 }
936
937 /*
938 * Sync the rsp and rip registers into the vcpu structure. This allows
939 * registers to be accessed by indexing vcpu->arch.regs.
940 */
941 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
942 {
943 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
944 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
945 }
946
947 /*
948 * Syncs rsp and rip back into the vmcs. Should be called after possible
949 * modification.
950 */
951 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
952 {
953 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
954 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
955 }
956
957 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
958 {
959 unsigned long dr7 = 0x400;
960 int old_singlestep;
961
962 old_singlestep = vcpu->guest_debug.singlestep;
963
964 vcpu->guest_debug.enabled = dbg->enabled;
965 if (vcpu->guest_debug.enabled) {
966 int i;
967
968 dr7 |= 0x200; /* exact */
969 for (i = 0; i < 4; ++i) {
970 if (!dbg->breakpoints[i].enabled)
971 continue;
972 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
973 dr7 |= 2 << (i*2); /* global enable */
974 dr7 |= 0 << (i*4+16); /* execution breakpoint */
975 }
976
977 vcpu->guest_debug.singlestep = dbg->singlestep;
978 } else
979 vcpu->guest_debug.singlestep = 0;
980
981 if (old_singlestep && !vcpu->guest_debug.singlestep) {
982 unsigned long flags;
983
984 flags = vmcs_readl(GUEST_RFLAGS);
985 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
986 vmcs_writel(GUEST_RFLAGS, flags);
987 }
988
989 update_exception_bitmap(vcpu);
990 vmcs_writel(GUEST_DR7, dr7);
991
992 return 0;
993 }
994
995 static int vmx_get_irq(struct kvm_vcpu *vcpu)
996 {
997 struct vcpu_vmx *vmx = to_vmx(vcpu);
998 u32 idtv_info_field;
999
1000 idtv_info_field = vmx->idt_vectoring_info;
1001 if (idtv_info_field & INTR_INFO_VALID_MASK) {
1002 if (is_external_interrupt(idtv_info_field))
1003 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
1004 else
1005 printk(KERN_DEBUG "pending exception: not handled yet\n");
1006 }
1007 return -1;
1008 }
1009
1010 static __init int cpu_has_kvm_support(void)
1011 {
1012 unsigned long ecx = cpuid_ecx(1);
1013 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
1014 }
1015
1016 static __init int vmx_disabled_by_bios(void)
1017 {
1018 u64 msr;
1019
1020 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1021 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1022 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1023 == MSR_IA32_FEATURE_CONTROL_LOCKED;
1024 /* locked but not enabled */
1025 }
1026
1027 static void hardware_enable(void *garbage)
1028 {
1029 int cpu = raw_smp_processor_id();
1030 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1031 u64 old;
1032
1033 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1034 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1035 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
1036 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1037 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
1038 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
1039 /* enable and lock */
1040 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1041 MSR_IA32_FEATURE_CONTROL_LOCKED |
1042 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
1043 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1044 asm volatile (ASM_VMX_VMXON_RAX
1045 : : "a"(&phys_addr), "m"(phys_addr)
1046 : "memory", "cc");
1047 }
1048
1049 static void vmclear_local_vcpus(void)
1050 {
1051 int cpu = raw_smp_processor_id();
1052 struct vcpu_vmx *vmx, *n;
1053
1054 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1055 local_vcpus_link)
1056 __vcpu_clear(vmx);
1057 }
1058
1059 static void hardware_disable(void *garbage)
1060 {
1061 vmclear_local_vcpus();
1062 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1063 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1064 }
1065
1066 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1067 u32 msr, u32 *result)
1068 {
1069 u32 vmx_msr_low, vmx_msr_high;
1070 u32 ctl = ctl_min | ctl_opt;
1071
1072 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1073
1074 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1075 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1076
1077 /* Ensure minimum (required) set of control bits are supported. */
1078 if (ctl_min & ~ctl)
1079 return -EIO;
1080
1081 *result = ctl;
1082 return 0;
1083 }
1084
1085 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1086 {
1087 u32 vmx_msr_low, vmx_msr_high;
1088 u32 min, opt, min2, opt2;
1089 u32 _pin_based_exec_control = 0;
1090 u32 _cpu_based_exec_control = 0;
1091 u32 _cpu_based_2nd_exec_control = 0;
1092 u32 _vmexit_control = 0;
1093 u32 _vmentry_control = 0;
1094
1095 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1096 opt = PIN_BASED_VIRTUAL_NMIS;
1097 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1098 &_pin_based_exec_control) < 0)
1099 return -EIO;
1100
1101 min = CPU_BASED_HLT_EXITING |
1102 #ifdef CONFIG_X86_64
1103 CPU_BASED_CR8_LOAD_EXITING |
1104 CPU_BASED_CR8_STORE_EXITING |
1105 #endif
1106 CPU_BASED_CR3_LOAD_EXITING |
1107 CPU_BASED_CR3_STORE_EXITING |
1108 CPU_BASED_USE_IO_BITMAPS |
1109 CPU_BASED_MOV_DR_EXITING |
1110 CPU_BASED_USE_TSC_OFFSETING;
1111 opt = CPU_BASED_TPR_SHADOW |
1112 CPU_BASED_USE_MSR_BITMAPS |
1113 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1114 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1115 &_cpu_based_exec_control) < 0)
1116 return -EIO;
1117 #ifdef CONFIG_X86_64
1118 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1119 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1120 ~CPU_BASED_CR8_STORE_EXITING;
1121 #endif
1122 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1123 min2 = 0;
1124 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1125 SECONDARY_EXEC_WBINVD_EXITING |
1126 SECONDARY_EXEC_ENABLE_VPID |
1127 SECONDARY_EXEC_ENABLE_EPT;
1128 if (adjust_vmx_controls(min2, opt2,
1129 MSR_IA32_VMX_PROCBASED_CTLS2,
1130 &_cpu_based_2nd_exec_control) < 0)
1131 return -EIO;
1132 }
1133 #ifndef CONFIG_X86_64
1134 if (!(_cpu_based_2nd_exec_control &
1135 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1136 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1137 #endif
1138 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1139 /* CR3 accesses don't need to cause VM Exits when EPT enabled */
1140 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1141 CPU_BASED_CR3_STORE_EXITING);
1142 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1143 &_cpu_based_exec_control) < 0)
1144 return -EIO;
1145 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1146 vmx_capability.ept, vmx_capability.vpid);
1147 }
1148
1149 min = 0;
1150 #ifdef CONFIG_X86_64
1151 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1152 #endif
1153 opt = 0;
1154 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1155 &_vmexit_control) < 0)
1156 return -EIO;
1157
1158 min = opt = 0;
1159 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1160 &_vmentry_control) < 0)
1161 return -EIO;
1162
1163 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1164
1165 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1166 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1167 return -EIO;
1168
1169 #ifdef CONFIG_X86_64
1170 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1171 if (vmx_msr_high & (1u<<16))
1172 return -EIO;
1173 #endif
1174
1175 /* Require Write-Back (WB) memory type for VMCS accesses. */
1176 if (((vmx_msr_high >> 18) & 15) != 6)
1177 return -EIO;
1178
1179 vmcs_conf->size = vmx_msr_high & 0x1fff;
1180 vmcs_conf->order = get_order(vmcs_config.size);
1181 vmcs_conf->revision_id = vmx_msr_low;
1182
1183 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1184 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1185 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1186 vmcs_conf->vmexit_ctrl = _vmexit_control;
1187 vmcs_conf->vmentry_ctrl = _vmentry_control;
1188
1189 return 0;
1190 }
1191
1192 static struct vmcs *alloc_vmcs_cpu(int cpu)
1193 {
1194 int node = cpu_to_node(cpu);
1195 struct page *pages;
1196 struct vmcs *vmcs;
1197
1198 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1199 if (!pages)
1200 return NULL;
1201 vmcs = page_address(pages);
1202 memset(vmcs, 0, vmcs_config.size);
1203 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1204 return vmcs;
1205 }
1206
1207 static struct vmcs *alloc_vmcs(void)
1208 {
1209 return alloc_vmcs_cpu(raw_smp_processor_id());
1210 }
1211
1212 static void free_vmcs(struct vmcs *vmcs)
1213 {
1214 free_pages((unsigned long)vmcs, vmcs_config.order);
1215 }
1216
1217 static void free_kvm_area(void)
1218 {
1219 int cpu;
1220
1221 for_each_online_cpu(cpu)
1222 free_vmcs(per_cpu(vmxarea, cpu));
1223 }
1224
1225 static __init int alloc_kvm_area(void)
1226 {
1227 int cpu;
1228
1229 for_each_online_cpu(cpu) {
1230 struct vmcs *vmcs;
1231
1232 vmcs = alloc_vmcs_cpu(cpu);
1233 if (!vmcs) {
1234 free_kvm_area();
1235 return -ENOMEM;
1236 }
1237
1238 per_cpu(vmxarea, cpu) = vmcs;
1239 }
1240 return 0;
1241 }
1242
1243 static __init int hardware_setup(void)
1244 {
1245 if (setup_vmcs_config(&vmcs_config) < 0)
1246 return -EIO;
1247
1248 if (boot_cpu_has(X86_FEATURE_NX))
1249 kvm_enable_efer_bits(EFER_NX);
1250
1251 return alloc_kvm_area();
1252 }
1253
1254 static __exit void hardware_unsetup(void)
1255 {
1256 free_kvm_area();
1257 }
1258
1259 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1260 {
1261 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1262
1263 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1264 vmcs_write16(sf->selector, save->selector);
1265 vmcs_writel(sf->base, save->base);
1266 vmcs_write32(sf->limit, save->limit);
1267 vmcs_write32(sf->ar_bytes, save->ar);
1268 } else {
1269 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1270 << AR_DPL_SHIFT;
1271 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1272 }
1273 }
1274
1275 static void enter_pmode(struct kvm_vcpu *vcpu)
1276 {
1277 unsigned long flags;
1278
1279 vcpu->arch.rmode.active = 0;
1280
1281 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1282 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1283 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1284
1285 flags = vmcs_readl(GUEST_RFLAGS);
1286 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1287 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1288 vmcs_writel(GUEST_RFLAGS, flags);
1289
1290 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1291 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1292
1293 update_exception_bitmap(vcpu);
1294
1295 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1296 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1297 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1298 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1299
1300 vmcs_write16(GUEST_SS_SELECTOR, 0);
1301 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1302
1303 vmcs_write16(GUEST_CS_SELECTOR,
1304 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1305 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1306 }
1307
1308 static gva_t rmode_tss_base(struct kvm *kvm)
1309 {
1310 if (!kvm->arch.tss_addr) {
1311 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1312 kvm->memslots[0].npages - 3;
1313 return base_gfn << PAGE_SHIFT;
1314 }
1315 return kvm->arch.tss_addr;
1316 }
1317
1318 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1319 {
1320 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1321
1322 save->selector = vmcs_read16(sf->selector);
1323 save->base = vmcs_readl(sf->base);
1324 save->limit = vmcs_read32(sf->limit);
1325 save->ar = vmcs_read32(sf->ar_bytes);
1326 vmcs_write16(sf->selector, save->base >> 4);
1327 vmcs_write32(sf->base, save->base & 0xfffff);
1328 vmcs_write32(sf->limit, 0xffff);
1329 vmcs_write32(sf->ar_bytes, 0xf3);
1330 }
1331
1332 static void enter_rmode(struct kvm_vcpu *vcpu)
1333 {
1334 unsigned long flags;
1335
1336 vcpu->arch.rmode.active = 1;
1337
1338 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1339 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1340
1341 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1342 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1343
1344 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1345 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1346
1347 flags = vmcs_readl(GUEST_RFLAGS);
1348 vcpu->arch.rmode.save_iopl
1349 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1350
1351 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1352
1353 vmcs_writel(GUEST_RFLAGS, flags);
1354 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1355 update_exception_bitmap(vcpu);
1356
1357 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1358 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1359 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1360
1361 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1362 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1363 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1364 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1365 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1366
1367 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1368 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1369 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1370 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1371
1372 kvm_mmu_reset_context(vcpu);
1373 init_rmode(vcpu->kvm);
1374 }
1375
1376 #ifdef CONFIG_X86_64
1377
1378 static void enter_lmode(struct kvm_vcpu *vcpu)
1379 {
1380 u32 guest_tr_ar;
1381
1382 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1383 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1384 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1385 __func__);
1386 vmcs_write32(GUEST_TR_AR_BYTES,
1387 (guest_tr_ar & ~AR_TYPE_MASK)
1388 | AR_TYPE_BUSY_64_TSS);
1389 }
1390
1391 vcpu->arch.shadow_efer |= EFER_LMA;
1392
1393 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1394 vmcs_write32(VM_ENTRY_CONTROLS,
1395 vmcs_read32(VM_ENTRY_CONTROLS)
1396 | VM_ENTRY_IA32E_MODE);
1397 }
1398
1399 static void exit_lmode(struct kvm_vcpu *vcpu)
1400 {
1401 vcpu->arch.shadow_efer &= ~EFER_LMA;
1402
1403 vmcs_write32(VM_ENTRY_CONTROLS,
1404 vmcs_read32(VM_ENTRY_CONTROLS)
1405 & ~VM_ENTRY_IA32E_MODE);
1406 }
1407
1408 #endif
1409
1410 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1411 {
1412 vpid_sync_vcpu_all(to_vmx(vcpu));
1413 }
1414
1415 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1416 {
1417 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1418 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1419 }
1420
1421 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1422 {
1423 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1424 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1425 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1426 return;
1427 }
1428 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1429 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1430 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1431 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1432 }
1433 }
1434
1435 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1436
1437 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1438 unsigned long cr0,
1439 struct kvm_vcpu *vcpu)
1440 {
1441 if (!(cr0 & X86_CR0_PG)) {
1442 /* From paging/starting to nonpaging */
1443 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1444 vmcs_config.cpu_based_exec_ctrl |
1445 (CPU_BASED_CR3_LOAD_EXITING |
1446 CPU_BASED_CR3_STORE_EXITING));
1447 vcpu->arch.cr0 = cr0;
1448 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1449 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1450 *hw_cr0 &= ~X86_CR0_WP;
1451 } else if (!is_paging(vcpu)) {
1452 /* From nonpaging to paging */
1453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1454 vmcs_config.cpu_based_exec_ctrl &
1455 ~(CPU_BASED_CR3_LOAD_EXITING |
1456 CPU_BASED_CR3_STORE_EXITING));
1457 vcpu->arch.cr0 = cr0;
1458 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1459 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1460 *hw_cr0 &= ~X86_CR0_WP;
1461 }
1462 }
1463
1464 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1465 struct kvm_vcpu *vcpu)
1466 {
1467 if (!is_paging(vcpu)) {
1468 *hw_cr4 &= ~X86_CR4_PAE;
1469 *hw_cr4 |= X86_CR4_PSE;
1470 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1471 *hw_cr4 &= ~X86_CR4_PAE;
1472 }
1473
1474 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1475 {
1476 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1477 KVM_VM_CR0_ALWAYS_ON;
1478
1479 vmx_fpu_deactivate(vcpu);
1480
1481 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1482 enter_pmode(vcpu);
1483
1484 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1485 enter_rmode(vcpu);
1486
1487 #ifdef CONFIG_X86_64
1488 if (vcpu->arch.shadow_efer & EFER_LME) {
1489 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1490 enter_lmode(vcpu);
1491 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1492 exit_lmode(vcpu);
1493 }
1494 #endif
1495
1496 if (vm_need_ept())
1497 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1498
1499 vmcs_writel(CR0_READ_SHADOW, cr0);
1500 vmcs_writel(GUEST_CR0, hw_cr0);
1501 vcpu->arch.cr0 = cr0;
1502
1503 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1504 vmx_fpu_activate(vcpu);
1505 }
1506
1507 static u64 construct_eptp(unsigned long root_hpa)
1508 {
1509 u64 eptp;
1510
1511 /* TODO write the value reading from MSR */
1512 eptp = VMX_EPT_DEFAULT_MT |
1513 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1514 eptp |= (root_hpa & PAGE_MASK);
1515
1516 return eptp;
1517 }
1518
1519 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1520 {
1521 unsigned long guest_cr3;
1522 u64 eptp;
1523
1524 guest_cr3 = cr3;
1525 if (vm_need_ept()) {
1526 eptp = construct_eptp(cr3);
1527 vmcs_write64(EPT_POINTER, eptp);
1528 ept_sync_context(eptp);
1529 ept_load_pdptrs(vcpu);
1530 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1531 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1532 }
1533
1534 vmx_flush_tlb(vcpu);
1535 vmcs_writel(GUEST_CR3, guest_cr3);
1536 if (vcpu->arch.cr0 & X86_CR0_PE)
1537 vmx_fpu_deactivate(vcpu);
1538 }
1539
1540 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1541 {
1542 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1543 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1544
1545 vcpu->arch.cr4 = cr4;
1546 if (vm_need_ept())
1547 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1548
1549 vmcs_writel(CR4_READ_SHADOW, cr4);
1550 vmcs_writel(GUEST_CR4, hw_cr4);
1551 }
1552
1553 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1554 {
1555 struct vcpu_vmx *vmx = to_vmx(vcpu);
1556 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1557
1558 vcpu->arch.shadow_efer = efer;
1559 if (!msr)
1560 return;
1561 if (efer & EFER_LMA) {
1562 vmcs_write32(VM_ENTRY_CONTROLS,
1563 vmcs_read32(VM_ENTRY_CONTROLS) |
1564 VM_ENTRY_IA32E_MODE);
1565 msr->data = efer;
1566
1567 } else {
1568 vmcs_write32(VM_ENTRY_CONTROLS,
1569 vmcs_read32(VM_ENTRY_CONTROLS) &
1570 ~VM_ENTRY_IA32E_MODE);
1571
1572 msr->data = efer & ~EFER_LME;
1573 }
1574 setup_msrs(vmx);
1575 }
1576
1577 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1578 {
1579 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1580
1581 return vmcs_readl(sf->base);
1582 }
1583
1584 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1585 struct kvm_segment *var, int seg)
1586 {
1587 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1588 u32 ar;
1589
1590 var->base = vmcs_readl(sf->base);
1591 var->limit = vmcs_read32(sf->limit);
1592 var->selector = vmcs_read16(sf->selector);
1593 ar = vmcs_read32(sf->ar_bytes);
1594 if (ar & AR_UNUSABLE_MASK)
1595 ar = 0;
1596 var->type = ar & 15;
1597 var->s = (ar >> 4) & 1;
1598 var->dpl = (ar >> 5) & 3;
1599 var->present = (ar >> 7) & 1;
1600 var->avl = (ar >> 12) & 1;
1601 var->l = (ar >> 13) & 1;
1602 var->db = (ar >> 14) & 1;
1603 var->g = (ar >> 15) & 1;
1604 var->unusable = (ar >> 16) & 1;
1605 }
1606
1607 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1608 {
1609 struct kvm_segment kvm_seg;
1610
1611 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1612 return 0;
1613
1614 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1615 return 3;
1616
1617 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1618 return kvm_seg.selector & 3;
1619 }
1620
1621 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1622 {
1623 u32 ar;
1624
1625 if (var->unusable)
1626 ar = 1 << 16;
1627 else {
1628 ar = var->type & 15;
1629 ar |= (var->s & 1) << 4;
1630 ar |= (var->dpl & 3) << 5;
1631 ar |= (var->present & 1) << 7;
1632 ar |= (var->avl & 1) << 12;
1633 ar |= (var->l & 1) << 13;
1634 ar |= (var->db & 1) << 14;
1635 ar |= (var->g & 1) << 15;
1636 }
1637 if (ar == 0) /* a 0 value means unusable */
1638 ar = AR_UNUSABLE_MASK;
1639
1640 return ar;
1641 }
1642
1643 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1644 struct kvm_segment *var, int seg)
1645 {
1646 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1647 u32 ar;
1648
1649 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1650 vcpu->arch.rmode.tr.selector = var->selector;
1651 vcpu->arch.rmode.tr.base = var->base;
1652 vcpu->arch.rmode.tr.limit = var->limit;
1653 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1654 return;
1655 }
1656 vmcs_writel(sf->base, var->base);
1657 vmcs_write32(sf->limit, var->limit);
1658 vmcs_write16(sf->selector, var->selector);
1659 if (vcpu->arch.rmode.active && var->s) {
1660 /*
1661 * Hack real-mode segments into vm86 compatibility.
1662 */
1663 if (var->base == 0xffff0000 && var->selector == 0xf000)
1664 vmcs_writel(sf->base, 0xf0000);
1665 ar = 0xf3;
1666 } else
1667 ar = vmx_segment_access_rights(var);
1668 vmcs_write32(sf->ar_bytes, ar);
1669 }
1670
1671 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1672 {
1673 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1674
1675 *db = (ar >> 14) & 1;
1676 *l = (ar >> 13) & 1;
1677 }
1678
1679 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1680 {
1681 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1682 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1683 }
1684
1685 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1686 {
1687 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1688 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1689 }
1690
1691 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1692 {
1693 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1694 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1695 }
1696
1697 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1698 {
1699 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1700 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1701 }
1702
1703 static int init_rmode_tss(struct kvm *kvm)
1704 {
1705 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1706 u16 data = 0;
1707 int ret = 0;
1708 int r;
1709
1710 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1711 if (r < 0)
1712 goto out;
1713 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1714 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1715 if (r < 0)
1716 goto out;
1717 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1718 if (r < 0)
1719 goto out;
1720 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1721 if (r < 0)
1722 goto out;
1723 data = ~0;
1724 r = kvm_write_guest_page(kvm, fn, &data,
1725 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1726 sizeof(u8));
1727 if (r < 0)
1728 goto out;
1729
1730 ret = 1;
1731 out:
1732 return ret;
1733 }
1734
1735 static int init_rmode_identity_map(struct kvm *kvm)
1736 {
1737 int i, r, ret;
1738 pfn_t identity_map_pfn;
1739 u32 tmp;
1740
1741 if (!vm_need_ept())
1742 return 1;
1743 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1744 printk(KERN_ERR "EPT: identity-mapping pagetable "
1745 "haven't been allocated!\n");
1746 return 0;
1747 }
1748 if (likely(kvm->arch.ept_identity_pagetable_done))
1749 return 1;
1750 ret = 0;
1751 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
1752 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
1753 if (r < 0)
1754 goto out;
1755 /* Set up identity-mapping pagetable for EPT in real mode */
1756 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
1757 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
1758 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
1759 r = kvm_write_guest_page(kvm, identity_map_pfn,
1760 &tmp, i * sizeof(tmp), sizeof(tmp));
1761 if (r < 0)
1762 goto out;
1763 }
1764 kvm->arch.ept_identity_pagetable_done = true;
1765 ret = 1;
1766 out:
1767 return ret;
1768 }
1769
1770 static void seg_setup(int seg)
1771 {
1772 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1773
1774 vmcs_write16(sf->selector, 0);
1775 vmcs_writel(sf->base, 0);
1776 vmcs_write32(sf->limit, 0xffff);
1777 vmcs_write32(sf->ar_bytes, 0x93);
1778 }
1779
1780 static int alloc_apic_access_page(struct kvm *kvm)
1781 {
1782 struct kvm_userspace_memory_region kvm_userspace_mem;
1783 int r = 0;
1784
1785 down_write(&kvm->slots_lock);
1786 if (kvm->arch.apic_access_page)
1787 goto out;
1788 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1789 kvm_userspace_mem.flags = 0;
1790 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1791 kvm_userspace_mem.memory_size = PAGE_SIZE;
1792 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1793 if (r)
1794 goto out;
1795
1796 down_read(&current->mm->mmap_sem);
1797 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1798 up_read(&current->mm->mmap_sem);
1799 out:
1800 up_write(&kvm->slots_lock);
1801 return r;
1802 }
1803
1804 static int alloc_identity_pagetable(struct kvm *kvm)
1805 {
1806 struct kvm_userspace_memory_region kvm_userspace_mem;
1807 int r = 0;
1808
1809 down_write(&kvm->slots_lock);
1810 if (kvm->arch.ept_identity_pagetable)
1811 goto out;
1812 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
1813 kvm_userspace_mem.flags = 0;
1814 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1815 kvm_userspace_mem.memory_size = PAGE_SIZE;
1816 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1817 if (r)
1818 goto out;
1819
1820 down_read(&current->mm->mmap_sem);
1821 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
1822 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
1823 up_read(&current->mm->mmap_sem);
1824 out:
1825 up_write(&kvm->slots_lock);
1826 return r;
1827 }
1828
1829 static void allocate_vpid(struct vcpu_vmx *vmx)
1830 {
1831 int vpid;
1832
1833 vmx->vpid = 0;
1834 if (!enable_vpid || !cpu_has_vmx_vpid())
1835 return;
1836 spin_lock(&vmx_vpid_lock);
1837 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1838 if (vpid < VMX_NR_VPIDS) {
1839 vmx->vpid = vpid;
1840 __set_bit(vpid, vmx_vpid_bitmap);
1841 }
1842 spin_unlock(&vmx_vpid_lock);
1843 }
1844
1845 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1846 {
1847 void *va;
1848
1849 if (!cpu_has_vmx_msr_bitmap())
1850 return;
1851
1852 /*
1853 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1854 * have the write-low and read-high bitmap offsets the wrong way round.
1855 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1856 */
1857 va = kmap(msr_bitmap);
1858 if (msr <= 0x1fff) {
1859 __clear_bit(msr, va + 0x000); /* read-low */
1860 __clear_bit(msr, va + 0x800); /* write-low */
1861 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1862 msr &= 0x1fff;
1863 __clear_bit(msr, va + 0x400); /* read-high */
1864 __clear_bit(msr, va + 0xc00); /* write-high */
1865 }
1866 kunmap(msr_bitmap);
1867 }
1868
1869 /*
1870 * Sets up the vmcs for emulated real mode.
1871 */
1872 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1873 {
1874 u32 host_sysenter_cs;
1875 u32 junk;
1876 unsigned long a;
1877 struct descriptor_table dt;
1878 int i;
1879 unsigned long kvm_vmx_return;
1880 u32 exec_control;
1881
1882 /* I/O */
1883 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1884 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1885
1886 if (cpu_has_vmx_msr_bitmap())
1887 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1888
1889 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1890
1891 /* Control */
1892 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1893 vmcs_config.pin_based_exec_ctrl);
1894
1895 exec_control = vmcs_config.cpu_based_exec_ctrl;
1896 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1897 exec_control &= ~CPU_BASED_TPR_SHADOW;
1898 #ifdef CONFIG_X86_64
1899 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1900 CPU_BASED_CR8_LOAD_EXITING;
1901 #endif
1902 }
1903 if (!vm_need_ept())
1904 exec_control |= CPU_BASED_CR3_STORE_EXITING |
1905 CPU_BASED_CR3_LOAD_EXITING;
1906 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1907
1908 if (cpu_has_secondary_exec_ctrls()) {
1909 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1910 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1911 exec_control &=
1912 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1913 if (vmx->vpid == 0)
1914 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1915 if (!vm_need_ept())
1916 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
1917 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1918 }
1919
1920 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1921 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1922 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1923
1924 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1925 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1926 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1927
1928 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1929 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1930 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1931 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1932 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1933 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1934 #ifdef CONFIG_X86_64
1935 rdmsrl(MSR_FS_BASE, a);
1936 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1937 rdmsrl(MSR_GS_BASE, a);
1938 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1939 #else
1940 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1941 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1942 #endif
1943
1944 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1945
1946 get_idt(&dt);
1947 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1948
1949 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1950 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1951 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1952 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1953 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1954
1955 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1956 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1957 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1958 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1959 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1960 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1961
1962 for (i = 0; i < NR_VMX_MSR; ++i) {
1963 u32 index = vmx_msr_index[i];
1964 u32 data_low, data_high;
1965 u64 data;
1966 int j = vmx->nmsrs;
1967
1968 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1969 continue;
1970 if (wrmsr_safe(index, data_low, data_high) < 0)
1971 continue;
1972 data = data_low | ((u64)data_high << 32);
1973 vmx->host_msrs[j].index = index;
1974 vmx->host_msrs[j].reserved = 0;
1975 vmx->host_msrs[j].data = data;
1976 vmx->guest_msrs[j] = vmx->host_msrs[j];
1977 ++vmx->nmsrs;
1978 }
1979
1980 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1981
1982 /* 22.2.1, 20.8.1 */
1983 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1984
1985 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1986 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1987
1988
1989 return 0;
1990 }
1991
1992 static int init_rmode(struct kvm *kvm)
1993 {
1994 if (!init_rmode_tss(kvm))
1995 return 0;
1996 if (!init_rmode_identity_map(kvm))
1997 return 0;
1998 return 1;
1999 }
2000
2001 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2002 {
2003 struct vcpu_vmx *vmx = to_vmx(vcpu);
2004 u64 msr;
2005 int ret;
2006
2007 down_read(&vcpu->kvm->slots_lock);
2008 if (!init_rmode(vmx->vcpu.kvm)) {
2009 ret = -ENOMEM;
2010 goto out;
2011 }
2012
2013 vmx->vcpu.arch.rmode.active = 0;
2014
2015 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2016 kvm_set_cr8(&vmx->vcpu, 0);
2017 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2018 if (vmx->vcpu.vcpu_id == 0)
2019 msr |= MSR_IA32_APICBASE_BSP;
2020 kvm_set_apic_base(&vmx->vcpu, msr);
2021
2022 fx_init(&vmx->vcpu);
2023
2024 /*
2025 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2026 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2027 */
2028 if (vmx->vcpu.vcpu_id == 0) {
2029 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2030 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2031 } else {
2032 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2033 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2034 }
2035 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2036 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2037
2038 seg_setup(VCPU_SREG_DS);
2039 seg_setup(VCPU_SREG_ES);
2040 seg_setup(VCPU_SREG_FS);
2041 seg_setup(VCPU_SREG_GS);
2042 seg_setup(VCPU_SREG_SS);
2043
2044 vmcs_write16(GUEST_TR_SELECTOR, 0);
2045 vmcs_writel(GUEST_TR_BASE, 0);
2046 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2047 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2048
2049 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2050 vmcs_writel(GUEST_LDTR_BASE, 0);
2051 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2052 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2053
2054 vmcs_write32(GUEST_SYSENTER_CS, 0);
2055 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2056 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2057
2058 vmcs_writel(GUEST_RFLAGS, 0x02);
2059 if (vmx->vcpu.vcpu_id == 0)
2060 vmcs_writel(GUEST_RIP, 0xfff0);
2061 else
2062 vmcs_writel(GUEST_RIP, 0);
2063 vmcs_writel(GUEST_RSP, 0);
2064
2065 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
2066 vmcs_writel(GUEST_DR7, 0x400);
2067
2068 vmcs_writel(GUEST_GDTR_BASE, 0);
2069 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2070
2071 vmcs_writel(GUEST_IDTR_BASE, 0);
2072 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2073
2074 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2075 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2076 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2077
2078 guest_write_tsc(0);
2079
2080 /* Special registers */
2081 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2082
2083 setup_msrs(vmx);
2084
2085 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2086
2087 if (cpu_has_vmx_tpr_shadow()) {
2088 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2089 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2090 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2091 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2092 vmcs_write32(TPR_THRESHOLD, 0);
2093 }
2094
2095 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2096 vmcs_write64(APIC_ACCESS_ADDR,
2097 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2098
2099 if (vmx->vpid != 0)
2100 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2101
2102 vmx->vcpu.arch.cr0 = 0x60000010;
2103 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2104 vmx_set_cr4(&vmx->vcpu, 0);
2105 vmx_set_efer(&vmx->vcpu, 0);
2106 vmx_fpu_activate(&vmx->vcpu);
2107 update_exception_bitmap(&vmx->vcpu);
2108
2109 vpid_sync_vcpu_all(vmx);
2110
2111 ret = 0;
2112
2113 out:
2114 up_read(&vcpu->kvm->slots_lock);
2115 return ret;
2116 }
2117
2118 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2119 {
2120 struct vcpu_vmx *vmx = to_vmx(vcpu);
2121
2122 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2123
2124 if (vcpu->arch.rmode.active) {
2125 vmx->rmode.irq.pending = true;
2126 vmx->rmode.irq.vector = irq;
2127 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
2128 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2129 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2130 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2131 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
2132 return;
2133 }
2134 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2135 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2136 }
2137
2138 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2139 {
2140 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2141 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2142 vcpu->arch.nmi_pending = 0;
2143 }
2144
2145 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2146 {
2147 int word_index = __ffs(vcpu->arch.irq_summary);
2148 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2149 int irq = word_index * BITS_PER_LONG + bit_index;
2150
2151 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2152 if (!vcpu->arch.irq_pending[word_index])
2153 clear_bit(word_index, &vcpu->arch.irq_summary);
2154 vmx_inject_irq(vcpu, irq);
2155 }
2156
2157
2158 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2159 struct kvm_run *kvm_run)
2160 {
2161 u32 cpu_based_vm_exec_control;
2162
2163 vcpu->arch.interrupt_window_open =
2164 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2165 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2166
2167 if (vcpu->arch.interrupt_window_open &&
2168 vcpu->arch.irq_summary &&
2169 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
2170 /*
2171 * If interrupts enabled, and not blocked by sti or mov ss. Good.
2172 */
2173 kvm_do_inject_irq(vcpu);
2174
2175 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2176 if (!vcpu->arch.interrupt_window_open &&
2177 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2178 /*
2179 * Interrupts blocked. Wait for unblock.
2180 */
2181 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2182 else
2183 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2184 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2185 }
2186
2187 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2188 {
2189 int ret;
2190 struct kvm_userspace_memory_region tss_mem = {
2191 .slot = 8,
2192 .guest_phys_addr = addr,
2193 .memory_size = PAGE_SIZE * 3,
2194 .flags = 0,
2195 };
2196
2197 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2198 if (ret)
2199 return ret;
2200 kvm->arch.tss_addr = addr;
2201 return 0;
2202 }
2203
2204 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
2205 {
2206 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
2207
2208 set_debugreg(dbg->bp[0], 0);
2209 set_debugreg(dbg->bp[1], 1);
2210 set_debugreg(dbg->bp[2], 2);
2211 set_debugreg(dbg->bp[3], 3);
2212
2213 if (dbg->singlestep) {
2214 unsigned long flags;
2215
2216 flags = vmcs_readl(GUEST_RFLAGS);
2217 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
2218 vmcs_writel(GUEST_RFLAGS, flags);
2219 }
2220 }
2221
2222 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2223 int vec, u32 err_code)
2224 {
2225 if (!vcpu->arch.rmode.active)
2226 return 0;
2227
2228 /*
2229 * Instruction with address size override prefix opcode 0x67
2230 * Cause the #SS fault with 0 error code in VM86 mode.
2231 */
2232 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2233 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2234 return 1;
2235 return 0;
2236 }
2237
2238 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2239 {
2240 struct vcpu_vmx *vmx = to_vmx(vcpu);
2241 u32 intr_info, error_code;
2242 unsigned long cr2, rip;
2243 u32 vect_info;
2244 enum emulation_result er;
2245
2246 vect_info = vmx->idt_vectoring_info;
2247 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2248
2249 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2250 !is_page_fault(intr_info))
2251 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2252 "intr info 0x%x\n", __func__, vect_info, intr_info);
2253
2254 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2255 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2256 set_bit(irq, vcpu->arch.irq_pending);
2257 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2258 }
2259
2260 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2261 return 1; /* already handled by vmx_vcpu_run() */
2262
2263 if (is_no_device(intr_info)) {
2264 vmx_fpu_activate(vcpu);
2265 return 1;
2266 }
2267
2268 if (is_invalid_opcode(intr_info)) {
2269 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2270 if (er != EMULATE_DONE)
2271 kvm_queue_exception(vcpu, UD_VECTOR);
2272 return 1;
2273 }
2274
2275 error_code = 0;
2276 rip = vmcs_readl(GUEST_RIP);
2277 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2278 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2279 if (is_page_fault(intr_info)) {
2280 /* EPT won't cause page fault directly */
2281 if (vm_need_ept())
2282 BUG();
2283 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2284 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2285 (u32)((u64)cr2 >> 32), handler);
2286 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2287 }
2288
2289 if (vcpu->arch.rmode.active &&
2290 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2291 error_code)) {
2292 if (vcpu->arch.halt_request) {
2293 vcpu->arch.halt_request = 0;
2294 return kvm_emulate_halt(vcpu);
2295 }
2296 return 1;
2297 }
2298
2299 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2300 (INTR_TYPE_EXCEPTION | 1)) {
2301 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2302 return 0;
2303 }
2304 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2305 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2306 kvm_run->ex.error_code = error_code;
2307 return 0;
2308 }
2309
2310 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2311 struct kvm_run *kvm_run)
2312 {
2313 ++vcpu->stat.irq_exits;
2314 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2315 return 1;
2316 }
2317
2318 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2319 {
2320 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2321 return 0;
2322 }
2323
2324 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2325 {
2326 unsigned long exit_qualification;
2327 int size, down, in, string, rep;
2328 unsigned port;
2329
2330 ++vcpu->stat.io_exits;
2331 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2332 string = (exit_qualification & 16) != 0;
2333
2334 if (string) {
2335 if (emulate_instruction(vcpu,
2336 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2337 return 0;
2338 return 1;
2339 }
2340
2341 size = (exit_qualification & 7) + 1;
2342 in = (exit_qualification & 8) != 0;
2343 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2344 rep = (exit_qualification & 32) != 0;
2345 port = exit_qualification >> 16;
2346
2347 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2348 }
2349
2350 static void
2351 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2352 {
2353 /*
2354 * Patch in the VMCALL instruction:
2355 */
2356 hypercall[0] = 0x0f;
2357 hypercall[1] = 0x01;
2358 hypercall[2] = 0xc1;
2359 }
2360
2361 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2362 {
2363 unsigned long exit_qualification;
2364 int cr;
2365 int reg;
2366
2367 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2368 cr = exit_qualification & 15;
2369 reg = (exit_qualification >> 8) & 15;
2370 switch ((exit_qualification >> 4) & 3) {
2371 case 0: /* mov to cr */
2372 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2373 (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
2374 switch (cr) {
2375 case 0:
2376 vcpu_load_rsp_rip(vcpu);
2377 kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
2378 skip_emulated_instruction(vcpu);
2379 return 1;
2380 case 3:
2381 vcpu_load_rsp_rip(vcpu);
2382 kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
2383 skip_emulated_instruction(vcpu);
2384 return 1;
2385 case 4:
2386 vcpu_load_rsp_rip(vcpu);
2387 kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
2388 skip_emulated_instruction(vcpu);
2389 return 1;
2390 case 8:
2391 vcpu_load_rsp_rip(vcpu);
2392 kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
2393 skip_emulated_instruction(vcpu);
2394 if (irqchip_in_kernel(vcpu->kvm))
2395 return 1;
2396 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2397 return 0;
2398 };
2399 break;
2400 case 2: /* clts */
2401 vcpu_load_rsp_rip(vcpu);
2402 vmx_fpu_deactivate(vcpu);
2403 vcpu->arch.cr0 &= ~X86_CR0_TS;
2404 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2405 vmx_fpu_activate(vcpu);
2406 KVMTRACE_0D(CLTS, vcpu, handler);
2407 skip_emulated_instruction(vcpu);
2408 return 1;
2409 case 1: /*mov from cr*/
2410 switch (cr) {
2411 case 3:
2412 vcpu_load_rsp_rip(vcpu);
2413 vcpu->arch.regs[reg] = vcpu->arch.cr3;
2414 vcpu_put_rsp_rip(vcpu);
2415 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2416 (u32)vcpu->arch.regs[reg],
2417 (u32)((u64)vcpu->arch.regs[reg] >> 32),
2418 handler);
2419 skip_emulated_instruction(vcpu);
2420 return 1;
2421 case 8:
2422 vcpu_load_rsp_rip(vcpu);
2423 vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
2424 vcpu_put_rsp_rip(vcpu);
2425 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2426 (u32)vcpu->arch.regs[reg], handler);
2427 skip_emulated_instruction(vcpu);
2428 return 1;
2429 }
2430 break;
2431 case 3: /* lmsw */
2432 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2433
2434 skip_emulated_instruction(vcpu);
2435 return 1;
2436 default:
2437 break;
2438 }
2439 kvm_run->exit_reason = 0;
2440 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2441 (int)(exit_qualification >> 4) & 3, cr);
2442 return 0;
2443 }
2444
2445 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2446 {
2447 unsigned long exit_qualification;
2448 unsigned long val;
2449 int dr, reg;
2450
2451 /*
2452 * FIXME: this code assumes the host is debugging the guest.
2453 * need to deal with guest debugging itself too.
2454 */
2455 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2456 dr = exit_qualification & 7;
2457 reg = (exit_qualification >> 8) & 15;
2458 vcpu_load_rsp_rip(vcpu);
2459 if (exit_qualification & 16) {
2460 /* mov from dr */
2461 switch (dr) {
2462 case 6:
2463 val = 0xffff0ff0;
2464 break;
2465 case 7:
2466 val = 0x400;
2467 break;
2468 default:
2469 val = 0;
2470 }
2471 vcpu->arch.regs[reg] = val;
2472 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2473 } else {
2474 /* mov to dr */
2475 }
2476 vcpu_put_rsp_rip(vcpu);
2477 skip_emulated_instruction(vcpu);
2478 return 1;
2479 }
2480
2481 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2482 {
2483 kvm_emulate_cpuid(vcpu);
2484 return 1;
2485 }
2486
2487 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2488 {
2489 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2490 u64 data;
2491
2492 if (vmx_get_msr(vcpu, ecx, &data)) {
2493 kvm_inject_gp(vcpu, 0);
2494 return 1;
2495 }
2496
2497 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2498 handler);
2499
2500 /* FIXME: handling of bits 32:63 of rax, rdx */
2501 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2502 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2503 skip_emulated_instruction(vcpu);
2504 return 1;
2505 }
2506
2507 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2508 {
2509 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2510 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2511 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2512
2513 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2514 handler);
2515
2516 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2517 kvm_inject_gp(vcpu, 0);
2518 return 1;
2519 }
2520
2521 skip_emulated_instruction(vcpu);
2522 return 1;
2523 }
2524
2525 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2526 struct kvm_run *kvm_run)
2527 {
2528 return 1;
2529 }
2530
2531 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2532 struct kvm_run *kvm_run)
2533 {
2534 u32 cpu_based_vm_exec_control;
2535
2536 /* clear pending irq */
2537 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2538 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2539 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2540
2541 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2542
2543 /*
2544 * If the user space waits to inject interrupts, exit as soon as
2545 * possible
2546 */
2547 if (kvm_run->request_interrupt_window &&
2548 !vcpu->arch.irq_summary) {
2549 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2550 ++vcpu->stat.irq_window_exits;
2551 return 0;
2552 }
2553 return 1;
2554 }
2555
2556 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2557 {
2558 skip_emulated_instruction(vcpu);
2559 return kvm_emulate_halt(vcpu);
2560 }
2561
2562 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2563 {
2564 skip_emulated_instruction(vcpu);
2565 kvm_emulate_hypercall(vcpu);
2566 return 1;
2567 }
2568
2569 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2570 {
2571 skip_emulated_instruction(vcpu);
2572 /* TODO: Add support for VT-d/pass-through device */
2573 return 1;
2574 }
2575
2576 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2577 {
2578 u64 exit_qualification;
2579 enum emulation_result er;
2580 unsigned long offset;
2581
2582 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2583 offset = exit_qualification & 0xffful;
2584
2585 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2586
2587 if (er != EMULATE_DONE) {
2588 printk(KERN_ERR
2589 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2590 offset);
2591 return -ENOTSUPP;
2592 }
2593 return 1;
2594 }
2595
2596 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2597 {
2598 unsigned long exit_qualification;
2599 u16 tss_selector;
2600 int reason;
2601
2602 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2603
2604 reason = (u32)exit_qualification >> 30;
2605 tss_selector = exit_qualification;
2606
2607 return kvm_task_switch(vcpu, tss_selector, reason);
2608 }
2609
2610 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2611 {
2612 u64 exit_qualification;
2613 enum emulation_result er;
2614 gpa_t gpa;
2615 unsigned long hva;
2616 int gla_validity;
2617 int r;
2618
2619 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2620
2621 if (exit_qualification & (1 << 6)) {
2622 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
2623 return -ENOTSUPP;
2624 }
2625
2626 gla_validity = (exit_qualification >> 7) & 0x3;
2627 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
2628 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
2629 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2630 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2631 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2632 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2633 (long unsigned int)exit_qualification);
2634 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2635 kvm_run->hw.hardware_exit_reason = 0;
2636 return -ENOTSUPP;
2637 }
2638
2639 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
2640 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
2641 if (!kvm_is_error_hva(hva)) {
2642 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
2643 if (r < 0) {
2644 printk(KERN_ERR "EPT: Not enough memory!\n");
2645 return -ENOMEM;
2646 }
2647 return 1;
2648 } else {
2649 /* must be MMIO */
2650 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2651
2652 if (er == EMULATE_FAIL) {
2653 printk(KERN_ERR
2654 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
2655 er);
2656 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
2657 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
2658 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
2659 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
2660 (long unsigned int)exit_qualification);
2661 return -ENOTSUPP;
2662 } else if (er == EMULATE_DO_MMIO)
2663 return 0;
2664 }
2665 return 1;
2666 }
2667
2668 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2669 {
2670 u32 cpu_based_vm_exec_control;
2671
2672 /* clear pending NMI */
2673 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2674 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
2675 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2676 ++vcpu->stat.nmi_window_exits;
2677
2678 return 1;
2679 }
2680
2681 /*
2682 * The exit handlers return 1 if the exit was handled fully and guest execution
2683 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2684 * to be done to userspace and return 0.
2685 */
2686 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2687 struct kvm_run *kvm_run) = {
2688 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2689 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2690 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2691 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
2692 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2693 [EXIT_REASON_CR_ACCESS] = handle_cr,
2694 [EXIT_REASON_DR_ACCESS] = handle_dr,
2695 [EXIT_REASON_CPUID] = handle_cpuid,
2696 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2697 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2698 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2699 [EXIT_REASON_HLT] = handle_halt,
2700 [EXIT_REASON_VMCALL] = handle_vmcall,
2701 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2702 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
2703 [EXIT_REASON_WBINVD] = handle_wbinvd,
2704 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
2705 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
2706 };
2707
2708 static const int kvm_vmx_max_exit_handlers =
2709 ARRAY_SIZE(kvm_vmx_exit_handlers);
2710
2711 /*
2712 * The guest has exited. See if we can fix it or if we need userspace
2713 * assistance.
2714 */
2715 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2716 {
2717 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2718 struct vcpu_vmx *vmx = to_vmx(vcpu);
2719 u32 vectoring_info = vmx->idt_vectoring_info;
2720
2721 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2722 (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2723
2724 /* Access CR3 don't cause VMExit in paging mode, so we need
2725 * to sync with guest real CR3. */
2726 if (vm_need_ept() && is_paging(vcpu)) {
2727 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2728 ept_load_pdptrs(vcpu);
2729 }
2730
2731 if (unlikely(vmx->fail)) {
2732 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2733 kvm_run->fail_entry.hardware_entry_failure_reason
2734 = vmcs_read32(VM_INSTRUCTION_ERROR);
2735 return 0;
2736 }
2737
2738 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2739 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
2740 exit_reason != EXIT_REASON_EPT_VIOLATION))
2741 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2742 "exit reason is 0x%x\n", __func__, exit_reason);
2743 if (exit_reason < kvm_vmx_max_exit_handlers
2744 && kvm_vmx_exit_handlers[exit_reason])
2745 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2746 else {
2747 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2748 kvm_run->hw.hardware_exit_reason = exit_reason;
2749 }
2750 return 0;
2751 }
2752
2753 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2754 {
2755 int max_irr, tpr;
2756
2757 if (!vm_need_tpr_shadow(vcpu->kvm))
2758 return;
2759
2760 if (!kvm_lapic_enabled(vcpu) ||
2761 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2762 vmcs_write32(TPR_THRESHOLD, 0);
2763 return;
2764 }
2765
2766 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2767 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2768 }
2769
2770 static void enable_irq_window(struct kvm_vcpu *vcpu)
2771 {
2772 u32 cpu_based_vm_exec_control;
2773
2774 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2775 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2776 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2777 }
2778
2779 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2780 {
2781 u32 cpu_based_vm_exec_control;
2782
2783 if (!cpu_has_virtual_nmis())
2784 return;
2785
2786 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2787 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2788 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2789 }
2790
2791 static int vmx_nmi_enabled(struct kvm_vcpu *vcpu)
2792 {
2793 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2794 return !(guest_intr & (GUEST_INTR_STATE_NMI |
2795 GUEST_INTR_STATE_MOV_SS |
2796 GUEST_INTR_STATE_STI));
2797 }
2798
2799 static int vmx_irq_enabled(struct kvm_vcpu *vcpu)
2800 {
2801 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2802 return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS |
2803 GUEST_INTR_STATE_STI)) &&
2804 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2805 }
2806
2807 static void enable_intr_window(struct kvm_vcpu *vcpu)
2808 {
2809 if (vcpu->arch.nmi_pending)
2810 enable_nmi_window(vcpu);
2811 else if (kvm_cpu_has_interrupt(vcpu))
2812 enable_irq_window(vcpu);
2813 }
2814
2815 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2816 {
2817 struct vcpu_vmx *vmx = to_vmx(vcpu);
2818 u32 idtv_info_field, intr_info_field, exit_intr_info_field;
2819 int vector;
2820
2821 update_tpr_threshold(vcpu);
2822
2823 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2824 exit_intr_info_field = vmcs_read32(VM_EXIT_INTR_INFO);
2825 idtv_info_field = vmx->idt_vectoring_info;
2826 if (intr_info_field & INTR_INFO_VALID_MASK) {
2827 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2828 /* TODO: fault when IDT_Vectoring */
2829 if (printk_ratelimit())
2830 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2831 }
2832 enable_intr_window(vcpu);
2833 return;
2834 }
2835 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2836 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2837 == INTR_TYPE_EXT_INTR
2838 && vcpu->arch.rmode.active) {
2839 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2840
2841 vmx_inject_irq(vcpu, vect);
2842 enable_intr_window(vcpu);
2843 return;
2844 }
2845
2846 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2847
2848 /*
2849 * SDM 3: 25.7.1.2
2850 * Clear bit "block by NMI" before VM entry if a NMI delivery
2851 * faulted.
2852 */
2853 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2854 == INTR_TYPE_NMI_INTR && cpu_has_virtual_nmis())
2855 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2856 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2857 ~GUEST_INTR_STATE_NMI);
2858
2859 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field
2860 & ~INTR_INFO_RESVD_BITS_MASK);
2861 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2862 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2863
2864 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2865 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2866 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2867 enable_intr_window(vcpu);
2868 return;
2869 }
2870 if (cpu_has_virtual_nmis()) {
2871 /*
2872 * SDM 3: 25.7.1.2
2873 * Re-set bit "block by NMI" before VM entry if vmexit caused by
2874 * a guest IRET fault.
2875 */
2876 if ((exit_intr_info_field & INTR_INFO_UNBLOCK_NMI) &&
2877 (exit_intr_info_field & INTR_INFO_VECTOR_MASK) != 8)
2878 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
2879 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) |
2880 GUEST_INTR_STATE_NMI);
2881 else if (vcpu->arch.nmi_pending) {
2882 if (vmx_nmi_enabled(vcpu))
2883 vmx_inject_nmi(vcpu);
2884 enable_intr_window(vcpu);
2885 return;
2886 }
2887
2888 }
2889 if (!kvm_cpu_has_interrupt(vcpu))
2890 return;
2891 if (vmx_irq_enabled(vcpu)) {
2892 vector = kvm_cpu_get_interrupt(vcpu);
2893 vmx_inject_irq(vcpu, vector);
2894 kvm_timer_intr_post(vcpu, vector);
2895 } else
2896 enable_irq_window(vcpu);
2897 }
2898
2899 /*
2900 * Failure to inject an interrupt should give us the information
2901 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2902 * when fetching the interrupt redirection bitmap in the real-mode
2903 * tss, this doesn't happen. So we do it ourselves.
2904 */
2905 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2906 {
2907 vmx->rmode.irq.pending = 0;
2908 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2909 return;
2910 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2911 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2912 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2913 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2914 return;
2915 }
2916 vmx->idt_vectoring_info =
2917 VECTORING_INFO_VALID_MASK
2918 | INTR_TYPE_EXT_INTR
2919 | vmx->rmode.irq.vector;
2920 }
2921
2922 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2923 {
2924 struct vcpu_vmx *vmx = to_vmx(vcpu);
2925 u32 intr_info;
2926
2927 /*
2928 * Loading guest fpu may have cleared host cr0.ts
2929 */
2930 vmcs_writel(HOST_CR0, read_cr0());
2931
2932 asm(
2933 /* Store host registers */
2934 #ifdef CONFIG_X86_64
2935 "push %%rdx; push %%rbp;"
2936 "push %%rcx \n\t"
2937 #else
2938 "push %%edx; push %%ebp;"
2939 "push %%ecx \n\t"
2940 #endif
2941 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
2942 /* Check if vmlaunch of vmresume is needed */
2943 "cmpl $0, %c[launched](%0) \n\t"
2944 /* Load guest registers. Don't clobber flags. */
2945 #ifdef CONFIG_X86_64
2946 "mov %c[cr2](%0), %%rax \n\t"
2947 "mov %%rax, %%cr2 \n\t"
2948 "mov %c[rax](%0), %%rax \n\t"
2949 "mov %c[rbx](%0), %%rbx \n\t"
2950 "mov %c[rdx](%0), %%rdx \n\t"
2951 "mov %c[rsi](%0), %%rsi \n\t"
2952 "mov %c[rdi](%0), %%rdi \n\t"
2953 "mov %c[rbp](%0), %%rbp \n\t"
2954 "mov %c[r8](%0), %%r8 \n\t"
2955 "mov %c[r9](%0), %%r9 \n\t"
2956 "mov %c[r10](%0), %%r10 \n\t"
2957 "mov %c[r11](%0), %%r11 \n\t"
2958 "mov %c[r12](%0), %%r12 \n\t"
2959 "mov %c[r13](%0), %%r13 \n\t"
2960 "mov %c[r14](%0), %%r14 \n\t"
2961 "mov %c[r15](%0), %%r15 \n\t"
2962 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2963 #else
2964 "mov %c[cr2](%0), %%eax \n\t"
2965 "mov %%eax, %%cr2 \n\t"
2966 "mov %c[rax](%0), %%eax \n\t"
2967 "mov %c[rbx](%0), %%ebx \n\t"
2968 "mov %c[rdx](%0), %%edx \n\t"
2969 "mov %c[rsi](%0), %%esi \n\t"
2970 "mov %c[rdi](%0), %%edi \n\t"
2971 "mov %c[rbp](%0), %%ebp \n\t"
2972 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2973 #endif
2974 /* Enter guest mode */
2975 "jne .Llaunched \n\t"
2976 __ex(ASM_VMX_VMLAUNCH) "\n\t"
2977 "jmp .Lkvm_vmx_return \n\t"
2978 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
2979 ".Lkvm_vmx_return: "
2980 /* Save guest registers, load host registers, keep flags */
2981 #ifdef CONFIG_X86_64
2982 "xchg %0, (%%rsp) \n\t"
2983 "mov %%rax, %c[rax](%0) \n\t"
2984 "mov %%rbx, %c[rbx](%0) \n\t"
2985 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2986 "mov %%rdx, %c[rdx](%0) \n\t"
2987 "mov %%rsi, %c[rsi](%0) \n\t"
2988 "mov %%rdi, %c[rdi](%0) \n\t"
2989 "mov %%rbp, %c[rbp](%0) \n\t"
2990 "mov %%r8, %c[r8](%0) \n\t"
2991 "mov %%r9, %c[r9](%0) \n\t"
2992 "mov %%r10, %c[r10](%0) \n\t"
2993 "mov %%r11, %c[r11](%0) \n\t"
2994 "mov %%r12, %c[r12](%0) \n\t"
2995 "mov %%r13, %c[r13](%0) \n\t"
2996 "mov %%r14, %c[r14](%0) \n\t"
2997 "mov %%r15, %c[r15](%0) \n\t"
2998 "mov %%cr2, %%rax \n\t"
2999 "mov %%rax, %c[cr2](%0) \n\t"
3000
3001 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
3002 #else
3003 "xchg %0, (%%esp) \n\t"
3004 "mov %%eax, %c[rax](%0) \n\t"
3005 "mov %%ebx, %c[rbx](%0) \n\t"
3006 "pushl (%%esp); popl %c[rcx](%0) \n\t"
3007 "mov %%edx, %c[rdx](%0) \n\t"
3008 "mov %%esi, %c[rsi](%0) \n\t"
3009 "mov %%edi, %c[rdi](%0) \n\t"
3010 "mov %%ebp, %c[rbp](%0) \n\t"
3011 "mov %%cr2, %%eax \n\t"
3012 "mov %%eax, %c[cr2](%0) \n\t"
3013
3014 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
3015 #endif
3016 "setbe %c[fail](%0) \n\t"
3017 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3018 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3019 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3020 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3021 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3022 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3023 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3024 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3025 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3026 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3027 #ifdef CONFIG_X86_64
3028 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3029 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3030 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3031 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3032 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3033 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3034 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3035 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3036 #endif
3037 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3038 : "cc", "memory"
3039 #ifdef CONFIG_X86_64
3040 , "rbx", "rdi", "rsi"
3041 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3042 #else
3043 , "ebx", "edi", "rsi"
3044 #endif
3045 );
3046
3047 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3048 if (vmx->rmode.irq.pending)
3049 fixup_rmode_irq(vmx);
3050
3051 vcpu->arch.interrupt_window_open =
3052 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3053 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0;
3054
3055 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3056 vmx->launched = 1;
3057
3058 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3059
3060 /* We need to handle NMIs before interrupts are enabled */
3061 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 &&
3062 (intr_info & INTR_INFO_VALID_MASK)) {
3063 KVMTRACE_0D(NMI, vcpu, handler);
3064 asm("int $2");
3065 }
3066 }
3067
3068 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3069 {
3070 struct vcpu_vmx *vmx = to_vmx(vcpu);
3071
3072 if (vmx->vmcs) {
3073 vcpu_clear(vmx);
3074 free_vmcs(vmx->vmcs);
3075 vmx->vmcs = NULL;
3076 }
3077 }
3078
3079 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3080 {
3081 struct vcpu_vmx *vmx = to_vmx(vcpu);
3082
3083 spin_lock(&vmx_vpid_lock);
3084 if (vmx->vpid != 0)
3085 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3086 spin_unlock(&vmx_vpid_lock);
3087 vmx_free_vmcs(vcpu);
3088 kfree(vmx->host_msrs);
3089 kfree(vmx->guest_msrs);
3090 kvm_vcpu_uninit(vcpu);
3091 kmem_cache_free(kvm_vcpu_cache, vmx);
3092 }
3093
3094 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3095 {
3096 int err;
3097 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3098 int cpu;
3099
3100 if (!vmx)
3101 return ERR_PTR(-ENOMEM);
3102
3103 allocate_vpid(vmx);
3104 if (id == 0 && vm_need_ept()) {
3105 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3106 VMX_EPT_WRITABLE_MASK |
3107 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3108 kvm_mmu_set_mask_ptes(0ull, VMX_EPT_FAKE_ACCESSED_MASK,
3109 VMX_EPT_FAKE_DIRTY_MASK, 0ull,
3110 VMX_EPT_EXECUTABLE_MASK);
3111 kvm_enable_tdp();
3112 }
3113
3114 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3115 if (err)
3116 goto free_vcpu;
3117
3118 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3119 if (!vmx->guest_msrs) {
3120 err = -ENOMEM;
3121 goto uninit_vcpu;
3122 }
3123
3124 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3125 if (!vmx->host_msrs)
3126 goto free_guest_msrs;
3127
3128 vmx->vmcs = alloc_vmcs();
3129 if (!vmx->vmcs)
3130 goto free_msrs;
3131
3132 vmcs_clear(vmx->vmcs);
3133
3134 cpu = get_cpu();
3135 vmx_vcpu_load(&vmx->vcpu, cpu);
3136 err = vmx_vcpu_setup(vmx);
3137 vmx_vcpu_put(&vmx->vcpu);
3138 put_cpu();
3139 if (err)
3140 goto free_vmcs;
3141 if (vm_need_virtualize_apic_accesses(kvm))
3142 if (alloc_apic_access_page(kvm) != 0)
3143 goto free_vmcs;
3144
3145 if (vm_need_ept())
3146 if (alloc_identity_pagetable(kvm) != 0)
3147 goto free_vmcs;
3148
3149 return &vmx->vcpu;
3150
3151 free_vmcs:
3152 free_vmcs(vmx->vmcs);
3153 free_msrs:
3154 kfree(vmx->host_msrs);
3155 free_guest_msrs:
3156 kfree(vmx->guest_msrs);
3157 uninit_vcpu:
3158 kvm_vcpu_uninit(&vmx->vcpu);
3159 free_vcpu:
3160 kmem_cache_free(kvm_vcpu_cache, vmx);
3161 return ERR_PTR(err);
3162 }
3163
3164 static void __init vmx_check_processor_compat(void *rtn)
3165 {
3166 struct vmcs_config vmcs_conf;
3167
3168 *(int *)rtn = 0;
3169 if (setup_vmcs_config(&vmcs_conf) < 0)
3170 *(int *)rtn = -EIO;
3171 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3172 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3173 smp_processor_id());
3174 *(int *)rtn = -EIO;
3175 }
3176 }
3177
3178 static int get_ept_level(void)
3179 {
3180 return VMX_EPT_DEFAULT_GAW + 1;
3181 }
3182
3183 static struct kvm_x86_ops vmx_x86_ops = {
3184 .cpu_has_kvm_support = cpu_has_kvm_support,
3185 .disabled_by_bios = vmx_disabled_by_bios,
3186 .hardware_setup = hardware_setup,
3187 .hardware_unsetup = hardware_unsetup,
3188 .check_processor_compatibility = vmx_check_processor_compat,
3189 .hardware_enable = hardware_enable,
3190 .hardware_disable = hardware_disable,
3191 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3192
3193 .vcpu_create = vmx_create_vcpu,
3194 .vcpu_free = vmx_free_vcpu,
3195 .vcpu_reset = vmx_vcpu_reset,
3196
3197 .prepare_guest_switch = vmx_save_host_state,
3198 .vcpu_load = vmx_vcpu_load,
3199 .vcpu_put = vmx_vcpu_put,
3200
3201 .set_guest_debug = set_guest_debug,
3202 .guest_debug_pre = kvm_guest_debug_pre,
3203 .get_msr = vmx_get_msr,
3204 .set_msr = vmx_set_msr,
3205 .get_segment_base = vmx_get_segment_base,
3206 .get_segment = vmx_get_segment,
3207 .set_segment = vmx_set_segment,
3208 .get_cpl = vmx_get_cpl,
3209 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3210 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3211 .set_cr0 = vmx_set_cr0,
3212 .set_cr3 = vmx_set_cr3,
3213 .set_cr4 = vmx_set_cr4,
3214 .set_efer = vmx_set_efer,
3215 .get_idt = vmx_get_idt,
3216 .set_idt = vmx_set_idt,
3217 .get_gdt = vmx_get_gdt,
3218 .set_gdt = vmx_set_gdt,
3219 .cache_regs = vcpu_load_rsp_rip,
3220 .decache_regs = vcpu_put_rsp_rip,
3221 .get_rflags = vmx_get_rflags,
3222 .set_rflags = vmx_set_rflags,
3223
3224 .tlb_flush = vmx_flush_tlb,
3225
3226 .run = vmx_vcpu_run,
3227 .handle_exit = kvm_handle_exit,
3228 .skip_emulated_instruction = skip_emulated_instruction,
3229 .patch_hypercall = vmx_patch_hypercall,
3230 .get_irq = vmx_get_irq,
3231 .set_irq = vmx_inject_irq,
3232 .queue_exception = vmx_queue_exception,
3233 .exception_injected = vmx_exception_injected,
3234 .inject_pending_irq = vmx_intr_assist,
3235 .inject_pending_vectors = do_interrupt_requests,
3236
3237 .set_tss_addr = vmx_set_tss_addr,
3238 .get_tdp_level = get_ept_level,
3239 };
3240
3241 static int __init vmx_init(void)
3242 {
3243 void *va;
3244 int r;
3245
3246 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3247 if (!vmx_io_bitmap_a)
3248 return -ENOMEM;
3249
3250 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3251 if (!vmx_io_bitmap_b) {
3252 r = -ENOMEM;
3253 goto out;
3254 }
3255
3256 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3257 if (!vmx_msr_bitmap) {
3258 r = -ENOMEM;
3259 goto out1;
3260 }
3261
3262 /*
3263 * Allow direct access to the PC debug port (it is often used for I/O
3264 * delays, but the vmexits simply slow things down).
3265 */
3266 va = kmap(vmx_io_bitmap_a);
3267 memset(va, 0xff, PAGE_SIZE);
3268 clear_bit(0x80, va);
3269 kunmap(vmx_io_bitmap_a);
3270
3271 va = kmap(vmx_io_bitmap_b);
3272 memset(va, 0xff, PAGE_SIZE);
3273 kunmap(vmx_io_bitmap_b);
3274
3275 va = kmap(vmx_msr_bitmap);
3276 memset(va, 0xff, PAGE_SIZE);
3277 kunmap(vmx_msr_bitmap);
3278
3279 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3280
3281 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3282 if (r)
3283 goto out2;
3284
3285 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3286 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3287 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3288 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3289 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3290
3291 if (cpu_has_vmx_ept())
3292 bypass_guest_pf = 0;
3293
3294 if (bypass_guest_pf)
3295 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3296
3297 ept_sync_global();
3298
3299 return 0;
3300
3301 out2:
3302 __free_page(vmx_msr_bitmap);
3303 out1:
3304 __free_page(vmx_io_bitmap_b);
3305 out:
3306 __free_page(vmx_io_bitmap_a);
3307 return r;
3308 }
3309
3310 static void __exit vmx_exit(void)
3311 {
3312 __free_page(vmx_msr_bitmap);
3313 __free_page(vmx_io_bitmap_b);
3314 __free_page(vmx_io_bitmap_a);
3315
3316 kvm_exit();
3317 }
3318
3319 module_init(vmx_init)
3320 module_exit(vmx_exit)
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