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Merge branch 'master' of git://git2.kernel.org/pub/scm/linux/kernel/git/torvalds...
[linux-2.6/linux-2.6-openrd.git] / arch / x86 / kvm / vmx.c
blobd4918d6fc9244207b20705ad74e2e620b3891b56
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include "kvm_cache_regs.h"
30 #include "x86.h"
31
32 #include <asm/io.h>
33 #include <asm/desc.h>
34 #include <asm/vmx.h>
35 #include <asm/virtext.h>
36 #include <asm/mce.h>
37
38 #include "trace.h"
39
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
44
45 static int __read_mostly bypass_guest_pf = 1;
46 module_param(bypass_guest_pf, bool, S_IRUGO);
47
48 static int __read_mostly enable_vpid = 1;
49 module_param_named(vpid, enable_vpid, bool, 0444);
50
51 static int __read_mostly flexpriority_enabled = 1;
52 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
53
54 static int __read_mostly enable_ept = 1;
55 module_param_named(ept, enable_ept, bool, S_IRUGO);
56
57 static int __read_mostly enable_unrestricted_guest = 1;
58 module_param_named(unrestricted_guest,
59 enable_unrestricted_guest, bool, S_IRUGO);
60
61 static int __read_mostly emulate_invalid_guest_state = 0;
62 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
63
64 /*
65 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
66 * ple_gap: upper bound on the amount of time between two successive
67 * executions of PAUSE in a loop. Also indicate if ple enabled.
68 * According to test, this time is usually small than 41 cycles.
69 * ple_window: upper bound on the amount of time a guest is allowed to execute
70 * in a PAUSE loop. Tests indicate that most spinlocks are held for
71 * less than 2^12 cycles
72 * Time is measured based on a counter that runs at the same rate as the TSC,
73 * refer SDM volume 3b section 21.6.13 & 22.1.3.
74 */
75 #define KVM_VMX_DEFAULT_PLE_GAP 41
76 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
77 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
78 module_param(ple_gap, int, S_IRUGO);
79
80 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
81 module_param(ple_window, int, S_IRUGO);
82
83 struct vmcs {
84 u32 revision_id;
85 u32 abort;
86 char data[0];
87 };
88
89 struct shared_msr_entry {
90 unsigned index;
91 u64 data;
92 u64 mask;
93 };
94
95 struct vcpu_vmx {
96 struct kvm_vcpu vcpu;
97 struct list_head local_vcpus_link;
98 unsigned long host_rsp;
99 int launched;
100 u8 fail;
101 u32 idt_vectoring_info;
102 struct shared_msr_entry *guest_msrs;
103 int nmsrs;
104 int save_nmsrs;
105 #ifdef CONFIG_X86_64
106 u64 msr_host_kernel_gs_base;
107 u64 msr_guest_kernel_gs_base;
108 #endif
109 struct vmcs *vmcs;
110 struct {
111 int loaded;
112 u16 fs_sel, gs_sel, ldt_sel;
113 int gs_ldt_reload_needed;
114 int fs_reload_needed;
115 } host_state;
116 struct {
117 int vm86_active;
118 u8 save_iopl;
119 struct kvm_save_segment {
120 u16 selector;
121 unsigned long base;
122 u32 limit;
123 u32 ar;
124 } tr, es, ds, fs, gs;
125 struct {
126 bool pending;
127 u8 vector;
128 unsigned rip;
129 } irq;
130 } rmode;
131 int vpid;
132 bool emulation_required;
133
134 /* Support for vnmi-less CPUs */
135 int soft_vnmi_blocked;
136 ktime_t entry_time;
137 s64 vnmi_blocked_time;
138 u32 exit_reason;
139 };
140
141 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
142 {
143 return container_of(vcpu, struct vcpu_vmx, vcpu);
144 }
145
146 static int init_rmode(struct kvm *kvm);
147 static u64 construct_eptp(unsigned long root_hpa);
148
149 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
150 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
151 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
152
153 static unsigned long *vmx_io_bitmap_a;
154 static unsigned long *vmx_io_bitmap_b;
155 static unsigned long *vmx_msr_bitmap_legacy;
156 static unsigned long *vmx_msr_bitmap_longmode;
157
158 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
159 static DEFINE_SPINLOCK(vmx_vpid_lock);
160
161 static struct vmcs_config {
162 int size;
163 int order;
164 u32 revision_id;
165 u32 pin_based_exec_ctrl;
166 u32 cpu_based_exec_ctrl;
167 u32 cpu_based_2nd_exec_ctrl;
168 u32 vmexit_ctrl;
169 u32 vmentry_ctrl;
170 } vmcs_config;
171
172 static struct vmx_capability {
173 u32 ept;
174 u32 vpid;
175 } vmx_capability;
176
177 #define VMX_SEGMENT_FIELD(seg) \
178 [VCPU_SREG_##seg] = { \
179 .selector = GUEST_##seg##_SELECTOR, \
180 .base = GUEST_##seg##_BASE, \
181 .limit = GUEST_##seg##_LIMIT, \
182 .ar_bytes = GUEST_##seg##_AR_BYTES, \
183 }
184
185 static struct kvm_vmx_segment_field {
186 unsigned selector;
187 unsigned base;
188 unsigned limit;
189 unsigned ar_bytes;
190 } kvm_vmx_segment_fields[] = {
191 VMX_SEGMENT_FIELD(CS),
192 VMX_SEGMENT_FIELD(DS),
193 VMX_SEGMENT_FIELD(ES),
194 VMX_SEGMENT_FIELD(FS),
195 VMX_SEGMENT_FIELD(GS),
196 VMX_SEGMENT_FIELD(SS),
197 VMX_SEGMENT_FIELD(TR),
198 VMX_SEGMENT_FIELD(LDTR),
199 };
200
201 static u64 host_efer;
202
203 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
204
205 /*
206 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
207 * away by decrementing the array size.
208 */
209 static const u32 vmx_msr_index[] = {
210 #ifdef CONFIG_X86_64
211 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
212 #endif
213 MSR_EFER, MSR_K6_STAR,
214 };
215 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
216
217 static inline int is_page_fault(u32 intr_info)
218 {
219 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
220 INTR_INFO_VALID_MASK)) ==
221 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
222 }
223
224 static inline int is_no_device(u32 intr_info)
225 {
226 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
227 INTR_INFO_VALID_MASK)) ==
228 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
229 }
230
231 static inline int is_invalid_opcode(u32 intr_info)
232 {
233 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
234 INTR_INFO_VALID_MASK)) ==
235 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
236 }
237
238 static inline int is_external_interrupt(u32 intr_info)
239 {
240 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
241 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
242 }
243
244 static inline int is_machine_check(u32 intr_info)
245 {
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
248 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
249 }
250
251 static inline int cpu_has_vmx_msr_bitmap(void)
252 {
253 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
254 }
255
256 static inline int cpu_has_vmx_tpr_shadow(void)
257 {
258 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
259 }
260
261 static inline int vm_need_tpr_shadow(struct kvm *kvm)
262 {
263 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
264 }
265
266 static inline int cpu_has_secondary_exec_ctrls(void)
267 {
268 return vmcs_config.cpu_based_exec_ctrl &
269 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
270 }
271
272 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
273 {
274 return vmcs_config.cpu_based_2nd_exec_ctrl &
275 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
276 }
277
278 static inline bool cpu_has_vmx_flexpriority(void)
279 {
280 return cpu_has_vmx_tpr_shadow() &&
281 cpu_has_vmx_virtualize_apic_accesses();
282 }
283
284 static inline bool cpu_has_vmx_ept_execute_only(void)
285 {
286 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
287 }
288
289 static inline bool cpu_has_vmx_eptp_uncacheable(void)
290 {
291 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
292 }
293
294 static inline bool cpu_has_vmx_eptp_writeback(void)
295 {
296 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
297 }
298
299 static inline bool cpu_has_vmx_ept_2m_page(void)
300 {
301 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
302 }
303
304 static inline int cpu_has_vmx_invept_individual_addr(void)
305 {
306 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
307 }
308
309 static inline int cpu_has_vmx_invept_context(void)
310 {
311 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
312 }
313
314 static inline int cpu_has_vmx_invept_global(void)
315 {
316 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
317 }
318
319 static inline int cpu_has_vmx_ept(void)
320 {
321 return vmcs_config.cpu_based_2nd_exec_ctrl &
322 SECONDARY_EXEC_ENABLE_EPT;
323 }
324
325 static inline int cpu_has_vmx_unrestricted_guest(void)
326 {
327 return vmcs_config.cpu_based_2nd_exec_ctrl &
328 SECONDARY_EXEC_UNRESTRICTED_GUEST;
329 }
330
331 static inline int cpu_has_vmx_ple(void)
332 {
333 return vmcs_config.cpu_based_2nd_exec_ctrl &
334 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
335 }
336
337 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
338 {
339 return flexpriority_enabled &&
340 (cpu_has_vmx_virtualize_apic_accesses()) &&
341 (irqchip_in_kernel(kvm));
342 }
343
344 static inline int cpu_has_vmx_vpid(void)
345 {
346 return vmcs_config.cpu_based_2nd_exec_ctrl &
347 SECONDARY_EXEC_ENABLE_VPID;
348 }
349
350 static inline int cpu_has_virtual_nmis(void)
351 {
352 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
353 }
354
355 static inline bool report_flexpriority(void)
356 {
357 return flexpriority_enabled;
358 }
359
360 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
361 {
362 int i;
363
364 for (i = 0; i < vmx->nmsrs; ++i)
365 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
366 return i;
367 return -1;
368 }
369
370 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
371 {
372 struct {
373 u64 vpid : 16;
374 u64 rsvd : 48;
375 u64 gva;
376 } operand = { vpid, 0, gva };
377
378 asm volatile (__ex(ASM_VMX_INVVPID)
379 /* CF==1 or ZF==1 --> rc = -1 */
380 "; ja 1f ; ud2 ; 1:"
381 : : "a"(&operand), "c"(ext) : "cc", "memory");
382 }
383
384 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
385 {
386 struct {
387 u64 eptp, gpa;
388 } operand = {eptp, gpa};
389
390 asm volatile (__ex(ASM_VMX_INVEPT)
391 /* CF==1 or ZF==1 --> rc = -1 */
392 "; ja 1f ; ud2 ; 1:\n"
393 : : "a" (&operand), "c" (ext) : "cc", "memory");
394 }
395
396 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
397 {
398 int i;
399
400 i = __find_msr_index(vmx, msr);
401 if (i >= 0)
402 return &vmx->guest_msrs[i];
403 return NULL;
404 }
405
406 static void vmcs_clear(struct vmcs *vmcs)
407 {
408 u64 phys_addr = __pa(vmcs);
409 u8 error;
410
411 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
412 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
413 : "cc", "memory");
414 if (error)
415 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
416 vmcs, phys_addr);
417 }
418
419 static void __vcpu_clear(void *arg)
420 {
421 struct vcpu_vmx *vmx = arg;
422 int cpu = raw_smp_processor_id();
423
424 if (vmx->vcpu.cpu == cpu)
425 vmcs_clear(vmx->vmcs);
426 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
427 per_cpu(current_vmcs, cpu) = NULL;
428 rdtscll(vmx->vcpu.arch.host_tsc);
429 list_del(&vmx->local_vcpus_link);
430 vmx->vcpu.cpu = -1;
431 vmx->launched = 0;
432 }
433
434 static void vcpu_clear(struct vcpu_vmx *vmx)
435 {
436 if (vmx->vcpu.cpu == -1)
437 return;
438 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
439 }
440
441 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
442 {
443 if (vmx->vpid == 0)
444 return;
445
446 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
447 }
448
449 static inline void ept_sync_global(void)
450 {
451 if (cpu_has_vmx_invept_global())
452 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
453 }
454
455 static inline void ept_sync_context(u64 eptp)
456 {
457 if (enable_ept) {
458 if (cpu_has_vmx_invept_context())
459 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
460 else
461 ept_sync_global();
462 }
463 }
464
465 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
466 {
467 if (enable_ept) {
468 if (cpu_has_vmx_invept_individual_addr())
469 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
470 eptp, gpa);
471 else
472 ept_sync_context(eptp);
473 }
474 }
475
476 static unsigned long vmcs_readl(unsigned long field)
477 {
478 unsigned long value;
479
480 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
481 : "=a"(value) : "d"(field) : "cc");
482 return value;
483 }
484
485 static u16 vmcs_read16(unsigned long field)
486 {
487 return vmcs_readl(field);
488 }
489
490 static u32 vmcs_read32(unsigned long field)
491 {
492 return vmcs_readl(field);
493 }
494
495 static u64 vmcs_read64(unsigned long field)
496 {
497 #ifdef CONFIG_X86_64
498 return vmcs_readl(field);
499 #else
500 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
501 #endif
502 }
503
504 static noinline void vmwrite_error(unsigned long field, unsigned long value)
505 {
506 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
507 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
508 dump_stack();
509 }
510
511 static void vmcs_writel(unsigned long field, unsigned long value)
512 {
513 u8 error;
514
515 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
516 : "=q"(error) : "a"(value), "d"(field) : "cc");
517 if (unlikely(error))
518 vmwrite_error(field, value);
519 }
520
521 static void vmcs_write16(unsigned long field, u16 value)
522 {
523 vmcs_writel(field, value);
524 }
525
526 static void vmcs_write32(unsigned long field, u32 value)
527 {
528 vmcs_writel(field, value);
529 }
530
531 static void vmcs_write64(unsigned long field, u64 value)
532 {
533 vmcs_writel(field, value);
534 #ifndef CONFIG_X86_64
535 asm volatile ("");
536 vmcs_writel(field+1, value >> 32);
537 #endif
538 }
539
540 static void vmcs_clear_bits(unsigned long field, u32 mask)
541 {
542 vmcs_writel(field, vmcs_readl(field) & ~mask);
543 }
544
545 static void vmcs_set_bits(unsigned long field, u32 mask)
546 {
547 vmcs_writel(field, vmcs_readl(field) | mask);
548 }
549
550 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
551 {
552 u32 eb;
553
554 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
555 if (!vcpu->fpu_active)
556 eb |= 1u << NM_VECTOR;
557 /*
558 * Unconditionally intercept #DB so we can maintain dr6 without
559 * reading it every exit.
560 */
561 eb |= 1u << DB_VECTOR;
562 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
563 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
564 eb |= 1u << BP_VECTOR;
565 }
566 if (to_vmx(vcpu)->rmode.vm86_active)
567 eb = ~0;
568 if (enable_ept)
569 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
570 vmcs_write32(EXCEPTION_BITMAP, eb);
571 }
572
573 static void reload_tss(void)
574 {
575 /*
576 * VT restores TR but not its size. Useless.
577 */
578 struct descriptor_table gdt;
579 struct desc_struct *descs;
580
581 kvm_get_gdt(&gdt);
582 descs = (void *)gdt.base;
583 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
584 load_TR_desc();
585 }
586
587 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
588 {
589 u64 guest_efer;
590 u64 ignore_bits;
591
592 guest_efer = vmx->vcpu.arch.shadow_efer;
593
594 /*
595 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
596 * outside long mode
597 */
598 ignore_bits = EFER_NX | EFER_SCE;
599 #ifdef CONFIG_X86_64
600 ignore_bits |= EFER_LMA | EFER_LME;
601 /* SCE is meaningful only in long mode on Intel */
602 if (guest_efer & EFER_LMA)
603 ignore_bits &= ~(u64)EFER_SCE;
604 #endif
605 guest_efer &= ~ignore_bits;
606 guest_efer |= host_efer & ignore_bits;
607 vmx->guest_msrs[efer_offset].data = guest_efer;
608 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
609 return true;
610 }
611
612 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
613 {
614 struct vcpu_vmx *vmx = to_vmx(vcpu);
615 int i;
616
617 if (vmx->host_state.loaded)
618 return;
619
620 vmx->host_state.loaded = 1;
621 /*
622 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
623 * allow segment selectors with cpl > 0 or ti == 1.
624 */
625 vmx->host_state.ldt_sel = kvm_read_ldt();
626 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
627 vmx->host_state.fs_sel = kvm_read_fs();
628 if (!(vmx->host_state.fs_sel & 7)) {
629 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
630 vmx->host_state.fs_reload_needed = 0;
631 } else {
632 vmcs_write16(HOST_FS_SELECTOR, 0);
633 vmx->host_state.fs_reload_needed = 1;
634 }
635 vmx->host_state.gs_sel = kvm_read_gs();
636 if (!(vmx->host_state.gs_sel & 7))
637 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
638 else {
639 vmcs_write16(HOST_GS_SELECTOR, 0);
640 vmx->host_state.gs_ldt_reload_needed = 1;
641 }
642
643 #ifdef CONFIG_X86_64
644 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
645 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
646 #else
647 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
648 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
649 #endif
650
651 #ifdef CONFIG_X86_64
652 if (is_long_mode(&vmx->vcpu)) {
653 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
654 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
655 }
656 #endif
657 for (i = 0; i < vmx->save_nmsrs; ++i)
658 kvm_set_shared_msr(vmx->guest_msrs[i].index,
659 vmx->guest_msrs[i].data,
660 vmx->guest_msrs[i].mask);
661 }
662
663 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
664 {
665 unsigned long flags;
666
667 if (!vmx->host_state.loaded)
668 return;
669
670 ++vmx->vcpu.stat.host_state_reload;
671 vmx->host_state.loaded = 0;
672 if (vmx->host_state.fs_reload_needed)
673 kvm_load_fs(vmx->host_state.fs_sel);
674 if (vmx->host_state.gs_ldt_reload_needed) {
675 kvm_load_ldt(vmx->host_state.ldt_sel);
676 /*
677 * If we have to reload gs, we must take care to
678 * preserve our gs base.
679 */
680 local_irq_save(flags);
681 kvm_load_gs(vmx->host_state.gs_sel);
682 #ifdef CONFIG_X86_64
683 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
684 #endif
685 local_irq_restore(flags);
686 }
687 reload_tss();
688 #ifdef CONFIG_X86_64
689 if (is_long_mode(&vmx->vcpu)) {
690 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
691 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
692 }
693 #endif
694 }
695
696 static void vmx_load_host_state(struct vcpu_vmx *vmx)
697 {
698 preempt_disable();
699 __vmx_load_host_state(vmx);
700 preempt_enable();
701 }
702
703 /*
704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
705 * vcpu mutex is already taken.
706 */
707 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
708 {
709 struct vcpu_vmx *vmx = to_vmx(vcpu);
710 u64 phys_addr = __pa(vmx->vmcs);
711 u64 tsc_this, delta, new_offset;
712
713 if (vcpu->cpu != cpu) {
714 vcpu_clear(vmx);
715 kvm_migrate_timers(vcpu);
716 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
717 local_irq_disable();
718 list_add(&vmx->local_vcpus_link,
719 &per_cpu(vcpus_on_cpu, cpu));
720 local_irq_enable();
721 }
722
723 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
724 u8 error;
725
726 per_cpu(current_vmcs, cpu) = vmx->vmcs;
727 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
728 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
729 : "cc");
730 if (error)
731 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
732 vmx->vmcs, phys_addr);
733 }
734
735 if (vcpu->cpu != cpu) {
736 struct descriptor_table dt;
737 unsigned long sysenter_esp;
738
739 vcpu->cpu = cpu;
740 /*
741 * Linux uses per-cpu TSS and GDT, so set these when switching
742 * processors.
743 */
744 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
745 kvm_get_gdt(&dt);
746 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
747
748 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
749 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
750
751 /*
752 * Make sure the time stamp counter is monotonous.
753 */
754 rdtscll(tsc_this);
755 if (tsc_this < vcpu->arch.host_tsc) {
756 delta = vcpu->arch.host_tsc - tsc_this;
757 new_offset = vmcs_read64(TSC_OFFSET) + delta;
758 vmcs_write64(TSC_OFFSET, new_offset);
759 }
760 }
761 }
762
763 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
764 {
765 __vmx_load_host_state(to_vmx(vcpu));
766 }
767
768 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
769 {
770 if (vcpu->fpu_active)
771 return;
772 vcpu->fpu_active = 1;
773 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
774 if (vcpu->arch.cr0 & X86_CR0_TS)
775 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
776 update_exception_bitmap(vcpu);
777 }
778
779 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
780 {
781 if (!vcpu->fpu_active)
782 return;
783 vcpu->fpu_active = 0;
784 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
785 update_exception_bitmap(vcpu);
786 }
787
788 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
789 {
790 unsigned long rflags;
791
792 rflags = vmcs_readl(GUEST_RFLAGS);
793 if (to_vmx(vcpu)->rmode.vm86_active)
794 rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
795 return rflags;
796 }
797
798 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
799 {
800 if (to_vmx(vcpu)->rmode.vm86_active)
801 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
802 vmcs_writel(GUEST_RFLAGS, rflags);
803 }
804
805 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
806 {
807 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
808 int ret = 0;
809
810 if (interruptibility & GUEST_INTR_STATE_STI)
811 ret |= X86_SHADOW_INT_STI;
812 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
813 ret |= X86_SHADOW_INT_MOV_SS;
814
815 return ret & mask;
816 }
817
818 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
819 {
820 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
821 u32 interruptibility = interruptibility_old;
822
823 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
824
825 if (mask & X86_SHADOW_INT_MOV_SS)
826 interruptibility |= GUEST_INTR_STATE_MOV_SS;
827 if (mask & X86_SHADOW_INT_STI)
828 interruptibility |= GUEST_INTR_STATE_STI;
829
830 if ((interruptibility != interruptibility_old))
831 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
832 }
833
834 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
835 {
836 unsigned long rip;
837
838 rip = kvm_rip_read(vcpu);
839 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
840 kvm_rip_write(vcpu, rip);
841
842 /* skipping an emulated instruction also counts */
843 vmx_set_interrupt_shadow(vcpu, 0);
844 }
845
846 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
847 bool has_error_code, u32 error_code)
848 {
849 struct vcpu_vmx *vmx = to_vmx(vcpu);
850 u32 intr_info = nr | INTR_INFO_VALID_MASK;
851
852 if (has_error_code) {
853 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
854 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
855 }
856
857 if (vmx->rmode.vm86_active) {
858 vmx->rmode.irq.pending = true;
859 vmx->rmode.irq.vector = nr;
860 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
861 if (kvm_exception_is_soft(nr))
862 vmx->rmode.irq.rip +=
863 vmx->vcpu.arch.event_exit_inst_len;
864 intr_info |= INTR_TYPE_SOFT_INTR;
865 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
866 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
867 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
868 return;
869 }
870
871 if (kvm_exception_is_soft(nr)) {
872 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
873 vmx->vcpu.arch.event_exit_inst_len);
874 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
875 } else
876 intr_info |= INTR_TYPE_HARD_EXCEPTION;
877
878 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
879 }
880
881 /*
882 * Swap MSR entry in host/guest MSR entry array.
883 */
884 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
885 {
886 struct shared_msr_entry tmp;
887
888 tmp = vmx->guest_msrs[to];
889 vmx->guest_msrs[to] = vmx->guest_msrs[from];
890 vmx->guest_msrs[from] = tmp;
891 }
892
893 /*
894 * Set up the vmcs to automatically save and restore system
895 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
896 * mode, as fiddling with msrs is very expensive.
897 */
898 static void setup_msrs(struct vcpu_vmx *vmx)
899 {
900 int save_nmsrs, index;
901 unsigned long *msr_bitmap;
902
903 vmx_load_host_state(vmx);
904 save_nmsrs = 0;
905 #ifdef CONFIG_X86_64
906 if (is_long_mode(&vmx->vcpu)) {
907 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
908 if (index >= 0)
909 move_msr_up(vmx, index, save_nmsrs++);
910 index = __find_msr_index(vmx, MSR_LSTAR);
911 if (index >= 0)
912 move_msr_up(vmx, index, save_nmsrs++);
913 index = __find_msr_index(vmx, MSR_CSTAR);
914 if (index >= 0)
915 move_msr_up(vmx, index, save_nmsrs++);
916 /*
917 * MSR_K6_STAR is only needed on long mode guests, and only
918 * if efer.sce is enabled.
919 */
920 index = __find_msr_index(vmx, MSR_K6_STAR);
921 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
922 move_msr_up(vmx, index, save_nmsrs++);
923 }
924 #endif
925 index = __find_msr_index(vmx, MSR_EFER);
926 if (index >= 0 && update_transition_efer(vmx, index))
927 move_msr_up(vmx, index, save_nmsrs++);
928
929 vmx->save_nmsrs = save_nmsrs;
930
931 if (cpu_has_vmx_msr_bitmap()) {
932 if (is_long_mode(&vmx->vcpu))
933 msr_bitmap = vmx_msr_bitmap_longmode;
934 else
935 msr_bitmap = vmx_msr_bitmap_legacy;
936
937 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
938 }
939 }
940
941 /*
942 * reads and returns guest's timestamp counter "register"
943 * guest_tsc = host_tsc + tsc_offset -- 21.3
944 */
945 static u64 guest_read_tsc(void)
946 {
947 u64 host_tsc, tsc_offset;
948
949 rdtscll(host_tsc);
950 tsc_offset = vmcs_read64(TSC_OFFSET);
951 return host_tsc + tsc_offset;
952 }
953
954 /*
955 * writes 'guest_tsc' into guest's timestamp counter "register"
956 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
957 */
958 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
959 {
960 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
961 }
962
963 /*
964 * Reads an msr value (of 'msr_index') into 'pdata'.
965 * Returns 0 on success, non-0 otherwise.
966 * Assumes vcpu_load() was already called.
967 */
968 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
969 {
970 u64 data;
971 struct shared_msr_entry *msr;
972
973 if (!pdata) {
974 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
975 return -EINVAL;
976 }
977
978 switch (msr_index) {
979 #ifdef CONFIG_X86_64
980 case MSR_FS_BASE:
981 data = vmcs_readl(GUEST_FS_BASE);
982 break;
983 case MSR_GS_BASE:
984 data = vmcs_readl(GUEST_GS_BASE);
985 break;
986 case MSR_KERNEL_GS_BASE:
987 vmx_load_host_state(to_vmx(vcpu));
988 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
989 break;
990 #endif
991 case MSR_EFER:
992 return kvm_get_msr_common(vcpu, msr_index, pdata);
993 case MSR_IA32_TSC:
994 data = guest_read_tsc();
995 break;
996 case MSR_IA32_SYSENTER_CS:
997 data = vmcs_read32(GUEST_SYSENTER_CS);
998 break;
999 case MSR_IA32_SYSENTER_EIP:
1000 data = vmcs_readl(GUEST_SYSENTER_EIP);
1001 break;
1002 case MSR_IA32_SYSENTER_ESP:
1003 data = vmcs_readl(GUEST_SYSENTER_ESP);
1004 break;
1005 default:
1006 vmx_load_host_state(to_vmx(vcpu));
1007 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1008 if (msr) {
1009 vmx_load_host_state(to_vmx(vcpu));
1010 data = msr->data;
1011 break;
1012 }
1013 return kvm_get_msr_common(vcpu, msr_index, pdata);
1014 }
1015
1016 *pdata = data;
1017 return 0;
1018 }
1019
1020 /*
1021 * Writes msr value into into the appropriate "register".
1022 * Returns 0 on success, non-0 otherwise.
1023 * Assumes vcpu_load() was already called.
1024 */
1025 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1026 {
1027 struct vcpu_vmx *vmx = to_vmx(vcpu);
1028 struct shared_msr_entry *msr;
1029 u64 host_tsc;
1030 int ret = 0;
1031
1032 switch (msr_index) {
1033 case MSR_EFER:
1034 vmx_load_host_state(vmx);
1035 ret = kvm_set_msr_common(vcpu, msr_index, data);
1036 break;
1037 #ifdef CONFIG_X86_64
1038 case MSR_FS_BASE:
1039 vmcs_writel(GUEST_FS_BASE, data);
1040 break;
1041 case MSR_GS_BASE:
1042 vmcs_writel(GUEST_GS_BASE, data);
1043 break;
1044 case MSR_KERNEL_GS_BASE:
1045 vmx_load_host_state(vmx);
1046 vmx->msr_guest_kernel_gs_base = data;
1047 break;
1048 #endif
1049 case MSR_IA32_SYSENTER_CS:
1050 vmcs_write32(GUEST_SYSENTER_CS, data);
1051 break;
1052 case MSR_IA32_SYSENTER_EIP:
1053 vmcs_writel(GUEST_SYSENTER_EIP, data);
1054 break;
1055 case MSR_IA32_SYSENTER_ESP:
1056 vmcs_writel(GUEST_SYSENTER_ESP, data);
1057 break;
1058 case MSR_IA32_TSC:
1059 rdtscll(host_tsc);
1060 guest_write_tsc(data, host_tsc);
1061 break;
1062 case MSR_IA32_CR_PAT:
1063 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1064 vmcs_write64(GUEST_IA32_PAT, data);
1065 vcpu->arch.pat = data;
1066 break;
1067 }
1068 /* Otherwise falls through to kvm_set_msr_common */
1069 default:
1070 msr = find_msr_entry(vmx, msr_index);
1071 if (msr) {
1072 vmx_load_host_state(vmx);
1073 msr->data = data;
1074 break;
1075 }
1076 ret = kvm_set_msr_common(vcpu, msr_index, data);
1077 }
1078
1079 return ret;
1080 }
1081
1082 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1083 {
1084 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1085 switch (reg) {
1086 case VCPU_REGS_RSP:
1087 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1088 break;
1089 case VCPU_REGS_RIP:
1090 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1091 break;
1092 case VCPU_EXREG_PDPTR:
1093 if (enable_ept)
1094 ept_save_pdptrs(vcpu);
1095 break;
1096 default:
1097 break;
1098 }
1099 }
1100
1101 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1102 {
1103 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1105 else
1106 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1107
1108 update_exception_bitmap(vcpu);
1109 }
1110
1111 static __init int cpu_has_kvm_support(void)
1112 {
1113 return cpu_has_vmx();
1114 }
1115
1116 static __init int vmx_disabled_by_bios(void)
1117 {
1118 u64 msr;
1119
1120 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1121 return (msr & (FEATURE_CONTROL_LOCKED |
1122 FEATURE_CONTROL_VMXON_ENABLED))
1123 == FEATURE_CONTROL_LOCKED;
1124 /* locked but not enabled */
1125 }
1126
1127 static int hardware_enable(void *garbage)
1128 {
1129 int cpu = raw_smp_processor_id();
1130 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1131 u64 old;
1132
1133 if (read_cr4() & X86_CR4_VMXE)
1134 return -EBUSY;
1135
1136 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1137 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1138 if ((old & (FEATURE_CONTROL_LOCKED |
1139 FEATURE_CONTROL_VMXON_ENABLED))
1140 != (FEATURE_CONTROL_LOCKED |
1141 FEATURE_CONTROL_VMXON_ENABLED))
1142 /* enable and lock */
1143 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1144 FEATURE_CONTROL_LOCKED |
1145 FEATURE_CONTROL_VMXON_ENABLED);
1146 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1147 asm volatile (ASM_VMX_VMXON_RAX
1148 : : "a"(&phys_addr), "m"(phys_addr)
1149 : "memory", "cc");
1150
1151 ept_sync_global();
1152
1153 return 0;
1154 }
1155
1156 static void vmclear_local_vcpus(void)
1157 {
1158 int cpu = raw_smp_processor_id();
1159 struct vcpu_vmx *vmx, *n;
1160
1161 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1162 local_vcpus_link)
1163 __vcpu_clear(vmx);
1164 }
1165
1166
1167 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1168 * tricks.
1169 */
1170 static void kvm_cpu_vmxoff(void)
1171 {
1172 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1173 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1174 }
1175
1176 static void hardware_disable(void *garbage)
1177 {
1178 vmclear_local_vcpus();
1179 kvm_cpu_vmxoff();
1180 }
1181
1182 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1183 u32 msr, u32 *result)
1184 {
1185 u32 vmx_msr_low, vmx_msr_high;
1186 u32 ctl = ctl_min | ctl_opt;
1187
1188 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1189
1190 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1191 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1192
1193 /* Ensure minimum (required) set of control bits are supported. */
1194 if (ctl_min & ~ctl)
1195 return -EIO;
1196
1197 *result = ctl;
1198 return 0;
1199 }
1200
1201 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1202 {
1203 u32 vmx_msr_low, vmx_msr_high;
1204 u32 min, opt, min2, opt2;
1205 u32 _pin_based_exec_control = 0;
1206 u32 _cpu_based_exec_control = 0;
1207 u32 _cpu_based_2nd_exec_control = 0;
1208 u32 _vmexit_control = 0;
1209 u32 _vmentry_control = 0;
1210
1211 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1212 opt = PIN_BASED_VIRTUAL_NMIS;
1213 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1214 &_pin_based_exec_control) < 0)
1215 return -EIO;
1216
1217 min = CPU_BASED_HLT_EXITING |
1218 #ifdef CONFIG_X86_64
1219 CPU_BASED_CR8_LOAD_EXITING |
1220 CPU_BASED_CR8_STORE_EXITING |
1221 #endif
1222 CPU_BASED_CR3_LOAD_EXITING |
1223 CPU_BASED_CR3_STORE_EXITING |
1224 CPU_BASED_USE_IO_BITMAPS |
1225 CPU_BASED_MOV_DR_EXITING |
1226 CPU_BASED_USE_TSC_OFFSETING |
1227 CPU_BASED_INVLPG_EXITING;
1228 opt = CPU_BASED_TPR_SHADOW |
1229 CPU_BASED_USE_MSR_BITMAPS |
1230 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1231 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1232 &_cpu_based_exec_control) < 0)
1233 return -EIO;
1234 #ifdef CONFIG_X86_64
1235 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1236 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1237 ~CPU_BASED_CR8_STORE_EXITING;
1238 #endif
1239 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1240 min2 = 0;
1241 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1242 SECONDARY_EXEC_WBINVD_EXITING |
1243 SECONDARY_EXEC_ENABLE_VPID |
1244 SECONDARY_EXEC_ENABLE_EPT |
1245 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1246 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1247 if (adjust_vmx_controls(min2, opt2,
1248 MSR_IA32_VMX_PROCBASED_CTLS2,
1249 &_cpu_based_2nd_exec_control) < 0)
1250 return -EIO;
1251 }
1252 #ifndef CONFIG_X86_64
1253 if (!(_cpu_based_2nd_exec_control &
1254 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1255 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1256 #endif
1257 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1258 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1259 enabled */
1260 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1261 CPU_BASED_CR3_STORE_EXITING |
1262 CPU_BASED_INVLPG_EXITING);
1263 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1264 vmx_capability.ept, vmx_capability.vpid);
1265 }
1266
1267 min = 0;
1268 #ifdef CONFIG_X86_64
1269 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1270 #endif
1271 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1272 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1273 &_vmexit_control) < 0)
1274 return -EIO;
1275
1276 min = 0;
1277 opt = VM_ENTRY_LOAD_IA32_PAT;
1278 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1279 &_vmentry_control) < 0)
1280 return -EIO;
1281
1282 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1283
1284 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1285 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1286 return -EIO;
1287
1288 #ifdef CONFIG_X86_64
1289 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1290 if (vmx_msr_high & (1u<<16))
1291 return -EIO;
1292 #endif
1293
1294 /* Require Write-Back (WB) memory type for VMCS accesses. */
1295 if (((vmx_msr_high >> 18) & 15) != 6)
1296 return -EIO;
1297
1298 vmcs_conf->size = vmx_msr_high & 0x1fff;
1299 vmcs_conf->order = get_order(vmcs_config.size);
1300 vmcs_conf->revision_id = vmx_msr_low;
1301
1302 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1303 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1304 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1305 vmcs_conf->vmexit_ctrl = _vmexit_control;
1306 vmcs_conf->vmentry_ctrl = _vmentry_control;
1307
1308 return 0;
1309 }
1310
1311 static struct vmcs *alloc_vmcs_cpu(int cpu)
1312 {
1313 int node = cpu_to_node(cpu);
1314 struct page *pages;
1315 struct vmcs *vmcs;
1316
1317 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1318 if (!pages)
1319 return NULL;
1320 vmcs = page_address(pages);
1321 memset(vmcs, 0, vmcs_config.size);
1322 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1323 return vmcs;
1324 }
1325
1326 static struct vmcs *alloc_vmcs(void)
1327 {
1328 return alloc_vmcs_cpu(raw_smp_processor_id());
1329 }
1330
1331 static void free_vmcs(struct vmcs *vmcs)
1332 {
1333 free_pages((unsigned long)vmcs, vmcs_config.order);
1334 }
1335
1336 static void free_kvm_area(void)
1337 {
1338 int cpu;
1339
1340 for_each_possible_cpu(cpu) {
1341 free_vmcs(per_cpu(vmxarea, cpu));
1342 per_cpu(vmxarea, cpu) = NULL;
1343 }
1344 }
1345
1346 static __init int alloc_kvm_area(void)
1347 {
1348 int cpu;
1349
1350 for_each_possible_cpu(cpu) {
1351 struct vmcs *vmcs;
1352
1353 vmcs = alloc_vmcs_cpu(cpu);
1354 if (!vmcs) {
1355 free_kvm_area();
1356 return -ENOMEM;
1357 }
1358
1359 per_cpu(vmxarea, cpu) = vmcs;
1360 }
1361 return 0;
1362 }
1363
1364 static __init int hardware_setup(void)
1365 {
1366 if (setup_vmcs_config(&vmcs_config) < 0)
1367 return -EIO;
1368
1369 if (boot_cpu_has(X86_FEATURE_NX))
1370 kvm_enable_efer_bits(EFER_NX);
1371
1372 if (!cpu_has_vmx_vpid())
1373 enable_vpid = 0;
1374
1375 if (!cpu_has_vmx_ept()) {
1376 enable_ept = 0;
1377 enable_unrestricted_guest = 0;
1378 }
1379
1380 if (!cpu_has_vmx_unrestricted_guest())
1381 enable_unrestricted_guest = 0;
1382
1383 if (!cpu_has_vmx_flexpriority())
1384 flexpriority_enabled = 0;
1385
1386 if (!cpu_has_vmx_tpr_shadow())
1387 kvm_x86_ops->update_cr8_intercept = NULL;
1388
1389 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1390 kvm_disable_largepages();
1391
1392 if (!cpu_has_vmx_ple())
1393 ple_gap = 0;
1394
1395 return alloc_kvm_area();
1396 }
1397
1398 static __exit void hardware_unsetup(void)
1399 {
1400 free_kvm_area();
1401 }
1402
1403 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1404 {
1405 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1406
1407 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1408 vmcs_write16(sf->selector, save->selector);
1409 vmcs_writel(sf->base, save->base);
1410 vmcs_write32(sf->limit, save->limit);
1411 vmcs_write32(sf->ar_bytes, save->ar);
1412 } else {
1413 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1414 << AR_DPL_SHIFT;
1415 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1416 }
1417 }
1418
1419 static void enter_pmode(struct kvm_vcpu *vcpu)
1420 {
1421 unsigned long flags;
1422 struct vcpu_vmx *vmx = to_vmx(vcpu);
1423
1424 vmx->emulation_required = 1;
1425 vmx->rmode.vm86_active = 0;
1426
1427 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1428 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1429 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1430
1431 flags = vmcs_readl(GUEST_RFLAGS);
1432 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1433 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1434 vmcs_writel(GUEST_RFLAGS, flags);
1435
1436 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1437 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1438
1439 update_exception_bitmap(vcpu);
1440
1441 if (emulate_invalid_guest_state)
1442 return;
1443
1444 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1445 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1446 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1447 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1448
1449 vmcs_write16(GUEST_SS_SELECTOR, 0);
1450 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1451
1452 vmcs_write16(GUEST_CS_SELECTOR,
1453 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1454 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1455 }
1456
1457 static gva_t rmode_tss_base(struct kvm *kvm)
1458 {
1459 if (!kvm->arch.tss_addr) {
1460 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1461 kvm->memslots[0].npages - 3;
1462 return base_gfn << PAGE_SHIFT;
1463 }
1464 return kvm->arch.tss_addr;
1465 }
1466
1467 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1468 {
1469 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1470
1471 save->selector = vmcs_read16(sf->selector);
1472 save->base = vmcs_readl(sf->base);
1473 save->limit = vmcs_read32(sf->limit);
1474 save->ar = vmcs_read32(sf->ar_bytes);
1475 vmcs_write16(sf->selector, save->base >> 4);
1476 vmcs_write32(sf->base, save->base & 0xfffff);
1477 vmcs_write32(sf->limit, 0xffff);
1478 vmcs_write32(sf->ar_bytes, 0xf3);
1479 }
1480
1481 static void enter_rmode(struct kvm_vcpu *vcpu)
1482 {
1483 unsigned long flags;
1484 struct vcpu_vmx *vmx = to_vmx(vcpu);
1485
1486 if (enable_unrestricted_guest)
1487 return;
1488
1489 vmx->emulation_required = 1;
1490 vmx->rmode.vm86_active = 1;
1491
1492 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1493 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1494
1495 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1496 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1497
1498 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1499 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1500
1501 flags = vmcs_readl(GUEST_RFLAGS);
1502 vmx->rmode.save_iopl
1503 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1504
1505 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1506
1507 vmcs_writel(GUEST_RFLAGS, flags);
1508 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1509 update_exception_bitmap(vcpu);
1510
1511 if (emulate_invalid_guest_state)
1512 goto continue_rmode;
1513
1514 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1515 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1516 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1517
1518 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1519 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1520 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1521 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1522 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1523
1524 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1525 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1526 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1527 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1528
1529 continue_rmode:
1530 kvm_mmu_reset_context(vcpu);
1531 init_rmode(vcpu->kvm);
1532 }
1533
1534 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1535 {
1536 struct vcpu_vmx *vmx = to_vmx(vcpu);
1537 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1538
1539 if (!msr)
1540 return;
1541
1542 /*
1543 * Force kernel_gs_base reloading before EFER changes, as control
1544 * of this msr depends on is_long_mode().
1545 */
1546 vmx_load_host_state(to_vmx(vcpu));
1547 vcpu->arch.shadow_efer = efer;
1548 if (!msr)
1549 return;
1550 if (efer & EFER_LMA) {
1551 vmcs_write32(VM_ENTRY_CONTROLS,
1552 vmcs_read32(VM_ENTRY_CONTROLS) |
1553 VM_ENTRY_IA32E_MODE);
1554 msr->data = efer;
1555 } else {
1556 vmcs_write32(VM_ENTRY_CONTROLS,
1557 vmcs_read32(VM_ENTRY_CONTROLS) &
1558 ~VM_ENTRY_IA32E_MODE);
1559
1560 msr->data = efer & ~EFER_LME;
1561 }
1562 setup_msrs(vmx);
1563 }
1564
1565 #ifdef CONFIG_X86_64
1566
1567 static void enter_lmode(struct kvm_vcpu *vcpu)
1568 {
1569 u32 guest_tr_ar;
1570
1571 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1572 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1573 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1574 __func__);
1575 vmcs_write32(GUEST_TR_AR_BYTES,
1576 (guest_tr_ar & ~AR_TYPE_MASK)
1577 | AR_TYPE_BUSY_64_TSS);
1578 }
1579 vcpu->arch.shadow_efer |= EFER_LMA;
1580 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1581 }
1582
1583 static void exit_lmode(struct kvm_vcpu *vcpu)
1584 {
1585 vcpu->arch.shadow_efer &= ~EFER_LMA;
1586
1587 vmcs_write32(VM_ENTRY_CONTROLS,
1588 vmcs_read32(VM_ENTRY_CONTROLS)
1589 & ~VM_ENTRY_IA32E_MODE);
1590 }
1591
1592 #endif
1593
1594 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1595 {
1596 vpid_sync_vcpu_all(to_vmx(vcpu));
1597 if (enable_ept)
1598 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1599 }
1600
1601 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1602 {
1603 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1604 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1605 }
1606
1607 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1608 {
1609 if (!test_bit(VCPU_EXREG_PDPTR,
1610 (unsigned long *)&vcpu->arch.regs_dirty))
1611 return;
1612
1613 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1614 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1615 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1616 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1617 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1618 }
1619 }
1620
1621 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1622 {
1623 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1624 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1625 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1626 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1627 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1628 }
1629
1630 __set_bit(VCPU_EXREG_PDPTR,
1631 (unsigned long *)&vcpu->arch.regs_avail);
1632 __set_bit(VCPU_EXREG_PDPTR,
1633 (unsigned long *)&vcpu->arch.regs_dirty);
1634 }
1635
1636 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1637
1638 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1639 unsigned long cr0,
1640 struct kvm_vcpu *vcpu)
1641 {
1642 if (!(cr0 & X86_CR0_PG)) {
1643 /* From paging/starting to nonpaging */
1644 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1645 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1646 (CPU_BASED_CR3_LOAD_EXITING |
1647 CPU_BASED_CR3_STORE_EXITING));
1648 vcpu->arch.cr0 = cr0;
1649 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1650 } else if (!is_paging(vcpu)) {
1651 /* From nonpaging to paging */
1652 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1653 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1654 ~(CPU_BASED_CR3_LOAD_EXITING |
1655 CPU_BASED_CR3_STORE_EXITING));
1656 vcpu->arch.cr0 = cr0;
1657 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1658 }
1659
1660 if (!(cr0 & X86_CR0_WP))
1661 *hw_cr0 &= ~X86_CR0_WP;
1662 }
1663
1664 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1665 struct kvm_vcpu *vcpu)
1666 {
1667 if (!is_paging(vcpu)) {
1668 *hw_cr4 &= ~X86_CR4_PAE;
1669 *hw_cr4 |= X86_CR4_PSE;
1670 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1671 *hw_cr4 &= ~X86_CR4_PAE;
1672 }
1673
1674 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1675 {
1676 struct vcpu_vmx *vmx = to_vmx(vcpu);
1677 unsigned long hw_cr0;
1678
1679 if (enable_unrestricted_guest)
1680 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1681 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1682 else
1683 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1684
1685 vmx_fpu_deactivate(vcpu);
1686
1687 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1688 enter_pmode(vcpu);
1689
1690 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1691 enter_rmode(vcpu);
1692
1693 #ifdef CONFIG_X86_64
1694 if (vcpu->arch.shadow_efer & EFER_LME) {
1695 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1696 enter_lmode(vcpu);
1697 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1698 exit_lmode(vcpu);
1699 }
1700 #endif
1701
1702 if (enable_ept)
1703 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1704
1705 vmcs_writel(CR0_READ_SHADOW, cr0);
1706 vmcs_writel(GUEST_CR0, hw_cr0);
1707 vcpu->arch.cr0 = cr0;
1708
1709 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1710 vmx_fpu_activate(vcpu);
1711 }
1712
1713 static u64 construct_eptp(unsigned long root_hpa)
1714 {
1715 u64 eptp;
1716
1717 /* TODO write the value reading from MSR */
1718 eptp = VMX_EPT_DEFAULT_MT |
1719 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1720 eptp |= (root_hpa & PAGE_MASK);
1721
1722 return eptp;
1723 }
1724
1725 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1726 {
1727 unsigned long guest_cr3;
1728 u64 eptp;
1729
1730 guest_cr3 = cr3;
1731 if (enable_ept) {
1732 eptp = construct_eptp(cr3);
1733 vmcs_write64(EPT_POINTER, eptp);
1734 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1735 vcpu->kvm->arch.ept_identity_map_addr;
1736 ept_load_pdptrs(vcpu);
1737 }
1738
1739 vmx_flush_tlb(vcpu);
1740 vmcs_writel(GUEST_CR3, guest_cr3);
1741 if (vcpu->arch.cr0 & X86_CR0_PE)
1742 vmx_fpu_deactivate(vcpu);
1743 }
1744
1745 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1746 {
1747 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1748 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1749
1750 vcpu->arch.cr4 = cr4;
1751 if (enable_ept)
1752 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1753
1754 vmcs_writel(CR4_READ_SHADOW, cr4);
1755 vmcs_writel(GUEST_CR4, hw_cr4);
1756 }
1757
1758 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1759 {
1760 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1761
1762 return vmcs_readl(sf->base);
1763 }
1764
1765 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1766 struct kvm_segment *var, int seg)
1767 {
1768 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1769 u32 ar;
1770
1771 var->base = vmcs_readl(sf->base);
1772 var->limit = vmcs_read32(sf->limit);
1773 var->selector = vmcs_read16(sf->selector);
1774 ar = vmcs_read32(sf->ar_bytes);
1775 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1776 ar = 0;
1777 var->type = ar & 15;
1778 var->s = (ar >> 4) & 1;
1779 var->dpl = (ar >> 5) & 3;
1780 var->present = (ar >> 7) & 1;
1781 var->avl = (ar >> 12) & 1;
1782 var->l = (ar >> 13) & 1;
1783 var->db = (ar >> 14) & 1;
1784 var->g = (ar >> 15) & 1;
1785 var->unusable = (ar >> 16) & 1;
1786 }
1787
1788 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1789 {
1790 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1791 return 0;
1792
1793 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1794 return 3;
1795
1796 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1797 }
1798
1799 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1800 {
1801 u32 ar;
1802
1803 if (var->unusable)
1804 ar = 1 << 16;
1805 else {
1806 ar = var->type & 15;
1807 ar |= (var->s & 1) << 4;
1808 ar |= (var->dpl & 3) << 5;
1809 ar |= (var->present & 1) << 7;
1810 ar |= (var->avl & 1) << 12;
1811 ar |= (var->l & 1) << 13;
1812 ar |= (var->db & 1) << 14;
1813 ar |= (var->g & 1) << 15;
1814 }
1815 if (ar == 0) /* a 0 value means unusable */
1816 ar = AR_UNUSABLE_MASK;
1817
1818 return ar;
1819 }
1820
1821 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1822 struct kvm_segment *var, int seg)
1823 {
1824 struct vcpu_vmx *vmx = to_vmx(vcpu);
1825 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1826 u32 ar;
1827
1828 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1829 vmx->rmode.tr.selector = var->selector;
1830 vmx->rmode.tr.base = var->base;
1831 vmx->rmode.tr.limit = var->limit;
1832 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1833 return;
1834 }
1835 vmcs_writel(sf->base, var->base);
1836 vmcs_write32(sf->limit, var->limit);
1837 vmcs_write16(sf->selector, var->selector);
1838 if (vmx->rmode.vm86_active && var->s) {
1839 /*
1840 * Hack real-mode segments into vm86 compatibility.
1841 */
1842 if (var->base == 0xffff0000 && var->selector == 0xf000)
1843 vmcs_writel(sf->base, 0xf0000);
1844 ar = 0xf3;
1845 } else
1846 ar = vmx_segment_access_rights(var);
1847
1848 /*
1849 * Fix the "Accessed" bit in AR field of segment registers for older
1850 * qemu binaries.
1851 * IA32 arch specifies that at the time of processor reset the
1852 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1853 * is setting it to 0 in the usedland code. This causes invalid guest
1854 * state vmexit when "unrestricted guest" mode is turned on.
1855 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1856 * tree. Newer qemu binaries with that qemu fix would not need this
1857 * kvm hack.
1858 */
1859 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1860 ar |= 0x1; /* Accessed */
1861
1862 vmcs_write32(sf->ar_bytes, ar);
1863 }
1864
1865 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1866 {
1867 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1868
1869 *db = (ar >> 14) & 1;
1870 *l = (ar >> 13) & 1;
1871 }
1872
1873 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1874 {
1875 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1876 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1877 }
1878
1879 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1880 {
1881 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1882 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1883 }
1884
1885 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1886 {
1887 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1888 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1889 }
1890
1891 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1892 {
1893 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1894 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1895 }
1896
1897 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1898 {
1899 struct kvm_segment var;
1900 u32 ar;
1901
1902 vmx_get_segment(vcpu, &var, seg);
1903 ar = vmx_segment_access_rights(&var);
1904
1905 if (var.base != (var.selector << 4))
1906 return false;
1907 if (var.limit != 0xffff)
1908 return false;
1909 if (ar != 0xf3)
1910 return false;
1911
1912 return true;
1913 }
1914
1915 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1916 {
1917 struct kvm_segment cs;
1918 unsigned int cs_rpl;
1919
1920 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1921 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1922
1923 if (cs.unusable)
1924 return false;
1925 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1926 return false;
1927 if (!cs.s)
1928 return false;
1929 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1930 if (cs.dpl > cs_rpl)
1931 return false;
1932 } else {
1933 if (cs.dpl != cs_rpl)
1934 return false;
1935 }
1936 if (!cs.present)
1937 return false;
1938
1939 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1940 return true;
1941 }
1942
1943 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1944 {
1945 struct kvm_segment ss;
1946 unsigned int ss_rpl;
1947
1948 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1949 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1950
1951 if (ss.unusable)
1952 return true;
1953 if (ss.type != 3 && ss.type != 7)
1954 return false;
1955 if (!ss.s)
1956 return false;
1957 if (ss.dpl != ss_rpl) /* DPL != RPL */
1958 return false;
1959 if (!ss.present)
1960 return false;
1961
1962 return true;
1963 }
1964
1965 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1966 {
1967 struct kvm_segment var;
1968 unsigned int rpl;
1969
1970 vmx_get_segment(vcpu, &var, seg);
1971 rpl = var.selector & SELECTOR_RPL_MASK;
1972
1973 if (var.unusable)
1974 return true;
1975 if (!var.s)
1976 return false;
1977 if (!var.present)
1978 return false;
1979 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1980 if (var.dpl < rpl) /* DPL < RPL */
1981 return false;
1982 }
1983
1984 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1985 * rights flags
1986 */
1987 return true;
1988 }
1989
1990 static bool tr_valid(struct kvm_vcpu *vcpu)
1991 {
1992 struct kvm_segment tr;
1993
1994 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1995
1996 if (tr.unusable)
1997 return false;
1998 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1999 return false;
2000 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2001 return false;
2002 if (!tr.present)
2003 return false;
2004
2005 return true;
2006 }
2007
2008 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2009 {
2010 struct kvm_segment ldtr;
2011
2012 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2013
2014 if (ldtr.unusable)
2015 return true;
2016 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2017 return false;
2018 if (ldtr.type != 2)
2019 return false;
2020 if (!ldtr.present)
2021 return false;
2022
2023 return true;
2024 }
2025
2026 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2027 {
2028 struct kvm_segment cs, ss;
2029
2030 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2031 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2032
2033 return ((cs.selector & SELECTOR_RPL_MASK) ==
2034 (ss.selector & SELECTOR_RPL_MASK));
2035 }
2036
2037 /*
2038 * Check if guest state is valid. Returns true if valid, false if
2039 * not.
2040 * We assume that registers are always usable
2041 */
2042 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2043 {
2044 /* real mode guest state checks */
2045 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2046 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2047 return false;
2048 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2049 return false;
2050 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2051 return false;
2052 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2053 return false;
2054 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2055 return false;
2056 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2057 return false;
2058 } else {
2059 /* protected mode guest state checks */
2060 if (!cs_ss_rpl_check(vcpu))
2061 return false;
2062 if (!code_segment_valid(vcpu))
2063 return false;
2064 if (!stack_segment_valid(vcpu))
2065 return false;
2066 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2067 return false;
2068 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2069 return false;
2070 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2071 return false;
2072 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2073 return false;
2074 if (!tr_valid(vcpu))
2075 return false;
2076 if (!ldtr_valid(vcpu))
2077 return false;
2078 }
2079 /* TODO:
2080 * - Add checks on RIP
2081 * - Add checks on RFLAGS
2082 */
2083
2084 return true;
2085 }
2086
2087 static int init_rmode_tss(struct kvm *kvm)
2088 {
2089 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2090 u16 data = 0;
2091 int ret = 0;
2092 int r;
2093
2094 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2095 if (r < 0)
2096 goto out;
2097 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2098 r = kvm_write_guest_page(kvm, fn++, &data,
2099 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2100 if (r < 0)
2101 goto out;
2102 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2103 if (r < 0)
2104 goto out;
2105 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2106 if (r < 0)
2107 goto out;
2108 data = ~0;
2109 r = kvm_write_guest_page(kvm, fn, &data,
2110 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2111 sizeof(u8));
2112 if (r < 0)
2113 goto out;
2114
2115 ret = 1;
2116 out:
2117 return ret;
2118 }
2119
2120 static int init_rmode_identity_map(struct kvm *kvm)
2121 {
2122 int i, r, ret;
2123 pfn_t identity_map_pfn;
2124 u32 tmp;
2125
2126 if (!enable_ept)
2127 return 1;
2128 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2129 printk(KERN_ERR "EPT: identity-mapping pagetable "
2130 "haven't been allocated!\n");
2131 return 0;
2132 }
2133 if (likely(kvm->arch.ept_identity_pagetable_done))
2134 return 1;
2135 ret = 0;
2136 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2137 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2138 if (r < 0)
2139 goto out;
2140 /* Set up identity-mapping pagetable for EPT in real mode */
2141 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2142 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2143 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2144 r = kvm_write_guest_page(kvm, identity_map_pfn,
2145 &tmp, i * sizeof(tmp), sizeof(tmp));
2146 if (r < 0)
2147 goto out;
2148 }
2149 kvm->arch.ept_identity_pagetable_done = true;
2150 ret = 1;
2151 out:
2152 return ret;
2153 }
2154
2155 static void seg_setup(int seg)
2156 {
2157 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2158 unsigned int ar;
2159
2160 vmcs_write16(sf->selector, 0);
2161 vmcs_writel(sf->base, 0);
2162 vmcs_write32(sf->limit, 0xffff);
2163 if (enable_unrestricted_guest) {
2164 ar = 0x93;
2165 if (seg == VCPU_SREG_CS)
2166 ar |= 0x08; /* code segment */
2167 } else
2168 ar = 0xf3;
2169
2170 vmcs_write32(sf->ar_bytes, ar);
2171 }
2172
2173 static int alloc_apic_access_page(struct kvm *kvm)
2174 {
2175 struct kvm_userspace_memory_region kvm_userspace_mem;
2176 int r = 0;
2177
2178 down_write(&kvm->slots_lock);
2179 if (kvm->arch.apic_access_page)
2180 goto out;
2181 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2182 kvm_userspace_mem.flags = 0;
2183 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2184 kvm_userspace_mem.memory_size = PAGE_SIZE;
2185 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2186 if (r)
2187 goto out;
2188
2189 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2190 out:
2191 up_write(&kvm->slots_lock);
2192 return r;
2193 }
2194
2195 static int alloc_identity_pagetable(struct kvm *kvm)
2196 {
2197 struct kvm_userspace_memory_region kvm_userspace_mem;
2198 int r = 0;
2199
2200 down_write(&kvm->slots_lock);
2201 if (kvm->arch.ept_identity_pagetable)
2202 goto out;
2203 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2204 kvm_userspace_mem.flags = 0;
2205 kvm_userspace_mem.guest_phys_addr =
2206 kvm->arch.ept_identity_map_addr;
2207 kvm_userspace_mem.memory_size = PAGE_SIZE;
2208 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2209 if (r)
2210 goto out;
2211
2212 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2213 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2214 out:
2215 up_write(&kvm->slots_lock);
2216 return r;
2217 }
2218
2219 static void allocate_vpid(struct vcpu_vmx *vmx)
2220 {
2221 int vpid;
2222
2223 vmx->vpid = 0;
2224 if (!enable_vpid)
2225 return;
2226 spin_lock(&vmx_vpid_lock);
2227 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2228 if (vpid < VMX_NR_VPIDS) {
2229 vmx->vpid = vpid;
2230 __set_bit(vpid, vmx_vpid_bitmap);
2231 }
2232 spin_unlock(&vmx_vpid_lock);
2233 }
2234
2235 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2236 {
2237 int f = sizeof(unsigned long);
2238
2239 if (!cpu_has_vmx_msr_bitmap())
2240 return;
2241
2242 /*
2243 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2244 * have the write-low and read-high bitmap offsets the wrong way round.
2245 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2246 */
2247 if (msr <= 0x1fff) {
2248 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2249 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2250 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2251 msr &= 0x1fff;
2252 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2253 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2254 }
2255 }
2256
2257 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2258 {
2259 if (!longmode_only)
2260 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2261 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2262 }
2263
2264 /*
2265 * Sets up the vmcs for emulated real mode.
2266 */
2267 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2268 {
2269 u32 host_sysenter_cs, msr_low, msr_high;
2270 u32 junk;
2271 u64 host_pat, tsc_this, tsc_base;
2272 unsigned long a;
2273 struct descriptor_table dt;
2274 int i;
2275 unsigned long kvm_vmx_return;
2276 u32 exec_control;
2277
2278 /* I/O */
2279 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2280 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2281
2282 if (cpu_has_vmx_msr_bitmap())
2283 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2284
2285 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2286
2287 /* Control */
2288 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2289 vmcs_config.pin_based_exec_ctrl);
2290
2291 exec_control = vmcs_config.cpu_based_exec_ctrl;
2292 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2293 exec_control &= ~CPU_BASED_TPR_SHADOW;
2294 #ifdef CONFIG_X86_64
2295 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2296 CPU_BASED_CR8_LOAD_EXITING;
2297 #endif
2298 }
2299 if (!enable_ept)
2300 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2301 CPU_BASED_CR3_LOAD_EXITING |
2302 CPU_BASED_INVLPG_EXITING;
2303 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2304
2305 if (cpu_has_secondary_exec_ctrls()) {
2306 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2307 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2308 exec_control &=
2309 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2310 if (vmx->vpid == 0)
2311 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2312 if (!enable_ept) {
2313 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2314 enable_unrestricted_guest = 0;
2315 }
2316 if (!enable_unrestricted_guest)
2317 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2318 if (!ple_gap)
2319 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2320 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2321 }
2322
2323 if (ple_gap) {
2324 vmcs_write32(PLE_GAP, ple_gap);
2325 vmcs_write32(PLE_WINDOW, ple_window);
2326 }
2327
2328 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2329 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2330 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2331
2332 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2333 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2334 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2335
2336 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2337 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2338 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2339 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2340 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2341 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2342 #ifdef CONFIG_X86_64
2343 rdmsrl(MSR_FS_BASE, a);
2344 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2345 rdmsrl(MSR_GS_BASE, a);
2346 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2347 #else
2348 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2349 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2350 #endif
2351
2352 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2353
2354 kvm_get_idt(&dt);
2355 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2356
2357 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2358 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2359 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2360 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2361 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2362
2363 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2364 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2365 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2366 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2367 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2368 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2369
2370 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2371 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2372 host_pat = msr_low | ((u64) msr_high << 32);
2373 vmcs_write64(HOST_IA32_PAT, host_pat);
2374 }
2375 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2376 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2377 host_pat = msr_low | ((u64) msr_high << 32);
2378 /* Write the default value follow host pat */
2379 vmcs_write64(GUEST_IA32_PAT, host_pat);
2380 /* Keep arch.pat sync with GUEST_IA32_PAT */
2381 vmx->vcpu.arch.pat = host_pat;
2382 }
2383
2384 for (i = 0; i < NR_VMX_MSR; ++i) {
2385 u32 index = vmx_msr_index[i];
2386 u32 data_low, data_high;
2387 u64 data;
2388 int j = vmx->nmsrs;
2389
2390 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2391 continue;
2392 if (wrmsr_safe(index, data_low, data_high) < 0)
2393 continue;
2394 data = data_low | ((u64)data_high << 32);
2395 vmx->guest_msrs[j].index = i;
2396 vmx->guest_msrs[j].data = 0;
2397 vmx->guest_msrs[j].mask = -1ull;
2398 ++vmx->nmsrs;
2399 }
2400
2401 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2402
2403 /* 22.2.1, 20.8.1 */
2404 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2405
2406 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2407 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2408
2409 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2410 rdtscll(tsc_this);
2411 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2412 tsc_base = tsc_this;
2413
2414 guest_write_tsc(0, tsc_base);
2415
2416 return 0;
2417 }
2418
2419 static int init_rmode(struct kvm *kvm)
2420 {
2421 if (!init_rmode_tss(kvm))
2422 return 0;
2423 if (!init_rmode_identity_map(kvm))
2424 return 0;
2425 return 1;
2426 }
2427
2428 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2429 {
2430 struct vcpu_vmx *vmx = to_vmx(vcpu);
2431 u64 msr;
2432 int ret;
2433
2434 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2435 down_read(&vcpu->kvm->slots_lock);
2436 if (!init_rmode(vmx->vcpu.kvm)) {
2437 ret = -ENOMEM;
2438 goto out;
2439 }
2440
2441 vmx->rmode.vm86_active = 0;
2442
2443 vmx->soft_vnmi_blocked = 0;
2444
2445 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2446 kvm_set_cr8(&vmx->vcpu, 0);
2447 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2448 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2449 msr |= MSR_IA32_APICBASE_BSP;
2450 kvm_set_apic_base(&vmx->vcpu, msr);
2451
2452 fx_init(&vmx->vcpu);
2453
2454 seg_setup(VCPU_SREG_CS);
2455 /*
2456 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2457 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2458 */
2459 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2460 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2461 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2462 } else {
2463 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2464 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2465 }
2466
2467 seg_setup(VCPU_SREG_DS);
2468 seg_setup(VCPU_SREG_ES);
2469 seg_setup(VCPU_SREG_FS);
2470 seg_setup(VCPU_SREG_GS);
2471 seg_setup(VCPU_SREG_SS);
2472
2473 vmcs_write16(GUEST_TR_SELECTOR, 0);
2474 vmcs_writel(GUEST_TR_BASE, 0);
2475 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2476 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2477
2478 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2479 vmcs_writel(GUEST_LDTR_BASE, 0);
2480 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2481 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2482
2483 vmcs_write32(GUEST_SYSENTER_CS, 0);
2484 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2485 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2486
2487 vmcs_writel(GUEST_RFLAGS, 0x02);
2488 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2489 kvm_rip_write(vcpu, 0xfff0);
2490 else
2491 kvm_rip_write(vcpu, 0);
2492 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2493
2494 vmcs_writel(GUEST_DR7, 0x400);
2495
2496 vmcs_writel(GUEST_GDTR_BASE, 0);
2497 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2498
2499 vmcs_writel(GUEST_IDTR_BASE, 0);
2500 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2501
2502 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2503 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2504 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2505
2506 /* Special registers */
2507 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2508
2509 setup_msrs(vmx);
2510
2511 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2512
2513 if (cpu_has_vmx_tpr_shadow()) {
2514 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2515 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2516 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2517 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2518 vmcs_write32(TPR_THRESHOLD, 0);
2519 }
2520
2521 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2522 vmcs_write64(APIC_ACCESS_ADDR,
2523 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2524
2525 if (vmx->vpid != 0)
2526 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2527
2528 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2529 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2530 vmx_set_cr4(&vmx->vcpu, 0);
2531 vmx_set_efer(&vmx->vcpu, 0);
2532 vmx_fpu_activate(&vmx->vcpu);
2533 update_exception_bitmap(&vmx->vcpu);
2534
2535 vpid_sync_vcpu_all(vmx);
2536
2537 ret = 0;
2538
2539 /* HACK: Don't enable emulation on guest boot/reset */
2540 vmx->emulation_required = 0;
2541
2542 out:
2543 up_read(&vcpu->kvm->slots_lock);
2544 return ret;
2545 }
2546
2547 static void enable_irq_window(struct kvm_vcpu *vcpu)
2548 {
2549 u32 cpu_based_vm_exec_control;
2550
2551 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2552 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2553 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2554 }
2555
2556 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2557 {
2558 u32 cpu_based_vm_exec_control;
2559
2560 if (!cpu_has_virtual_nmis()) {
2561 enable_irq_window(vcpu);
2562 return;
2563 }
2564
2565 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2566 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2567 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2568 }
2569
2570 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2571 {
2572 struct vcpu_vmx *vmx = to_vmx(vcpu);
2573 uint32_t intr;
2574 int irq = vcpu->arch.interrupt.nr;
2575
2576 trace_kvm_inj_virq(irq);
2577
2578 ++vcpu->stat.irq_injections;
2579 if (vmx->rmode.vm86_active) {
2580 vmx->rmode.irq.pending = true;
2581 vmx->rmode.irq.vector = irq;
2582 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2583 if (vcpu->arch.interrupt.soft)
2584 vmx->rmode.irq.rip +=
2585 vmx->vcpu.arch.event_exit_inst_len;
2586 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2587 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2588 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2589 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2590 return;
2591 }
2592 intr = irq | INTR_INFO_VALID_MASK;
2593 if (vcpu->arch.interrupt.soft) {
2594 intr |= INTR_TYPE_SOFT_INTR;
2595 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2596 vmx->vcpu.arch.event_exit_inst_len);
2597 } else
2598 intr |= INTR_TYPE_EXT_INTR;
2599 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2600 }
2601
2602 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2603 {
2604 struct vcpu_vmx *vmx = to_vmx(vcpu);
2605
2606 if (!cpu_has_virtual_nmis()) {
2607 /*
2608 * Tracking the NMI-blocked state in software is built upon
2609 * finding the next open IRQ window. This, in turn, depends on
2610 * well-behaving guests: They have to keep IRQs disabled at
2611 * least as long as the NMI handler runs. Otherwise we may
2612 * cause NMI nesting, maybe breaking the guest. But as this is
2613 * highly unlikely, we can live with the residual risk.
2614 */
2615 vmx->soft_vnmi_blocked = 1;
2616 vmx->vnmi_blocked_time = 0;
2617 }
2618
2619 ++vcpu->stat.nmi_injections;
2620 if (vmx->rmode.vm86_active) {
2621 vmx->rmode.irq.pending = true;
2622 vmx->rmode.irq.vector = NMI_VECTOR;
2623 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2624 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2625 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2626 INTR_INFO_VALID_MASK);
2627 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2628 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2629 return;
2630 }
2631 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2632 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2633 }
2634
2635 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2636 {
2637 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2638 return 0;
2639
2640 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2641 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2642 GUEST_INTR_STATE_NMI));
2643 }
2644
2645 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2646 {
2647 if (!cpu_has_virtual_nmis())
2648 return to_vmx(vcpu)->soft_vnmi_blocked;
2649 else
2650 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2651 GUEST_INTR_STATE_NMI);
2652 }
2653
2654 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2655 {
2656 struct vcpu_vmx *vmx = to_vmx(vcpu);
2657
2658 if (!cpu_has_virtual_nmis()) {
2659 if (vmx->soft_vnmi_blocked != masked) {
2660 vmx->soft_vnmi_blocked = masked;
2661 vmx->vnmi_blocked_time = 0;
2662 }
2663 } else {
2664 if (masked)
2665 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2666 GUEST_INTR_STATE_NMI);
2667 else
2668 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2669 GUEST_INTR_STATE_NMI);
2670 }
2671 }
2672
2673 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2674 {
2675 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2676 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2677 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2678 }
2679
2680 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2681 {
2682 int ret;
2683 struct kvm_userspace_memory_region tss_mem = {
2684 .slot = TSS_PRIVATE_MEMSLOT,
2685 .guest_phys_addr = addr,
2686 .memory_size = PAGE_SIZE * 3,
2687 .flags = 0,
2688 };
2689
2690 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2691 if (ret)
2692 return ret;
2693 kvm->arch.tss_addr = addr;
2694 return 0;
2695 }
2696
2697 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2698 int vec, u32 err_code)
2699 {
2700 /*
2701 * Instruction with address size override prefix opcode 0x67
2702 * Cause the #SS fault with 0 error code in VM86 mode.
2703 */
2704 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2705 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2706 return 1;
2707 /*
2708 * Forward all other exceptions that are valid in real mode.
2709 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2710 * the required debugging infrastructure rework.
2711 */
2712 switch (vec) {
2713 case DB_VECTOR:
2714 if (vcpu->guest_debug &
2715 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2716 return 0;
2717 kvm_queue_exception(vcpu, vec);
2718 return 1;
2719 case BP_VECTOR:
2720 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2721 return 0;
2722 /* fall through */
2723 case DE_VECTOR:
2724 case OF_VECTOR:
2725 case BR_VECTOR:
2726 case UD_VECTOR:
2727 case DF_VECTOR:
2728 case SS_VECTOR:
2729 case GP_VECTOR:
2730 case MF_VECTOR:
2731 kvm_queue_exception(vcpu, vec);
2732 return 1;
2733 }
2734 return 0;
2735 }
2736
2737 /*
2738 * Trigger machine check on the host. We assume all the MSRs are already set up
2739 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2740 * We pass a fake environment to the machine check handler because we want
2741 * the guest to be always treated like user space, no matter what context
2742 * it used internally.
2743 */
2744 static void kvm_machine_check(void)
2745 {
2746 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2747 struct pt_regs regs = {
2748 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2749 .flags = X86_EFLAGS_IF,
2750 };
2751
2752 do_machine_check(&regs, 0);
2753 #endif
2754 }
2755
2756 static int handle_machine_check(struct kvm_vcpu *vcpu)
2757 {
2758 /* already handled by vcpu_run */
2759 return 1;
2760 }
2761
2762 static int handle_exception(struct kvm_vcpu *vcpu)
2763 {
2764 struct vcpu_vmx *vmx = to_vmx(vcpu);
2765 struct kvm_run *kvm_run = vcpu->run;
2766 u32 intr_info, ex_no, error_code;
2767 unsigned long cr2, rip, dr6;
2768 u32 vect_info;
2769 enum emulation_result er;
2770
2771 vect_info = vmx->idt_vectoring_info;
2772 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2773
2774 if (is_machine_check(intr_info))
2775 return handle_machine_check(vcpu);
2776
2777 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2778 !is_page_fault(intr_info)) {
2779 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2780 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2781 vcpu->run->internal.ndata = 2;
2782 vcpu->run->internal.data[0] = vect_info;
2783 vcpu->run->internal.data[1] = intr_info;
2784 return 0;
2785 }
2786
2787 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2788 return 1; /* already handled by vmx_vcpu_run() */
2789
2790 if (is_no_device(intr_info)) {
2791 vmx_fpu_activate(vcpu);
2792 return 1;
2793 }
2794
2795 if (is_invalid_opcode(intr_info)) {
2796 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2797 if (er != EMULATE_DONE)
2798 kvm_queue_exception(vcpu, UD_VECTOR);
2799 return 1;
2800 }
2801
2802 error_code = 0;
2803 rip = kvm_rip_read(vcpu);
2804 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2805 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2806 if (is_page_fault(intr_info)) {
2807 /* EPT won't cause page fault directly */
2808 if (enable_ept)
2809 BUG();
2810 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2811 trace_kvm_page_fault(cr2, error_code);
2812
2813 if (kvm_event_needs_reinjection(vcpu))
2814 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2815 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2816 }
2817
2818 if (vmx->rmode.vm86_active &&
2819 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2820 error_code)) {
2821 if (vcpu->arch.halt_request) {
2822 vcpu->arch.halt_request = 0;
2823 return kvm_emulate_halt(vcpu);
2824 }
2825 return 1;
2826 }
2827
2828 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2829 switch (ex_no) {
2830 case DB_VECTOR:
2831 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2832 if (!(vcpu->guest_debug &
2833 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2834 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2835 kvm_queue_exception(vcpu, DB_VECTOR);
2836 return 1;
2837 }
2838 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2839 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2840 /* fall through */
2841 case BP_VECTOR:
2842 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2843 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2844 kvm_run->debug.arch.exception = ex_no;
2845 break;
2846 default:
2847 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2848 kvm_run->ex.exception = ex_no;
2849 kvm_run->ex.error_code = error_code;
2850 break;
2851 }
2852 return 0;
2853 }
2854
2855 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2856 {
2857 ++vcpu->stat.irq_exits;
2858 return 1;
2859 }
2860
2861 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2862 {
2863 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2864 return 0;
2865 }
2866
2867 static int handle_io(struct kvm_vcpu *vcpu)
2868 {
2869 unsigned long exit_qualification;
2870 int size, in, string;
2871 unsigned port;
2872
2873 ++vcpu->stat.io_exits;
2874 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2875 string = (exit_qualification & 16) != 0;
2876
2877 if (string) {
2878 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO)
2879 return 0;
2880 return 1;
2881 }
2882
2883 size = (exit_qualification & 7) + 1;
2884 in = (exit_qualification & 8) != 0;
2885 port = exit_qualification >> 16;
2886
2887 skip_emulated_instruction(vcpu);
2888 return kvm_emulate_pio(vcpu, in, size, port);
2889 }
2890
2891 static void
2892 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2893 {
2894 /*
2895 * Patch in the VMCALL instruction:
2896 */
2897 hypercall[0] = 0x0f;
2898 hypercall[1] = 0x01;
2899 hypercall[2] = 0xc1;
2900 }
2901
2902 static int handle_cr(struct kvm_vcpu *vcpu)
2903 {
2904 unsigned long exit_qualification, val;
2905 int cr;
2906 int reg;
2907
2908 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2909 cr = exit_qualification & 15;
2910 reg = (exit_qualification >> 8) & 15;
2911 switch ((exit_qualification >> 4) & 3) {
2912 case 0: /* mov to cr */
2913 val = kvm_register_read(vcpu, reg);
2914 trace_kvm_cr_write(cr, val);
2915 switch (cr) {
2916 case 0:
2917 kvm_set_cr0(vcpu, val);
2918 skip_emulated_instruction(vcpu);
2919 return 1;
2920 case 3:
2921 kvm_set_cr3(vcpu, val);
2922 skip_emulated_instruction(vcpu);
2923 return 1;
2924 case 4:
2925 kvm_set_cr4(vcpu, val);
2926 skip_emulated_instruction(vcpu);
2927 return 1;
2928 case 8: {
2929 u8 cr8_prev = kvm_get_cr8(vcpu);
2930 u8 cr8 = kvm_register_read(vcpu, reg);
2931 kvm_set_cr8(vcpu, cr8);
2932 skip_emulated_instruction(vcpu);
2933 if (irqchip_in_kernel(vcpu->kvm))
2934 return 1;
2935 if (cr8_prev <= cr8)
2936 return 1;
2937 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2938 return 0;
2939 }
2940 };
2941 break;
2942 case 2: /* clts */
2943 vmx_fpu_deactivate(vcpu);
2944 vcpu->arch.cr0 &= ~X86_CR0_TS;
2945 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2946 vmx_fpu_activate(vcpu);
2947 skip_emulated_instruction(vcpu);
2948 return 1;
2949 case 1: /*mov from cr*/
2950 switch (cr) {
2951 case 3:
2952 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2953 trace_kvm_cr_read(cr, vcpu->arch.cr3);
2954 skip_emulated_instruction(vcpu);
2955 return 1;
2956 case 8:
2957 val = kvm_get_cr8(vcpu);
2958 kvm_register_write(vcpu, reg, val);
2959 trace_kvm_cr_read(cr, val);
2960 skip_emulated_instruction(vcpu);
2961 return 1;
2962 }
2963 break;
2964 case 3: /* lmsw */
2965 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2966
2967 skip_emulated_instruction(vcpu);
2968 return 1;
2969 default:
2970 break;
2971 }
2972 vcpu->run->exit_reason = 0;
2973 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2974 (int)(exit_qualification >> 4) & 3, cr);
2975 return 0;
2976 }
2977
2978 static int handle_dr(struct kvm_vcpu *vcpu)
2979 {
2980 unsigned long exit_qualification;
2981 unsigned long val;
2982 int dr, reg;
2983
2984 if (!kvm_require_cpl(vcpu, 0))
2985 return 1;
2986 dr = vmcs_readl(GUEST_DR7);
2987 if (dr & DR7_GD) {
2988 /*
2989 * As the vm-exit takes precedence over the debug trap, we
2990 * need to emulate the latter, either for the host or the
2991 * guest debugging itself.
2992 */
2993 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2994 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
2995 vcpu->run->debug.arch.dr7 = dr;
2996 vcpu->run->debug.arch.pc =
2997 vmcs_readl(GUEST_CS_BASE) +
2998 vmcs_readl(GUEST_RIP);
2999 vcpu->run->debug.arch.exception = DB_VECTOR;
3000 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3001 return 0;
3002 } else {
3003 vcpu->arch.dr7 &= ~DR7_GD;
3004 vcpu->arch.dr6 |= DR6_BD;
3005 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3006 kvm_queue_exception(vcpu, DB_VECTOR);
3007 return 1;
3008 }
3009 }
3010
3011 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3012 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3013 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3014 if (exit_qualification & TYPE_MOV_FROM_DR) {
3015 switch (dr) {
3016 case 0 ... 3:
3017 val = vcpu->arch.db[dr];
3018 break;
3019 case 6:
3020 val = vcpu->arch.dr6;
3021 break;
3022 case 7:
3023 val = vcpu->arch.dr7;
3024 break;
3025 default:
3026 val = 0;
3027 }
3028 kvm_register_write(vcpu, reg, val);
3029 } else {
3030 val = vcpu->arch.regs[reg];
3031 switch (dr) {
3032 case 0 ... 3:
3033 vcpu->arch.db[dr] = val;
3034 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
3035 vcpu->arch.eff_db[dr] = val;
3036 break;
3037 case 4 ... 5:
3038 if (vcpu->arch.cr4 & X86_CR4_DE)
3039 kvm_queue_exception(vcpu, UD_VECTOR);
3040 break;
3041 case 6:
3042 if (val & 0xffffffff00000000ULL) {
3043 kvm_queue_exception(vcpu, GP_VECTOR);
3044 break;
3045 }
3046 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
3047 break;
3048 case 7:
3049 if (val & 0xffffffff00000000ULL) {
3050 kvm_queue_exception(vcpu, GP_VECTOR);
3051 break;
3052 }
3053 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3054 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3055 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3056 vcpu->arch.switch_db_regs =
3057 (val & DR7_BP_EN_MASK);
3058 }
3059 break;
3060 }
3061 }
3062 skip_emulated_instruction(vcpu);
3063 return 1;
3064 }
3065
3066 static int handle_cpuid(struct kvm_vcpu *vcpu)
3067 {
3068 kvm_emulate_cpuid(vcpu);
3069 return 1;
3070 }
3071
3072 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3073 {
3074 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3075 u64 data;
3076
3077 if (vmx_get_msr(vcpu, ecx, &data)) {
3078 kvm_inject_gp(vcpu, 0);
3079 return 1;
3080 }
3081
3082 trace_kvm_msr_read(ecx, data);
3083
3084 /* FIXME: handling of bits 32:63 of rax, rdx */
3085 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3086 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3087 skip_emulated_instruction(vcpu);
3088 return 1;
3089 }
3090
3091 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3092 {
3093 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3094 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3095 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3096
3097 trace_kvm_msr_write(ecx, data);
3098
3099 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3100 kvm_inject_gp(vcpu, 0);
3101 return 1;
3102 }
3103
3104 skip_emulated_instruction(vcpu);
3105 return 1;
3106 }
3107
3108 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3109 {
3110 return 1;
3111 }
3112
3113 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3114 {
3115 u32 cpu_based_vm_exec_control;
3116
3117 /* clear pending irq */
3118 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3119 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3120 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3121
3122 ++vcpu->stat.irq_window_exits;
3123
3124 /*
3125 * If the user space waits to inject interrupts, exit as soon as
3126 * possible
3127 */
3128 if (!irqchip_in_kernel(vcpu->kvm) &&
3129 vcpu->run->request_interrupt_window &&
3130 !kvm_cpu_has_interrupt(vcpu)) {
3131 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3132 return 0;
3133 }
3134 return 1;
3135 }
3136
3137 static int handle_halt(struct kvm_vcpu *vcpu)
3138 {
3139 skip_emulated_instruction(vcpu);
3140 return kvm_emulate_halt(vcpu);
3141 }
3142
3143 static int handle_vmcall(struct kvm_vcpu *vcpu)
3144 {
3145 skip_emulated_instruction(vcpu);
3146 kvm_emulate_hypercall(vcpu);
3147 return 1;
3148 }
3149
3150 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3151 {
3152 kvm_queue_exception(vcpu, UD_VECTOR);
3153 return 1;
3154 }
3155
3156 static int handle_invlpg(struct kvm_vcpu *vcpu)
3157 {
3158 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3159
3160 kvm_mmu_invlpg(vcpu, exit_qualification);
3161 skip_emulated_instruction(vcpu);
3162 return 1;
3163 }
3164
3165 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3166 {
3167 skip_emulated_instruction(vcpu);
3168 /* TODO: Add support for VT-d/pass-through device */
3169 return 1;
3170 }
3171
3172 static int handle_apic_access(struct kvm_vcpu *vcpu)
3173 {
3174 unsigned long exit_qualification;
3175 enum emulation_result er;
3176 unsigned long offset;
3177
3178 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3179 offset = exit_qualification & 0xffful;
3180
3181 er = emulate_instruction(vcpu, 0, 0, 0);
3182
3183 if (er != EMULATE_DONE) {
3184 printk(KERN_ERR
3185 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3186 offset);
3187 return -ENOEXEC;
3188 }
3189 return 1;
3190 }
3191
3192 static int handle_task_switch(struct kvm_vcpu *vcpu)
3193 {
3194 struct vcpu_vmx *vmx = to_vmx(vcpu);
3195 unsigned long exit_qualification;
3196 u16 tss_selector;
3197 int reason, type, idt_v;
3198
3199 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3200 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3201
3202 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3203
3204 reason = (u32)exit_qualification >> 30;
3205 if (reason == TASK_SWITCH_GATE && idt_v) {
3206 switch (type) {
3207 case INTR_TYPE_NMI_INTR:
3208 vcpu->arch.nmi_injected = false;
3209 if (cpu_has_virtual_nmis())
3210 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3211 GUEST_INTR_STATE_NMI);
3212 break;
3213 case INTR_TYPE_EXT_INTR:
3214 case INTR_TYPE_SOFT_INTR:
3215 kvm_clear_interrupt_queue(vcpu);
3216 break;
3217 case INTR_TYPE_HARD_EXCEPTION:
3218 case INTR_TYPE_SOFT_EXCEPTION:
3219 kvm_clear_exception_queue(vcpu);
3220 break;
3221 default:
3222 break;
3223 }
3224 }
3225 tss_selector = exit_qualification;
3226
3227 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3228 type != INTR_TYPE_EXT_INTR &&
3229 type != INTR_TYPE_NMI_INTR))
3230 skip_emulated_instruction(vcpu);
3231
3232 if (!kvm_task_switch(vcpu, tss_selector, reason))
3233 return 0;
3234
3235 /* clear all local breakpoint enable flags */
3236 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3237
3238 /*
3239 * TODO: What about debug traps on tss switch?
3240 * Are we supposed to inject them and update dr6?
3241 */
3242
3243 return 1;
3244 }
3245
3246 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3247 {
3248 unsigned long exit_qualification;
3249 gpa_t gpa;
3250 int gla_validity;
3251
3252 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3253
3254 if (exit_qualification & (1 << 6)) {
3255 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3256 return -EINVAL;
3257 }
3258
3259 gla_validity = (exit_qualification >> 7) & 0x3;
3260 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3261 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3262 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3263 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3264 vmcs_readl(GUEST_LINEAR_ADDRESS));
3265 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3266 (long unsigned int)exit_qualification);
3267 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3268 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3269 return 0;
3270 }
3271
3272 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3273 trace_kvm_page_fault(gpa, exit_qualification);
3274 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3275 }
3276
3277 static u64 ept_rsvd_mask(u64 spte, int level)
3278 {
3279 int i;
3280 u64 mask = 0;
3281
3282 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3283 mask |= (1ULL << i);
3284
3285 if (level > 2)
3286 /* bits 7:3 reserved */
3287 mask |= 0xf8;
3288 else if (level == 2) {
3289 if (spte & (1ULL << 7))
3290 /* 2MB ref, bits 20:12 reserved */
3291 mask |= 0x1ff000;
3292 else
3293 /* bits 6:3 reserved */
3294 mask |= 0x78;
3295 }
3296
3297 return mask;
3298 }
3299
3300 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3301 int level)
3302 {
3303 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3304
3305 /* 010b (write-only) */
3306 WARN_ON((spte & 0x7) == 0x2);
3307
3308 /* 110b (write/execute) */
3309 WARN_ON((spte & 0x7) == 0x6);
3310
3311 /* 100b (execute-only) and value not supported by logical processor */
3312 if (!cpu_has_vmx_ept_execute_only())
3313 WARN_ON((spte & 0x7) == 0x4);
3314
3315 /* not 000b */
3316 if ((spte & 0x7)) {
3317 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3318
3319 if (rsvd_bits != 0) {
3320 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3321 __func__, rsvd_bits);
3322 WARN_ON(1);
3323 }
3324
3325 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3326 u64 ept_mem_type = (spte & 0x38) >> 3;
3327
3328 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3329 ept_mem_type == 7) {
3330 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3331 __func__, ept_mem_type);
3332 WARN_ON(1);
3333 }
3334 }
3335 }
3336 }
3337
3338 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3339 {
3340 u64 sptes[4];
3341 int nr_sptes, i;
3342 gpa_t gpa;
3343
3344 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3345
3346 printk(KERN_ERR "EPT: Misconfiguration.\n");
3347 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3348
3349 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3350
3351 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3352 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3353
3354 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3355 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3356
3357 return 0;
3358 }
3359
3360 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3361 {
3362 u32 cpu_based_vm_exec_control;
3363
3364 /* clear pending NMI */
3365 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3366 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3367 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3368 ++vcpu->stat.nmi_window_exits;
3369
3370 return 1;
3371 }
3372
3373 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3374 {
3375 struct vcpu_vmx *vmx = to_vmx(vcpu);
3376 enum emulation_result err = EMULATE_DONE;
3377 int ret = 1;
3378
3379 while (!guest_state_valid(vcpu)) {
3380 err = emulate_instruction(vcpu, 0, 0, 0);
3381
3382 if (err == EMULATE_DO_MMIO) {
3383 ret = 0;
3384 goto out;
3385 }
3386
3387 if (err != EMULATE_DONE) {
3388 kvm_report_emulation_failure(vcpu, "emulation failure");
3389 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3390 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3391 vcpu->run->internal.ndata = 0;
3392 ret = 0;
3393 goto out;
3394 }
3395
3396 if (signal_pending(current))
3397 goto out;
3398 if (need_resched())
3399 schedule();
3400 }
3401
3402 vmx->emulation_required = 0;
3403 out:
3404 return ret;
3405 }
3406
3407 /*
3408 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3409 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3410 */
3411 static int handle_pause(struct kvm_vcpu *vcpu)
3412 {
3413 skip_emulated_instruction(vcpu);
3414 kvm_vcpu_on_spin(vcpu);
3415
3416 return 1;
3417 }
3418
3419 /*
3420 * The exit handlers return 1 if the exit was handled fully and guest execution
3421 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3422 * to be done to userspace and return 0.
3423 */
3424 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3425 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3426 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3427 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3428 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3429 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3430 [EXIT_REASON_CR_ACCESS] = handle_cr,
3431 [EXIT_REASON_DR_ACCESS] = handle_dr,
3432 [EXIT_REASON_CPUID] = handle_cpuid,
3433 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3434 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3435 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3436 [EXIT_REASON_HLT] = handle_halt,
3437 [EXIT_REASON_INVLPG] = handle_invlpg,
3438 [EXIT_REASON_VMCALL] = handle_vmcall,
3439 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3440 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3441 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3442 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3443 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3444 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3445 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3446 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3447 [EXIT_REASON_VMON] = handle_vmx_insn,
3448 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3449 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3450 [EXIT_REASON_WBINVD] = handle_wbinvd,
3451 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3452 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3453 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3454 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3455 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3456 };
3457
3458 static const int kvm_vmx_max_exit_handlers =
3459 ARRAY_SIZE(kvm_vmx_exit_handlers);
3460
3461 /*
3462 * The guest has exited. See if we can fix it or if we need userspace
3463 * assistance.
3464 */
3465 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3466 {
3467 struct vcpu_vmx *vmx = to_vmx(vcpu);
3468 u32 exit_reason = vmx->exit_reason;
3469 u32 vectoring_info = vmx->idt_vectoring_info;
3470
3471 trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
3472
3473 /* If guest state is invalid, start emulating */
3474 if (vmx->emulation_required && emulate_invalid_guest_state)
3475 return handle_invalid_guest_state(vcpu);
3476
3477 /* Access CR3 don't cause VMExit in paging mode, so we need
3478 * to sync with guest real CR3. */
3479 if (enable_ept && is_paging(vcpu))
3480 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3481
3482 if (unlikely(vmx->fail)) {
3483 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3484 vcpu->run->fail_entry.hardware_entry_failure_reason
3485 = vmcs_read32(VM_INSTRUCTION_ERROR);
3486 return 0;
3487 }
3488
3489 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3490 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3491 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3492 exit_reason != EXIT_REASON_TASK_SWITCH))
3493 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3494 "(0x%x) and exit reason is 0x%x\n",
3495 __func__, vectoring_info, exit_reason);
3496
3497 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3498 if (vmx_interrupt_allowed(vcpu)) {
3499 vmx->soft_vnmi_blocked = 0;
3500 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3501 vcpu->arch.nmi_pending) {
3502 /*
3503 * This CPU don't support us in finding the end of an
3504 * NMI-blocked window if the guest runs with IRQs
3505 * disabled. So we pull the trigger after 1 s of
3506 * futile waiting, but inform the user about this.
3507 */
3508 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3509 "state on VCPU %d after 1 s timeout\n",
3510 __func__, vcpu->vcpu_id);
3511 vmx->soft_vnmi_blocked = 0;
3512 }
3513 }
3514
3515 if (exit_reason < kvm_vmx_max_exit_handlers
3516 && kvm_vmx_exit_handlers[exit_reason])
3517 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3518 else {
3519 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3520 vcpu->run->hw.hardware_exit_reason = exit_reason;
3521 }
3522 return 0;
3523 }
3524
3525 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3526 {
3527 if (irr == -1 || tpr < irr) {
3528 vmcs_write32(TPR_THRESHOLD, 0);
3529 return;
3530 }
3531
3532 vmcs_write32(TPR_THRESHOLD, irr);
3533 }
3534
3535 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3536 {
3537 u32 exit_intr_info;
3538 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3539 bool unblock_nmi;
3540 u8 vector;
3541 int type;
3542 bool idtv_info_valid;
3543
3544 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3545
3546 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3547
3548 /* Handle machine checks before interrupts are enabled */
3549 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3550 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3551 && is_machine_check(exit_intr_info)))
3552 kvm_machine_check();
3553
3554 /* We need to handle NMIs before interrupts are enabled */
3555 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3556 (exit_intr_info & INTR_INFO_VALID_MASK))
3557 asm("int $2");
3558
3559 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3560
3561 if (cpu_has_virtual_nmis()) {
3562 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3563 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3564 /*
3565 * SDM 3: 27.7.1.2 (September 2008)
3566 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3567 * a guest IRET fault.
3568 * SDM 3: 23.2.2 (September 2008)
3569 * Bit 12 is undefined in any of the following cases:
3570 * If the VM exit sets the valid bit in the IDT-vectoring
3571 * information field.
3572 * If the VM exit is due to a double fault.
3573 */
3574 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3575 vector != DF_VECTOR && !idtv_info_valid)
3576 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3577 GUEST_INTR_STATE_NMI);
3578 } else if (unlikely(vmx->soft_vnmi_blocked))
3579 vmx->vnmi_blocked_time +=
3580 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3581
3582 vmx->vcpu.arch.nmi_injected = false;
3583 kvm_clear_exception_queue(&vmx->vcpu);
3584 kvm_clear_interrupt_queue(&vmx->vcpu);
3585
3586 if (!idtv_info_valid)
3587 return;
3588
3589 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3590 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3591
3592 switch (type) {
3593 case INTR_TYPE_NMI_INTR:
3594 vmx->vcpu.arch.nmi_injected = true;
3595 /*
3596 * SDM 3: 27.7.1.2 (September 2008)
3597 * Clear bit "block by NMI" before VM entry if a NMI
3598 * delivery faulted.
3599 */
3600 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3601 GUEST_INTR_STATE_NMI);
3602 break;
3603 case INTR_TYPE_SOFT_EXCEPTION:
3604 vmx->vcpu.arch.event_exit_inst_len =
3605 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3606 /* fall through */
3607 case INTR_TYPE_HARD_EXCEPTION:
3608 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3609 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3610 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3611 } else
3612 kvm_queue_exception(&vmx->vcpu, vector);
3613 break;
3614 case INTR_TYPE_SOFT_INTR:
3615 vmx->vcpu.arch.event_exit_inst_len =
3616 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3617 /* fall through */
3618 case INTR_TYPE_EXT_INTR:
3619 kvm_queue_interrupt(&vmx->vcpu, vector,
3620 type == INTR_TYPE_SOFT_INTR);
3621 break;
3622 default:
3623 break;
3624 }
3625 }
3626
3627 /*
3628 * Failure to inject an interrupt should give us the information
3629 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3630 * when fetching the interrupt redirection bitmap in the real-mode
3631 * tss, this doesn't happen. So we do it ourselves.
3632 */
3633 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3634 {
3635 vmx->rmode.irq.pending = 0;
3636 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3637 return;
3638 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3639 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3640 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3641 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3642 return;
3643 }
3644 vmx->idt_vectoring_info =
3645 VECTORING_INFO_VALID_MASK
3646 | INTR_TYPE_EXT_INTR
3647 | vmx->rmode.irq.vector;
3648 }
3649
3650 #ifdef CONFIG_X86_64
3651 #define R "r"
3652 #define Q "q"
3653 #else
3654 #define R "e"
3655 #define Q "l"
3656 #endif
3657
3658 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3659 {
3660 struct vcpu_vmx *vmx = to_vmx(vcpu);
3661
3662 /* Record the guest's net vcpu time for enforced NMI injections. */
3663 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3664 vmx->entry_time = ktime_get();
3665
3666 /* Don't enter VMX if guest state is invalid, let the exit handler
3667 start emulation until we arrive back to a valid state */
3668 if (vmx->emulation_required && emulate_invalid_guest_state)
3669 return;
3670
3671 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3672 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3673 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3674 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3675
3676 /* When single-stepping over STI and MOV SS, we must clear the
3677 * corresponding interruptibility bits in the guest state. Otherwise
3678 * vmentry fails as it then expects bit 14 (BS) in pending debug
3679 * exceptions being set, but that's not correct for the guest debugging
3680 * case. */
3681 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3682 vmx_set_interrupt_shadow(vcpu, 0);
3683
3684 /*
3685 * Loading guest fpu may have cleared host cr0.ts
3686 */
3687 vmcs_writel(HOST_CR0, read_cr0());
3688
3689 if (vcpu->arch.switch_db_regs)
3690 set_debugreg(vcpu->arch.dr6, 6);
3691
3692 asm(
3693 /* Store host registers */
3694 "push %%"R"dx; push %%"R"bp;"
3695 "push %%"R"cx \n\t"
3696 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3697 "je 1f \n\t"
3698 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3699 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3700 "1: \n\t"
3701 /* Reload cr2 if changed */
3702 "mov %c[cr2](%0), %%"R"ax \n\t"
3703 "mov %%cr2, %%"R"dx \n\t"
3704 "cmp %%"R"ax, %%"R"dx \n\t"
3705 "je 2f \n\t"
3706 "mov %%"R"ax, %%cr2 \n\t"
3707 "2: \n\t"
3708 /* Check if vmlaunch of vmresume is needed */
3709 "cmpl $0, %c[launched](%0) \n\t"
3710 /* Load guest registers. Don't clobber flags. */
3711 "mov %c[rax](%0), %%"R"ax \n\t"
3712 "mov %c[rbx](%0), %%"R"bx \n\t"
3713 "mov %c[rdx](%0), %%"R"dx \n\t"
3714 "mov %c[rsi](%0), %%"R"si \n\t"
3715 "mov %c[rdi](%0), %%"R"di \n\t"
3716 "mov %c[rbp](%0), %%"R"bp \n\t"
3717 #ifdef CONFIG_X86_64
3718 "mov %c[r8](%0), %%r8 \n\t"
3719 "mov %c[r9](%0), %%r9 \n\t"
3720 "mov %c[r10](%0), %%r10 \n\t"
3721 "mov %c[r11](%0), %%r11 \n\t"
3722 "mov %c[r12](%0), %%r12 \n\t"
3723 "mov %c[r13](%0), %%r13 \n\t"
3724 "mov %c[r14](%0), %%r14 \n\t"
3725 "mov %c[r15](%0), %%r15 \n\t"
3726 #endif
3727 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3728
3729 /* Enter guest mode */
3730 "jne .Llaunched \n\t"
3731 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3732 "jmp .Lkvm_vmx_return \n\t"
3733 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3734 ".Lkvm_vmx_return: "
3735 /* Save guest registers, load host registers, keep flags */
3736 "xchg %0, (%%"R"sp) \n\t"
3737 "mov %%"R"ax, %c[rax](%0) \n\t"
3738 "mov %%"R"bx, %c[rbx](%0) \n\t"
3739 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3740 "mov %%"R"dx, %c[rdx](%0) \n\t"
3741 "mov %%"R"si, %c[rsi](%0) \n\t"
3742 "mov %%"R"di, %c[rdi](%0) \n\t"
3743 "mov %%"R"bp, %c[rbp](%0) \n\t"
3744 #ifdef CONFIG_X86_64
3745 "mov %%r8, %c[r8](%0) \n\t"
3746 "mov %%r9, %c[r9](%0) \n\t"
3747 "mov %%r10, %c[r10](%0) \n\t"
3748 "mov %%r11, %c[r11](%0) \n\t"
3749 "mov %%r12, %c[r12](%0) \n\t"
3750 "mov %%r13, %c[r13](%0) \n\t"
3751 "mov %%r14, %c[r14](%0) \n\t"
3752 "mov %%r15, %c[r15](%0) \n\t"
3753 #endif
3754 "mov %%cr2, %%"R"ax \n\t"
3755 "mov %%"R"ax, %c[cr2](%0) \n\t"
3756
3757 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3758 "setbe %c[fail](%0) \n\t"
3759 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3760 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3761 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3762 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3763 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3764 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3765 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3766 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3767 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3768 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3769 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3770 #ifdef CONFIG_X86_64
3771 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3772 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3773 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3774 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3775 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3776 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3777 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3778 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3779 #endif
3780 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3781 : "cc", "memory"
3782 , R"bx", R"di", R"si"
3783 #ifdef CONFIG_X86_64
3784 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3785 #endif
3786 );
3787
3788 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3789 | (1 << VCPU_EXREG_PDPTR));
3790 vcpu->arch.regs_dirty = 0;
3791
3792 if (vcpu->arch.switch_db_regs)
3793 get_debugreg(vcpu->arch.dr6, 6);
3794
3795 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3796 if (vmx->rmode.irq.pending)
3797 fixup_rmode_irq(vmx);
3798
3799 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3800 vmx->launched = 1;
3801
3802 vmx_complete_interrupts(vmx);
3803 }
3804
3805 #undef R
3806 #undef Q
3807
3808 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3809 {
3810 struct vcpu_vmx *vmx = to_vmx(vcpu);
3811
3812 if (vmx->vmcs) {
3813 vcpu_clear(vmx);
3814 free_vmcs(vmx->vmcs);
3815 vmx->vmcs = NULL;
3816 }
3817 }
3818
3819 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3820 {
3821 struct vcpu_vmx *vmx = to_vmx(vcpu);
3822
3823 spin_lock(&vmx_vpid_lock);
3824 if (vmx->vpid != 0)
3825 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3826 spin_unlock(&vmx_vpid_lock);
3827 vmx_free_vmcs(vcpu);
3828 kfree(vmx->guest_msrs);
3829 kvm_vcpu_uninit(vcpu);
3830 kmem_cache_free(kvm_vcpu_cache, vmx);
3831 }
3832
3833 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3834 {
3835 int err;
3836 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3837 int cpu;
3838
3839 if (!vmx)
3840 return ERR_PTR(-ENOMEM);
3841
3842 allocate_vpid(vmx);
3843
3844 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3845 if (err)
3846 goto free_vcpu;
3847
3848 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3849 if (!vmx->guest_msrs) {
3850 err = -ENOMEM;
3851 goto uninit_vcpu;
3852 }
3853
3854 vmx->vmcs = alloc_vmcs();
3855 if (!vmx->vmcs)
3856 goto free_msrs;
3857
3858 vmcs_clear(vmx->vmcs);
3859
3860 cpu = get_cpu();
3861 vmx_vcpu_load(&vmx->vcpu, cpu);
3862 err = vmx_vcpu_setup(vmx);
3863 vmx_vcpu_put(&vmx->vcpu);
3864 put_cpu();
3865 if (err)
3866 goto free_vmcs;
3867 if (vm_need_virtualize_apic_accesses(kvm))
3868 if (alloc_apic_access_page(kvm) != 0)
3869 goto free_vmcs;
3870
3871 if (enable_ept) {
3872 if (!kvm->arch.ept_identity_map_addr)
3873 kvm->arch.ept_identity_map_addr =
3874 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3875 if (alloc_identity_pagetable(kvm) != 0)
3876 goto free_vmcs;
3877 }
3878
3879 return &vmx->vcpu;
3880
3881 free_vmcs:
3882 free_vmcs(vmx->vmcs);
3883 free_msrs:
3884 kfree(vmx->guest_msrs);
3885 uninit_vcpu:
3886 kvm_vcpu_uninit(&vmx->vcpu);
3887 free_vcpu:
3888 kmem_cache_free(kvm_vcpu_cache, vmx);
3889 return ERR_PTR(err);
3890 }
3891
3892 static void __init vmx_check_processor_compat(void *rtn)
3893 {
3894 struct vmcs_config vmcs_conf;
3895
3896 *(int *)rtn = 0;
3897 if (setup_vmcs_config(&vmcs_conf) < 0)
3898 *(int *)rtn = -EIO;
3899 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3900 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3901 smp_processor_id());
3902 *(int *)rtn = -EIO;
3903 }
3904 }
3905
3906 static int get_ept_level(void)
3907 {
3908 return VMX_EPT_DEFAULT_GAW + 1;
3909 }
3910
3911 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3912 {
3913 u64 ret;
3914
3915 /* For VT-d and EPT combination
3916 * 1. MMIO: always map as UC
3917 * 2. EPT with VT-d:
3918 * a. VT-d without snooping control feature: can't guarantee the
3919 * result, try to trust guest.
3920 * b. VT-d with snooping control feature: snooping control feature of
3921 * VT-d engine can guarantee the cache correctness. Just set it
3922 * to WB to keep consistent with host. So the same as item 3.
3923 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3924 * consistent with host MTRR
3925 */
3926 if (is_mmio)
3927 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3928 else if (vcpu->kvm->arch.iommu_domain &&
3929 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3930 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3931 VMX_EPT_MT_EPTE_SHIFT;
3932 else
3933 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3934 | VMX_EPT_IGMT_BIT;
3935
3936 return ret;
3937 }
3938
3939 static const struct trace_print_flags vmx_exit_reasons_str[] = {
3940 { EXIT_REASON_EXCEPTION_NMI, "exception" },
3941 { EXIT_REASON_EXTERNAL_INTERRUPT, "ext_irq" },
3942 { EXIT_REASON_TRIPLE_FAULT, "triple_fault" },
3943 { EXIT_REASON_NMI_WINDOW, "nmi_window" },
3944 { EXIT_REASON_IO_INSTRUCTION, "io_instruction" },
3945 { EXIT_REASON_CR_ACCESS, "cr_access" },
3946 { EXIT_REASON_DR_ACCESS, "dr_access" },
3947 { EXIT_REASON_CPUID, "cpuid" },
3948 { EXIT_REASON_MSR_READ, "rdmsr" },
3949 { EXIT_REASON_MSR_WRITE, "wrmsr" },
3950 { EXIT_REASON_PENDING_INTERRUPT, "interrupt_window" },
3951 { EXIT_REASON_HLT, "halt" },
3952 { EXIT_REASON_INVLPG, "invlpg" },
3953 { EXIT_REASON_VMCALL, "hypercall" },
3954 { EXIT_REASON_TPR_BELOW_THRESHOLD, "tpr_below_thres" },
3955 { EXIT_REASON_APIC_ACCESS, "apic_access" },
3956 { EXIT_REASON_WBINVD, "wbinvd" },
3957 { EXIT_REASON_TASK_SWITCH, "task_switch" },
3958 { EXIT_REASON_EPT_VIOLATION, "ept_violation" },
3959 { -1, NULL }
3960 };
3961
3962 static bool vmx_gb_page_enable(void)
3963 {
3964 return false;
3965 }
3966
3967 static struct kvm_x86_ops vmx_x86_ops = {
3968 .cpu_has_kvm_support = cpu_has_kvm_support,
3969 .disabled_by_bios = vmx_disabled_by_bios,
3970 .hardware_setup = hardware_setup,
3971 .hardware_unsetup = hardware_unsetup,
3972 .check_processor_compatibility = vmx_check_processor_compat,
3973 .hardware_enable = hardware_enable,
3974 .hardware_disable = hardware_disable,
3975 .cpu_has_accelerated_tpr = report_flexpriority,
3976
3977 .vcpu_create = vmx_create_vcpu,
3978 .vcpu_free = vmx_free_vcpu,
3979 .vcpu_reset = vmx_vcpu_reset,
3980
3981 .prepare_guest_switch = vmx_save_host_state,
3982 .vcpu_load = vmx_vcpu_load,
3983 .vcpu_put = vmx_vcpu_put,
3984
3985 .set_guest_debug = set_guest_debug,
3986 .get_msr = vmx_get_msr,
3987 .set_msr = vmx_set_msr,
3988 .get_segment_base = vmx_get_segment_base,
3989 .get_segment = vmx_get_segment,
3990 .set_segment = vmx_set_segment,
3991 .get_cpl = vmx_get_cpl,
3992 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3993 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3994 .set_cr0 = vmx_set_cr0,
3995 .set_cr3 = vmx_set_cr3,
3996 .set_cr4 = vmx_set_cr4,
3997 .set_efer = vmx_set_efer,
3998 .get_idt = vmx_get_idt,
3999 .set_idt = vmx_set_idt,
4000 .get_gdt = vmx_get_gdt,
4001 .set_gdt = vmx_set_gdt,
4002 .cache_reg = vmx_cache_reg,
4003 .get_rflags = vmx_get_rflags,
4004 .set_rflags = vmx_set_rflags,
4005
4006 .tlb_flush = vmx_flush_tlb,
4007
4008 .run = vmx_vcpu_run,
4009 .handle_exit = vmx_handle_exit,
4010 .skip_emulated_instruction = skip_emulated_instruction,
4011 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4012 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4013 .patch_hypercall = vmx_patch_hypercall,
4014 .set_irq = vmx_inject_irq,
4015 .set_nmi = vmx_inject_nmi,
4016 .queue_exception = vmx_queue_exception,
4017 .interrupt_allowed = vmx_interrupt_allowed,
4018 .nmi_allowed = vmx_nmi_allowed,
4019 .get_nmi_mask = vmx_get_nmi_mask,
4020 .set_nmi_mask = vmx_set_nmi_mask,
4021 .enable_nmi_window = enable_nmi_window,
4022 .enable_irq_window = enable_irq_window,
4023 .update_cr8_intercept = update_cr8_intercept,
4024
4025 .set_tss_addr = vmx_set_tss_addr,
4026 .get_tdp_level = get_ept_level,
4027 .get_mt_mask = vmx_get_mt_mask,
4028
4029 .exit_reasons_str = vmx_exit_reasons_str,
4030 .gb_page_enable = vmx_gb_page_enable,
4031 };
4032
4033 static int __init vmx_init(void)
4034 {
4035 int r, i;
4036
4037 rdmsrl_safe(MSR_EFER, &host_efer);
4038
4039 for (i = 0; i < NR_VMX_MSR; ++i)
4040 kvm_define_shared_msr(i, vmx_msr_index[i]);
4041
4042 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4043 if (!vmx_io_bitmap_a)
4044 return -ENOMEM;
4045
4046 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4047 if (!vmx_io_bitmap_b) {
4048 r = -ENOMEM;
4049 goto out;
4050 }
4051
4052 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4053 if (!vmx_msr_bitmap_legacy) {
4054 r = -ENOMEM;
4055 goto out1;
4056 }
4057
4058 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4059 if (!vmx_msr_bitmap_longmode) {
4060 r = -ENOMEM;
4061 goto out2;
4062 }
4063
4064 /*
4065 * Allow direct access to the PC debug port (it is often used for I/O
4066 * delays, but the vmexits simply slow things down).
4067 */
4068 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4069 clear_bit(0x80, vmx_io_bitmap_a);
4070
4071 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4072
4073 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4074 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4075
4076 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4077
4078 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
4079 if (r)
4080 goto out3;
4081
4082 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4083 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4084 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4085 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4086 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4087 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4088
4089 if (enable_ept) {
4090 bypass_guest_pf = 0;
4091 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4092 VMX_EPT_WRITABLE_MASK);
4093 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4094 VMX_EPT_EXECUTABLE_MASK);
4095 kvm_enable_tdp();
4096 } else
4097 kvm_disable_tdp();
4098
4099 if (bypass_guest_pf)
4100 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4101
4102 return 0;
4103
4104 out3:
4105 free_page((unsigned long)vmx_msr_bitmap_longmode);
4106 out2:
4107 free_page((unsigned long)vmx_msr_bitmap_legacy);
4108 out1:
4109 free_page((unsigned long)vmx_io_bitmap_b);
4110 out:
4111 free_page((unsigned long)vmx_io_bitmap_a);
4112 return r;
4113 }
4114
4115 static void __exit vmx_exit(void)
4116 {
4117 free_page((unsigned long)vmx_msr_bitmap_legacy);
4118 free_page((unsigned long)vmx_msr_bitmap_longmode);
4119 free_page((unsigned long)vmx_io_bitmap_b);
4120 free_page((unsigned long)vmx_io_bitmap_a);
4121
4122 kvm_exit();
4123 }
4124
4125 module_init(vmx_init)
4126 module_exit(vmx_exit)
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