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KVM: VMX: When emulating on invalid vmx state, don't return to userspace unnecessarily
[linux-2.6/linux-2.6-openrd.git] / arch / x86 / kvm / vmx.c
blobdf454de8acfa2af8bf35fa96446ed300331cf6ba
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
40
41 static int bypass_guest_pf = 1;
42 module_param(bypass_guest_pf, bool, 0);
43
44 static int enable_vpid = 1;
45 module_param(enable_vpid, bool, 0);
46
47 static int flexpriority_enabled = 1;
48 module_param(flexpriority_enabled, bool, 0);
49
50 static int enable_ept = 1;
51 module_param(enable_ept, bool, 0);
52
53 static int emulate_invalid_guest_state = 0;
54 module_param(emulate_invalid_guest_state, bool, 0);
55
56 struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60 };
61
62 struct vcpu_vmx {
63 struct kvm_vcpu vcpu;
64 struct list_head local_vcpus_link;
65 unsigned long host_rsp;
66 int launched;
67 u8 fail;
68 u32 idt_vectoring_info;
69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74 #ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76 #endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
83 int guest_efer_loaded;
84 } host_state;
85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
92 int vpid;
93 bool emulation_required;
94 enum emulation_result invalid_state_emulation_result;
95
96 /* Support for vnmi-less CPUs */
97 int soft_vnmi_blocked;
98 ktime_t entry_time;
99 s64 vnmi_blocked_time;
100 };
101
102 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
103 {
104 return container_of(vcpu, struct vcpu_vmx, vcpu);
105 }
106
107 static int init_rmode(struct kvm *kvm);
108 static u64 construct_eptp(unsigned long root_hpa);
109
110 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
111 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
112 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
113
114 static struct page *vmx_io_bitmap_a;
115 static struct page *vmx_io_bitmap_b;
116 static struct page *vmx_msr_bitmap;
117
118 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
119 static DEFINE_SPINLOCK(vmx_vpid_lock);
120
121 static struct vmcs_config {
122 int size;
123 int order;
124 u32 revision_id;
125 u32 pin_based_exec_ctrl;
126 u32 cpu_based_exec_ctrl;
127 u32 cpu_based_2nd_exec_ctrl;
128 u32 vmexit_ctrl;
129 u32 vmentry_ctrl;
130 } vmcs_config;
131
132 static struct vmx_capability {
133 u32 ept;
134 u32 vpid;
135 } vmx_capability;
136
137 #define VMX_SEGMENT_FIELD(seg) \
138 [VCPU_SREG_##seg] = { \
139 .selector = GUEST_##seg##_SELECTOR, \
140 .base = GUEST_##seg##_BASE, \
141 .limit = GUEST_##seg##_LIMIT, \
142 .ar_bytes = GUEST_##seg##_AR_BYTES, \
143 }
144
145 static struct kvm_vmx_segment_field {
146 unsigned selector;
147 unsigned base;
148 unsigned limit;
149 unsigned ar_bytes;
150 } kvm_vmx_segment_fields[] = {
151 VMX_SEGMENT_FIELD(CS),
152 VMX_SEGMENT_FIELD(DS),
153 VMX_SEGMENT_FIELD(ES),
154 VMX_SEGMENT_FIELD(FS),
155 VMX_SEGMENT_FIELD(GS),
156 VMX_SEGMENT_FIELD(SS),
157 VMX_SEGMENT_FIELD(TR),
158 VMX_SEGMENT_FIELD(LDTR),
159 };
160
161 /*
162 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
163 * away by decrementing the array size.
164 */
165 static const u32 vmx_msr_index[] = {
166 #ifdef CONFIG_X86_64
167 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
168 #endif
169 MSR_EFER, MSR_K6_STAR,
170 };
171 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
172
173 static void load_msrs(struct kvm_msr_entry *e, int n)
174 {
175 int i;
176
177 for (i = 0; i < n; ++i)
178 wrmsrl(e[i].index, e[i].data);
179 }
180
181 static void save_msrs(struct kvm_msr_entry *e, int n)
182 {
183 int i;
184
185 for (i = 0; i < n; ++i)
186 rdmsrl(e[i].index, e[i].data);
187 }
188
189 static inline int is_page_fault(u32 intr_info)
190 {
191 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
192 INTR_INFO_VALID_MASK)) ==
193 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
194 }
195
196 static inline int is_no_device(u32 intr_info)
197 {
198 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
199 INTR_INFO_VALID_MASK)) ==
200 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
201 }
202
203 static inline int is_invalid_opcode(u32 intr_info)
204 {
205 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
206 INTR_INFO_VALID_MASK)) ==
207 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
208 }
209
210 static inline int is_external_interrupt(u32 intr_info)
211 {
212 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
213 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
214 }
215
216 static inline int cpu_has_vmx_msr_bitmap(void)
217 {
218 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
219 }
220
221 static inline int cpu_has_vmx_tpr_shadow(void)
222 {
223 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
224 }
225
226 static inline int vm_need_tpr_shadow(struct kvm *kvm)
227 {
228 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
229 }
230
231 static inline int cpu_has_secondary_exec_ctrls(void)
232 {
233 return (vmcs_config.cpu_based_exec_ctrl &
234 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
235 }
236
237 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
238 {
239 return flexpriority_enabled
240 && (vmcs_config.cpu_based_2nd_exec_ctrl &
241 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
242 }
243
244 static inline int cpu_has_vmx_invept_individual_addr(void)
245 {
246 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
247 }
248
249 static inline int cpu_has_vmx_invept_context(void)
250 {
251 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
252 }
253
254 static inline int cpu_has_vmx_invept_global(void)
255 {
256 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
257 }
258
259 static inline int cpu_has_vmx_ept(void)
260 {
261 return (vmcs_config.cpu_based_2nd_exec_ctrl &
262 SECONDARY_EXEC_ENABLE_EPT);
263 }
264
265 static inline int vm_need_ept(void)
266 {
267 return (cpu_has_vmx_ept() && enable_ept);
268 }
269
270 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
271 {
272 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
273 (irqchip_in_kernel(kvm)));
274 }
275
276 static inline int cpu_has_vmx_vpid(void)
277 {
278 return (vmcs_config.cpu_based_2nd_exec_ctrl &
279 SECONDARY_EXEC_ENABLE_VPID);
280 }
281
282 static inline int cpu_has_virtual_nmis(void)
283 {
284 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
285 }
286
287 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
288 {
289 int i;
290
291 for (i = 0; i < vmx->nmsrs; ++i)
292 if (vmx->guest_msrs[i].index == msr)
293 return i;
294 return -1;
295 }
296
297 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
298 {
299 struct {
300 u64 vpid : 16;
301 u64 rsvd : 48;
302 u64 gva;
303 } operand = { vpid, 0, gva };
304
305 asm volatile (__ex(ASM_VMX_INVVPID)
306 /* CF==1 or ZF==1 --> rc = -1 */
307 "; ja 1f ; ud2 ; 1:"
308 : : "a"(&operand), "c"(ext) : "cc", "memory");
309 }
310
311 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
312 {
313 struct {
314 u64 eptp, gpa;
315 } operand = {eptp, gpa};
316
317 asm volatile (__ex(ASM_VMX_INVEPT)
318 /* CF==1 or ZF==1 --> rc = -1 */
319 "; ja 1f ; ud2 ; 1:\n"
320 : : "a" (&operand), "c" (ext) : "cc", "memory");
321 }
322
323 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
324 {
325 int i;
326
327 i = __find_msr_index(vmx, msr);
328 if (i >= 0)
329 return &vmx->guest_msrs[i];
330 return NULL;
331 }
332
333 static void vmcs_clear(struct vmcs *vmcs)
334 {
335 u64 phys_addr = __pa(vmcs);
336 u8 error;
337
338 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
339 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
340 : "cc", "memory");
341 if (error)
342 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
343 vmcs, phys_addr);
344 }
345
346 static void __vcpu_clear(void *arg)
347 {
348 struct vcpu_vmx *vmx = arg;
349 int cpu = raw_smp_processor_id();
350
351 if (vmx->vcpu.cpu == cpu)
352 vmcs_clear(vmx->vmcs);
353 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
354 per_cpu(current_vmcs, cpu) = NULL;
355 rdtscll(vmx->vcpu.arch.host_tsc);
356 list_del(&vmx->local_vcpus_link);
357 vmx->vcpu.cpu = -1;
358 vmx->launched = 0;
359 }
360
361 static void vcpu_clear(struct vcpu_vmx *vmx)
362 {
363 if (vmx->vcpu.cpu == -1)
364 return;
365 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
366 }
367
368 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
369 {
370 if (vmx->vpid == 0)
371 return;
372
373 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
374 }
375
376 static inline void ept_sync_global(void)
377 {
378 if (cpu_has_vmx_invept_global())
379 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
380 }
381
382 static inline void ept_sync_context(u64 eptp)
383 {
384 if (vm_need_ept()) {
385 if (cpu_has_vmx_invept_context())
386 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
387 else
388 ept_sync_global();
389 }
390 }
391
392 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
393 {
394 if (vm_need_ept()) {
395 if (cpu_has_vmx_invept_individual_addr())
396 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
397 eptp, gpa);
398 else
399 ept_sync_context(eptp);
400 }
401 }
402
403 static unsigned long vmcs_readl(unsigned long field)
404 {
405 unsigned long value;
406
407 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
408 : "=a"(value) : "d"(field) : "cc");
409 return value;
410 }
411
412 static u16 vmcs_read16(unsigned long field)
413 {
414 return vmcs_readl(field);
415 }
416
417 static u32 vmcs_read32(unsigned long field)
418 {
419 return vmcs_readl(field);
420 }
421
422 static u64 vmcs_read64(unsigned long field)
423 {
424 #ifdef CONFIG_X86_64
425 return vmcs_readl(field);
426 #else
427 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
428 #endif
429 }
430
431 static noinline void vmwrite_error(unsigned long field, unsigned long value)
432 {
433 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
434 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
435 dump_stack();
436 }
437
438 static void vmcs_writel(unsigned long field, unsigned long value)
439 {
440 u8 error;
441
442 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
443 : "=q"(error) : "a"(value), "d"(field) : "cc");
444 if (unlikely(error))
445 vmwrite_error(field, value);
446 }
447
448 static void vmcs_write16(unsigned long field, u16 value)
449 {
450 vmcs_writel(field, value);
451 }
452
453 static void vmcs_write32(unsigned long field, u32 value)
454 {
455 vmcs_writel(field, value);
456 }
457
458 static void vmcs_write64(unsigned long field, u64 value)
459 {
460 vmcs_writel(field, value);
461 #ifndef CONFIG_X86_64
462 asm volatile ("");
463 vmcs_writel(field+1, value >> 32);
464 #endif
465 }
466
467 static void vmcs_clear_bits(unsigned long field, u32 mask)
468 {
469 vmcs_writel(field, vmcs_readl(field) & ~mask);
470 }
471
472 static void vmcs_set_bits(unsigned long field, u32 mask)
473 {
474 vmcs_writel(field, vmcs_readl(field) | mask);
475 }
476
477 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
478 {
479 u32 eb;
480
481 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
482 if (!vcpu->fpu_active)
483 eb |= 1u << NM_VECTOR;
484 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
485 if (vcpu->guest_debug &
486 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
487 eb |= 1u << DB_VECTOR;
488 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
489 eb |= 1u << BP_VECTOR;
490 }
491 if (vcpu->arch.rmode.active)
492 eb = ~0;
493 if (vm_need_ept())
494 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
495 vmcs_write32(EXCEPTION_BITMAP, eb);
496 }
497
498 static void reload_tss(void)
499 {
500 /*
501 * VT restores TR but not its size. Useless.
502 */
503 struct descriptor_table gdt;
504 struct desc_struct *descs;
505
506 kvm_get_gdt(&gdt);
507 descs = (void *)gdt.base;
508 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
509 load_TR_desc();
510 }
511
512 static void load_transition_efer(struct vcpu_vmx *vmx)
513 {
514 int efer_offset = vmx->msr_offset_efer;
515 u64 host_efer = vmx->host_msrs[efer_offset].data;
516 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
517 u64 ignore_bits;
518
519 if (efer_offset < 0)
520 return;
521 /*
522 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
523 * outside long mode
524 */
525 ignore_bits = EFER_NX | EFER_SCE;
526 #ifdef CONFIG_X86_64
527 ignore_bits |= EFER_LMA | EFER_LME;
528 /* SCE is meaningful only in long mode on Intel */
529 if (guest_efer & EFER_LMA)
530 ignore_bits &= ~(u64)EFER_SCE;
531 #endif
532 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
533 return;
534
535 vmx->host_state.guest_efer_loaded = 1;
536 guest_efer &= ~ignore_bits;
537 guest_efer |= host_efer & ignore_bits;
538 wrmsrl(MSR_EFER, guest_efer);
539 vmx->vcpu.stat.efer_reload++;
540 }
541
542 static void reload_host_efer(struct vcpu_vmx *vmx)
543 {
544 if (vmx->host_state.guest_efer_loaded) {
545 vmx->host_state.guest_efer_loaded = 0;
546 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
547 }
548 }
549
550 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
551 {
552 struct vcpu_vmx *vmx = to_vmx(vcpu);
553
554 if (vmx->host_state.loaded)
555 return;
556
557 vmx->host_state.loaded = 1;
558 /*
559 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
560 * allow segment selectors with cpl > 0 or ti == 1.
561 */
562 vmx->host_state.ldt_sel = kvm_read_ldt();
563 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
564 vmx->host_state.fs_sel = kvm_read_fs();
565 if (!(vmx->host_state.fs_sel & 7)) {
566 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
567 vmx->host_state.fs_reload_needed = 0;
568 } else {
569 vmcs_write16(HOST_FS_SELECTOR, 0);
570 vmx->host_state.fs_reload_needed = 1;
571 }
572 vmx->host_state.gs_sel = kvm_read_gs();
573 if (!(vmx->host_state.gs_sel & 7))
574 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
575 else {
576 vmcs_write16(HOST_GS_SELECTOR, 0);
577 vmx->host_state.gs_ldt_reload_needed = 1;
578 }
579
580 #ifdef CONFIG_X86_64
581 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
582 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
583 #else
584 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
585 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
586 #endif
587
588 #ifdef CONFIG_X86_64
589 if (is_long_mode(&vmx->vcpu))
590 save_msrs(vmx->host_msrs +
591 vmx->msr_offset_kernel_gs_base, 1);
592
593 #endif
594 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
595 load_transition_efer(vmx);
596 }
597
598 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
599 {
600 unsigned long flags;
601
602 if (!vmx->host_state.loaded)
603 return;
604
605 ++vmx->vcpu.stat.host_state_reload;
606 vmx->host_state.loaded = 0;
607 if (vmx->host_state.fs_reload_needed)
608 kvm_load_fs(vmx->host_state.fs_sel);
609 if (vmx->host_state.gs_ldt_reload_needed) {
610 kvm_load_ldt(vmx->host_state.ldt_sel);
611 /*
612 * If we have to reload gs, we must take care to
613 * preserve our gs base.
614 */
615 local_irq_save(flags);
616 kvm_load_gs(vmx->host_state.gs_sel);
617 #ifdef CONFIG_X86_64
618 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
619 #endif
620 local_irq_restore(flags);
621 }
622 reload_tss();
623 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
624 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
625 reload_host_efer(vmx);
626 }
627
628 static void vmx_load_host_state(struct vcpu_vmx *vmx)
629 {
630 preempt_disable();
631 __vmx_load_host_state(vmx);
632 preempt_enable();
633 }
634
635 /*
636 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
637 * vcpu mutex is already taken.
638 */
639 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
640 {
641 struct vcpu_vmx *vmx = to_vmx(vcpu);
642 u64 phys_addr = __pa(vmx->vmcs);
643 u64 tsc_this, delta, new_offset;
644
645 if (vcpu->cpu != cpu) {
646 vcpu_clear(vmx);
647 kvm_migrate_timers(vcpu);
648 vpid_sync_vcpu_all(vmx);
649 local_irq_disable();
650 list_add(&vmx->local_vcpus_link,
651 &per_cpu(vcpus_on_cpu, cpu));
652 local_irq_enable();
653 }
654
655 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
656 u8 error;
657
658 per_cpu(current_vmcs, cpu) = vmx->vmcs;
659 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
660 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
661 : "cc");
662 if (error)
663 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
664 vmx->vmcs, phys_addr);
665 }
666
667 if (vcpu->cpu != cpu) {
668 struct descriptor_table dt;
669 unsigned long sysenter_esp;
670
671 vcpu->cpu = cpu;
672 /*
673 * Linux uses per-cpu TSS and GDT, so set these when switching
674 * processors.
675 */
676 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
677 kvm_get_gdt(&dt);
678 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
679
680 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
681 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
682
683 /*
684 * Make sure the time stamp counter is monotonous.
685 */
686 rdtscll(tsc_this);
687 if (tsc_this < vcpu->arch.host_tsc) {
688 delta = vcpu->arch.host_tsc - tsc_this;
689 new_offset = vmcs_read64(TSC_OFFSET) + delta;
690 vmcs_write64(TSC_OFFSET, new_offset);
691 }
692 }
693 }
694
695 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
696 {
697 __vmx_load_host_state(to_vmx(vcpu));
698 }
699
700 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
701 {
702 if (vcpu->fpu_active)
703 return;
704 vcpu->fpu_active = 1;
705 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
706 if (vcpu->arch.cr0 & X86_CR0_TS)
707 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
708 update_exception_bitmap(vcpu);
709 }
710
711 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
712 {
713 if (!vcpu->fpu_active)
714 return;
715 vcpu->fpu_active = 0;
716 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
717 update_exception_bitmap(vcpu);
718 }
719
720 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
721 {
722 return vmcs_readl(GUEST_RFLAGS);
723 }
724
725 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
726 {
727 if (vcpu->arch.rmode.active)
728 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
729 vmcs_writel(GUEST_RFLAGS, rflags);
730 }
731
732 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
733 {
734 unsigned long rip;
735 u32 interruptibility;
736
737 rip = kvm_rip_read(vcpu);
738 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
739 kvm_rip_write(vcpu, rip);
740
741 /*
742 * We emulated an instruction, so temporary interrupt blocking
743 * should be removed, if set.
744 */
745 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
746 if (interruptibility & 3)
747 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
748 interruptibility & ~3);
749 vcpu->arch.interrupt_window_open = 1;
750 }
751
752 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
753 bool has_error_code, u32 error_code)
754 {
755 struct vcpu_vmx *vmx = to_vmx(vcpu);
756 u32 intr_info = nr | INTR_INFO_VALID_MASK;
757
758 if (has_error_code) {
759 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
760 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
761 }
762
763 if (vcpu->arch.rmode.active) {
764 vmx->rmode.irq.pending = true;
765 vmx->rmode.irq.vector = nr;
766 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
767 if (nr == BP_VECTOR || nr == OF_VECTOR)
768 vmx->rmode.irq.rip++;
769 intr_info |= INTR_TYPE_SOFT_INTR;
770 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
771 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
772 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
773 return;
774 }
775
776 if (nr == BP_VECTOR || nr == OF_VECTOR) {
777 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
778 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
779 } else
780 intr_info |= INTR_TYPE_HARD_EXCEPTION;
781
782 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
783 }
784
785 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
786 {
787 return false;
788 }
789
790 /*
791 * Swap MSR entry in host/guest MSR entry array.
792 */
793 #ifdef CONFIG_X86_64
794 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
795 {
796 struct kvm_msr_entry tmp;
797
798 tmp = vmx->guest_msrs[to];
799 vmx->guest_msrs[to] = vmx->guest_msrs[from];
800 vmx->guest_msrs[from] = tmp;
801 tmp = vmx->host_msrs[to];
802 vmx->host_msrs[to] = vmx->host_msrs[from];
803 vmx->host_msrs[from] = tmp;
804 }
805 #endif
806
807 /*
808 * Set up the vmcs to automatically save and restore system
809 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
810 * mode, as fiddling with msrs is very expensive.
811 */
812 static void setup_msrs(struct vcpu_vmx *vmx)
813 {
814 int save_nmsrs;
815
816 vmx_load_host_state(vmx);
817 save_nmsrs = 0;
818 #ifdef CONFIG_X86_64
819 if (is_long_mode(&vmx->vcpu)) {
820 int index;
821
822 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
823 if (index >= 0)
824 move_msr_up(vmx, index, save_nmsrs++);
825 index = __find_msr_index(vmx, MSR_LSTAR);
826 if (index >= 0)
827 move_msr_up(vmx, index, save_nmsrs++);
828 index = __find_msr_index(vmx, MSR_CSTAR);
829 if (index >= 0)
830 move_msr_up(vmx, index, save_nmsrs++);
831 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
832 if (index >= 0)
833 move_msr_up(vmx, index, save_nmsrs++);
834 /*
835 * MSR_K6_STAR is only needed on long mode guests, and only
836 * if efer.sce is enabled.
837 */
838 index = __find_msr_index(vmx, MSR_K6_STAR);
839 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
840 move_msr_up(vmx, index, save_nmsrs++);
841 }
842 #endif
843 vmx->save_nmsrs = save_nmsrs;
844
845 #ifdef CONFIG_X86_64
846 vmx->msr_offset_kernel_gs_base =
847 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
848 #endif
849 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
850 }
851
852 /*
853 * reads and returns guest's timestamp counter "register"
854 * guest_tsc = host_tsc + tsc_offset -- 21.3
855 */
856 static u64 guest_read_tsc(void)
857 {
858 u64 host_tsc, tsc_offset;
859
860 rdtscll(host_tsc);
861 tsc_offset = vmcs_read64(TSC_OFFSET);
862 return host_tsc + tsc_offset;
863 }
864
865 /*
866 * writes 'guest_tsc' into guest's timestamp counter "register"
867 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
868 */
869 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
870 {
871 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
872 }
873
874 /*
875 * Reads an msr value (of 'msr_index') into 'pdata'.
876 * Returns 0 on success, non-0 otherwise.
877 * Assumes vcpu_load() was already called.
878 */
879 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
880 {
881 u64 data;
882 struct kvm_msr_entry *msr;
883
884 if (!pdata) {
885 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
886 return -EINVAL;
887 }
888
889 switch (msr_index) {
890 #ifdef CONFIG_X86_64
891 case MSR_FS_BASE:
892 data = vmcs_readl(GUEST_FS_BASE);
893 break;
894 case MSR_GS_BASE:
895 data = vmcs_readl(GUEST_GS_BASE);
896 break;
897 case MSR_EFER:
898 return kvm_get_msr_common(vcpu, msr_index, pdata);
899 #endif
900 case MSR_IA32_TIME_STAMP_COUNTER:
901 data = guest_read_tsc();
902 break;
903 case MSR_IA32_SYSENTER_CS:
904 data = vmcs_read32(GUEST_SYSENTER_CS);
905 break;
906 case MSR_IA32_SYSENTER_EIP:
907 data = vmcs_readl(GUEST_SYSENTER_EIP);
908 break;
909 case MSR_IA32_SYSENTER_ESP:
910 data = vmcs_readl(GUEST_SYSENTER_ESP);
911 break;
912 default:
913 vmx_load_host_state(to_vmx(vcpu));
914 msr = find_msr_entry(to_vmx(vcpu), msr_index);
915 if (msr) {
916 data = msr->data;
917 break;
918 }
919 return kvm_get_msr_common(vcpu, msr_index, pdata);
920 }
921
922 *pdata = data;
923 return 0;
924 }
925
926 /*
927 * Writes msr value into into the appropriate "register".
928 * Returns 0 on success, non-0 otherwise.
929 * Assumes vcpu_load() was already called.
930 */
931 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
932 {
933 struct vcpu_vmx *vmx = to_vmx(vcpu);
934 struct kvm_msr_entry *msr;
935 u64 host_tsc;
936 int ret = 0;
937
938 switch (msr_index) {
939 #ifdef CONFIG_X86_64
940 case MSR_EFER:
941 vmx_load_host_state(vmx);
942 ret = kvm_set_msr_common(vcpu, msr_index, data);
943 break;
944 case MSR_FS_BASE:
945 vmcs_writel(GUEST_FS_BASE, data);
946 break;
947 case MSR_GS_BASE:
948 vmcs_writel(GUEST_GS_BASE, data);
949 break;
950 #endif
951 case MSR_IA32_SYSENTER_CS:
952 vmcs_write32(GUEST_SYSENTER_CS, data);
953 break;
954 case MSR_IA32_SYSENTER_EIP:
955 vmcs_writel(GUEST_SYSENTER_EIP, data);
956 break;
957 case MSR_IA32_SYSENTER_ESP:
958 vmcs_writel(GUEST_SYSENTER_ESP, data);
959 break;
960 case MSR_IA32_TIME_STAMP_COUNTER:
961 rdtscll(host_tsc);
962 guest_write_tsc(data, host_tsc);
963 break;
964 case MSR_P6_PERFCTR0:
965 case MSR_P6_PERFCTR1:
966 case MSR_P6_EVNTSEL0:
967 case MSR_P6_EVNTSEL1:
968 /*
969 * Just discard all writes to the performance counters; this
970 * should keep both older linux and windows 64-bit guests
971 * happy
972 */
973 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
974
975 break;
976 case MSR_IA32_CR_PAT:
977 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
978 vmcs_write64(GUEST_IA32_PAT, data);
979 vcpu->arch.pat = data;
980 break;
981 }
982 /* Otherwise falls through to kvm_set_msr_common */
983 default:
984 vmx_load_host_state(vmx);
985 msr = find_msr_entry(vmx, msr_index);
986 if (msr) {
987 msr->data = data;
988 break;
989 }
990 ret = kvm_set_msr_common(vcpu, msr_index, data);
991 }
992
993 return ret;
994 }
995
996 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
997 {
998 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
999 switch (reg) {
1000 case VCPU_REGS_RSP:
1001 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1002 break;
1003 case VCPU_REGS_RIP:
1004 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1005 break;
1006 default:
1007 break;
1008 }
1009 }
1010
1011 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1012 {
1013 int old_debug = vcpu->guest_debug;
1014 unsigned long flags;
1015
1016 vcpu->guest_debug = dbg->control;
1017 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1018 vcpu->guest_debug = 0;
1019
1020 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1021 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1022 else
1023 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1024
1025 flags = vmcs_readl(GUEST_RFLAGS);
1026 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1027 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1028 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1029 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1030 vmcs_writel(GUEST_RFLAGS, flags);
1031
1032 update_exception_bitmap(vcpu);
1033
1034 return 0;
1035 }
1036
1037 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1038 {
1039 if (!vcpu->arch.interrupt.pending)
1040 return -1;
1041 return vcpu->arch.interrupt.nr;
1042 }
1043
1044 static __init int cpu_has_kvm_support(void)
1045 {
1046 return cpu_has_vmx();
1047 }
1048
1049 static __init int vmx_disabled_by_bios(void)
1050 {
1051 u64 msr;
1052
1053 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1054 return (msr & (FEATURE_CONTROL_LOCKED |
1055 FEATURE_CONTROL_VMXON_ENABLED))
1056 == FEATURE_CONTROL_LOCKED;
1057 /* locked but not enabled */
1058 }
1059
1060 static void hardware_enable(void *garbage)
1061 {
1062 int cpu = raw_smp_processor_id();
1063 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1064 u64 old;
1065
1066 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1067 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1068 if ((old & (FEATURE_CONTROL_LOCKED |
1069 FEATURE_CONTROL_VMXON_ENABLED))
1070 != (FEATURE_CONTROL_LOCKED |
1071 FEATURE_CONTROL_VMXON_ENABLED))
1072 /* enable and lock */
1073 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1074 FEATURE_CONTROL_LOCKED |
1075 FEATURE_CONTROL_VMXON_ENABLED);
1076 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1077 asm volatile (ASM_VMX_VMXON_RAX
1078 : : "a"(&phys_addr), "m"(phys_addr)
1079 : "memory", "cc");
1080 }
1081
1082 static void vmclear_local_vcpus(void)
1083 {
1084 int cpu = raw_smp_processor_id();
1085 struct vcpu_vmx *vmx, *n;
1086
1087 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1088 local_vcpus_link)
1089 __vcpu_clear(vmx);
1090 }
1091
1092
1093 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1094 * tricks.
1095 */
1096 static void kvm_cpu_vmxoff(void)
1097 {
1098 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1099 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1100 }
1101
1102 static void hardware_disable(void *garbage)
1103 {
1104 vmclear_local_vcpus();
1105 kvm_cpu_vmxoff();
1106 }
1107
1108 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1109 u32 msr, u32 *result)
1110 {
1111 u32 vmx_msr_low, vmx_msr_high;
1112 u32 ctl = ctl_min | ctl_opt;
1113
1114 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1115
1116 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1117 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1118
1119 /* Ensure minimum (required) set of control bits are supported. */
1120 if (ctl_min & ~ctl)
1121 return -EIO;
1122
1123 *result = ctl;
1124 return 0;
1125 }
1126
1127 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1128 {
1129 u32 vmx_msr_low, vmx_msr_high;
1130 u32 min, opt, min2, opt2;
1131 u32 _pin_based_exec_control = 0;
1132 u32 _cpu_based_exec_control = 0;
1133 u32 _cpu_based_2nd_exec_control = 0;
1134 u32 _vmexit_control = 0;
1135 u32 _vmentry_control = 0;
1136
1137 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1138 opt = PIN_BASED_VIRTUAL_NMIS;
1139 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1140 &_pin_based_exec_control) < 0)
1141 return -EIO;
1142
1143 min = CPU_BASED_HLT_EXITING |
1144 #ifdef CONFIG_X86_64
1145 CPU_BASED_CR8_LOAD_EXITING |
1146 CPU_BASED_CR8_STORE_EXITING |
1147 #endif
1148 CPU_BASED_CR3_LOAD_EXITING |
1149 CPU_BASED_CR3_STORE_EXITING |
1150 CPU_BASED_USE_IO_BITMAPS |
1151 CPU_BASED_MOV_DR_EXITING |
1152 CPU_BASED_USE_TSC_OFFSETING |
1153 CPU_BASED_INVLPG_EXITING;
1154 opt = CPU_BASED_TPR_SHADOW |
1155 CPU_BASED_USE_MSR_BITMAPS |
1156 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1157 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1158 &_cpu_based_exec_control) < 0)
1159 return -EIO;
1160 #ifdef CONFIG_X86_64
1161 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1162 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1163 ~CPU_BASED_CR8_STORE_EXITING;
1164 #endif
1165 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1166 min2 = 0;
1167 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1168 SECONDARY_EXEC_WBINVD_EXITING |
1169 SECONDARY_EXEC_ENABLE_VPID |
1170 SECONDARY_EXEC_ENABLE_EPT;
1171 if (adjust_vmx_controls(min2, opt2,
1172 MSR_IA32_VMX_PROCBASED_CTLS2,
1173 &_cpu_based_2nd_exec_control) < 0)
1174 return -EIO;
1175 }
1176 #ifndef CONFIG_X86_64
1177 if (!(_cpu_based_2nd_exec_control &
1178 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1179 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1180 #endif
1181 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1182 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1183 enabled */
1184 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1185 CPU_BASED_CR3_STORE_EXITING |
1186 CPU_BASED_INVLPG_EXITING);
1187 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1188 &_cpu_based_exec_control) < 0)
1189 return -EIO;
1190 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1191 vmx_capability.ept, vmx_capability.vpid);
1192 }
1193
1194 min = 0;
1195 #ifdef CONFIG_X86_64
1196 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1197 #endif
1198 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1199 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1200 &_vmexit_control) < 0)
1201 return -EIO;
1202
1203 min = 0;
1204 opt = VM_ENTRY_LOAD_IA32_PAT;
1205 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1206 &_vmentry_control) < 0)
1207 return -EIO;
1208
1209 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1210
1211 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1212 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1213 return -EIO;
1214
1215 #ifdef CONFIG_X86_64
1216 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1217 if (vmx_msr_high & (1u<<16))
1218 return -EIO;
1219 #endif
1220
1221 /* Require Write-Back (WB) memory type for VMCS accesses. */
1222 if (((vmx_msr_high >> 18) & 15) != 6)
1223 return -EIO;
1224
1225 vmcs_conf->size = vmx_msr_high & 0x1fff;
1226 vmcs_conf->order = get_order(vmcs_config.size);
1227 vmcs_conf->revision_id = vmx_msr_low;
1228
1229 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1230 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1231 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1232 vmcs_conf->vmexit_ctrl = _vmexit_control;
1233 vmcs_conf->vmentry_ctrl = _vmentry_control;
1234
1235 return 0;
1236 }
1237
1238 static struct vmcs *alloc_vmcs_cpu(int cpu)
1239 {
1240 int node = cpu_to_node(cpu);
1241 struct page *pages;
1242 struct vmcs *vmcs;
1243
1244 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1245 if (!pages)
1246 return NULL;
1247 vmcs = page_address(pages);
1248 memset(vmcs, 0, vmcs_config.size);
1249 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1250 return vmcs;
1251 }
1252
1253 static struct vmcs *alloc_vmcs(void)
1254 {
1255 return alloc_vmcs_cpu(raw_smp_processor_id());
1256 }
1257
1258 static void free_vmcs(struct vmcs *vmcs)
1259 {
1260 free_pages((unsigned long)vmcs, vmcs_config.order);
1261 }
1262
1263 static void free_kvm_area(void)
1264 {
1265 int cpu;
1266
1267 for_each_online_cpu(cpu)
1268 free_vmcs(per_cpu(vmxarea, cpu));
1269 }
1270
1271 static __init int alloc_kvm_area(void)
1272 {
1273 int cpu;
1274
1275 for_each_online_cpu(cpu) {
1276 struct vmcs *vmcs;
1277
1278 vmcs = alloc_vmcs_cpu(cpu);
1279 if (!vmcs) {
1280 free_kvm_area();
1281 return -ENOMEM;
1282 }
1283
1284 per_cpu(vmxarea, cpu) = vmcs;
1285 }
1286 return 0;
1287 }
1288
1289 static __init int hardware_setup(void)
1290 {
1291 if (setup_vmcs_config(&vmcs_config) < 0)
1292 return -EIO;
1293
1294 if (boot_cpu_has(X86_FEATURE_NX))
1295 kvm_enable_efer_bits(EFER_NX);
1296
1297 return alloc_kvm_area();
1298 }
1299
1300 static __exit void hardware_unsetup(void)
1301 {
1302 free_kvm_area();
1303 }
1304
1305 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1306 {
1307 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1308
1309 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1310 vmcs_write16(sf->selector, save->selector);
1311 vmcs_writel(sf->base, save->base);
1312 vmcs_write32(sf->limit, save->limit);
1313 vmcs_write32(sf->ar_bytes, save->ar);
1314 } else {
1315 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1316 << AR_DPL_SHIFT;
1317 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1318 }
1319 }
1320
1321 static void enter_pmode(struct kvm_vcpu *vcpu)
1322 {
1323 unsigned long flags;
1324 struct vcpu_vmx *vmx = to_vmx(vcpu);
1325
1326 vmx->emulation_required = 1;
1327 vcpu->arch.rmode.active = 0;
1328
1329 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1330 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1331 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1332
1333 flags = vmcs_readl(GUEST_RFLAGS);
1334 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1335 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1336 vmcs_writel(GUEST_RFLAGS, flags);
1337
1338 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1339 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1340
1341 update_exception_bitmap(vcpu);
1342
1343 if (emulate_invalid_guest_state)
1344 return;
1345
1346 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1347 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1348 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1349 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1350
1351 vmcs_write16(GUEST_SS_SELECTOR, 0);
1352 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1353
1354 vmcs_write16(GUEST_CS_SELECTOR,
1355 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1356 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1357 }
1358
1359 static gva_t rmode_tss_base(struct kvm *kvm)
1360 {
1361 if (!kvm->arch.tss_addr) {
1362 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1363 kvm->memslots[0].npages - 3;
1364 return base_gfn << PAGE_SHIFT;
1365 }
1366 return kvm->arch.tss_addr;
1367 }
1368
1369 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1370 {
1371 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1372
1373 save->selector = vmcs_read16(sf->selector);
1374 save->base = vmcs_readl(sf->base);
1375 save->limit = vmcs_read32(sf->limit);
1376 save->ar = vmcs_read32(sf->ar_bytes);
1377 vmcs_write16(sf->selector, save->base >> 4);
1378 vmcs_write32(sf->base, save->base & 0xfffff);
1379 vmcs_write32(sf->limit, 0xffff);
1380 vmcs_write32(sf->ar_bytes, 0xf3);
1381 }
1382
1383 static void enter_rmode(struct kvm_vcpu *vcpu)
1384 {
1385 unsigned long flags;
1386 struct vcpu_vmx *vmx = to_vmx(vcpu);
1387
1388 vmx->emulation_required = 1;
1389 vcpu->arch.rmode.active = 1;
1390
1391 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1392 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1393
1394 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1395 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1396
1397 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1398 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1399
1400 flags = vmcs_readl(GUEST_RFLAGS);
1401 vcpu->arch.rmode.save_iopl
1402 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1403
1404 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1405
1406 vmcs_writel(GUEST_RFLAGS, flags);
1407 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1408 update_exception_bitmap(vcpu);
1409
1410 if (emulate_invalid_guest_state)
1411 goto continue_rmode;
1412
1413 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1414 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1415 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1416
1417 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1418 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1419 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1420 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1421 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1422
1423 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1424 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1425 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1426 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1427
1428 continue_rmode:
1429 kvm_mmu_reset_context(vcpu);
1430 init_rmode(vcpu->kvm);
1431 }
1432
1433 #ifdef CONFIG_X86_64
1434
1435 static void enter_lmode(struct kvm_vcpu *vcpu)
1436 {
1437 u32 guest_tr_ar;
1438
1439 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1440 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1441 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1442 __func__);
1443 vmcs_write32(GUEST_TR_AR_BYTES,
1444 (guest_tr_ar & ~AR_TYPE_MASK)
1445 | AR_TYPE_BUSY_64_TSS);
1446 }
1447
1448 vcpu->arch.shadow_efer |= EFER_LMA;
1449
1450 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1451 vmcs_write32(VM_ENTRY_CONTROLS,
1452 vmcs_read32(VM_ENTRY_CONTROLS)
1453 | VM_ENTRY_IA32E_MODE);
1454 }
1455
1456 static void exit_lmode(struct kvm_vcpu *vcpu)
1457 {
1458 vcpu->arch.shadow_efer &= ~EFER_LMA;
1459
1460 vmcs_write32(VM_ENTRY_CONTROLS,
1461 vmcs_read32(VM_ENTRY_CONTROLS)
1462 & ~VM_ENTRY_IA32E_MODE);
1463 }
1464
1465 #endif
1466
1467 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1468 {
1469 vpid_sync_vcpu_all(to_vmx(vcpu));
1470 if (vm_need_ept())
1471 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1472 }
1473
1474 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1475 {
1476 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1477 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1478 }
1479
1480 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1481 {
1482 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1483 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1484 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1485 return;
1486 }
1487 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1488 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1489 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1490 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1491 }
1492 }
1493
1494 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1495
1496 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1497 unsigned long cr0,
1498 struct kvm_vcpu *vcpu)
1499 {
1500 if (!(cr0 & X86_CR0_PG)) {
1501 /* From paging/starting to nonpaging */
1502 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1503 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1504 (CPU_BASED_CR3_LOAD_EXITING |
1505 CPU_BASED_CR3_STORE_EXITING));
1506 vcpu->arch.cr0 = cr0;
1507 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1508 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1509 *hw_cr0 &= ~X86_CR0_WP;
1510 } else if (!is_paging(vcpu)) {
1511 /* From nonpaging to paging */
1512 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1513 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1514 ~(CPU_BASED_CR3_LOAD_EXITING |
1515 CPU_BASED_CR3_STORE_EXITING));
1516 vcpu->arch.cr0 = cr0;
1517 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1518 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1519 *hw_cr0 &= ~X86_CR0_WP;
1520 }
1521 }
1522
1523 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1524 struct kvm_vcpu *vcpu)
1525 {
1526 if (!is_paging(vcpu)) {
1527 *hw_cr4 &= ~X86_CR4_PAE;
1528 *hw_cr4 |= X86_CR4_PSE;
1529 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1530 *hw_cr4 &= ~X86_CR4_PAE;
1531 }
1532
1533 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1534 {
1535 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1536 KVM_VM_CR0_ALWAYS_ON;
1537
1538 vmx_fpu_deactivate(vcpu);
1539
1540 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1541 enter_pmode(vcpu);
1542
1543 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1544 enter_rmode(vcpu);
1545
1546 #ifdef CONFIG_X86_64
1547 if (vcpu->arch.shadow_efer & EFER_LME) {
1548 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1549 enter_lmode(vcpu);
1550 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1551 exit_lmode(vcpu);
1552 }
1553 #endif
1554
1555 if (vm_need_ept())
1556 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1557
1558 vmcs_writel(CR0_READ_SHADOW, cr0);
1559 vmcs_writel(GUEST_CR0, hw_cr0);
1560 vcpu->arch.cr0 = cr0;
1561
1562 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1563 vmx_fpu_activate(vcpu);
1564 }
1565
1566 static u64 construct_eptp(unsigned long root_hpa)
1567 {
1568 u64 eptp;
1569
1570 /* TODO write the value reading from MSR */
1571 eptp = VMX_EPT_DEFAULT_MT |
1572 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1573 eptp |= (root_hpa & PAGE_MASK);
1574
1575 return eptp;
1576 }
1577
1578 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1579 {
1580 unsigned long guest_cr3;
1581 u64 eptp;
1582
1583 guest_cr3 = cr3;
1584 if (vm_need_ept()) {
1585 eptp = construct_eptp(cr3);
1586 vmcs_write64(EPT_POINTER, eptp);
1587 ept_sync_context(eptp);
1588 ept_load_pdptrs(vcpu);
1589 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1590 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1591 }
1592
1593 vmx_flush_tlb(vcpu);
1594 vmcs_writel(GUEST_CR3, guest_cr3);
1595 if (vcpu->arch.cr0 & X86_CR0_PE)
1596 vmx_fpu_deactivate(vcpu);
1597 }
1598
1599 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1600 {
1601 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1602 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1603
1604 vcpu->arch.cr4 = cr4;
1605 if (vm_need_ept())
1606 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1607
1608 vmcs_writel(CR4_READ_SHADOW, cr4);
1609 vmcs_writel(GUEST_CR4, hw_cr4);
1610 }
1611
1612 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1613 {
1614 struct vcpu_vmx *vmx = to_vmx(vcpu);
1615 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1616
1617 vcpu->arch.shadow_efer = efer;
1618 if (!msr)
1619 return;
1620 if (efer & EFER_LMA) {
1621 vmcs_write32(VM_ENTRY_CONTROLS,
1622 vmcs_read32(VM_ENTRY_CONTROLS) |
1623 VM_ENTRY_IA32E_MODE);
1624 msr->data = efer;
1625
1626 } else {
1627 vmcs_write32(VM_ENTRY_CONTROLS,
1628 vmcs_read32(VM_ENTRY_CONTROLS) &
1629 ~VM_ENTRY_IA32E_MODE);
1630
1631 msr->data = efer & ~EFER_LME;
1632 }
1633 setup_msrs(vmx);
1634 }
1635
1636 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1637 {
1638 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1639
1640 return vmcs_readl(sf->base);
1641 }
1642
1643 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1644 struct kvm_segment *var, int seg)
1645 {
1646 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1647 u32 ar;
1648
1649 var->base = vmcs_readl(sf->base);
1650 var->limit = vmcs_read32(sf->limit);
1651 var->selector = vmcs_read16(sf->selector);
1652 ar = vmcs_read32(sf->ar_bytes);
1653 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1654 ar = 0;
1655 var->type = ar & 15;
1656 var->s = (ar >> 4) & 1;
1657 var->dpl = (ar >> 5) & 3;
1658 var->present = (ar >> 7) & 1;
1659 var->avl = (ar >> 12) & 1;
1660 var->l = (ar >> 13) & 1;
1661 var->db = (ar >> 14) & 1;
1662 var->g = (ar >> 15) & 1;
1663 var->unusable = (ar >> 16) & 1;
1664 }
1665
1666 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1667 {
1668 struct kvm_segment kvm_seg;
1669
1670 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1671 return 0;
1672
1673 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1674 return 3;
1675
1676 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1677 return kvm_seg.selector & 3;
1678 }
1679
1680 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1681 {
1682 u32 ar;
1683
1684 if (var->unusable)
1685 ar = 1 << 16;
1686 else {
1687 ar = var->type & 15;
1688 ar |= (var->s & 1) << 4;
1689 ar |= (var->dpl & 3) << 5;
1690 ar |= (var->present & 1) << 7;
1691 ar |= (var->avl & 1) << 12;
1692 ar |= (var->l & 1) << 13;
1693 ar |= (var->db & 1) << 14;
1694 ar |= (var->g & 1) << 15;
1695 }
1696 if (ar == 0) /* a 0 value means unusable */
1697 ar = AR_UNUSABLE_MASK;
1698
1699 return ar;
1700 }
1701
1702 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1703 struct kvm_segment *var, int seg)
1704 {
1705 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1706 u32 ar;
1707
1708 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1709 vcpu->arch.rmode.tr.selector = var->selector;
1710 vcpu->arch.rmode.tr.base = var->base;
1711 vcpu->arch.rmode.tr.limit = var->limit;
1712 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1713 return;
1714 }
1715 vmcs_writel(sf->base, var->base);
1716 vmcs_write32(sf->limit, var->limit);
1717 vmcs_write16(sf->selector, var->selector);
1718 if (vcpu->arch.rmode.active && var->s) {
1719 /*
1720 * Hack real-mode segments into vm86 compatibility.
1721 */
1722 if (var->base == 0xffff0000 && var->selector == 0xf000)
1723 vmcs_writel(sf->base, 0xf0000);
1724 ar = 0xf3;
1725 } else
1726 ar = vmx_segment_access_rights(var);
1727 vmcs_write32(sf->ar_bytes, ar);
1728 }
1729
1730 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1731 {
1732 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1733
1734 *db = (ar >> 14) & 1;
1735 *l = (ar >> 13) & 1;
1736 }
1737
1738 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1739 {
1740 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1741 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1742 }
1743
1744 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1745 {
1746 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1747 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1748 }
1749
1750 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1751 {
1752 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1753 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1754 }
1755
1756 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1757 {
1758 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1759 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1760 }
1761
1762 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1763 {
1764 struct kvm_segment var;
1765 u32 ar;
1766
1767 vmx_get_segment(vcpu, &var, seg);
1768 ar = vmx_segment_access_rights(&var);
1769
1770 if (var.base != (var.selector << 4))
1771 return false;
1772 if (var.limit != 0xffff)
1773 return false;
1774 if (ar != 0xf3)
1775 return false;
1776
1777 return true;
1778 }
1779
1780 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1781 {
1782 struct kvm_segment cs;
1783 unsigned int cs_rpl;
1784
1785 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1786 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1787
1788 if (cs.unusable)
1789 return false;
1790 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1791 return false;
1792 if (!cs.s)
1793 return false;
1794 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1795 if (cs.dpl > cs_rpl)
1796 return false;
1797 } else {
1798 if (cs.dpl != cs_rpl)
1799 return false;
1800 }
1801 if (!cs.present)
1802 return false;
1803
1804 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1805 return true;
1806 }
1807
1808 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1809 {
1810 struct kvm_segment ss;
1811 unsigned int ss_rpl;
1812
1813 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1814 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1815
1816 if (ss.unusable)
1817 return true;
1818 if (ss.type != 3 && ss.type != 7)
1819 return false;
1820 if (!ss.s)
1821 return false;
1822 if (ss.dpl != ss_rpl) /* DPL != RPL */
1823 return false;
1824 if (!ss.present)
1825 return false;
1826
1827 return true;
1828 }
1829
1830 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1831 {
1832 struct kvm_segment var;
1833 unsigned int rpl;
1834
1835 vmx_get_segment(vcpu, &var, seg);
1836 rpl = var.selector & SELECTOR_RPL_MASK;
1837
1838 if (var.unusable)
1839 return true;
1840 if (!var.s)
1841 return false;
1842 if (!var.present)
1843 return false;
1844 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1845 if (var.dpl < rpl) /* DPL < RPL */
1846 return false;
1847 }
1848
1849 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1850 * rights flags
1851 */
1852 return true;
1853 }
1854
1855 static bool tr_valid(struct kvm_vcpu *vcpu)
1856 {
1857 struct kvm_segment tr;
1858
1859 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1860
1861 if (tr.unusable)
1862 return false;
1863 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1864 return false;
1865 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1866 return false;
1867 if (!tr.present)
1868 return false;
1869
1870 return true;
1871 }
1872
1873 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1874 {
1875 struct kvm_segment ldtr;
1876
1877 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1878
1879 if (ldtr.unusable)
1880 return true;
1881 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1882 return false;
1883 if (ldtr.type != 2)
1884 return false;
1885 if (!ldtr.present)
1886 return false;
1887
1888 return true;
1889 }
1890
1891 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1892 {
1893 struct kvm_segment cs, ss;
1894
1895 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1896 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1897
1898 return ((cs.selector & SELECTOR_RPL_MASK) ==
1899 (ss.selector & SELECTOR_RPL_MASK));
1900 }
1901
1902 /*
1903 * Check if guest state is valid. Returns true if valid, false if
1904 * not.
1905 * We assume that registers are always usable
1906 */
1907 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1908 {
1909 /* real mode guest state checks */
1910 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1911 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1912 return false;
1913 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1914 return false;
1915 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1916 return false;
1917 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1918 return false;
1919 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1920 return false;
1921 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1922 return false;
1923 } else {
1924 /* protected mode guest state checks */
1925 if (!cs_ss_rpl_check(vcpu))
1926 return false;
1927 if (!code_segment_valid(vcpu))
1928 return false;
1929 if (!stack_segment_valid(vcpu))
1930 return false;
1931 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1932 return false;
1933 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1934 return false;
1935 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1936 return false;
1937 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1938 return false;
1939 if (!tr_valid(vcpu))
1940 return false;
1941 if (!ldtr_valid(vcpu))
1942 return false;
1943 }
1944 /* TODO:
1945 * - Add checks on RIP
1946 * - Add checks on RFLAGS
1947 */
1948
1949 return true;
1950 }
1951
1952 static int init_rmode_tss(struct kvm *kvm)
1953 {
1954 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1955 u16 data = 0;
1956 int ret = 0;
1957 int r;
1958
1959 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1960 if (r < 0)
1961 goto out;
1962 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1963 r = kvm_write_guest_page(kvm, fn++, &data,
1964 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1965 if (r < 0)
1966 goto out;
1967 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1968 if (r < 0)
1969 goto out;
1970 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1971 if (r < 0)
1972 goto out;
1973 data = ~0;
1974 r = kvm_write_guest_page(kvm, fn, &data,
1975 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1976 sizeof(u8));
1977 if (r < 0)
1978 goto out;
1979
1980 ret = 1;
1981 out:
1982 return ret;
1983 }
1984
1985 static int init_rmode_identity_map(struct kvm *kvm)
1986 {
1987 int i, r, ret;
1988 pfn_t identity_map_pfn;
1989 u32 tmp;
1990
1991 if (!vm_need_ept())
1992 return 1;
1993 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
1994 printk(KERN_ERR "EPT: identity-mapping pagetable "
1995 "haven't been allocated!\n");
1996 return 0;
1997 }
1998 if (likely(kvm->arch.ept_identity_pagetable_done))
1999 return 1;
2000 ret = 0;
2001 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2002 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2003 if (r < 0)
2004 goto out;
2005 /* Set up identity-mapping pagetable for EPT in real mode */
2006 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2007 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2008 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2009 r = kvm_write_guest_page(kvm, identity_map_pfn,
2010 &tmp, i * sizeof(tmp), sizeof(tmp));
2011 if (r < 0)
2012 goto out;
2013 }
2014 kvm->arch.ept_identity_pagetable_done = true;
2015 ret = 1;
2016 out:
2017 return ret;
2018 }
2019
2020 static void seg_setup(int seg)
2021 {
2022 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2023
2024 vmcs_write16(sf->selector, 0);
2025 vmcs_writel(sf->base, 0);
2026 vmcs_write32(sf->limit, 0xffff);
2027 vmcs_write32(sf->ar_bytes, 0xf3);
2028 }
2029
2030 static int alloc_apic_access_page(struct kvm *kvm)
2031 {
2032 struct kvm_userspace_memory_region kvm_userspace_mem;
2033 int r = 0;
2034
2035 down_write(&kvm->slots_lock);
2036 if (kvm->arch.apic_access_page)
2037 goto out;
2038 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2039 kvm_userspace_mem.flags = 0;
2040 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2041 kvm_userspace_mem.memory_size = PAGE_SIZE;
2042 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2043 if (r)
2044 goto out;
2045
2046 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2047 out:
2048 up_write(&kvm->slots_lock);
2049 return r;
2050 }
2051
2052 static int alloc_identity_pagetable(struct kvm *kvm)
2053 {
2054 struct kvm_userspace_memory_region kvm_userspace_mem;
2055 int r = 0;
2056
2057 down_write(&kvm->slots_lock);
2058 if (kvm->arch.ept_identity_pagetable)
2059 goto out;
2060 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2061 kvm_userspace_mem.flags = 0;
2062 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2063 kvm_userspace_mem.memory_size = PAGE_SIZE;
2064 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2065 if (r)
2066 goto out;
2067
2068 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2069 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2070 out:
2071 up_write(&kvm->slots_lock);
2072 return r;
2073 }
2074
2075 static void allocate_vpid(struct vcpu_vmx *vmx)
2076 {
2077 int vpid;
2078
2079 vmx->vpid = 0;
2080 if (!enable_vpid || !cpu_has_vmx_vpid())
2081 return;
2082 spin_lock(&vmx_vpid_lock);
2083 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2084 if (vpid < VMX_NR_VPIDS) {
2085 vmx->vpid = vpid;
2086 __set_bit(vpid, vmx_vpid_bitmap);
2087 }
2088 spin_unlock(&vmx_vpid_lock);
2089 }
2090
2091 static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
2092 {
2093 void *va;
2094
2095 if (!cpu_has_vmx_msr_bitmap())
2096 return;
2097
2098 /*
2099 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2100 * have the write-low and read-high bitmap offsets the wrong way round.
2101 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2102 */
2103 va = kmap(msr_bitmap);
2104 if (msr <= 0x1fff) {
2105 __clear_bit(msr, va + 0x000); /* read-low */
2106 __clear_bit(msr, va + 0x800); /* write-low */
2107 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2108 msr &= 0x1fff;
2109 __clear_bit(msr, va + 0x400); /* read-high */
2110 __clear_bit(msr, va + 0xc00); /* write-high */
2111 }
2112 kunmap(msr_bitmap);
2113 }
2114
2115 /*
2116 * Sets up the vmcs for emulated real mode.
2117 */
2118 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2119 {
2120 u32 host_sysenter_cs, msr_low, msr_high;
2121 u32 junk;
2122 u64 host_pat, tsc_this, tsc_base;
2123 unsigned long a;
2124 struct descriptor_table dt;
2125 int i;
2126 unsigned long kvm_vmx_return;
2127 u32 exec_control;
2128
2129 /* I/O */
2130 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
2131 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
2132
2133 if (cpu_has_vmx_msr_bitmap())
2134 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
2135
2136 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2137
2138 /* Control */
2139 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2140 vmcs_config.pin_based_exec_ctrl);
2141
2142 exec_control = vmcs_config.cpu_based_exec_ctrl;
2143 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2144 exec_control &= ~CPU_BASED_TPR_SHADOW;
2145 #ifdef CONFIG_X86_64
2146 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2147 CPU_BASED_CR8_LOAD_EXITING;
2148 #endif
2149 }
2150 if (!vm_need_ept())
2151 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2152 CPU_BASED_CR3_LOAD_EXITING |
2153 CPU_BASED_INVLPG_EXITING;
2154 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2155
2156 if (cpu_has_secondary_exec_ctrls()) {
2157 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2158 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2159 exec_control &=
2160 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2161 if (vmx->vpid == 0)
2162 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2163 if (!vm_need_ept())
2164 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2165 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2166 }
2167
2168 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2169 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2170 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2171
2172 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2173 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2174 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2175
2176 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2177 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2178 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2179 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2180 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2181 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2182 #ifdef CONFIG_X86_64
2183 rdmsrl(MSR_FS_BASE, a);
2184 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2185 rdmsrl(MSR_GS_BASE, a);
2186 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2187 #else
2188 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2189 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2190 #endif
2191
2192 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2193
2194 kvm_get_idt(&dt);
2195 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2196
2197 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2198 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2199 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2200 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2201 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2202
2203 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2204 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2205 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2206 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2207 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2208 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2209
2210 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2211 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2212 host_pat = msr_low | ((u64) msr_high << 32);
2213 vmcs_write64(HOST_IA32_PAT, host_pat);
2214 }
2215 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2216 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2217 host_pat = msr_low | ((u64) msr_high << 32);
2218 /* Write the default value follow host pat */
2219 vmcs_write64(GUEST_IA32_PAT, host_pat);
2220 /* Keep arch.pat sync with GUEST_IA32_PAT */
2221 vmx->vcpu.arch.pat = host_pat;
2222 }
2223
2224 for (i = 0; i < NR_VMX_MSR; ++i) {
2225 u32 index = vmx_msr_index[i];
2226 u32 data_low, data_high;
2227 u64 data;
2228 int j = vmx->nmsrs;
2229
2230 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2231 continue;
2232 if (wrmsr_safe(index, data_low, data_high) < 0)
2233 continue;
2234 data = data_low | ((u64)data_high << 32);
2235 vmx->host_msrs[j].index = index;
2236 vmx->host_msrs[j].reserved = 0;
2237 vmx->host_msrs[j].data = data;
2238 vmx->guest_msrs[j] = vmx->host_msrs[j];
2239 ++vmx->nmsrs;
2240 }
2241
2242 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2243
2244 /* 22.2.1, 20.8.1 */
2245 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2246
2247 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2248 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2249
2250 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2251 rdtscll(tsc_this);
2252 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2253 tsc_base = tsc_this;
2254
2255 guest_write_tsc(0, tsc_base);
2256
2257 return 0;
2258 }
2259
2260 static int init_rmode(struct kvm *kvm)
2261 {
2262 if (!init_rmode_tss(kvm))
2263 return 0;
2264 if (!init_rmode_identity_map(kvm))
2265 return 0;
2266 return 1;
2267 }
2268
2269 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2270 {
2271 struct vcpu_vmx *vmx = to_vmx(vcpu);
2272 u64 msr;
2273 int ret;
2274
2275 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2276 down_read(&vcpu->kvm->slots_lock);
2277 if (!init_rmode(vmx->vcpu.kvm)) {
2278 ret = -ENOMEM;
2279 goto out;
2280 }
2281
2282 vmx->vcpu.arch.rmode.active = 0;
2283
2284 vmx->soft_vnmi_blocked = 0;
2285
2286 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2287 kvm_set_cr8(&vmx->vcpu, 0);
2288 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2289 if (vmx->vcpu.vcpu_id == 0)
2290 msr |= MSR_IA32_APICBASE_BSP;
2291 kvm_set_apic_base(&vmx->vcpu, msr);
2292
2293 fx_init(&vmx->vcpu);
2294
2295 seg_setup(VCPU_SREG_CS);
2296 /*
2297 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2298 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2299 */
2300 if (vmx->vcpu.vcpu_id == 0) {
2301 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2302 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2303 } else {
2304 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2305 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2306 }
2307
2308 seg_setup(VCPU_SREG_DS);
2309 seg_setup(VCPU_SREG_ES);
2310 seg_setup(VCPU_SREG_FS);
2311 seg_setup(VCPU_SREG_GS);
2312 seg_setup(VCPU_SREG_SS);
2313
2314 vmcs_write16(GUEST_TR_SELECTOR, 0);
2315 vmcs_writel(GUEST_TR_BASE, 0);
2316 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2317 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2318
2319 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2320 vmcs_writel(GUEST_LDTR_BASE, 0);
2321 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2322 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2323
2324 vmcs_write32(GUEST_SYSENTER_CS, 0);
2325 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2326 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2327
2328 vmcs_writel(GUEST_RFLAGS, 0x02);
2329 if (vmx->vcpu.vcpu_id == 0)
2330 kvm_rip_write(vcpu, 0xfff0);
2331 else
2332 kvm_rip_write(vcpu, 0);
2333 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2334
2335 vmcs_writel(GUEST_DR7, 0x400);
2336
2337 vmcs_writel(GUEST_GDTR_BASE, 0);
2338 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2339
2340 vmcs_writel(GUEST_IDTR_BASE, 0);
2341 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2342
2343 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2344 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2345 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2346
2347 /* Special registers */
2348 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2349
2350 setup_msrs(vmx);
2351
2352 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2353
2354 if (cpu_has_vmx_tpr_shadow()) {
2355 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2356 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2357 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2358 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2359 vmcs_write32(TPR_THRESHOLD, 0);
2360 }
2361
2362 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2363 vmcs_write64(APIC_ACCESS_ADDR,
2364 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2365
2366 if (vmx->vpid != 0)
2367 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2368
2369 vmx->vcpu.arch.cr0 = 0x60000010;
2370 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2371 vmx_set_cr4(&vmx->vcpu, 0);
2372 vmx_set_efer(&vmx->vcpu, 0);
2373 vmx_fpu_activate(&vmx->vcpu);
2374 update_exception_bitmap(&vmx->vcpu);
2375
2376 vpid_sync_vcpu_all(vmx);
2377
2378 ret = 0;
2379
2380 /* HACK: Don't enable emulation on guest boot/reset */
2381 vmx->emulation_required = 0;
2382
2383 out:
2384 up_read(&vcpu->kvm->slots_lock);
2385 return ret;
2386 }
2387
2388 static void enable_irq_window(struct kvm_vcpu *vcpu)
2389 {
2390 u32 cpu_based_vm_exec_control;
2391
2392 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2393 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2394 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2395 }
2396
2397 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2398 {
2399 u32 cpu_based_vm_exec_control;
2400
2401 if (!cpu_has_virtual_nmis()) {
2402 enable_irq_window(vcpu);
2403 return;
2404 }
2405
2406 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2407 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2408 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2409 }
2410
2411 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2412 {
2413 struct vcpu_vmx *vmx = to_vmx(vcpu);
2414
2415 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2416
2417 ++vcpu->stat.irq_injections;
2418 if (vcpu->arch.rmode.active) {
2419 vmx->rmode.irq.pending = true;
2420 vmx->rmode.irq.vector = irq;
2421 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2422 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2423 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2424 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2425 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2426 return;
2427 }
2428 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2429 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2430 }
2431
2432 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2433 {
2434 struct vcpu_vmx *vmx = to_vmx(vcpu);
2435
2436 if (!cpu_has_virtual_nmis()) {
2437 /*
2438 * Tracking the NMI-blocked state in software is built upon
2439 * finding the next open IRQ window. This, in turn, depends on
2440 * well-behaving guests: They have to keep IRQs disabled at
2441 * least as long as the NMI handler runs. Otherwise we may
2442 * cause NMI nesting, maybe breaking the guest. But as this is
2443 * highly unlikely, we can live with the residual risk.
2444 */
2445 vmx->soft_vnmi_blocked = 1;
2446 vmx->vnmi_blocked_time = 0;
2447 }
2448
2449 ++vcpu->stat.nmi_injections;
2450 if (vcpu->arch.rmode.active) {
2451 vmx->rmode.irq.pending = true;
2452 vmx->rmode.irq.vector = NMI_VECTOR;
2453 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2454 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2455 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2456 INTR_INFO_VALID_MASK);
2457 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2458 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2459 return;
2460 }
2461 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2462 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2463 }
2464
2465 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2466 {
2467 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2468
2469 vcpu->arch.nmi_window_open =
2470 !(guest_intr & (GUEST_INTR_STATE_STI |
2471 GUEST_INTR_STATE_MOV_SS |
2472 GUEST_INTR_STATE_NMI));
2473 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2474 vcpu->arch.nmi_window_open = 0;
2475
2476 vcpu->arch.interrupt_window_open =
2477 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2478 !(guest_intr & (GUEST_INTR_STATE_STI |
2479 GUEST_INTR_STATE_MOV_SS)));
2480 }
2481
2482 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
2483 {
2484 int word_index = __ffs(vcpu->arch.irq_summary);
2485 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
2486 int irq = word_index * BITS_PER_LONG + bit_index;
2487
2488 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
2489 if (!vcpu->arch.irq_pending[word_index])
2490 clear_bit(word_index, &vcpu->arch.irq_summary);
2491 kvm_queue_interrupt(vcpu, irq);
2492 }
2493
2494 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2495 struct kvm_run *kvm_run)
2496 {
2497 vmx_update_window_states(vcpu);
2498
2499 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2500 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2501 GUEST_INTR_STATE_STI |
2502 GUEST_INTR_STATE_MOV_SS);
2503
2504 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2505 if (vcpu->arch.interrupt.pending) {
2506 enable_nmi_window(vcpu);
2507 } else if (vcpu->arch.nmi_window_open) {
2508 vcpu->arch.nmi_pending = false;
2509 vcpu->arch.nmi_injected = true;
2510 } else {
2511 enable_nmi_window(vcpu);
2512 return;
2513 }
2514 }
2515 if (vcpu->arch.nmi_injected) {
2516 vmx_inject_nmi(vcpu);
2517 if (vcpu->arch.nmi_pending)
2518 enable_nmi_window(vcpu);
2519 else if (vcpu->arch.irq_summary
2520 || kvm_run->request_interrupt_window)
2521 enable_irq_window(vcpu);
2522 return;
2523 }
2524
2525 if (vcpu->arch.interrupt_window_open) {
2526 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2527 kvm_do_inject_irq(vcpu);
2528
2529 if (vcpu->arch.interrupt.pending)
2530 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2531 }
2532 if (!vcpu->arch.interrupt_window_open &&
2533 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2534 enable_irq_window(vcpu);
2535 }
2536
2537 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2538 {
2539 int ret;
2540 struct kvm_userspace_memory_region tss_mem = {
2541 .slot = TSS_PRIVATE_MEMSLOT,
2542 .guest_phys_addr = addr,
2543 .memory_size = PAGE_SIZE * 3,
2544 .flags = 0,
2545 };
2546
2547 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2548 if (ret)
2549 return ret;
2550 kvm->arch.tss_addr = addr;
2551 return 0;
2552 }
2553
2554 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2555 int vec, u32 err_code)
2556 {
2557 /*
2558 * Instruction with address size override prefix opcode 0x67
2559 * Cause the #SS fault with 0 error code in VM86 mode.
2560 */
2561 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2562 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2563 return 1;
2564 /*
2565 * Forward all other exceptions that are valid in real mode.
2566 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2567 * the required debugging infrastructure rework.
2568 */
2569 switch (vec) {
2570 case DB_VECTOR:
2571 if (vcpu->guest_debug &
2572 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2573 return 0;
2574 kvm_queue_exception(vcpu, vec);
2575 return 1;
2576 case BP_VECTOR:
2577 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2578 return 0;
2579 /* fall through */
2580 case DE_VECTOR:
2581 case OF_VECTOR:
2582 case BR_VECTOR:
2583 case UD_VECTOR:
2584 case DF_VECTOR:
2585 case SS_VECTOR:
2586 case GP_VECTOR:
2587 case MF_VECTOR:
2588 kvm_queue_exception(vcpu, vec);
2589 return 1;
2590 }
2591 return 0;
2592 }
2593
2594 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2595 {
2596 struct vcpu_vmx *vmx = to_vmx(vcpu);
2597 u32 intr_info, ex_no, error_code;
2598 unsigned long cr2, rip, dr6;
2599 u32 vect_info;
2600 enum emulation_result er;
2601
2602 vect_info = vmx->idt_vectoring_info;
2603 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2604
2605 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2606 !is_page_fault(intr_info))
2607 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2608 "intr info 0x%x\n", __func__, vect_info, intr_info);
2609
2610 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2611 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2612 set_bit(irq, vcpu->arch.irq_pending);
2613 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
2614 }
2615
2616 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2617 return 1; /* already handled by vmx_vcpu_run() */
2618
2619 if (is_no_device(intr_info)) {
2620 vmx_fpu_activate(vcpu);
2621 return 1;
2622 }
2623
2624 if (is_invalid_opcode(intr_info)) {
2625 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2626 if (er != EMULATE_DONE)
2627 kvm_queue_exception(vcpu, UD_VECTOR);
2628 return 1;
2629 }
2630
2631 error_code = 0;
2632 rip = kvm_rip_read(vcpu);
2633 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2634 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2635 if (is_page_fault(intr_info)) {
2636 /* EPT won't cause page fault directly */
2637 if (vm_need_ept())
2638 BUG();
2639 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2640 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2641 (u32)((u64)cr2 >> 32), handler);
2642 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2643 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2644 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2645 }
2646
2647 if (vcpu->arch.rmode.active &&
2648 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2649 error_code)) {
2650 if (vcpu->arch.halt_request) {
2651 vcpu->arch.halt_request = 0;
2652 return kvm_emulate_halt(vcpu);
2653 }
2654 return 1;
2655 }
2656
2657 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2658 switch (ex_no) {
2659 case DB_VECTOR:
2660 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2661 if (!(vcpu->guest_debug &
2662 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2663 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2664 kvm_queue_exception(vcpu, DB_VECTOR);
2665 return 1;
2666 }
2667 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2668 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2669 /* fall through */
2670 case BP_VECTOR:
2671 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2672 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2673 kvm_run->debug.arch.exception = ex_no;
2674 break;
2675 default:
2676 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2677 kvm_run->ex.exception = ex_no;
2678 kvm_run->ex.error_code = error_code;
2679 break;
2680 }
2681 return 0;
2682 }
2683
2684 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2685 struct kvm_run *kvm_run)
2686 {
2687 ++vcpu->stat.irq_exits;
2688 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2689 return 1;
2690 }
2691
2692 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2693 {
2694 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2695 return 0;
2696 }
2697
2698 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2699 {
2700 unsigned long exit_qualification;
2701 int size, down, in, string, rep;
2702 unsigned port;
2703
2704 ++vcpu->stat.io_exits;
2705 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2706 string = (exit_qualification & 16) != 0;
2707
2708 if (string) {
2709 if (emulate_instruction(vcpu,
2710 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2711 return 0;
2712 return 1;
2713 }
2714
2715 size = (exit_qualification & 7) + 1;
2716 in = (exit_qualification & 8) != 0;
2717 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2718 rep = (exit_qualification & 32) != 0;
2719 port = exit_qualification >> 16;
2720
2721 skip_emulated_instruction(vcpu);
2722 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2723 }
2724
2725 static void
2726 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2727 {
2728 /*
2729 * Patch in the VMCALL instruction:
2730 */
2731 hypercall[0] = 0x0f;
2732 hypercall[1] = 0x01;
2733 hypercall[2] = 0xc1;
2734 }
2735
2736 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2737 {
2738 unsigned long exit_qualification;
2739 int cr;
2740 int reg;
2741
2742 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2743 cr = exit_qualification & 15;
2744 reg = (exit_qualification >> 8) & 15;
2745 switch ((exit_qualification >> 4) & 3) {
2746 case 0: /* mov to cr */
2747 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2748 (u32)kvm_register_read(vcpu, reg),
2749 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2750 handler);
2751 switch (cr) {
2752 case 0:
2753 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2754 skip_emulated_instruction(vcpu);
2755 return 1;
2756 case 3:
2757 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2758 skip_emulated_instruction(vcpu);
2759 return 1;
2760 case 4:
2761 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2762 skip_emulated_instruction(vcpu);
2763 return 1;
2764 case 8:
2765 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2766 skip_emulated_instruction(vcpu);
2767 if (irqchip_in_kernel(vcpu->kvm))
2768 return 1;
2769 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2770 return 0;
2771 };
2772 break;
2773 case 2: /* clts */
2774 vmx_fpu_deactivate(vcpu);
2775 vcpu->arch.cr0 &= ~X86_CR0_TS;
2776 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2777 vmx_fpu_activate(vcpu);
2778 KVMTRACE_0D(CLTS, vcpu, handler);
2779 skip_emulated_instruction(vcpu);
2780 return 1;
2781 case 1: /*mov from cr*/
2782 switch (cr) {
2783 case 3:
2784 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2785 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2786 (u32)kvm_register_read(vcpu, reg),
2787 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2788 handler);
2789 skip_emulated_instruction(vcpu);
2790 return 1;
2791 case 8:
2792 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2793 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2794 (u32)kvm_register_read(vcpu, reg), handler);
2795 skip_emulated_instruction(vcpu);
2796 return 1;
2797 }
2798 break;
2799 case 3: /* lmsw */
2800 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2801
2802 skip_emulated_instruction(vcpu);
2803 return 1;
2804 default:
2805 break;
2806 }
2807 kvm_run->exit_reason = 0;
2808 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2809 (int)(exit_qualification >> 4) & 3, cr);
2810 return 0;
2811 }
2812
2813 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2814 {
2815 unsigned long exit_qualification;
2816 unsigned long val;
2817 int dr, reg;
2818
2819 dr = vmcs_readl(GUEST_DR7);
2820 if (dr & DR7_GD) {
2821 /*
2822 * As the vm-exit takes precedence over the debug trap, we
2823 * need to emulate the latter, either for the host or the
2824 * guest debugging itself.
2825 */
2826 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2827 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2828 kvm_run->debug.arch.dr7 = dr;
2829 kvm_run->debug.arch.pc =
2830 vmcs_readl(GUEST_CS_BASE) +
2831 vmcs_readl(GUEST_RIP);
2832 kvm_run->debug.arch.exception = DB_VECTOR;
2833 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2834 return 0;
2835 } else {
2836 vcpu->arch.dr7 &= ~DR7_GD;
2837 vcpu->arch.dr6 |= DR6_BD;
2838 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2839 kvm_queue_exception(vcpu, DB_VECTOR);
2840 return 1;
2841 }
2842 }
2843
2844 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2845 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2846 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2847 if (exit_qualification & TYPE_MOV_FROM_DR) {
2848 switch (dr) {
2849 case 0 ... 3:
2850 val = vcpu->arch.db[dr];
2851 break;
2852 case 6:
2853 val = vcpu->arch.dr6;
2854 break;
2855 case 7:
2856 val = vcpu->arch.dr7;
2857 break;
2858 default:
2859 val = 0;
2860 }
2861 kvm_register_write(vcpu, reg, val);
2862 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2863 } else {
2864 val = vcpu->arch.regs[reg];
2865 switch (dr) {
2866 case 0 ... 3:
2867 vcpu->arch.db[dr] = val;
2868 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2869 vcpu->arch.eff_db[dr] = val;
2870 break;
2871 case 4 ... 5:
2872 if (vcpu->arch.cr4 & X86_CR4_DE)
2873 kvm_queue_exception(vcpu, UD_VECTOR);
2874 break;
2875 case 6:
2876 if (val & 0xffffffff00000000ULL) {
2877 kvm_queue_exception(vcpu, GP_VECTOR);
2878 break;
2879 }
2880 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2881 break;
2882 case 7:
2883 if (val & 0xffffffff00000000ULL) {
2884 kvm_queue_exception(vcpu, GP_VECTOR);
2885 break;
2886 }
2887 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2888 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2889 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2890 vcpu->arch.switch_db_regs =
2891 (val & DR7_BP_EN_MASK);
2892 }
2893 break;
2894 }
2895 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2896 }
2897 skip_emulated_instruction(vcpu);
2898 return 1;
2899 }
2900
2901 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2902 {
2903 kvm_emulate_cpuid(vcpu);
2904 return 1;
2905 }
2906
2907 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2908 {
2909 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2910 u64 data;
2911
2912 if (vmx_get_msr(vcpu, ecx, &data)) {
2913 kvm_inject_gp(vcpu, 0);
2914 return 1;
2915 }
2916
2917 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2918 handler);
2919
2920 /* FIXME: handling of bits 32:63 of rax, rdx */
2921 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2922 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2923 skip_emulated_instruction(vcpu);
2924 return 1;
2925 }
2926
2927 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2928 {
2929 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2930 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2931 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2932
2933 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2934 handler);
2935
2936 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2937 kvm_inject_gp(vcpu, 0);
2938 return 1;
2939 }
2940
2941 skip_emulated_instruction(vcpu);
2942 return 1;
2943 }
2944
2945 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2946 struct kvm_run *kvm_run)
2947 {
2948 return 1;
2949 }
2950
2951 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2952 struct kvm_run *kvm_run)
2953 {
2954 u32 cpu_based_vm_exec_control;
2955
2956 /* clear pending irq */
2957 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2958 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2959 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2960
2961 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2962 ++vcpu->stat.irq_window_exits;
2963
2964 /*
2965 * If the user space waits to inject interrupts, exit as soon as
2966 * possible
2967 */
2968 if (kvm_run->request_interrupt_window &&
2969 !vcpu->arch.irq_summary) {
2970 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2971 return 0;
2972 }
2973 return 1;
2974 }
2975
2976 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2977 {
2978 skip_emulated_instruction(vcpu);
2979 return kvm_emulate_halt(vcpu);
2980 }
2981
2982 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2983 {
2984 skip_emulated_instruction(vcpu);
2985 kvm_emulate_hypercall(vcpu);
2986 return 1;
2987 }
2988
2989 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2990 {
2991 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2992
2993 kvm_mmu_invlpg(vcpu, exit_qualification);
2994 skip_emulated_instruction(vcpu);
2995 return 1;
2996 }
2997
2998 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2999 {
3000 skip_emulated_instruction(vcpu);
3001 /* TODO: Add support for VT-d/pass-through device */
3002 return 1;
3003 }
3004
3005 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3006 {
3007 u64 exit_qualification;
3008 enum emulation_result er;
3009 unsigned long offset;
3010
3011 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3012 offset = exit_qualification & 0xffful;
3013
3014 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3015
3016 if (er != EMULATE_DONE) {
3017 printk(KERN_ERR
3018 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3019 offset);
3020 return -ENOTSUPP;
3021 }
3022 return 1;
3023 }
3024
3025 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3026 {
3027 struct vcpu_vmx *vmx = to_vmx(vcpu);
3028 unsigned long exit_qualification;
3029 u16 tss_selector;
3030 int reason;
3031
3032 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3033
3034 reason = (u32)exit_qualification >> 30;
3035 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3036 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3037 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3038 == INTR_TYPE_NMI_INTR) {
3039 vcpu->arch.nmi_injected = false;
3040 if (cpu_has_virtual_nmis())
3041 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3042 GUEST_INTR_STATE_NMI);
3043 }
3044 tss_selector = exit_qualification;
3045
3046 if (!kvm_task_switch(vcpu, tss_selector, reason))
3047 return 0;
3048
3049 /* clear all local breakpoint enable flags */
3050 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3051
3052 /*
3053 * TODO: What about debug traps on tss switch?
3054 * Are we supposed to inject them and update dr6?
3055 */
3056
3057 return 1;
3058 }
3059
3060 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3061 {
3062 u64 exit_qualification;
3063 enum emulation_result er;
3064 gpa_t gpa;
3065 unsigned long hva;
3066 int gla_validity;
3067 int r;
3068
3069 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3070
3071 if (exit_qualification & (1 << 6)) {
3072 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3073 return -ENOTSUPP;
3074 }
3075
3076 gla_validity = (exit_qualification >> 7) & 0x3;
3077 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3078 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3079 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3080 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3081 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3082 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3083 (long unsigned int)exit_qualification);
3084 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3085 kvm_run->hw.hardware_exit_reason = 0;
3086 return -ENOTSUPP;
3087 }
3088
3089 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3090 hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT);
3091 if (!kvm_is_error_hva(hva)) {
3092 r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3093 if (r < 0) {
3094 printk(KERN_ERR "EPT: Not enough memory!\n");
3095 return -ENOMEM;
3096 }
3097 return 1;
3098 } else {
3099 /* must be MMIO */
3100 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3101
3102 if (er == EMULATE_FAIL) {
3103 printk(KERN_ERR
3104 "EPT: Fail to handle EPT violation vmexit!er is %d\n",
3105 er);
3106 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3107 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3108 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3109 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3110 (long unsigned int)exit_qualification);
3111 return -ENOTSUPP;
3112 } else if (er == EMULATE_DO_MMIO)
3113 return 0;
3114 }
3115 return 1;
3116 }
3117
3118 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3119 {
3120 u32 cpu_based_vm_exec_control;
3121
3122 /* clear pending NMI */
3123 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3124 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3125 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3126 ++vcpu->stat.nmi_window_exits;
3127
3128 return 1;
3129 }
3130
3131 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3132 struct kvm_run *kvm_run)
3133 {
3134 struct vcpu_vmx *vmx = to_vmx(vcpu);
3135 enum emulation_result err = EMULATE_DONE;
3136
3137 preempt_enable();
3138 local_irq_enable();
3139
3140 while (!guest_state_valid(vcpu)) {
3141 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3142
3143 if (err == EMULATE_DO_MMIO)
3144 break;
3145
3146 if (err != EMULATE_DONE) {
3147 kvm_report_emulation_failure(vcpu, "emulation failure");
3148 return;
3149 }
3150
3151 if (signal_pending(current))
3152 break;
3153 if (need_resched())
3154 schedule();
3155 }
3156
3157 local_irq_disable();
3158 preempt_disable();
3159
3160 vmx->invalid_state_emulation_result = err;
3161 }
3162
3163 /*
3164 * The exit handlers return 1 if the exit was handled fully and guest execution
3165 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3166 * to be done to userspace and return 0.
3167 */
3168 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3169 struct kvm_run *kvm_run) = {
3170 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3171 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3172 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3173 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3174 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3175 [EXIT_REASON_CR_ACCESS] = handle_cr,
3176 [EXIT_REASON_DR_ACCESS] = handle_dr,
3177 [EXIT_REASON_CPUID] = handle_cpuid,
3178 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3179 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3180 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3181 [EXIT_REASON_HLT] = handle_halt,
3182 [EXIT_REASON_INVLPG] = handle_invlpg,
3183 [EXIT_REASON_VMCALL] = handle_vmcall,
3184 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3185 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3186 [EXIT_REASON_WBINVD] = handle_wbinvd,
3187 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3188 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3189 };
3190
3191 static const int kvm_vmx_max_exit_handlers =
3192 ARRAY_SIZE(kvm_vmx_exit_handlers);
3193
3194 /*
3195 * The guest has exited. See if we can fix it or if we need userspace
3196 * assistance.
3197 */
3198 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3199 {
3200 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3201 struct vcpu_vmx *vmx = to_vmx(vcpu);
3202 u32 vectoring_info = vmx->idt_vectoring_info;
3203
3204 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3205 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3206
3207 /* If we need to emulate an MMIO from handle_invalid_guest_state
3208 * we just return 0 */
3209 if (vmx->emulation_required && emulate_invalid_guest_state) {
3210 if (guest_state_valid(vcpu))
3211 vmx->emulation_required = 0;
3212 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3213 }
3214
3215 /* Access CR3 don't cause VMExit in paging mode, so we need
3216 * to sync with guest real CR3. */
3217 if (vm_need_ept() && is_paging(vcpu)) {
3218 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3219 ept_load_pdptrs(vcpu);
3220 }
3221
3222 if (unlikely(vmx->fail)) {
3223 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3224 kvm_run->fail_entry.hardware_entry_failure_reason
3225 = vmcs_read32(VM_INSTRUCTION_ERROR);
3226 return 0;
3227 }
3228
3229 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3230 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3231 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3232 exit_reason != EXIT_REASON_TASK_SWITCH))
3233 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3234 "(0x%x) and exit reason is 0x%x\n",
3235 __func__, vectoring_info, exit_reason);
3236
3237 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3238 if (vcpu->arch.interrupt_window_open) {
3239 vmx->soft_vnmi_blocked = 0;
3240 vcpu->arch.nmi_window_open = 1;
3241 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3242 vcpu->arch.nmi_pending) {
3243 /*
3244 * This CPU don't support us in finding the end of an
3245 * NMI-blocked window if the guest runs with IRQs
3246 * disabled. So we pull the trigger after 1 s of
3247 * futile waiting, but inform the user about this.
3248 */
3249 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3250 "state on VCPU %d after 1 s timeout\n",
3251 __func__, vcpu->vcpu_id);
3252 vmx->soft_vnmi_blocked = 0;
3253 vmx->vcpu.arch.nmi_window_open = 1;
3254 }
3255 }
3256
3257 if (exit_reason < kvm_vmx_max_exit_handlers
3258 && kvm_vmx_exit_handlers[exit_reason])
3259 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3260 else {
3261 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3262 kvm_run->hw.hardware_exit_reason = exit_reason;
3263 }
3264 return 0;
3265 }
3266
3267 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3268 {
3269 int max_irr, tpr;
3270
3271 if (!vm_need_tpr_shadow(vcpu->kvm))
3272 return;
3273
3274 if (!kvm_lapic_enabled(vcpu) ||
3275 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3276 vmcs_write32(TPR_THRESHOLD, 0);
3277 return;
3278 }
3279
3280 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3281 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3282 }
3283
3284 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3285 {
3286 u32 exit_intr_info;
3287 u32 idt_vectoring_info;
3288 bool unblock_nmi;
3289 u8 vector;
3290 int type;
3291 bool idtv_info_valid;
3292 u32 error;
3293
3294 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3295 if (cpu_has_virtual_nmis()) {
3296 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3297 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3298 /*
3299 * SDM 3: 25.7.1.2
3300 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3301 * a guest IRET fault.
3302 */
3303 if (unblock_nmi && vector != DF_VECTOR)
3304 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3305 GUEST_INTR_STATE_NMI);
3306 } else if (unlikely(vmx->soft_vnmi_blocked))
3307 vmx->vnmi_blocked_time +=
3308 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3309
3310 idt_vectoring_info = vmx->idt_vectoring_info;
3311 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3312 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3313 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3314 if (vmx->vcpu.arch.nmi_injected) {
3315 /*
3316 * SDM 3: 25.7.1.2
3317 * Clear bit "block by NMI" before VM entry if a NMI delivery
3318 * faulted.
3319 */
3320 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3321 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3322 GUEST_INTR_STATE_NMI);
3323 else
3324 vmx->vcpu.arch.nmi_injected = false;
3325 }
3326 kvm_clear_exception_queue(&vmx->vcpu);
3327 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3328 type == INTR_TYPE_SOFT_EXCEPTION)) {
3329 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3330 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3331 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3332 } else
3333 kvm_queue_exception(&vmx->vcpu, vector);
3334 vmx->idt_vectoring_info = 0;
3335 }
3336 kvm_clear_interrupt_queue(&vmx->vcpu);
3337 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3338 kvm_queue_interrupt(&vmx->vcpu, vector);
3339 vmx->idt_vectoring_info = 0;
3340 }
3341 }
3342
3343 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3344 {
3345 update_tpr_threshold(vcpu);
3346
3347 vmx_update_window_states(vcpu);
3348
3349 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3350 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3351 GUEST_INTR_STATE_STI |
3352 GUEST_INTR_STATE_MOV_SS);
3353
3354 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3355 if (vcpu->arch.interrupt.pending) {
3356 enable_nmi_window(vcpu);
3357 } else if (vcpu->arch.nmi_window_open) {
3358 vcpu->arch.nmi_pending = false;
3359 vcpu->arch.nmi_injected = true;
3360 } else {
3361 enable_nmi_window(vcpu);
3362 return;
3363 }
3364 }
3365 if (vcpu->arch.nmi_injected) {
3366 vmx_inject_nmi(vcpu);
3367 if (vcpu->arch.nmi_pending)
3368 enable_nmi_window(vcpu);
3369 else if (kvm_cpu_has_interrupt(vcpu))
3370 enable_irq_window(vcpu);
3371 return;
3372 }
3373 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3374 if (vcpu->arch.interrupt_window_open)
3375 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3376 else
3377 enable_irq_window(vcpu);
3378 }
3379 if (vcpu->arch.interrupt.pending) {
3380 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3381 if (kvm_cpu_has_interrupt(vcpu))
3382 enable_irq_window(vcpu);
3383 }
3384 }
3385
3386 /*
3387 * Failure to inject an interrupt should give us the information
3388 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3389 * when fetching the interrupt redirection bitmap in the real-mode
3390 * tss, this doesn't happen. So we do it ourselves.
3391 */
3392 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3393 {
3394 vmx->rmode.irq.pending = 0;
3395 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3396 return;
3397 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3398 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3399 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3400 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3401 return;
3402 }
3403 vmx->idt_vectoring_info =
3404 VECTORING_INFO_VALID_MASK
3405 | INTR_TYPE_EXT_INTR
3406 | vmx->rmode.irq.vector;
3407 }
3408
3409 #ifdef CONFIG_X86_64
3410 #define R "r"
3411 #define Q "q"
3412 #else
3413 #define R "e"
3414 #define Q "l"
3415 #endif
3416
3417 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3418 {
3419 struct vcpu_vmx *vmx = to_vmx(vcpu);
3420 u32 intr_info;
3421
3422 /* Record the guest's net vcpu time for enforced NMI injections. */
3423 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3424 vmx->entry_time = ktime_get();
3425
3426 /* Handle invalid guest state instead of entering VMX */
3427 if (vmx->emulation_required && emulate_invalid_guest_state) {
3428 handle_invalid_guest_state(vcpu, kvm_run);
3429 return;
3430 }
3431
3432 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3433 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3434 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3435 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3436
3437 /*
3438 * Loading guest fpu may have cleared host cr0.ts
3439 */
3440 vmcs_writel(HOST_CR0, read_cr0());
3441
3442 set_debugreg(vcpu->arch.dr6, 6);
3443
3444 asm(
3445 /* Store host registers */
3446 "push %%"R"dx; push %%"R"bp;"
3447 "push %%"R"cx \n\t"
3448 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3449 "je 1f \n\t"
3450 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3451 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3452 "1: \n\t"
3453 /* Check if vmlaunch of vmresume is needed */
3454 "cmpl $0, %c[launched](%0) \n\t"
3455 /* Load guest registers. Don't clobber flags. */
3456 "mov %c[cr2](%0), %%"R"ax \n\t"
3457 "mov %%"R"ax, %%cr2 \n\t"
3458 "mov %c[rax](%0), %%"R"ax \n\t"
3459 "mov %c[rbx](%0), %%"R"bx \n\t"
3460 "mov %c[rdx](%0), %%"R"dx \n\t"
3461 "mov %c[rsi](%0), %%"R"si \n\t"
3462 "mov %c[rdi](%0), %%"R"di \n\t"
3463 "mov %c[rbp](%0), %%"R"bp \n\t"
3464 #ifdef CONFIG_X86_64
3465 "mov %c[r8](%0), %%r8 \n\t"
3466 "mov %c[r9](%0), %%r9 \n\t"
3467 "mov %c[r10](%0), %%r10 \n\t"
3468 "mov %c[r11](%0), %%r11 \n\t"
3469 "mov %c[r12](%0), %%r12 \n\t"
3470 "mov %c[r13](%0), %%r13 \n\t"
3471 "mov %c[r14](%0), %%r14 \n\t"
3472 "mov %c[r15](%0), %%r15 \n\t"
3473 #endif
3474 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3475
3476 /* Enter guest mode */
3477 "jne .Llaunched \n\t"
3478 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3479 "jmp .Lkvm_vmx_return \n\t"
3480 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3481 ".Lkvm_vmx_return: "
3482 /* Save guest registers, load host registers, keep flags */
3483 "xchg %0, (%%"R"sp) \n\t"
3484 "mov %%"R"ax, %c[rax](%0) \n\t"
3485 "mov %%"R"bx, %c[rbx](%0) \n\t"
3486 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3487 "mov %%"R"dx, %c[rdx](%0) \n\t"
3488 "mov %%"R"si, %c[rsi](%0) \n\t"
3489 "mov %%"R"di, %c[rdi](%0) \n\t"
3490 "mov %%"R"bp, %c[rbp](%0) \n\t"
3491 #ifdef CONFIG_X86_64
3492 "mov %%r8, %c[r8](%0) \n\t"
3493 "mov %%r9, %c[r9](%0) \n\t"
3494 "mov %%r10, %c[r10](%0) \n\t"
3495 "mov %%r11, %c[r11](%0) \n\t"
3496 "mov %%r12, %c[r12](%0) \n\t"
3497 "mov %%r13, %c[r13](%0) \n\t"
3498 "mov %%r14, %c[r14](%0) \n\t"
3499 "mov %%r15, %c[r15](%0) \n\t"
3500 #endif
3501 "mov %%cr2, %%"R"ax \n\t"
3502 "mov %%"R"ax, %c[cr2](%0) \n\t"
3503
3504 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3505 "setbe %c[fail](%0) \n\t"
3506 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3507 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3508 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3509 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3510 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3511 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3512 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3513 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3514 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3515 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3516 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3517 #ifdef CONFIG_X86_64
3518 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3519 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3520 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3521 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3522 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3523 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3524 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3525 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3526 #endif
3527 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3528 : "cc", "memory"
3529 , R"bx", R"di", R"si"
3530 #ifdef CONFIG_X86_64
3531 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3532 #endif
3533 );
3534
3535 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3536 vcpu->arch.regs_dirty = 0;
3537
3538 get_debugreg(vcpu->arch.dr6, 6);
3539
3540 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3541 if (vmx->rmode.irq.pending)
3542 fixup_rmode_irq(vmx);
3543
3544 vmx_update_window_states(vcpu);
3545
3546 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3547 vmx->launched = 1;
3548
3549 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3550
3551 /* We need to handle NMIs before interrupts are enabled */
3552 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3553 (intr_info & INTR_INFO_VALID_MASK)) {
3554 KVMTRACE_0D(NMI, vcpu, handler);
3555 asm("int $2");
3556 }
3557
3558 vmx_complete_interrupts(vmx);
3559 }
3560
3561 #undef R
3562 #undef Q
3563
3564 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3565 {
3566 struct vcpu_vmx *vmx = to_vmx(vcpu);
3567
3568 if (vmx->vmcs) {
3569 vcpu_clear(vmx);
3570 free_vmcs(vmx->vmcs);
3571 vmx->vmcs = NULL;
3572 }
3573 }
3574
3575 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3576 {
3577 struct vcpu_vmx *vmx = to_vmx(vcpu);
3578
3579 spin_lock(&vmx_vpid_lock);
3580 if (vmx->vpid != 0)
3581 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3582 spin_unlock(&vmx_vpid_lock);
3583 vmx_free_vmcs(vcpu);
3584 kfree(vmx->host_msrs);
3585 kfree(vmx->guest_msrs);
3586 kvm_vcpu_uninit(vcpu);
3587 kmem_cache_free(kvm_vcpu_cache, vmx);
3588 }
3589
3590 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3591 {
3592 int err;
3593 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3594 int cpu;
3595
3596 if (!vmx)
3597 return ERR_PTR(-ENOMEM);
3598
3599 allocate_vpid(vmx);
3600
3601 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3602 if (err)
3603 goto free_vcpu;
3604
3605 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3606 if (!vmx->guest_msrs) {
3607 err = -ENOMEM;
3608 goto uninit_vcpu;
3609 }
3610
3611 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3612 if (!vmx->host_msrs)
3613 goto free_guest_msrs;
3614
3615 vmx->vmcs = alloc_vmcs();
3616 if (!vmx->vmcs)
3617 goto free_msrs;
3618
3619 vmcs_clear(vmx->vmcs);
3620
3621 cpu = get_cpu();
3622 vmx_vcpu_load(&vmx->vcpu, cpu);
3623 err = vmx_vcpu_setup(vmx);
3624 vmx_vcpu_put(&vmx->vcpu);
3625 put_cpu();
3626 if (err)
3627 goto free_vmcs;
3628 if (vm_need_virtualize_apic_accesses(kvm))
3629 if (alloc_apic_access_page(kvm) != 0)
3630 goto free_vmcs;
3631
3632 if (vm_need_ept())
3633 if (alloc_identity_pagetable(kvm) != 0)
3634 goto free_vmcs;
3635
3636 return &vmx->vcpu;
3637
3638 free_vmcs:
3639 free_vmcs(vmx->vmcs);
3640 free_msrs:
3641 kfree(vmx->host_msrs);
3642 free_guest_msrs:
3643 kfree(vmx->guest_msrs);
3644 uninit_vcpu:
3645 kvm_vcpu_uninit(&vmx->vcpu);
3646 free_vcpu:
3647 kmem_cache_free(kvm_vcpu_cache, vmx);
3648 return ERR_PTR(err);
3649 }
3650
3651 static void __init vmx_check_processor_compat(void *rtn)
3652 {
3653 struct vmcs_config vmcs_conf;
3654
3655 *(int *)rtn = 0;
3656 if (setup_vmcs_config(&vmcs_conf) < 0)
3657 *(int *)rtn = -EIO;
3658 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3659 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3660 smp_processor_id());
3661 *(int *)rtn = -EIO;
3662 }
3663 }
3664
3665 static int get_ept_level(void)
3666 {
3667 return VMX_EPT_DEFAULT_GAW + 1;
3668 }
3669
3670 static int vmx_get_mt_mask_shift(void)
3671 {
3672 return VMX_EPT_MT_EPTE_SHIFT;
3673 }
3674
3675 static struct kvm_x86_ops vmx_x86_ops = {
3676 .cpu_has_kvm_support = cpu_has_kvm_support,
3677 .disabled_by_bios = vmx_disabled_by_bios,
3678 .hardware_setup = hardware_setup,
3679 .hardware_unsetup = hardware_unsetup,
3680 .check_processor_compatibility = vmx_check_processor_compat,
3681 .hardware_enable = hardware_enable,
3682 .hardware_disable = hardware_disable,
3683 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3684
3685 .vcpu_create = vmx_create_vcpu,
3686 .vcpu_free = vmx_free_vcpu,
3687 .vcpu_reset = vmx_vcpu_reset,
3688
3689 .prepare_guest_switch = vmx_save_host_state,
3690 .vcpu_load = vmx_vcpu_load,
3691 .vcpu_put = vmx_vcpu_put,
3692
3693 .set_guest_debug = set_guest_debug,
3694 .get_msr = vmx_get_msr,
3695 .set_msr = vmx_set_msr,
3696 .get_segment_base = vmx_get_segment_base,
3697 .get_segment = vmx_get_segment,
3698 .set_segment = vmx_set_segment,
3699 .get_cpl = vmx_get_cpl,
3700 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3701 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3702 .set_cr0 = vmx_set_cr0,
3703 .set_cr3 = vmx_set_cr3,
3704 .set_cr4 = vmx_set_cr4,
3705 .set_efer = vmx_set_efer,
3706 .get_idt = vmx_get_idt,
3707 .set_idt = vmx_set_idt,
3708 .get_gdt = vmx_get_gdt,
3709 .set_gdt = vmx_set_gdt,
3710 .cache_reg = vmx_cache_reg,
3711 .get_rflags = vmx_get_rflags,
3712 .set_rflags = vmx_set_rflags,
3713
3714 .tlb_flush = vmx_flush_tlb,
3715
3716 .run = vmx_vcpu_run,
3717 .handle_exit = kvm_handle_exit,
3718 .skip_emulated_instruction = skip_emulated_instruction,
3719 .patch_hypercall = vmx_patch_hypercall,
3720 .get_irq = vmx_get_irq,
3721 .set_irq = vmx_inject_irq,
3722 .queue_exception = vmx_queue_exception,
3723 .exception_injected = vmx_exception_injected,
3724 .inject_pending_irq = vmx_intr_assist,
3725 .inject_pending_vectors = do_interrupt_requests,
3726
3727 .set_tss_addr = vmx_set_tss_addr,
3728 .get_tdp_level = get_ept_level,
3729 .get_mt_mask_shift = vmx_get_mt_mask_shift,
3730 };
3731
3732 static int __init vmx_init(void)
3733 {
3734 void *va;
3735 int r;
3736
3737 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3738 if (!vmx_io_bitmap_a)
3739 return -ENOMEM;
3740
3741 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3742 if (!vmx_io_bitmap_b) {
3743 r = -ENOMEM;
3744 goto out;
3745 }
3746
3747 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
3748 if (!vmx_msr_bitmap) {
3749 r = -ENOMEM;
3750 goto out1;
3751 }
3752
3753 /*
3754 * Allow direct access to the PC debug port (it is often used for I/O
3755 * delays, but the vmexits simply slow things down).
3756 */
3757 va = kmap(vmx_io_bitmap_a);
3758 memset(va, 0xff, PAGE_SIZE);
3759 clear_bit(0x80, va);
3760 kunmap(vmx_io_bitmap_a);
3761
3762 va = kmap(vmx_io_bitmap_b);
3763 memset(va, 0xff, PAGE_SIZE);
3764 kunmap(vmx_io_bitmap_b);
3765
3766 va = kmap(vmx_msr_bitmap);
3767 memset(va, 0xff, PAGE_SIZE);
3768 kunmap(vmx_msr_bitmap);
3769
3770 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3771
3772 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3773 if (r)
3774 goto out2;
3775
3776 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
3777 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
3778 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
3779 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
3780 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
3781
3782 if (vm_need_ept()) {
3783 bypass_guest_pf = 0;
3784 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3785 VMX_EPT_WRITABLE_MASK);
3786 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3787 VMX_EPT_EXECUTABLE_MASK,
3788 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3789 kvm_enable_tdp();
3790 } else
3791 kvm_disable_tdp();
3792
3793 if (bypass_guest_pf)
3794 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3795
3796 ept_sync_global();
3797
3798 return 0;
3799
3800 out2:
3801 __free_page(vmx_msr_bitmap);
3802 out1:
3803 __free_page(vmx_io_bitmap_b);
3804 out:
3805 __free_page(vmx_io_bitmap_a);
3806 return r;
3807 }
3808
3809 static void __exit vmx_exit(void)
3810 {
3811 __free_page(vmx_msr_bitmap);
3812 __free_page(vmx_io_bitmap_b);
3813 __free_page(vmx_io_bitmap_a);
3814
3815 kvm_exit();
3816 }
3817
3818 module_init(vmx_init)
3819 module_exit(vmx_exit)
linux 2.6 git repository for openrd