2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg
=
86 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
87 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
90 static int debug
= -1; /* defaults above */
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly
= 128;
95 module_param(copybreak
, int, 0);
96 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
98 static int disable_msi
= 0;
99 module_param(disable_msi
, int, 0);
100 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table
) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4381) }, /* 88E8059 */
147 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
151 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
152 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
154 static void sky2_set_multicast(struct net_device
*dev
);
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
161 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
162 gma_write16(hw
, port
, GM_SMI_CTRL
,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
165 for (i
= 0; i
< PHY_RETRIES
; i
++) {
166 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
170 if (!(ctrl
& GM_SMI_CT_BUSY
))
176 dev_warn(&hw
->pdev
->dev
,"%s: phy write timeout\n", hw
->dev
[port
]->name
);
180 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
184 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
188 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
189 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
191 for (i
= 0; i
< PHY_RETRIES
; i
++) {
192 u16 ctrl
= gma_read16(hw
, port
, GM_SMI_CTRL
);
196 if (ctrl
& GM_SMI_CT_RD_VAL
) {
197 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
204 dev_warn(&hw
->pdev
->dev
, "%s: phy read timeout\n", hw
->dev
[port
]->name
);
207 dev_err(&hw
->pdev
->dev
, "%s: phy I/O error\n", hw
->dev
[port
]->name
);
211 static inline u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
214 __gm_phy_read(hw
, port
, reg
, &v
);
219 static void sky2_power_on(struct sky2_hw
*hw
)
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw
, B0_POWER_CTRL
,
223 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
225 /* disable Core Clock Division, */
226 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
228 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
229 /* enable bits are inverted */
230 sky2_write8(hw
, B2_Y2_CLK_GATE
,
231 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
232 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
233 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
235 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
237 if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
) {
240 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
242 reg
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg
&= P_ASPM_CONTROL_MSK
;
245 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg
);
247 reg
= sky2_pci_read32(hw
, PCI_DEV_REG5
);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg
&= P_CTL_TIM_VMAIN_AV_MSK
;
250 sky2_pci_write32(hw
, PCI_DEV_REG5
, reg
);
252 sky2_pci_write32(hw
, PCI_CFG_REG_1
, 0);
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg
= sky2_read32(hw
, B2_GP_IO
);
256 reg
|= GLB_GPIO_STAT_RACE_DIS
;
257 sky2_write32(hw
, B2_GP_IO
, reg
);
259 sky2_read32(hw
, B2_GP_IO
);
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_ON
);
266 static void sky2_power_aux(struct sky2_hw
*hw
)
268 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
269 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
271 /* enable bits are inverted */
272 sky2_write8(hw
, B2_Y2_CLK_GATE
,
273 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
274 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
275 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
279 pci_pme_capable(hw
->pdev
, PCI_D3cold
))
280 sky2_write8(hw
, B0_POWER_CTRL
,
281 (PC_VAUX_ENA
| PC_VCC_ENA
|
282 PC_VAUX_ON
| PC_VCC_OFF
));
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw
, B0_CTST
, Y2_LED_STAT_OFF
);
288 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
295 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
296 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
297 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
298 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
300 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
301 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
302 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv
[] = {
308 [FC_TX
] = PHY_M_AN_ASP
,
309 [FC_RX
] = PHY_M_AN_PC
,
310 [FC_BOTH
] = PHY_M_AN_PC
| PHY_M_AN_ASP
,
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv
[] = {
315 [FC_NONE
] = PHY_M_P_NO_PAUSE_X
,
316 [FC_TX
] = PHY_M_P_ASYM_MD_X
,
317 [FC_RX
] = PHY_M_P_SYM_MD_X
,
318 [FC_BOTH
] = PHY_M_P_BOTH_MD_X
,
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable
[] = {
323 [FC_NONE
] = GM_GPCR_FC_RX_DIS
| GM_GPCR_FC_TX_DIS
,
324 [FC_TX
] = GM_GPCR_FC_RX_DIS
,
325 [FC_RX
] = GM_GPCR_FC_TX_DIS
,
330 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
332 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
333 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
335 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
336 !(hw
->flags
& SKY2_HW_NEWER_PHY
)) {
337 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
339 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
341 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
348 /* set master & slave downshift counter to 1x */
349 ectrl
|= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
351 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
354 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
355 if (sky2_is_copper(hw
)) {
356 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
357 /* enable automatic crossover */
358 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
360 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
361 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
364 /* Enable Class A driver for FE+ A0 */
365 spec
= gm_phy_read(hw
, port
, PHY_MARV_FE_SPEC_2
);
366 spec
|= PHY_M_FESC_SEL_CL_A
;
367 gm_phy_write(hw
, port
, PHY_MARV_FE_SPEC_2
, spec
);
370 /* disable energy detect */
371 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
373 /* enable automatic crossover */
374 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if ( (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) &&
378 (hw
->flags
& SKY2_HW_NEWER_PHY
)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl
&= ~PHY_M_PC_DSC_MSK
;
381 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
388 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
391 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& (hw
->flags
& SKY2_HW_FIBRE_PHY
)) {
395 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
399 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
400 ctrl
&= ~PHY_M_MAC_MD_MSK
;
401 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
402 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
404 if (hw
->pmd_type
== 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
410 ctrl
|= PHY_M_FIB_SIGD_POL
;
411 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
414 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
422 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) {
423 if (sky2_is_copper(hw
)) {
424 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
425 ct1000
|= PHY_M_1000C_AFD
;
426 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
427 ct1000
|= PHY_M_1000C_AHD
;
428 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
429 adv
|= PHY_M_AN_100_FD
;
430 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
431 adv
|= PHY_M_AN_100_HD
;
432 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
433 adv
|= PHY_M_AN_10_FD
;
434 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
435 adv
|= PHY_M_AN_10_HD
;
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
439 adv
|= PHY_M_AN_1000X_AFD
;
440 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
441 adv
|= PHY_M_AN_1000X_AHD
;
444 /* Restart Auto-negotiation */
445 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
447 /* forced speed/duplex settings */
448 ct1000
= PHY_M_1000C_MSE
;
450 /* Disable auto update for duplex flow control and duplex */
451 reg
|= GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_SPD_DIS
;
453 switch (sky2
->speed
) {
455 ctrl
|= PHY_CT_SP1000
;
456 reg
|= GM_GPCR_SPEED_1000
;
459 ctrl
|= PHY_CT_SP100
;
460 reg
|= GM_GPCR_SPEED_100
;
464 if (sky2
->duplex
== DUPLEX_FULL
) {
465 reg
|= GM_GPCR_DUP_FULL
;
466 ctrl
|= PHY_CT_DUP_MD
;
467 } else if (sky2
->speed
< SPEED_1000
)
468 sky2
->flow_mode
= FC_NONE
;
471 if (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
) {
472 if (sky2_is_copper(hw
))
473 adv
|= copper_fc_adv
[sky2
->flow_mode
];
475 adv
|= fiber_fc_adv
[sky2
->flow_mode
];
477 reg
|= GM_GPCR_AU_FCT_DIS
;
478 reg
|= gm_fc_disable
[sky2
->flow_mode
];
480 /* Forward pause packets to GMAC? */
481 if (sky2
->flow_mode
& FC_RX
)
482 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
484 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
487 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
489 if (hw
->flags
& SKY2_HW_GIGABIT
)
490 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
492 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
493 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
495 /* Setup Phy LED's */
496 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
499 switch (hw
->chip_id
) {
500 case CHIP_ID_YUKON_FE
:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
504 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
506 /* delete ACT LED control bits */
507 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
508 /* change ACT LED control to blink mode */
509 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
510 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
513 case CHIP_ID_YUKON_FE_P
:
514 /* Enable Link Partner Next Page */
515 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
516 ctrl
|= PHY_M_PC_ENA_LIP_NP
;
518 /* disable Energy Detect and enable scrambler */
519 ctrl
&= ~(PHY_M_PC_ENA_ENE_DT
| PHY_M_PC_DIS_SCRAMB
);
520 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl
= PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL
) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK
) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED
);
527 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
530 case CHIP_ID_YUKON_XL
:
531 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
536 /* set LED Function Control register */
537 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
543 /* set Polarity Control register */
544 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
552 /* restore page register */
553 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
556 case CHIP_ID_YUKON_EC_U
:
557 case CHIP_ID_YUKON_EX
:
558 case CHIP_ID_YUKON_SUPR
:
559 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
564 /* set LED Function Control register */
565 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
573 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
574 /* restore page register */
575 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
582 /* turn off the Rx LED (LED_RX) */
583 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
586 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_UL_2
) {
587 /* apply fixes in PHY AFE */
588 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
590 /* increase differential signal amplitude in 10BASE-T */
591 gm_phy_write(hw
, port
, 0x18, 0xaa99);
592 gm_phy_write(hw
, port
, 0x17, 0x2011);
594 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw
, port
, 0x18, 0xa204);
597 gm_phy_write(hw
, port
, 0x17, 0x2002);
600 /* set page register to 0 */
601 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
602 } else if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
603 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw
, port
, PHY_MARV_PAGE_ADDR
, 17);
606 gm_phy_write(hw
, port
, PHY_MARV_PAGE_DATA
, 0x3f60);
607 } else if (hw
->chip_id
== CHIP_ID_YUKON_OPT
&& hw
->chip_rev
== 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0x00ff);
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw
, port
, 24, 0x2800);
613 gm_phy_write(hw
, port
, 23, 0x2001);
615 /* set page register back to 0 */
616 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
617 } else if (hw
->chip_id
!= CHIP_ID_YUKON_EX
&&
618 hw
->chip_id
< CHIP_ID_YUKON_SUPR
) {
619 /* no effect on Yukon-XL */
620 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
622 if (!(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
) ||
623 sky2
->speed
== SPEED_100
) {
624 /* turn on 100 Mbps LED (LED_LINK100) */
625 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
629 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
634 if (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
635 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
637 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
640 static const u32 phy_power
[] = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
641 static const u32 coma_mode
[] = { PCI_Y2_PHY1_COMA
, PCI_Y2_PHY2_COMA
};
643 static void sky2_phy_power_up(struct sky2_hw
*hw
, unsigned port
)
647 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
648 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
649 reg1
&= ~phy_power
[port
];
651 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
652 reg1
|= coma_mode
[port
];
654 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
655 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
656 sky2_pci_read32(hw
, PCI_DEV_REG1
);
658 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
659 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_ANE
);
660 else if (hw
->flags
& SKY2_HW_ADV_POWER_CTL
)
661 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
664 static void sky2_phy_power_down(struct sky2_hw
*hw
, unsigned port
)
669 /* release GPHY Control reset */
670 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
672 /* release GMAC reset */
673 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
675 if (hw
->flags
& SKY2_HW_NEWER_PHY
) {
676 /* select page 2 to access MAC control register */
677 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
679 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
680 /* allow GMII Power Down */
681 ctrl
&= ~PHY_M_MAC_GMIF_PUP
;
682 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
684 /* set page register back to 0 */
685 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
688 /* setup General Purpose Control Register */
689 gma_write16(hw
, port
, GM_GP_CTRL
,
690 GM_GPCR_FL_PASS
| GM_GPCR_SPEED_100
|
691 GM_GPCR_AU_DUP_DIS
| GM_GPCR_AU_FCT_DIS
|
694 if (hw
->chip_id
!= CHIP_ID_YUKON_EC
) {
695 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
696 /* select page 2 to access MAC control register */
697 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
699 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
700 /* enable Power Down */
701 ctrl
|= PHY_M_PC_POW_D_ENA
;
702 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
704 /* set page register back to 0 */
705 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 0);
708 /* set IEEE compatible Power Down Mode (dev. #4.99) */
709 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, PHY_CT_PDOWN
);
712 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
713 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
714 reg1
|= phy_power
[port
]; /* set PHY to PowerDown/COMA Mode */
715 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
716 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
719 /* Force a renegotiation */
720 static void sky2_phy_reinit(struct sky2_port
*sky2
)
722 spin_lock_bh(&sky2
->phy_lock
);
723 sky2_phy_init(sky2
->hw
, sky2
->port
);
724 spin_unlock_bh(&sky2
->phy_lock
);
727 /* Put device in state to listen for Wake On Lan */
728 static void sky2_wol_init(struct sky2_port
*sky2
)
730 struct sky2_hw
*hw
= sky2
->hw
;
731 unsigned port
= sky2
->port
;
732 enum flow_control save_mode
;
736 /* Bring hardware out of reset */
737 sky2_write16(hw
, B0_CTST
, CS_RST_CLR
);
738 sky2_write16(hw
, SK_REG(port
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
740 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
741 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
744 * sky2_reset will re-enable on resume
746 save_mode
= sky2
->flow_mode
;
747 ctrl
= sky2
->advertising
;
749 sky2
->advertising
&= ~(ADVERTISED_1000baseT_Half
|ADVERTISED_1000baseT_Full
);
750 sky2
->flow_mode
= FC_NONE
;
752 spin_lock_bh(&sky2
->phy_lock
);
753 sky2_phy_power_up(hw
, port
);
754 sky2_phy_init(hw
, port
);
755 spin_unlock_bh(&sky2
->phy_lock
);
757 sky2
->flow_mode
= save_mode
;
758 sky2
->advertising
= ctrl
;
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw
, port
, GM_GP_CTRL
,
762 GM_GPCR_FC_TX_DIS
|GM_GPCR_TX_ENA
|GM_GPCR_RX_ENA
|
763 GM_GPCR_DUP_FULL
|GM_GPCR_FC_RX_DIS
|GM_GPCR_AU_FCT_DIS
);
765 /* Set WOL address */
766 memcpy_toio(hw
->regs
+ WOL_REGS(port
, WOL_MAC_ADDR
),
767 sky2
->netdev
->dev_addr
, ETH_ALEN
);
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), WOL_CTL_CLEAR_RESULT
);
772 if (sky2
->wol
& WAKE_PHY
)
773 ctrl
|= WOL_CTL_ENA_PME_ON_LINK_CHG
|WOL_CTL_ENA_LINK_CHG_UNIT
;
775 ctrl
|= WOL_CTL_DIS_PME_ON_LINK_CHG
|WOL_CTL_DIS_LINK_CHG_UNIT
;
777 if (sky2
->wol
& WAKE_MAGIC
)
778 ctrl
|= WOL_CTL_ENA_PME_ON_MAGIC_PKT
|WOL_CTL_ENA_MAGIC_PKT_UNIT
;
780 ctrl
|= WOL_CTL_DIS_PME_ON_MAGIC_PKT
|WOL_CTL_DIS_MAGIC_PKT_UNIT
;
782 ctrl
|= WOL_CTL_DIS_PME_ON_PATTERN
|WOL_CTL_DIS_PATTERN_UNIT
;
783 sky2_write16(hw
, WOL_REGS(port
, WOL_CTRL_STAT
), ctrl
);
785 /* Turn on legacy PCI-Express PME mode */
786 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
787 reg1
|= PCI_Y2_PME_LEGACY
;
788 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
791 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
795 static void sky2_set_tx_stfwd(struct sky2_hw
*hw
, unsigned port
)
797 struct net_device
*dev
= hw
->dev
[port
];
799 if ( (hw
->chip_id
== CHIP_ID_YUKON_EX
&&
800 hw
->chip_rev
!= CHIP_REV_YU_EX_A0
) ||
801 hw
->chip_id
>= CHIP_ID_YUKON_FE_P
) {
802 /* Yukon-Extreme B0 and further Extreme devices */
803 /* enable Store & Forward mode for TX */
805 if (dev
->mtu
<= ETH_DATA_LEN
)
806 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
807 TX_JUMBO_DIS
| TX_STFW_ENA
);
810 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
811 TX_JUMBO_ENA
| TX_STFW_ENA
);
813 if (dev
->mtu
<= ETH_DATA_LEN
)
814 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_ENA
);
816 /* set Tx GMAC FIFO Almost Empty Threshold */
817 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
),
818 (ECU_JUMBO_WM
<< 16) | ECU_AE_THR
);
820 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
822 /* Can't do offload because of lack of store/forward */
823 dev
->features
&= ~(NETIF_F_TSO
| NETIF_F_SG
| NETIF_F_ALL_CSUM
);
828 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
830 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
834 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
836 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
837 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
);
839 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
841 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
842 /* WA DEV_472 -- looks like crossed wires on port 2 */
843 /* clear GMAC 1 Control reset */
844 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
846 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
847 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
848 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
849 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
850 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
853 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
855 /* Enable Transmit FIFO Underrun */
856 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
858 spin_lock_bh(&sky2
->phy_lock
);
859 sky2_phy_power_up(hw
, port
);
860 sky2_phy_init(hw
, port
);
861 spin_unlock_bh(&sky2
->phy_lock
);
864 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
865 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
867 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
868 gma_read16(hw
, port
, i
);
869 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
871 /* transmit control */
872 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
874 /* receive control reg: unicast + multicast + no FCS */
875 gma_write16(hw
, port
, GM_RX_CTRL
,
876 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
878 /* transmit flow control */
879 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
881 /* transmit parameter */
882 gma_write16(hw
, port
, GM_TX_PARAM
,
883 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
884 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
885 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
886 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
888 /* serial mode register */
889 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
890 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
892 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
893 reg
|= GM_SMOD_JUMBO_ENA
;
895 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
897 /* virtual address for data */
898 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
900 /* physical address: used for pause frames */
901 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
903 /* ignore counter overflows */
904 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
905 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
906 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
908 /* Configure Rx MAC FIFO */
909 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
910 rx_reg
= GMF_OPER_ON
| GMF_RX_F_FL_ON
;
911 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
912 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
913 rx_reg
|= GMF_RX_OVER_ON
;
915 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), rx_reg
);
917 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
918 /* Hardware errata - clear flush mask */
919 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), 0);
921 /* Flush Rx MAC FIFO on any flow control or error */
922 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
925 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
926 reg
= RX_GMF_FL_THR_DEF
+ 1;
927 /* Another magic mystery workaround from sk98lin */
928 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
929 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
931 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), reg
);
933 /* Configure Tx MAC FIFO */
934 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
935 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
937 /* On chips without ram buffer, pause is controled by MAC level */
938 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
)) {
939 /* Pause threshold is scaled by 8 in bytes */
940 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
941 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)
945 sky2_write16(hw
, SK_REG(port
, RX_GMF_UP_THR
), reg
);
946 sky2_write16(hw
, SK_REG(port
, RX_GMF_LP_THR
), 768 / 8);
948 sky2_set_tx_stfwd(hw
, port
);
951 if (hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
952 hw
->chip_rev
== CHIP_REV_YU_FE2_A0
) {
953 /* disable dynamic watermark */
954 reg
= sky2_read16(hw
, SK_REG(port
, TX_GMF_EA
));
955 reg
&= ~TX_DYN_WM_ENA
;
956 sky2_write16(hw
, SK_REG(port
, TX_GMF_EA
), reg
);
960 /* Assign Ram Buffer allocation to queue */
961 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u32 start
, u32 space
)
965 /* convert from K bytes to qwords used for hw register */
968 end
= start
+ space
- 1;
970 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
971 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
972 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
973 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
974 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
976 if (q
== Q_R1
|| q
== Q_R2
) {
977 u32 tp
= space
- space
/4;
979 /* On receive queue's set the thresholds
980 * give receiver priority when > 3/4 full
981 * send pause when down to 2K
983 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
984 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
987 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
988 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
990 /* Enable store & forward on Tx queue's because
991 * Tx FIFO is only 1K on Yukon
993 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
996 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
997 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
1000 /* Setup Bus Memory Interface */
1001 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
1003 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
1004 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
1005 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
1006 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
1009 /* Setup prefetch unit registers. This is the interface between
1010 * hardware and driver list elements
1012 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
1013 dma_addr_t addr
, u32 last
)
1015 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1016 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
1017 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), upper_32_bits(addr
));
1018 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), lower_32_bits(addr
));
1019 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
1020 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
1022 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
1025 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
, u16
*slot
)
1027 struct sky2_tx_le
*le
= sky2
->tx_le
+ *slot
;
1028 struct tx_ring_info
*re
= sky2
->tx_ring
+ *slot
;
1030 *slot
= RING_NEXT(*slot
, sky2
->tx_ring_size
);
1037 static void tx_init(struct sky2_port
*sky2
)
1039 struct sky2_tx_le
*le
;
1041 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1042 sky2
->tx_tcpsum
= 0;
1043 sky2
->tx_last_mss
= 0;
1045 le
= get_tx_le(sky2
, &sky2
->tx_prod
);
1047 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1048 sky2
->tx_last_upper
= 0;
1051 /* Update chip's next pointer */
1052 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
1054 /* Make sure write' to descriptors are complete before we tell hardware */
1056 sky2_write16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
), idx
);
1058 /* Synchronize I/O on since next processor may write to tail */
1063 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
1065 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
1066 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
1071 /* Build description to hardware for one receive segment */
1072 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
1073 dma_addr_t map
, unsigned len
)
1075 struct sky2_rx_le
*le
;
1077 if (sizeof(dma_addr_t
) > sizeof(u32
)) {
1078 le
= sky2_next_rx(sky2
);
1079 le
->addr
= cpu_to_le32(upper_32_bits(map
));
1080 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1083 le
= sky2_next_rx(sky2
);
1084 le
->addr
= cpu_to_le32(lower_32_bits(map
));
1085 le
->length
= cpu_to_le16(len
);
1086 le
->opcode
= op
| HW_OWNER
;
1089 /* Build description to hardware for one possibly fragmented skb */
1090 static void sky2_rx_submit(struct sky2_port
*sky2
,
1091 const struct rx_ring_info
*re
)
1095 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
1097 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
1098 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
1102 static int sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
1105 struct sk_buff
*skb
= re
->skb
;
1108 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
1109 if (unlikely(pci_dma_mapping_error(pdev
, re
->data_addr
)))
1112 pci_unmap_len_set(re
, data_size
, size
);
1114 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1115 re
->frag_addr
[i
] = pci_map_page(pdev
,
1116 skb_shinfo(skb
)->frags
[i
].page
,
1117 skb_shinfo(skb
)->frags
[i
].page_offset
,
1118 skb_shinfo(skb
)->frags
[i
].size
,
1119 PCI_DMA_FROMDEVICE
);
1123 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
1125 struct sk_buff
*skb
= re
->skb
;
1128 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
1129 PCI_DMA_FROMDEVICE
);
1131 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
1132 pci_unmap_page(pdev
, re
->frag_addr
[i
],
1133 skb_shinfo(skb
)->frags
[i
].size
,
1134 PCI_DMA_FROMDEVICE
);
1137 /* Tell chip where to start receive checksum.
1138 * Actually has two checksums, but set both same to avoid possible byte
1141 static void rx_set_checksum(struct sky2_port
*sky2
)
1143 struct sky2_rx_le
*le
= sky2_next_rx(sky2
);
1145 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
1147 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
1149 sky2_write32(sky2
->hw
,
1150 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
1151 (sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
)
1152 ? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
1156 * The RX Stop command will not work for Yukon-2 if the BMU does not
1157 * reach the end of packet and since we can't make sure that we have
1158 * incoming data, we must reset the BMU while it is not doing a DMA
1159 * transfer. Since it is possible that the RX path is still active,
1160 * the RX RAM buffer will be stopped first, so any possible incoming
1161 * data will not trigger a DMA. After the RAM buffer is stopped, the
1162 * BMU is polled until any DMA in progress is ended and only then it
1165 static void sky2_rx_stop(struct sky2_port
*sky2
)
1167 struct sky2_hw
*hw
= sky2
->hw
;
1168 unsigned rxq
= rxqaddr
[sky2
->port
];
1171 /* disable the RAM Buffer receive queue */
1172 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
1174 for (i
= 0; i
< 0xffff; i
++)
1175 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
1176 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
1179 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
1180 sky2
->netdev
->name
);
1182 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
1184 /* reset the Rx prefetch unit */
1185 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1189 /* Clean out receive buffer area, assumes receiver hardware stopped */
1190 static void sky2_rx_clean(struct sky2_port
*sky2
)
1194 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1195 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1196 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
1199 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1206 /* Basic MII support */
1207 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1209 struct mii_ioctl_data
*data
= if_mii(ifr
);
1210 struct sky2_port
*sky2
= netdev_priv(dev
);
1211 struct sky2_hw
*hw
= sky2
->hw
;
1212 int err
= -EOPNOTSUPP
;
1214 if (!netif_running(dev
))
1215 return -ENODEV
; /* Phy still in reset */
1219 data
->phy_id
= PHY_ADDR_MARV
;
1225 spin_lock_bh(&sky2
->phy_lock
);
1226 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
1227 spin_unlock_bh(&sky2
->phy_lock
);
1229 data
->val_out
= val
;
1234 spin_lock_bh(&sky2
->phy_lock
);
1235 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
1237 spin_unlock_bh(&sky2
->phy_lock
);
1243 #ifdef SKY2_VLAN_TAG_USED
1244 static void sky2_set_vlan_mode(struct sky2_hw
*hw
, u16 port
, bool onoff
)
1247 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1249 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1252 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
1254 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1259 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
1261 struct sky2_port
*sky2
= netdev_priv(dev
);
1262 struct sky2_hw
*hw
= sky2
->hw
;
1263 u16 port
= sky2
->port
;
1265 netif_tx_lock_bh(dev
);
1266 napi_disable(&hw
->napi
);
1269 sky2_set_vlan_mode(hw
, port
, grp
!= NULL
);
1271 sky2_read32(hw
, B0_Y2_SP_LISR
);
1272 napi_enable(&hw
->napi
);
1273 netif_tx_unlock_bh(dev
);
1277 /* Amount of required worst case padding in rx buffer */
1278 static inline unsigned sky2_rx_pad(const struct sky2_hw
*hw
)
1280 return (hw
->flags
& SKY2_HW_RAM_BUFFER
) ? 8 : 2;
1284 * Allocate an skb for receiving. If the MTU is large enough
1285 * make the skb non-linear with a fragment list of pages.
1287 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1289 struct sk_buff
*skb
;
1292 skb
= netdev_alloc_skb(sky2
->netdev
,
1293 sky2
->rx_data_size
+ sky2_rx_pad(sky2
->hw
));
1297 if (sky2
->hw
->flags
& SKY2_HW_RAM_BUFFER
) {
1298 unsigned char *start
;
1300 * Workaround for a bug in FIFO that cause hang
1301 * if the FIFO if the receive buffer is not 64 byte aligned.
1302 * The buffer returned from netdev_alloc_skb is
1303 * aligned except if slab debugging is enabled.
1305 start
= PTR_ALIGN(skb
->data
, 8);
1306 skb_reserve(skb
, start
- skb
->data
);
1308 skb_reserve(skb
, NET_IP_ALIGN
);
1310 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1311 struct page
*page
= alloc_page(GFP_ATOMIC
);
1315 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1325 static inline void sky2_rx_update(struct sky2_port
*sky2
, unsigned rxq
)
1327 sky2_put_idx(sky2
->hw
, rxq
, sky2
->rx_put
);
1331 * Allocate and setup receiver buffer pool.
1332 * Normal case this ends up creating one list element for skb
1333 * in the receive ring. Worst case if using large MTU and each
1334 * allocation falls on a different 64 bit region, that results
1335 * in 6 list elements per ring entry.
1336 * One element is used for checksum enable/disable, and one
1337 * extra to avoid wrap.
1339 static int sky2_rx_start(struct sky2_port
*sky2
)
1341 struct sky2_hw
*hw
= sky2
->hw
;
1342 struct rx_ring_info
*re
;
1343 unsigned rxq
= rxqaddr
[sky2
->port
];
1344 unsigned i
, size
, thresh
;
1346 sky2
->rx_put
= sky2
->rx_next
= 0;
1349 /* On PCI express lowering the watermark gives better performance */
1350 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
1351 sky2_write32(hw
, Q_ADDR(rxq
, Q_WM
), BMU_WM_PEX
);
1353 /* These chips have no ram buffer?
1354 * MAC Rx RAM Read is controlled by hardware */
1355 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1356 (hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
||
1357 hw
->chip_rev
== CHIP_REV_YU_EC_U_B0
))
1358 sky2_write32(hw
, Q_ADDR(rxq
, Q_TEST
), F_M_RX_RAM_DIS
);
1360 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1362 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1363 rx_set_checksum(sky2
);
1365 /* Space needed for frame data + headers rounded up */
1366 size
= roundup(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8);
1368 /* Stopping point for hardware truncation */
1369 thresh
= (size
- 8) / sizeof(u32
);
1371 sky2
->rx_nfrags
= size
>> PAGE_SHIFT
;
1372 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1374 /* Compute residue after pages */
1375 size
-= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1377 /* Optimize to handle small packets and headers */
1378 if (size
< copybreak
)
1380 if (size
< ETH_HLEN
)
1383 sky2
->rx_data_size
= size
;
1386 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1387 re
= sky2
->rx_ring
+ i
;
1389 re
->skb
= sky2_rx_alloc(sky2
);
1393 if (sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
)) {
1394 dev_kfree_skb(re
->skb
);
1399 sky2_rx_submit(sky2
, re
);
1403 * The receiver hangs if it receives frames larger than the
1404 * packet buffer. As a workaround, truncate oversize frames, but
1405 * the register is limited to 9 bits, so if you do frames > 2052
1406 * you better get the MTU right!
1409 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1411 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1412 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1415 /* Tell chip about available buffers */
1416 sky2_rx_update(sky2
, rxq
);
1418 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
1419 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
1421 * Disable flushing of non ASF packets;
1422 * must be done after initializing the BMUs;
1423 * drivers without ASF support should do this too, otherwise
1424 * it may happen that they cannot run on ASF devices;
1425 * remember that the MAC FIFO isn't reset during initialization.
1427 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_MACSEC_FLUSH_OFF
);
1430 if (hw
->chip_id
>= CHIP_ID_YUKON_SUPR
) {
1431 /* Enable RX Home Address & Routing Header checksum fix */
1432 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_FL_CTRL
),
1433 RX_IPV6_SA_MOB_ENA
| RX_IPV6_DA_MOB_ENA
);
1435 /* Enable TX Home Address & Routing Header checksum fix */
1436 sky2_write32(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_TEST
),
1437 TBMU_TEST_HOME_ADD_FIX_EN
| TBMU_TEST_ROUTING_ADD_FIX_EN
);
1444 sky2_rx_clean(sky2
);
1448 static int sky2_alloc_buffers(struct sky2_port
*sky2
)
1450 struct sky2_hw
*hw
= sky2
->hw
;
1452 /* must be power of 2 */
1453 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1454 sky2
->tx_ring_size
*
1455 sizeof(struct sky2_tx_le
),
1460 sky2
->tx_ring
= kcalloc(sky2
->tx_ring_size
, sizeof(struct tx_ring_info
),
1465 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1469 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1471 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1481 static void sky2_free_buffers(struct sky2_port
*sky2
)
1483 struct sky2_hw
*hw
= sky2
->hw
;
1486 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1487 sky2
->rx_le
, sky2
->rx_le_map
);
1491 pci_free_consistent(hw
->pdev
,
1492 sky2
->tx_ring_size
* sizeof(struct sky2_tx_le
),
1493 sky2
->tx_le
, sky2
->tx_le_map
);
1496 kfree(sky2
->tx_ring
);
1497 kfree(sky2
->rx_ring
);
1499 sky2
->tx_ring
= NULL
;
1500 sky2
->rx_ring
= NULL
;
1503 /* Bring up network interface. */
1504 static int sky2_up(struct net_device
*dev
)
1506 struct sky2_port
*sky2
= netdev_priv(dev
);
1507 struct sky2_hw
*hw
= sky2
->hw
;
1508 unsigned port
= sky2
->port
;
1511 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1514 * On dual port PCI-X card, there is an problem where status
1515 * can be received out of order due to split transactions
1517 if (otherdev
&& netif_running(otherdev
) &&
1518 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1521 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1522 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1523 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1527 netif_carrier_off(dev
);
1529 err
= sky2_alloc_buffers(sky2
);
1535 sky2_mac_init(hw
, port
);
1537 /* Register is number of 4K blocks on internal RAM buffer. */
1538 ramsize
= sky2_read8(hw
, B2_E_0
) * 4;
1542 pr_debug(PFX
"%s: ram buffer %dK\n", dev
->name
, ramsize
);
1544 rxspace
= ramsize
/ 2;
1546 rxspace
= 8 + (2*(ramsize
- 16))/3;
1548 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1549 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
- rxspace
);
1551 /* Make sure SyncQ is disabled */
1552 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1556 sky2_qset(hw
, txqaddr
[port
]);
1558 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1559 if (hw
->chip_id
== CHIP_ID_YUKON_EX
&& hw
->chip_rev
== CHIP_REV_YU_EX_B0
)
1560 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_TEST
), F_TX_CHK_AUTO_OFF
);
1562 /* Set almost empty threshold */
1563 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&&
1564 hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1565 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), ECU_TXFF_LEV
);
1567 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1568 sky2
->tx_ring_size
- 1);
1570 #ifdef SKY2_VLAN_TAG_USED
1571 sky2_set_vlan_mode(hw
, port
, sky2
->vlgrp
!= NULL
);
1574 err
= sky2_rx_start(sky2
);
1578 /* Enable interrupts from phy/mac for port */
1579 imask
= sky2_read32(hw
, B0_IMSK
);
1580 imask
|= portirq_msk
[port
];
1581 sky2_write32(hw
, B0_IMSK
, imask
);
1582 sky2_read32(hw
, B0_IMSK
);
1584 if (netif_msg_ifup(sky2
))
1585 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1590 sky2_free_buffers(sky2
);
1594 /* Modular subtraction in ring */
1595 static inline int tx_inuse(const struct sky2_port
*sky2
)
1597 return (sky2
->tx_prod
- sky2
->tx_cons
) & (sky2
->tx_ring_size
- 1);
1600 /* Number of list elements available for next tx */
1601 static inline int tx_avail(const struct sky2_port
*sky2
)
1603 return sky2
->tx_pending
- tx_inuse(sky2
);
1606 /* Estimate of number of transmit list elements required */
1607 static unsigned tx_le_req(const struct sk_buff
*skb
)
1611 count
= (skb_shinfo(skb
)->nr_frags
+ 1)
1612 * (sizeof(dma_addr_t
) / sizeof(u32
));
1614 if (skb_is_gso(skb
))
1616 else if (sizeof(dma_addr_t
) == sizeof(u32
))
1617 ++count
; /* possible vlan */
1619 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1625 static void sky2_tx_unmap(struct pci_dev
*pdev
,
1626 const struct tx_ring_info
*re
)
1628 if (re
->flags
& TX_MAP_SINGLE
)
1629 pci_unmap_single(pdev
, pci_unmap_addr(re
, mapaddr
),
1630 pci_unmap_len(re
, maplen
),
1632 else if (re
->flags
& TX_MAP_PAGE
)
1633 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1634 pci_unmap_len(re
, maplen
),
1639 * Put one packet in ring for transmit.
1640 * A single packet can generate multiple list elements, and
1641 * the number of ring elements will probably be less than the number
1642 * of list elements used.
1644 static netdev_tx_t
sky2_xmit_frame(struct sk_buff
*skb
,
1645 struct net_device
*dev
)
1647 struct sky2_port
*sky2
= netdev_priv(dev
);
1648 struct sky2_hw
*hw
= sky2
->hw
;
1649 struct sky2_tx_le
*le
= NULL
;
1650 struct tx_ring_info
*re
;
1658 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1659 return NETDEV_TX_BUSY
;
1661 len
= skb_headlen(skb
);
1662 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1664 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1667 slot
= sky2
->tx_prod
;
1668 if (unlikely(netif_msg_tx_queued(sky2
)))
1669 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1670 dev
->name
, slot
, skb
->len
);
1672 /* Send high bits if needed */
1673 upper
= upper_32_bits(mapping
);
1674 if (upper
!= sky2
->tx_last_upper
) {
1675 le
= get_tx_le(sky2
, &slot
);
1676 le
->addr
= cpu_to_le32(upper
);
1677 sky2
->tx_last_upper
= upper
;
1678 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1681 /* Check for TCP Segmentation Offload */
1682 mss
= skb_shinfo(skb
)->gso_size
;
1685 if (!(hw
->flags
& SKY2_HW_NEW_LE
))
1686 mss
+= ETH_HLEN
+ ip_hdrlen(skb
) + tcp_hdrlen(skb
);
1688 if (mss
!= sky2
->tx_last_mss
) {
1689 le
= get_tx_le(sky2
, &slot
);
1690 le
->addr
= cpu_to_le32(mss
);
1692 if (hw
->flags
& SKY2_HW_NEW_LE
)
1693 le
->opcode
= OP_MSS
| HW_OWNER
;
1695 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1696 sky2
->tx_last_mss
= mss
;
1701 #ifdef SKY2_VLAN_TAG_USED
1702 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1703 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1705 le
= get_tx_le(sky2
, &slot
);
1707 le
->opcode
= OP_VLAN
|HW_OWNER
;
1709 le
->opcode
|= OP_VLAN
;
1710 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1715 /* Handle TCP checksum offload */
1716 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1717 /* On Yukon EX (some versions) encoding change. */
1718 if (hw
->flags
& SKY2_HW_AUTO_TX_SUM
)
1719 ctrl
|= CALSUM
; /* auto checksum */
1721 const unsigned offset
= skb_transport_offset(skb
);
1724 tcpsum
= offset
<< 16; /* sum start */
1725 tcpsum
|= offset
+ skb
->csum_offset
; /* sum write */
1727 ctrl
|= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1728 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
)
1731 if (tcpsum
!= sky2
->tx_tcpsum
) {
1732 sky2
->tx_tcpsum
= tcpsum
;
1734 le
= get_tx_le(sky2
, &slot
);
1735 le
->addr
= cpu_to_le32(tcpsum
);
1736 le
->length
= 0; /* initial checksum value */
1737 le
->ctrl
= 1; /* one packet */
1738 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1743 re
= sky2
->tx_ring
+ slot
;
1744 re
->flags
= TX_MAP_SINGLE
;
1745 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1746 pci_unmap_len_set(re
, maplen
, len
);
1748 le
= get_tx_le(sky2
, &slot
);
1749 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1750 le
->length
= cpu_to_le16(len
);
1752 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1755 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1756 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1758 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1759 frag
->size
, PCI_DMA_TODEVICE
);
1761 if (pci_dma_mapping_error(hw
->pdev
, mapping
))
1762 goto mapping_unwind
;
1764 upper
= upper_32_bits(mapping
);
1765 if (upper
!= sky2
->tx_last_upper
) {
1766 le
= get_tx_le(sky2
, &slot
);
1767 le
->addr
= cpu_to_le32(upper
);
1768 sky2
->tx_last_upper
= upper
;
1769 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1772 re
= sky2
->tx_ring
+ slot
;
1773 re
->flags
= TX_MAP_PAGE
;
1774 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1775 pci_unmap_len_set(re
, maplen
, frag
->size
);
1777 le
= get_tx_le(sky2
, &slot
);
1778 le
->addr
= cpu_to_le32(lower_32_bits(mapping
));
1779 le
->length
= cpu_to_le16(frag
->size
);
1781 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1787 sky2
->tx_prod
= slot
;
1789 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1790 netif_stop_queue(dev
);
1792 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1794 return NETDEV_TX_OK
;
1797 for (i
= sky2
->tx_prod
; i
!= slot
; i
= RING_NEXT(i
, sky2
->tx_ring_size
)) {
1798 re
= sky2
->tx_ring
+ i
;
1800 sky2_tx_unmap(hw
->pdev
, re
);
1804 if (net_ratelimit())
1805 dev_warn(&hw
->pdev
->dev
, "%s: tx mapping error\n", dev
->name
);
1807 return NETDEV_TX_OK
;
1811 * Free ring elements from starting at tx_cons until "done"
1814 * 1. The hardware will tell us about partial completion of multi-part
1815 * buffers so make sure not to free skb to early.
1816 * 2. This may run in parallel start_xmit because the it only
1817 * looks at the tail of the queue of FIFO (tx_cons), not
1818 * the head (tx_prod)
1820 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1822 struct net_device
*dev
= sky2
->netdev
;
1825 BUG_ON(done
>= sky2
->tx_ring_size
);
1827 for (idx
= sky2
->tx_cons
; idx
!= done
;
1828 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
1829 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1830 struct sk_buff
*skb
= re
->skb
;
1832 sky2_tx_unmap(sky2
->hw
->pdev
, re
);
1835 if (unlikely(netif_msg_tx_done(sky2
)))
1836 printk(KERN_DEBUG
"%s: tx done %u\n",
1839 dev
->stats
.tx_packets
++;
1840 dev
->stats
.tx_bytes
+= skb
->len
;
1842 dev_kfree_skb_any(skb
);
1844 sky2
->tx_next
= RING_NEXT(idx
, sky2
->tx_ring_size
);
1848 sky2
->tx_cons
= idx
;
1851 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1852 netif_wake_queue(dev
);
1855 static void sky2_tx_reset(struct sky2_hw
*hw
, unsigned port
)
1857 /* Disable Force Sync bit and Enable Alloc bit */
1858 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1859 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1861 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1862 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1863 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1865 /* Reset the PCI FIFO of the async Tx queue */
1866 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1867 BMU_RST_SET
| BMU_FIFO_RST
);
1869 /* Reset the Tx prefetch units */
1870 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1873 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1874 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1877 /* Network shutdown */
1878 static int sky2_down(struct net_device
*dev
)
1880 struct sky2_port
*sky2
= netdev_priv(dev
);
1881 struct sky2_hw
*hw
= sky2
->hw
;
1882 unsigned port
= sky2
->port
;
1886 /* Never really got started! */
1890 if (netif_msg_ifdown(sky2
))
1891 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1893 /* Force flow control off */
1894 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1896 /* Stop transmitter */
1897 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1898 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1900 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1901 RB_RST_SET
| RB_DIS_OP_MD
);
1903 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1904 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1905 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1907 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1909 /* Workaround shared GMAC reset */
1910 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 &&
1911 port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1912 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1914 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1916 /* Force any delayed status interrrupt and NAPI */
1917 sky2_write32(hw
, STAT_LEV_TIMER_CNT
, 0);
1918 sky2_write32(hw
, STAT_TX_TIMER_CNT
, 0);
1919 sky2_write32(hw
, STAT_ISR_TIMER_CNT
, 0);
1920 sky2_read8(hw
, STAT_ISR_TIMER_CTRL
);
1924 /* Disable port IRQ */
1925 imask
= sky2_read32(hw
, B0_IMSK
);
1926 imask
&= ~portirq_msk
[port
];
1927 sky2_write32(hw
, B0_IMSK
, imask
);
1928 sky2_read32(hw
, B0_IMSK
);
1930 synchronize_irq(hw
->pdev
->irq
);
1931 napi_synchronize(&hw
->napi
);
1933 spin_lock_bh(&sky2
->phy_lock
);
1934 sky2_phy_power_down(hw
, port
);
1935 spin_unlock_bh(&sky2
->phy_lock
);
1937 sky2_tx_reset(hw
, port
);
1939 /* Free any pending frames stuck in HW queue */
1940 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1942 sky2_rx_clean(sky2
);
1944 sky2_free_buffers(sky2
);
1949 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1951 if (hw
->flags
& SKY2_HW_FIBRE_PHY
)
1954 if (!(hw
->flags
& SKY2_HW_GIGABIT
)) {
1955 if (aux
& PHY_M_PS_SPEED_100
)
1961 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1962 case PHY_M_PS_SPEED_1000
:
1964 case PHY_M_PS_SPEED_100
:
1971 static void sky2_link_up(struct sky2_port
*sky2
)
1973 struct sky2_hw
*hw
= sky2
->hw
;
1974 unsigned port
= sky2
->port
;
1976 static const char *fc_name
[] = {
1984 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1985 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1986 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1988 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1990 netif_carrier_on(sky2
->netdev
);
1992 mod_timer(&hw
->watchdog_timer
, jiffies
+ 1);
1994 /* Turn on link LED */
1995 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1996 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1998 if (netif_msg_link(sky2
))
1999 printk(KERN_INFO PFX
2000 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2001 sky2
->netdev
->name
, sky2
->speed
,
2002 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
2003 fc_name
[sky2
->flow_status
]);
2006 static void sky2_link_down(struct sky2_port
*sky2
)
2008 struct sky2_hw
*hw
= sky2
->hw
;
2009 unsigned port
= sky2
->port
;
2012 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
2014 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
2015 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
2016 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
2018 netif_carrier_off(sky2
->netdev
);
2020 /* Turn off link LED */
2021 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
2023 if (netif_msg_link(sky2
))
2024 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
2026 sky2_phy_init(hw
, port
);
2029 static enum flow_control
sky2_flow(int rx
, int tx
)
2032 return tx
? FC_BOTH
: FC_RX
;
2034 return tx
? FC_TX
: FC_NONE
;
2037 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
2039 struct sky2_hw
*hw
= sky2
->hw
;
2040 unsigned port
= sky2
->port
;
2043 advert
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
2044 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
2045 if (lpa
& PHY_M_AN_RF
) {
2046 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
2050 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
2051 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
2052 sky2
->netdev
->name
);
2056 sky2
->speed
= sky2_phy_speed(hw
, aux
);
2057 sky2
->duplex
= (aux
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2059 /* Since the pause result bits seem to in different positions on
2060 * different chips. look at registers.
2062 if (hw
->flags
& SKY2_HW_FIBRE_PHY
) {
2063 /* Shift for bits in fiber PHY */
2064 advert
&= ~(ADVERTISE_PAUSE_CAP
|ADVERTISE_PAUSE_ASYM
);
2065 lpa
&= ~(LPA_PAUSE_CAP
|LPA_PAUSE_ASYM
);
2067 if (advert
& ADVERTISE_1000XPAUSE
)
2068 advert
|= ADVERTISE_PAUSE_CAP
;
2069 if (advert
& ADVERTISE_1000XPSE_ASYM
)
2070 advert
|= ADVERTISE_PAUSE_ASYM
;
2071 if (lpa
& LPA_1000XPAUSE
)
2072 lpa
|= LPA_PAUSE_CAP
;
2073 if (lpa
& LPA_1000XPAUSE_ASYM
)
2074 lpa
|= LPA_PAUSE_ASYM
;
2077 sky2
->flow_status
= FC_NONE
;
2078 if (advert
& ADVERTISE_PAUSE_CAP
) {
2079 if (lpa
& LPA_PAUSE_CAP
)
2080 sky2
->flow_status
= FC_BOTH
;
2081 else if (advert
& ADVERTISE_PAUSE_ASYM
)
2082 sky2
->flow_status
= FC_RX
;
2083 } else if (advert
& ADVERTISE_PAUSE_ASYM
) {
2084 if ((lpa
& LPA_PAUSE_CAP
) && (lpa
& LPA_PAUSE_ASYM
))
2085 sky2
->flow_status
= FC_TX
;
2088 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
< SPEED_1000
&&
2089 !(hw
->chip_id
== CHIP_ID_YUKON_EC_U
|| hw
->chip_id
== CHIP_ID_YUKON_EX
))
2090 sky2
->flow_status
= FC_NONE
;
2092 if (sky2
->flow_status
& FC_TX
)
2093 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
2095 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
2100 /* Interrupt from PHY */
2101 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
2103 struct net_device
*dev
= hw
->dev
[port
];
2104 struct sky2_port
*sky2
= netdev_priv(dev
);
2105 u16 istatus
, phystat
;
2107 if (!netif_running(dev
))
2110 spin_lock(&sky2
->phy_lock
);
2111 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
2112 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
2114 if (netif_msg_intr(sky2
))
2115 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
2116 sky2
->netdev
->name
, istatus
, phystat
);
2118 if (istatus
& PHY_M_IS_AN_COMPL
) {
2119 if (sky2_autoneg_done(sky2
, phystat
) == 0)
2124 if (istatus
& PHY_M_IS_LSP_CHANGE
)
2125 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
2127 if (istatus
& PHY_M_IS_DUP_CHANGE
)
2129 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
2131 if (istatus
& PHY_M_IS_LST_CHANGE
) {
2132 if (phystat
& PHY_M_PS_LINK_UP
)
2135 sky2_link_down(sky2
);
2138 spin_unlock(&sky2
->phy_lock
);
2141 /* Special quick link interrupt (Yukon-2 Optima only) */
2142 static void sky2_qlink_intr(struct sky2_hw
*hw
)
2144 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[0]);
2149 imask
= sky2_read32(hw
, B0_IMSK
);
2150 imask
&= ~Y2_IS_PHY_QLNK
;
2151 sky2_write32(hw
, B0_IMSK
, imask
);
2153 /* reset PHY Link Detect */
2154 phy
= sky2_pci_read16(hw
, PSM_CONFIG_REG4
);
2155 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, phy
| 1);
2160 /* Transmit timeout is only called if we are running, carrier is up
2161 * and tx queue is full (stopped).
2163 static void sky2_tx_timeout(struct net_device
*dev
)
2165 struct sky2_port
*sky2
= netdev_priv(dev
);
2166 struct sky2_hw
*hw
= sky2
->hw
;
2168 if (netif_msg_timer(sky2
))
2169 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
2171 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
2172 dev
->name
, sky2
->tx_cons
, sky2
->tx_prod
,
2173 sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
2174 sky2_read16(hw
, Q_ADDR(txqaddr
[sky2
->port
], Q_DONE
)));
2176 /* can't restart safely under softirq */
2177 schedule_work(&hw
->restart_work
);
2180 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
2182 struct sky2_port
*sky2
= netdev_priv(dev
);
2183 struct sky2_hw
*hw
= sky2
->hw
;
2184 unsigned port
= sky2
->port
;
2189 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
2192 if (new_mtu
> ETH_DATA_LEN
&&
2193 (hw
->chip_id
== CHIP_ID_YUKON_FE
||
2194 hw
->chip_id
== CHIP_ID_YUKON_FE_P
))
2197 if (!netif_running(dev
)) {
2202 imask
= sky2_read32(hw
, B0_IMSK
);
2203 sky2_write32(hw
, B0_IMSK
, 0);
2205 dev
->trans_start
= jiffies
; /* prevent tx timeout */
2206 netif_stop_queue(dev
);
2207 napi_disable(&hw
->napi
);
2209 synchronize_irq(hw
->pdev
->irq
);
2211 if (!(hw
->flags
& SKY2_HW_RAM_BUFFER
))
2212 sky2_set_tx_stfwd(hw
, port
);
2214 ctl
= gma_read16(hw
, port
, GM_GP_CTRL
);
2215 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
2217 sky2_rx_clean(sky2
);
2221 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
2222 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
2224 if (dev
->mtu
> ETH_DATA_LEN
)
2225 mode
|= GM_SMOD_JUMBO_ENA
;
2227 gma_write16(hw
, port
, GM_SERIAL_MODE
, mode
);
2229 sky2_write8(hw
, RB_ADDR(rxqaddr
[port
], RB_CTRL
), RB_ENA_OP_MD
);
2231 err
= sky2_rx_start(sky2
);
2232 sky2_write32(hw
, B0_IMSK
, imask
);
2234 sky2_read32(hw
, B0_Y2_SP_LISR
);
2235 napi_enable(&hw
->napi
);
2240 gma_write16(hw
, port
, GM_GP_CTRL
, ctl
);
2242 netif_wake_queue(dev
);
2248 /* For small just reuse existing skb for next receive */
2249 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
2250 const struct rx_ring_info
*re
,
2253 struct sk_buff
*skb
;
2255 skb
= netdev_alloc_skb_ip_align(sky2
->netdev
, length
);
2257 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
2258 length
, PCI_DMA_FROMDEVICE
);
2259 skb_copy_from_linear_data(re
->skb
, skb
->data
, length
);
2260 skb
->ip_summed
= re
->skb
->ip_summed
;
2261 skb
->csum
= re
->skb
->csum
;
2262 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
2263 length
, PCI_DMA_FROMDEVICE
);
2264 re
->skb
->ip_summed
= CHECKSUM_NONE
;
2265 skb_put(skb
, length
);
2270 /* Adjust length of skb with fragments to match received data */
2271 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
2272 unsigned int length
)
2277 /* put header into skb */
2278 size
= min(length
, hdr_space
);
2283 num_frags
= skb_shinfo(skb
)->nr_frags
;
2284 for (i
= 0; i
< num_frags
; i
++) {
2285 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
2288 /* don't need this page */
2289 __free_page(frag
->page
);
2290 --skb_shinfo(skb
)->nr_frags
;
2292 size
= min(length
, (unsigned) PAGE_SIZE
);
2295 skb
->data_len
+= size
;
2296 skb
->truesize
+= size
;
2303 /* Normal packet - take skb from ring element and put in a new one */
2304 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
2305 struct rx_ring_info
*re
,
2306 unsigned int length
)
2308 struct sk_buff
*skb
, *nskb
;
2309 unsigned hdr_space
= sky2
->rx_data_size
;
2311 /* Don't be tricky about reusing pages (yet) */
2312 nskb
= sky2_rx_alloc(sky2
);
2313 if (unlikely(!nskb
))
2317 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
2319 prefetch(skb
->data
);
2321 if (sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
)) {
2322 dev_kfree_skb(nskb
);
2327 if (skb_shinfo(skb
)->nr_frags
)
2328 skb_put_frags(skb
, hdr_space
, length
);
2330 skb_put(skb
, length
);
2335 * Receive one packet.
2336 * For larger packets, get new buffer.
2338 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
2339 u16 length
, u32 status
)
2341 struct sky2_port
*sky2
= netdev_priv(dev
);
2342 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
2343 struct sk_buff
*skb
= NULL
;
2344 u16 count
= (status
& GMR_FS_LEN
) >> 16;
2346 #ifdef SKY2_VLAN_TAG_USED
2347 /* Account for vlan tag */
2348 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
))
2352 if (unlikely(netif_msg_rx_status(sky2
)))
2353 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
2354 dev
->name
, sky2
->rx_next
, status
, length
);
2356 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
2357 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
2359 /* This chip has hardware problems that generates bogus status.
2360 * So do only marginal checking and expect higher level protocols
2361 * to handle crap frames.
2363 if (sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
2364 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
&&
2368 if (status
& GMR_FS_ANY_ERR
)
2371 if (!(status
& GMR_FS_RX_OK
))
2374 /* if length reported by DMA does not match PHY, packet was truncated */
2375 if (length
!= count
)
2379 if (length
< copybreak
)
2380 skb
= receive_copy(sky2
, re
, length
);
2382 skb
= receive_new(sky2
, re
, length
);
2384 sky2_rx_submit(sky2
, re
);
2389 /* Truncation of overlength packets
2390 causes PHY length to not match MAC length */
2391 ++dev
->stats
.rx_length_errors
;
2392 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2393 pr_info(PFX
"%s: rx length error: status %#x length %d\n",
2394 dev
->name
, status
, length
);
2398 ++dev
->stats
.rx_errors
;
2399 if (status
& GMR_FS_RX_FF_OV
) {
2400 dev
->stats
.rx_over_errors
++;
2404 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2405 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2406 dev
->name
, status
, length
);
2408 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2409 dev
->stats
.rx_length_errors
++;
2410 if (status
& GMR_FS_FRAGMENT
)
2411 dev
->stats
.rx_frame_errors
++;
2412 if (status
& GMR_FS_CRC_ERR
)
2413 dev
->stats
.rx_crc_errors
++;
2418 /* Transmit complete */
2419 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2421 struct sky2_port
*sky2
= netdev_priv(dev
);
2423 if (netif_running(dev
))
2424 sky2_tx_complete(sky2
, last
);
2427 static inline void sky2_skb_rx(const struct sky2_port
*sky2
,
2428 u32 status
, struct sk_buff
*skb
)
2430 #ifdef SKY2_VLAN_TAG_USED
2431 u16 vlan_tag
= be16_to_cpu(sky2
->rx_tag
);
2432 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2433 if (skb
->ip_summed
== CHECKSUM_NONE
)
2434 vlan_hwaccel_receive_skb(skb
, sky2
->vlgrp
, vlan_tag
);
2436 vlan_gro_receive(&sky2
->hw
->napi
, sky2
->vlgrp
,
2441 if (skb
->ip_summed
== CHECKSUM_NONE
)
2442 netif_receive_skb(skb
);
2444 napi_gro_receive(&sky2
->hw
->napi
, skb
);
2447 static inline void sky2_rx_done(struct sky2_hw
*hw
, unsigned port
,
2448 unsigned packets
, unsigned bytes
)
2451 struct net_device
*dev
= hw
->dev
[port
];
2453 dev
->stats
.rx_packets
+= packets
;
2454 dev
->stats
.rx_bytes
+= bytes
;
2455 dev
->last_rx
= jiffies
;
2456 sky2_rx_update(netdev_priv(dev
), rxqaddr
[port
]);
2460 /* Process status response ring */
2461 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
, u16 idx
)
2464 unsigned int total_bytes
[2] = { 0 };
2465 unsigned int total_packets
[2] = { 0 };
2469 struct sky2_port
*sky2
;
2470 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2472 struct net_device
*dev
;
2473 struct sk_buff
*skb
;
2476 u8 opcode
= le
->opcode
;
2478 if (!(opcode
& HW_OWNER
))
2481 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2483 port
= le
->css
& CSS_LINK_BIT
;
2484 dev
= hw
->dev
[port
];
2485 sky2
= netdev_priv(dev
);
2486 length
= le16_to_cpu(le
->length
);
2487 status
= le32_to_cpu(le
->status
);
2490 switch (opcode
& ~HW_OWNER
) {
2492 total_packets
[port
]++;
2493 total_bytes
[port
] += length
;
2494 skb
= sky2_receive(dev
, length
, status
);
2495 if (unlikely(!skb
)) {
2496 dev
->stats
.rx_dropped
++;
2500 /* This chip reports checksum status differently */
2501 if (hw
->flags
& SKY2_HW_NEW_LE
) {
2502 if ((sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
) &&
2503 (le
->css
& (CSS_ISIPV4
| CSS_ISIPV6
)) &&
2504 (le
->css
& CSS_TCPUDPCSOK
))
2505 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2507 skb
->ip_summed
= CHECKSUM_NONE
;
2510 skb
->protocol
= eth_type_trans(skb
, dev
);
2512 sky2_skb_rx(sky2
, status
, skb
);
2514 /* Stop after net poll weight */
2515 if (++work_done
>= to_do
)
2519 #ifdef SKY2_VLAN_TAG_USED
2521 sky2
->rx_tag
= length
;
2525 sky2
->rx_tag
= length
;
2529 if (!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
))
2532 /* If this happens then driver assuming wrong format */
2533 if (unlikely(hw
->flags
& SKY2_HW_NEW_LE
)) {
2534 if (net_ratelimit())
2535 printk(KERN_NOTICE
"%s: unexpected"
2536 " checksum status\n",
2541 /* Both checksum counters are programmed to start at
2542 * the same offset, so unless there is a problem they
2543 * should match. This failure is an early indication that
2544 * hardware receive checksumming won't work.
2546 if (likely(status
>> 16 == (status
& 0xffff))) {
2547 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2548 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2549 skb
->csum
= le16_to_cpu(status
);
2551 printk(KERN_NOTICE PFX
"%s: hardware receive "
2552 "checksum problem (status = %#x)\n",
2554 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
2556 sky2_write32(sky2
->hw
,
2557 Q_ADDR(rxqaddr
[port
], Q_CSR
),
2563 /* TX index reports status for both ports */
2564 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2566 sky2_tx_done(hw
->dev
[1],
2567 ((status
>> 24) & 0xff)
2568 | (u16
)(length
& 0xf) << 8);
2572 if (net_ratelimit())
2573 printk(KERN_WARNING PFX
2574 "unknown status opcode 0x%x\n", opcode
);
2576 } while (hw
->st_idx
!= idx
);
2578 /* Fully processed status ring so clear irq */
2579 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2582 sky2_rx_done(hw
, 0, total_packets
[0], total_bytes
[0]);
2583 sky2_rx_done(hw
, 1, total_packets
[1], total_bytes
[1]);
2588 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2590 struct net_device
*dev
= hw
->dev
[port
];
2592 if (net_ratelimit())
2593 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2596 if (status
& Y2_IS_PAR_RD1
) {
2597 if (net_ratelimit())
2598 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2601 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2604 if (status
& Y2_IS_PAR_WR1
) {
2605 if (net_ratelimit())
2606 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2609 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2612 if (status
& Y2_IS_PAR_MAC1
) {
2613 if (net_ratelimit())
2614 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2615 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2618 if (status
& Y2_IS_PAR_RX1
) {
2619 if (net_ratelimit())
2620 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2621 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2624 if (status
& Y2_IS_TCP_TXA1
) {
2625 if (net_ratelimit())
2626 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2628 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2632 static void sky2_hw_intr(struct sky2_hw
*hw
)
2634 struct pci_dev
*pdev
= hw
->pdev
;
2635 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2636 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2640 if (status
& Y2_IS_TIST_OV
)
2641 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2643 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2646 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2647 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2648 if (net_ratelimit())
2649 dev_err(&pdev
->dev
, "PCI hardware error (0x%x)\n",
2652 sky2_pci_write16(hw
, PCI_STATUS
,
2653 pci_err
| PCI_STATUS_ERROR_BITS
);
2654 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2657 if (status
& Y2_IS_PCI_EXP
) {
2658 /* PCI-Express uncorrectable Error occurred */
2661 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2662 err
= sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2663 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
2665 if (net_ratelimit())
2666 dev_err(&pdev
->dev
, "PCI Express error (0x%x)\n", err
);
2668 sky2_read32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
);
2669 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2672 if (status
& Y2_HWE_L1_MASK
)
2673 sky2_hw_error(hw
, 0, status
);
2675 if (status
& Y2_HWE_L1_MASK
)
2676 sky2_hw_error(hw
, 1, status
);
2679 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2681 struct net_device
*dev
= hw
->dev
[port
];
2682 struct sky2_port
*sky2
= netdev_priv(dev
);
2683 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2685 if (netif_msg_intr(sky2
))
2686 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2689 if (status
& GM_IS_RX_CO_OV
)
2690 gma_read16(hw
, port
, GM_RX_IRQ_SRC
);
2692 if (status
& GM_IS_TX_CO_OV
)
2693 gma_read16(hw
, port
, GM_TX_IRQ_SRC
);
2695 if (status
& GM_IS_RX_FF_OR
) {
2696 ++dev
->stats
.rx_fifo_errors
;
2697 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2700 if (status
& GM_IS_TX_FF_UR
) {
2701 ++dev
->stats
.tx_fifo_errors
;
2702 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2706 /* This should never happen it is a bug. */
2707 static void sky2_le_error(struct sky2_hw
*hw
, unsigned port
, u16 q
)
2709 struct net_device
*dev
= hw
->dev
[port
];
2710 u16 idx
= sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_GET_IDX
));
2712 dev_err(&hw
->pdev
->dev
, PFX
2713 "%s: descriptor error q=%#x get=%u put=%u\n",
2714 dev
->name
, (unsigned) q
, (unsigned) idx
,
2715 (unsigned) sky2_read16(hw
, Y2_QADDR(q
, PREF_UNIT_PUT_IDX
)));
2717 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_IRQ_CHK
);
2720 static int sky2_rx_hung(struct net_device
*dev
)
2722 struct sky2_port
*sky2
= netdev_priv(dev
);
2723 struct sky2_hw
*hw
= sky2
->hw
;
2724 unsigned port
= sky2
->port
;
2725 unsigned rxq
= rxqaddr
[port
];
2726 u32 mac_rp
= sky2_read32(hw
, SK_REG(port
, RX_GMF_RP
));
2727 u8 mac_lev
= sky2_read8(hw
, SK_REG(port
, RX_GMF_RLEV
));
2728 u8 fifo_rp
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RP
));
2729 u8 fifo_lev
= sky2_read8(hw
, Q_ADDR(rxq
, Q_RL
));
2731 /* If idle and MAC or PCI is stuck */
2732 if (sky2
->check
.last
== dev
->last_rx
&&
2733 ((mac_rp
== sky2
->check
.mac_rp
&&
2734 mac_lev
!= 0 && mac_lev
>= sky2
->check
.mac_lev
) ||
2735 /* Check if the PCI RX hang */
2736 (fifo_rp
== sky2
->check
.fifo_rp
&&
2737 fifo_lev
!= 0 && fifo_lev
>= sky2
->check
.fifo_lev
))) {
2738 printk(KERN_DEBUG PFX
"%s: hung mac %d:%d fifo %d (%d:%d)\n",
2739 dev
->name
, mac_lev
, mac_rp
, fifo_lev
, fifo_rp
,
2740 sky2_read8(hw
, Q_ADDR(rxq
, Q_WP
)));
2743 sky2
->check
.last
= dev
->last_rx
;
2744 sky2
->check
.mac_rp
= mac_rp
;
2745 sky2
->check
.mac_lev
= mac_lev
;
2746 sky2
->check
.fifo_rp
= fifo_rp
;
2747 sky2
->check
.fifo_lev
= fifo_lev
;
2752 static void sky2_watchdog(unsigned long arg
)
2754 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2756 /* Check for lost IRQ once a second */
2757 if (sky2_read32(hw
, B0_ISRC
)) {
2758 napi_schedule(&hw
->napi
);
2762 for (i
= 0; i
< hw
->ports
; i
++) {
2763 struct net_device
*dev
= hw
->dev
[i
];
2764 if (!netif_running(dev
))
2768 /* For chips with Rx FIFO, check if stuck */
2769 if ((hw
->flags
& SKY2_HW_RAM_BUFFER
) &&
2770 sky2_rx_hung(dev
)) {
2771 pr_info(PFX
"%s: receiver hang detected\n",
2773 schedule_work(&hw
->restart_work
);
2782 mod_timer(&hw
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2785 /* Hardware/software error handling */
2786 static void sky2_err_intr(struct sky2_hw
*hw
, u32 status
)
2788 if (net_ratelimit())
2789 dev_warn(&hw
->pdev
->dev
, "error interrupt status=%#x\n", status
);
2791 if (status
& Y2_IS_HW_ERR
)
2794 if (status
& Y2_IS_IRQ_MAC1
)
2795 sky2_mac_intr(hw
, 0);
2797 if (status
& Y2_IS_IRQ_MAC2
)
2798 sky2_mac_intr(hw
, 1);
2800 if (status
& Y2_IS_CHK_RX1
)
2801 sky2_le_error(hw
, 0, Q_R1
);
2803 if (status
& Y2_IS_CHK_RX2
)
2804 sky2_le_error(hw
, 1, Q_R2
);
2806 if (status
& Y2_IS_CHK_TXA1
)
2807 sky2_le_error(hw
, 0, Q_XA1
);
2809 if (status
& Y2_IS_CHK_TXA2
)
2810 sky2_le_error(hw
, 1, Q_XA2
);
2813 static int sky2_poll(struct napi_struct
*napi
, int work_limit
)
2815 struct sky2_hw
*hw
= container_of(napi
, struct sky2_hw
, napi
);
2816 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2820 if (unlikely(status
& Y2_IS_ERROR
))
2821 sky2_err_intr(hw
, status
);
2823 if (status
& Y2_IS_IRQ_PHY1
)
2824 sky2_phy_intr(hw
, 0);
2826 if (status
& Y2_IS_IRQ_PHY2
)
2827 sky2_phy_intr(hw
, 1);
2829 if (status
& Y2_IS_PHY_QLNK
)
2830 sky2_qlink_intr(hw
);
2832 while ((idx
= sky2_read16(hw
, STAT_PUT_IDX
)) != hw
->st_idx
) {
2833 work_done
+= sky2_status_intr(hw
, work_limit
- work_done
, idx
);
2835 if (work_done
>= work_limit
)
2839 napi_complete(napi
);
2840 sky2_read32(hw
, B0_Y2_SP_LISR
);
2846 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2848 struct sky2_hw
*hw
= dev_id
;
2851 /* Reading this mask interrupts as side effect */
2852 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2853 if (status
== 0 || status
== ~0)
2856 prefetch(&hw
->st_le
[hw
->st_idx
]);
2858 napi_schedule(&hw
->napi
);
2863 #ifdef CONFIG_NET_POLL_CONTROLLER
2864 static void sky2_netpoll(struct net_device
*dev
)
2866 struct sky2_port
*sky2
= netdev_priv(dev
);
2868 napi_schedule(&sky2
->hw
->napi
);
2872 /* Chip internal frequency for clock calculations */
2873 static u32
sky2_mhz(const struct sky2_hw
*hw
)
2875 switch (hw
->chip_id
) {
2876 case CHIP_ID_YUKON_EC
:
2877 case CHIP_ID_YUKON_EC_U
:
2878 case CHIP_ID_YUKON_EX
:
2879 case CHIP_ID_YUKON_SUPR
:
2880 case CHIP_ID_YUKON_UL_2
:
2881 case CHIP_ID_YUKON_OPT
:
2884 case CHIP_ID_YUKON_FE
:
2887 case CHIP_ID_YUKON_FE_P
:
2890 case CHIP_ID_YUKON_XL
:
2898 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2900 return sky2_mhz(hw
) * us
;
2903 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2905 return clk
/ sky2_mhz(hw
);
2909 static int __devinit
sky2_init(struct sky2_hw
*hw
)
2913 /* Enable all clocks and check for bad PCI access */
2914 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
2916 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2918 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2919 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2921 switch(hw
->chip_id
) {
2922 case CHIP_ID_YUKON_XL
:
2923 hw
->flags
= SKY2_HW_GIGABIT
| SKY2_HW_NEWER_PHY
;
2926 case CHIP_ID_YUKON_EC_U
:
2927 hw
->flags
= SKY2_HW_GIGABIT
2929 | SKY2_HW_ADV_POWER_CTL
;
2932 case CHIP_ID_YUKON_EX
:
2933 hw
->flags
= SKY2_HW_GIGABIT
2936 | SKY2_HW_ADV_POWER_CTL
;
2938 /* New transmit checksum */
2939 if (hw
->chip_rev
!= CHIP_REV_YU_EX_B0
)
2940 hw
->flags
|= SKY2_HW_AUTO_TX_SUM
;
2943 case CHIP_ID_YUKON_EC
:
2944 /* This rev is really old, and requires untested workarounds */
2945 if (hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2946 dev_err(&hw
->pdev
->dev
, "unsupported revision Yukon-EC rev A1\n");
2949 hw
->flags
= SKY2_HW_GIGABIT
;
2952 case CHIP_ID_YUKON_FE
:
2955 case CHIP_ID_YUKON_FE_P
:
2956 hw
->flags
= SKY2_HW_NEWER_PHY
2958 | SKY2_HW_AUTO_TX_SUM
2959 | SKY2_HW_ADV_POWER_CTL
;
2962 case CHIP_ID_YUKON_SUPR
:
2963 hw
->flags
= SKY2_HW_GIGABIT
2966 | SKY2_HW_AUTO_TX_SUM
2967 | SKY2_HW_ADV_POWER_CTL
;
2970 case CHIP_ID_YUKON_UL_2
:
2971 case CHIP_ID_YUKON_OPT
:
2972 hw
->flags
= SKY2_HW_GIGABIT
2973 | SKY2_HW_ADV_POWER_CTL
;
2977 dev_err(&hw
->pdev
->dev
, "unsupported chip type 0x%x\n",
2982 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2983 if (hw
->pmd_type
== 'L' || hw
->pmd_type
== 'S' || hw
->pmd_type
== 'P')
2984 hw
->flags
|= SKY2_HW_FIBRE_PHY
;
2987 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2988 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2989 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2993 if (sky2_read8(hw
, B2_E_0
))
2994 hw
->flags
|= SKY2_HW_RAM_BUFFER
;
2999 static void sky2_reset(struct sky2_hw
*hw
)
3001 struct pci_dev
*pdev
= hw
->pdev
;
3004 u32 hwe_mask
= Y2_HWE_ALL_MASK
;
3007 if (hw
->chip_id
== CHIP_ID_YUKON_EX
) {
3008 status
= sky2_read16(hw
, HCU_CCSR
);
3009 status
&= ~(HCU_CCSR_AHB_RST
| HCU_CCSR_CPU_RST_MODE
|
3010 HCU_CCSR_UC_STATE_MSK
);
3011 sky2_write16(hw
, HCU_CCSR
, status
);
3013 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
3014 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
3017 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3018 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
3020 /* allow writes to PCI config */
3021 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
3023 /* clear PCI errors, if any */
3024 status
= sky2_pci_read16(hw
, PCI_STATUS
);
3025 status
|= PCI_STATUS_ERROR_BITS
;
3026 sky2_pci_write16(hw
, PCI_STATUS
, status
);
3028 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
3030 cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3032 sky2_write32(hw
, Y2_CFG_AER
+ PCI_ERR_UNCOR_STATUS
,
3035 /* If error bit is stuck on ignore it */
3036 if (sky2_read32(hw
, B0_HWE_ISRC
) & Y2_IS_PCI_EXP
)
3037 dev_info(&pdev
->dev
, "ignoring stuck error report bit\n");
3039 hwe_mask
|= Y2_IS_PCI_EXP
;
3043 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
3045 for (i
= 0; i
< hw
->ports
; i
++) {
3046 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
3047 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
3049 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
3050 hw
->chip_id
== CHIP_ID_YUKON_SUPR
)
3051 sky2_write16(hw
, SK_REG(i
, GMAC_CTRL
),
3052 GMC_BYP_MACSECRX_ON
| GMC_BYP_MACSECTX_ON
3057 if (hw
->chip_id
== CHIP_ID_YUKON_SUPR
&& hw
->chip_rev
> CHIP_REV_YU_SU_B0
) {
3058 /* enable MACSec clock gating */
3059 sky2_pci_write32(hw
, PCI_DEV_REG3
, P_CLK_MACSEC_DIS
);
3062 if (hw
->chip_id
== CHIP_ID_YUKON_OPT
) {
3066 if (hw
->chip_rev
== 0) {
3067 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3068 sky2_write32(hw
, Y2_PEX_PHY_DATA
, (0x80UL
<< 16) | (1 << 7));
3070 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3073 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3077 reg
<<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE
;
3079 /* reset PHY Link Detect */
3080 sky2_pci_write16(hw
, PSM_CONFIG_REG4
,
3081 reg
| PSM_CONFIG_REG4_RST_PHY_LINK_DETECT
);
3082 sky2_pci_write16(hw
, PSM_CONFIG_REG4
, reg
);
3085 /* enable PHY Quick Link */
3086 msk
= sky2_read32(hw
, B0_IMSK
);
3087 msk
|= Y2_IS_PHY_QLNK
;
3088 sky2_write32(hw
, B0_IMSK
, msk
);
3090 /* check if PSMv2 was running before */
3091 reg
= sky2_pci_read16(hw
, PSM_CONFIG_REG3
);
3092 if (reg
& PCI_EXP_LNKCTL_ASPMC
) {
3093 int cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
3094 /* restore the PCIe Link Control register */
3095 sky2_pci_write16(hw
, cap
+ PCI_EXP_LNKCTL
, reg
);
3098 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3099 sky2_write32(hw
, Y2_PEX_PHY_DATA
, PEX_DB_ACCESS
| (0x08UL
<< 16));
3102 /* Clear I2C IRQ noise */
3103 sky2_write32(hw
, B2_I2C_IRQ
, 1);
3105 /* turn off hardware timer (unused) */
3106 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
3107 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
3109 /* Turn off descriptor polling */
3110 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
3112 /* Turn off receive timestamp */
3113 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
3114 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
3116 /* enable the Tx Arbiters */
3117 for (i
= 0; i
< hw
->ports
; i
++)
3118 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
3120 /* Initialize ram interface */
3121 for (i
= 0; i
< hw
->ports
; i
++) {
3122 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
3124 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
3125 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
3126 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
3127 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
3128 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
3129 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
3130 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
3131 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
3132 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
3133 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
3134 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
3135 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
3138 sky2_write32(hw
, B0_HWE_IMSK
, hwe_mask
);
3140 for (i
= 0; i
< hw
->ports
; i
++)
3141 sky2_gmac_reset(hw
, i
);
3143 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
3146 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
3147 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
3149 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
3150 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
3152 /* Set the list last index */
3153 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
3155 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
3156 sky2_write8(hw
, STAT_FIFO_WM
, 16);
3158 /* set Status-FIFO ISR watermark */
3159 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
3160 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
3162 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
3164 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
3165 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
3166 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
3168 /* enable status unit */
3169 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
3171 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3172 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3173 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3176 /* Take device down (offline).
3177 * Equivalent to doing dev_stop() but this does not
3178 * inform upper layers of the transistion.
3180 static void sky2_detach(struct net_device
*dev
)
3182 if (netif_running(dev
)) {
3183 netif_device_detach(dev
); /* stop txq */
3188 /* Bring device back after doing sky2_detach */
3189 static int sky2_reattach(struct net_device
*dev
)
3193 if (netif_running(dev
)) {
3196 printk(KERN_INFO PFX
"%s: could not restart %d\n",
3200 netif_device_attach(dev
);
3201 sky2_set_multicast(dev
);
3208 static void sky2_restart(struct work_struct
*work
)
3210 struct sky2_hw
*hw
= container_of(work
, struct sky2_hw
, restart_work
);
3214 for (i
= 0; i
< hw
->ports
; i
++)
3215 sky2_detach(hw
->dev
[i
]);
3217 napi_disable(&hw
->napi
);
3218 sky2_write32(hw
, B0_IMSK
, 0);
3220 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3221 napi_enable(&hw
->napi
);
3223 for (i
= 0; i
< hw
->ports
; i
++)
3224 sky2_reattach(hw
->dev
[i
]);
3229 static inline u8
sky2_wol_supported(const struct sky2_hw
*hw
)
3231 return sky2_is_copper(hw
) ? (WAKE_PHY
| WAKE_MAGIC
) : 0;
3234 static void sky2_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3236 const struct sky2_port
*sky2
= netdev_priv(dev
);
3238 wol
->supported
= sky2_wol_supported(sky2
->hw
);
3239 wol
->wolopts
= sky2
->wol
;
3242 static int sky2_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
3244 struct sky2_port
*sky2
= netdev_priv(dev
);
3245 struct sky2_hw
*hw
= sky2
->hw
;
3247 if ((wol
->wolopts
& ~sky2_wol_supported(sky2
->hw
)) ||
3248 !device_can_wakeup(&hw
->pdev
->dev
))
3251 sky2
->wol
= wol
->wolopts
;
3253 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3254 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3255 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
3256 sky2_write32(hw
, B0_CTST
, sky2
->wol
3257 ? Y2_HW_WOL_ON
: Y2_HW_WOL_OFF
);
3259 device_set_wakeup_enable(&hw
->pdev
->dev
, sky2
->wol
);
3261 if (!netif_running(dev
))
3262 sky2_wol_init(sky2
);
3266 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
3268 if (sky2_is_copper(hw
)) {
3269 u32 modes
= SUPPORTED_10baseT_Half
3270 | SUPPORTED_10baseT_Full
3271 | SUPPORTED_100baseT_Half
3272 | SUPPORTED_100baseT_Full
3273 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
3275 if (hw
->flags
& SKY2_HW_GIGABIT
)
3276 modes
|= SUPPORTED_1000baseT_Half
3277 | SUPPORTED_1000baseT_Full
;
3280 return SUPPORTED_1000baseT_Half
3281 | SUPPORTED_1000baseT_Full
3286 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3288 struct sky2_port
*sky2
= netdev_priv(dev
);
3289 struct sky2_hw
*hw
= sky2
->hw
;
3291 ecmd
->transceiver
= XCVR_INTERNAL
;
3292 ecmd
->supported
= sky2_supported_modes(hw
);
3293 ecmd
->phy_address
= PHY_ADDR_MARV
;
3294 if (sky2_is_copper(hw
)) {
3295 ecmd
->port
= PORT_TP
;
3296 ecmd
->speed
= sky2
->speed
;
3298 ecmd
->speed
= SPEED_1000
;
3299 ecmd
->port
= PORT_FIBRE
;
3302 ecmd
->advertising
= sky2
->advertising
;
3303 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_SPEED
)
3304 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3305 ecmd
->duplex
= sky2
->duplex
;
3309 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
3311 struct sky2_port
*sky2
= netdev_priv(dev
);
3312 const struct sky2_hw
*hw
= sky2
->hw
;
3313 u32 supported
= sky2_supported_modes(hw
);
3315 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
3316 sky2
->flags
|= SKY2_FLAG_AUTO_SPEED
;
3317 ecmd
->advertising
= supported
;
3323 switch (ecmd
->speed
) {
3325 if (ecmd
->duplex
== DUPLEX_FULL
)
3326 setting
= SUPPORTED_1000baseT_Full
;
3327 else if (ecmd
->duplex
== DUPLEX_HALF
)
3328 setting
= SUPPORTED_1000baseT_Half
;
3333 if (ecmd
->duplex
== DUPLEX_FULL
)
3334 setting
= SUPPORTED_100baseT_Full
;
3335 else if (ecmd
->duplex
== DUPLEX_HALF
)
3336 setting
= SUPPORTED_100baseT_Half
;
3342 if (ecmd
->duplex
== DUPLEX_FULL
)
3343 setting
= SUPPORTED_10baseT_Full
;
3344 else if (ecmd
->duplex
== DUPLEX_HALF
)
3345 setting
= SUPPORTED_10baseT_Half
;
3353 if ((setting
& supported
) == 0)
3356 sky2
->speed
= ecmd
->speed
;
3357 sky2
->duplex
= ecmd
->duplex
;
3358 sky2
->flags
&= ~SKY2_FLAG_AUTO_SPEED
;
3361 sky2
->advertising
= ecmd
->advertising
;
3363 if (netif_running(dev
)) {
3364 sky2_phy_reinit(sky2
);
3365 sky2_set_multicast(dev
);
3371 static void sky2_get_drvinfo(struct net_device
*dev
,
3372 struct ethtool_drvinfo
*info
)
3374 struct sky2_port
*sky2
= netdev_priv(dev
);
3376 strcpy(info
->driver
, DRV_NAME
);
3377 strcpy(info
->version
, DRV_VERSION
);
3378 strcpy(info
->fw_version
, "N/A");
3379 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
3382 static const struct sky2_stat
{
3383 char name
[ETH_GSTRING_LEN
];
3386 { "tx_bytes", GM_TXO_OK_HI
},
3387 { "rx_bytes", GM_RXO_OK_HI
},
3388 { "tx_broadcast", GM_TXF_BC_OK
},
3389 { "rx_broadcast", GM_RXF_BC_OK
},
3390 { "tx_multicast", GM_TXF_MC_OK
},
3391 { "rx_multicast", GM_RXF_MC_OK
},
3392 { "tx_unicast", GM_TXF_UC_OK
},
3393 { "rx_unicast", GM_RXF_UC_OK
},
3394 { "tx_mac_pause", GM_TXF_MPAUSE
},
3395 { "rx_mac_pause", GM_RXF_MPAUSE
},
3396 { "collisions", GM_TXF_COL
},
3397 { "late_collision",GM_TXF_LAT_COL
},
3398 { "aborted", GM_TXF_ABO_COL
},
3399 { "single_collisions", GM_TXF_SNG_COL
},
3400 { "multi_collisions", GM_TXF_MUL_COL
},
3402 { "rx_short", GM_RXF_SHT
},
3403 { "rx_runt", GM_RXE_FRAG
},
3404 { "rx_64_byte_packets", GM_RXF_64B
},
3405 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
3406 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
3407 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
3408 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
3409 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
3410 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
3411 { "rx_too_long", GM_RXF_LNG_ERR
},
3412 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
3413 { "rx_jabber", GM_RXF_JAB_PKT
},
3414 { "rx_fcs_error", GM_RXF_FCS_ERR
},
3416 { "tx_64_byte_packets", GM_TXF_64B
},
3417 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
3418 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
3419 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
3420 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
3421 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
3422 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
3423 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
3426 static u32
sky2_get_rx_csum(struct net_device
*dev
)
3428 struct sky2_port
*sky2
= netdev_priv(dev
);
3430 return !!(sky2
->flags
& SKY2_FLAG_RX_CHECKSUM
);
3433 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
3435 struct sky2_port
*sky2
= netdev_priv(dev
);
3438 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
3440 sky2
->flags
&= ~SKY2_FLAG_RX_CHECKSUM
;
3442 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
3443 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
3448 static u32
sky2_get_msglevel(struct net_device
*netdev
)
3450 struct sky2_port
*sky2
= netdev_priv(netdev
);
3451 return sky2
->msg_enable
;
3454 static int sky2_nway_reset(struct net_device
*dev
)
3456 struct sky2_port
*sky2
= netdev_priv(dev
);
3458 if (!netif_running(dev
) || !(sky2
->flags
& SKY2_FLAG_AUTO_SPEED
))
3461 sky2_phy_reinit(sky2
);
3462 sky2_set_multicast(dev
);
3467 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
3469 struct sky2_hw
*hw
= sky2
->hw
;
3470 unsigned port
= sky2
->port
;
3473 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
3474 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
3475 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
3476 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
3478 for (i
= 2; i
< count
; i
++)
3479 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
3482 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
3484 struct sky2_port
*sky2
= netdev_priv(netdev
);
3485 sky2
->msg_enable
= value
;
3488 static int sky2_get_sset_count(struct net_device
*dev
, int sset
)
3492 return ARRAY_SIZE(sky2_stats
);
3498 static void sky2_get_ethtool_stats(struct net_device
*dev
,
3499 struct ethtool_stats
*stats
, u64
* data
)
3501 struct sky2_port
*sky2
= netdev_priv(dev
);
3503 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
3506 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
3510 switch (stringset
) {
3512 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
3513 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3514 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
3519 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
3521 struct sky2_port
*sky2
= netdev_priv(dev
);
3522 struct sky2_hw
*hw
= sky2
->hw
;
3523 unsigned port
= sky2
->port
;
3524 const struct sockaddr
*addr
= p
;
3526 if (!is_valid_ether_addr(addr
->sa_data
))
3527 return -EADDRNOTAVAIL
;
3529 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
3530 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
3531 dev
->dev_addr
, ETH_ALEN
);
3532 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
3533 dev
->dev_addr
, ETH_ALEN
);
3535 /* virtual address for data */
3536 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
3538 /* physical address: used for pause frames */
3539 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
3544 static void inline sky2_add_filter(u8 filter
[8], const u8
*addr
)
3548 bit
= ether_crc(ETH_ALEN
, addr
) & 63;
3549 filter
[bit
>> 3] |= 1 << (bit
& 7);
3552 static void sky2_set_multicast(struct net_device
*dev
)
3554 struct sky2_port
*sky2
= netdev_priv(dev
);
3555 struct sky2_hw
*hw
= sky2
->hw
;
3556 unsigned port
= sky2
->port
;
3557 struct dev_mc_list
*list
= dev
->mc_list
;
3561 static const u8 pause_mc_addr
[ETH_ALEN
] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3563 rx_pause
= (sky2
->flow_status
== FC_RX
|| sky2
->flow_status
== FC_BOTH
);
3564 memset(filter
, 0, sizeof(filter
));
3566 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
3567 reg
|= GM_RXCR_UCF_ENA
;
3569 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
3570 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
3571 else if (dev
->flags
& IFF_ALLMULTI
)
3572 memset(filter
, 0xff, sizeof(filter
));
3573 else if (dev
->mc_count
== 0 && !rx_pause
)
3574 reg
&= ~GM_RXCR_MCF_ENA
;
3577 reg
|= GM_RXCR_MCF_ENA
;
3580 sky2_add_filter(filter
, pause_mc_addr
);
3582 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
)
3583 sky2_add_filter(filter
, list
->dmi_addr
);
3586 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
3587 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
3588 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
3589 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
3590 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
3591 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
3592 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
3593 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
3595 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
3598 /* Can have one global because blinking is controlled by
3599 * ethtool and that is always under RTNL mutex
3601 static void sky2_led(struct sky2_port
*sky2
, enum led_mode mode
)
3603 struct sky2_hw
*hw
= sky2
->hw
;
3604 unsigned port
= sky2
->port
;
3606 spin_lock_bh(&sky2
->phy_lock
);
3607 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
3608 hw
->chip_id
== CHIP_ID_YUKON_EX
||
3609 hw
->chip_id
== CHIP_ID_YUKON_SUPR
) {
3611 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
3612 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
3616 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3617 PHY_M_LEDC_LOS_CTRL(8) |
3618 PHY_M_LEDC_INIT_CTRL(8) |
3619 PHY_M_LEDC_STA1_CTRL(8) |
3620 PHY_M_LEDC_STA0_CTRL(8));
3623 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3624 PHY_M_LEDC_LOS_CTRL(9) |
3625 PHY_M_LEDC_INIT_CTRL(9) |
3626 PHY_M_LEDC_STA1_CTRL(9) |
3627 PHY_M_LEDC_STA0_CTRL(9));
3630 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3631 PHY_M_LEDC_LOS_CTRL(0xa) |
3632 PHY_M_LEDC_INIT_CTRL(0xa) |
3633 PHY_M_LEDC_STA1_CTRL(0xa) |
3634 PHY_M_LEDC_STA0_CTRL(0xa));
3637 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
3638 PHY_M_LEDC_LOS_CTRL(1) |
3639 PHY_M_LEDC_INIT_CTRL(8) |
3640 PHY_M_LEDC_STA1_CTRL(7) |
3641 PHY_M_LEDC_STA0_CTRL(7));
3644 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
3646 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
3647 PHY_M_LED_MO_DUP(mode
) |
3648 PHY_M_LED_MO_10(mode
) |
3649 PHY_M_LED_MO_100(mode
) |
3650 PHY_M_LED_MO_1000(mode
) |
3651 PHY_M_LED_MO_RX(mode
) |
3652 PHY_M_LED_MO_TX(mode
));
3654 spin_unlock_bh(&sky2
->phy_lock
);
3657 /* blink LED's for finding board */
3658 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
3660 struct sky2_port
*sky2
= netdev_priv(dev
);
3666 for (i
= 0; i
< data
; i
++) {
3667 sky2_led(sky2
, MO_LED_ON
);
3668 if (msleep_interruptible(500))
3670 sky2_led(sky2
, MO_LED_OFF
);
3671 if (msleep_interruptible(500))
3674 sky2_led(sky2
, MO_LED_NORM
);
3679 static void sky2_get_pauseparam(struct net_device
*dev
,
3680 struct ethtool_pauseparam
*ecmd
)
3682 struct sky2_port
*sky2
= netdev_priv(dev
);
3684 switch (sky2
->flow_mode
) {
3686 ecmd
->tx_pause
= ecmd
->rx_pause
= 0;
3689 ecmd
->tx_pause
= 1, ecmd
->rx_pause
= 0;
3692 ecmd
->tx_pause
= 0, ecmd
->rx_pause
= 1;
3695 ecmd
->tx_pause
= ecmd
->rx_pause
= 1;
3698 ecmd
->autoneg
= (sky2
->flags
& SKY2_FLAG_AUTO_PAUSE
)
3699 ? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3702 static int sky2_set_pauseparam(struct net_device
*dev
,
3703 struct ethtool_pauseparam
*ecmd
)
3705 struct sky2_port
*sky2
= netdev_priv(dev
);
3707 if (ecmd
->autoneg
== AUTONEG_ENABLE
)
3708 sky2
->flags
|= SKY2_FLAG_AUTO_PAUSE
;
3710 sky2
->flags
&= ~SKY2_FLAG_AUTO_PAUSE
;
3712 sky2
->flow_mode
= sky2_flow(ecmd
->rx_pause
, ecmd
->tx_pause
);
3714 if (netif_running(dev
))
3715 sky2_phy_reinit(sky2
);
3720 static int sky2_get_coalesce(struct net_device
*dev
,
3721 struct ethtool_coalesce
*ecmd
)
3723 struct sky2_port
*sky2
= netdev_priv(dev
);
3724 struct sky2_hw
*hw
= sky2
->hw
;
3726 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3727 ecmd
->tx_coalesce_usecs
= 0;
3729 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3730 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3732 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3734 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3735 ecmd
->rx_coalesce_usecs
= 0;
3737 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3738 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3740 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3742 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3743 ecmd
->rx_coalesce_usecs_irq
= 0;
3745 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3746 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3749 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3754 /* Note: this affect both ports */
3755 static int sky2_set_coalesce(struct net_device
*dev
,
3756 struct ethtool_coalesce
*ecmd
)
3758 struct sky2_port
*sky2
= netdev_priv(dev
);
3759 struct sky2_hw
*hw
= sky2
->hw
;
3760 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3762 if (ecmd
->tx_coalesce_usecs
> tmax
||
3763 ecmd
->rx_coalesce_usecs
> tmax
||
3764 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3767 if (ecmd
->tx_max_coalesced_frames
>= sky2
->tx_ring_size
-1)
3769 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3771 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3774 if (ecmd
->tx_coalesce_usecs
== 0)
3775 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3777 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3778 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3779 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3781 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3783 if (ecmd
->rx_coalesce_usecs
== 0)
3784 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3786 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3787 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3788 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3790 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3792 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3793 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3795 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3796 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3797 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3799 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3803 static void sky2_get_ringparam(struct net_device
*dev
,
3804 struct ethtool_ringparam
*ering
)
3806 struct sky2_port
*sky2
= netdev_priv(dev
);
3808 ering
->rx_max_pending
= RX_MAX_PENDING
;
3809 ering
->rx_mini_max_pending
= 0;
3810 ering
->rx_jumbo_max_pending
= 0;
3811 ering
->tx_max_pending
= TX_MAX_PENDING
;
3813 ering
->rx_pending
= sky2
->rx_pending
;
3814 ering
->rx_mini_pending
= 0;
3815 ering
->rx_jumbo_pending
= 0;
3816 ering
->tx_pending
= sky2
->tx_pending
;
3819 static int sky2_set_ringparam(struct net_device
*dev
,
3820 struct ethtool_ringparam
*ering
)
3822 struct sky2_port
*sky2
= netdev_priv(dev
);
3824 if (ering
->rx_pending
> RX_MAX_PENDING
||
3825 ering
->rx_pending
< 8 ||
3826 ering
->tx_pending
< TX_MIN_PENDING
||
3827 ering
->tx_pending
> TX_MAX_PENDING
)
3832 sky2
->rx_pending
= ering
->rx_pending
;
3833 sky2
->tx_pending
= ering
->tx_pending
;
3834 sky2
->tx_ring_size
= roundup_pow_of_two(sky2
->tx_pending
+1);
3836 return sky2_reattach(dev
);
3839 static int sky2_get_regs_len(struct net_device
*dev
)
3845 * Returns copy of control register region
3846 * Note: ethtool_get_regs always provides full size (16k) buffer
3848 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3851 const struct sky2_port
*sky2
= netdev_priv(dev
);
3852 const void __iomem
*io
= sky2
->hw
->regs
;
3857 for (b
= 0; b
< 128; b
++) {
3858 /* This complicated switch statement is to make sure and
3859 * only access regions that are unreserved.
3860 * Some blocks are only valid on dual port cards.
3861 * and block 3 has some special diagnostic registers that
3866 /* skip diagnostic ram region */
3867 memcpy_fromio(p
+ 0x10, io
+ 0x10, 128 - 0x10);
3870 /* dual port cards only */
3871 case 5: /* Tx Arbiter 2 */
3873 case 14 ... 15: /* TX2 */
3874 case 17: case 19: /* Ram Buffer 2 */
3875 case 22 ... 23: /* Tx Ram Buffer 2 */
3876 case 25: /* Rx MAC Fifo 1 */
3877 case 27: /* Tx MAC Fifo 2 */
3878 case 31: /* GPHY 2 */
3879 case 40 ... 47: /* Pattern Ram 2 */
3880 case 52: case 54: /* TCP Segmentation 2 */
3881 case 112 ... 116: /* GMAC 2 */
3882 if (sky2
->hw
->ports
== 1)
3885 case 0: /* Control */
3886 case 2: /* Mac address */
3887 case 4: /* Tx Arbiter 1 */
3888 case 7: /* PCI express reg */
3890 case 12 ... 13: /* TX1 */
3891 case 16: case 18:/* Rx Ram Buffer 1 */
3892 case 20 ... 21: /* Tx Ram Buffer 1 */
3893 case 24: /* Rx MAC Fifo 1 */
3894 case 26: /* Tx MAC Fifo 1 */
3895 case 28 ... 29: /* Descriptor and status unit */
3896 case 30: /* GPHY 1*/
3897 case 32 ... 39: /* Pattern Ram 1 */
3898 case 48: case 50: /* TCP Segmentation 1 */
3899 case 56 ... 60: /* PCI space */
3900 case 80 ... 84: /* GMAC 1 */
3901 memcpy_fromio(p
, io
, 128);
3913 /* In order to do Jumbo packets on these chips, need to turn off the
3914 * transmit store/forward. Therefore checksum offload won't work.
3916 static int no_tx_offload(struct net_device
*dev
)
3918 const struct sky2_port
*sky2
= netdev_priv(dev
);
3919 const struct sky2_hw
*hw
= sky2
->hw
;
3921 return dev
->mtu
> ETH_DATA_LEN
&& hw
->chip_id
== CHIP_ID_YUKON_EC_U
;
3924 static int sky2_set_tx_csum(struct net_device
*dev
, u32 data
)
3926 if (data
&& no_tx_offload(dev
))
3929 return ethtool_op_set_tx_csum(dev
, data
);
3933 static int sky2_set_tso(struct net_device
*dev
, u32 data
)
3935 if (data
&& no_tx_offload(dev
))
3938 return ethtool_op_set_tso(dev
, data
);
3941 static int sky2_get_eeprom_len(struct net_device
*dev
)
3943 struct sky2_port
*sky2
= netdev_priv(dev
);
3944 struct sky2_hw
*hw
= sky2
->hw
;
3947 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
3948 return 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
3951 static int sky2_vpd_wait(const struct sky2_hw
*hw
, int cap
, u16 busy
)
3953 unsigned long start
= jiffies
;
3955 while ( (sky2_pci_read16(hw
, cap
+ PCI_VPD_ADDR
) & PCI_VPD_ADDR_F
) == busy
) {
3956 /* Can take up to 10.6 ms for write */
3957 if (time_after(jiffies
, start
+ HZ
/4)) {
3958 dev_err(&hw
->pdev
->dev
, PFX
"VPD cycle timed out");
3967 static int sky2_vpd_read(struct sky2_hw
*hw
, int cap
, void *data
,
3968 u16 offset
, size_t length
)
3972 while (length
> 0) {
3975 sky2_pci_write16(hw
, cap
+ PCI_VPD_ADDR
, offset
);
3976 rc
= sky2_vpd_wait(hw
, cap
, 0);
3980 val
= sky2_pci_read32(hw
, cap
+ PCI_VPD_DATA
);
3982 memcpy(data
, &val
, min(sizeof(val
), length
));
3983 offset
+= sizeof(u32
);
3984 data
+= sizeof(u32
);
3985 length
-= sizeof(u32
);
3991 static int sky2_vpd_write(struct sky2_hw
*hw
, int cap
, const void *data
,
3992 u16 offset
, unsigned int length
)
3997 for (i
= 0; i
< length
; i
+= sizeof(u32
)) {
3998 u32 val
= *(u32
*)(data
+ i
);
4000 sky2_pci_write32(hw
, cap
+ PCI_VPD_DATA
, val
);
4001 sky2_pci_write32(hw
, cap
+ PCI_VPD_ADDR
, offset
| PCI_VPD_ADDR_F
);
4003 rc
= sky2_vpd_wait(hw
, cap
, PCI_VPD_ADDR_F
);
4010 static int sky2_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4013 struct sky2_port
*sky2
= netdev_priv(dev
);
4014 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4019 eeprom
->magic
= SKY2_EEPROM_MAGIC
;
4021 return sky2_vpd_read(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4024 static int sky2_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
4027 struct sky2_port
*sky2
= netdev_priv(dev
);
4028 int cap
= pci_find_capability(sky2
->hw
->pdev
, PCI_CAP_ID_VPD
);
4033 if (eeprom
->magic
!= SKY2_EEPROM_MAGIC
)
4036 /* Partial writes not supported */
4037 if ((eeprom
->offset
& 3) || (eeprom
->len
& 3))
4040 return sky2_vpd_write(sky2
->hw
, cap
, data
, eeprom
->offset
, eeprom
->len
);
4044 static const struct ethtool_ops sky2_ethtool_ops
= {
4045 .get_settings
= sky2_get_settings
,
4046 .set_settings
= sky2_set_settings
,
4047 .get_drvinfo
= sky2_get_drvinfo
,
4048 .get_wol
= sky2_get_wol
,
4049 .set_wol
= sky2_set_wol
,
4050 .get_msglevel
= sky2_get_msglevel
,
4051 .set_msglevel
= sky2_set_msglevel
,
4052 .nway_reset
= sky2_nway_reset
,
4053 .get_regs_len
= sky2_get_regs_len
,
4054 .get_regs
= sky2_get_regs
,
4055 .get_link
= ethtool_op_get_link
,
4056 .get_eeprom_len
= sky2_get_eeprom_len
,
4057 .get_eeprom
= sky2_get_eeprom
,
4058 .set_eeprom
= sky2_set_eeprom
,
4059 .set_sg
= ethtool_op_set_sg
,
4060 .set_tx_csum
= sky2_set_tx_csum
,
4061 .set_tso
= sky2_set_tso
,
4062 .get_rx_csum
= sky2_get_rx_csum
,
4063 .set_rx_csum
= sky2_set_rx_csum
,
4064 .get_strings
= sky2_get_strings
,
4065 .get_coalesce
= sky2_get_coalesce
,
4066 .set_coalesce
= sky2_set_coalesce
,
4067 .get_ringparam
= sky2_get_ringparam
,
4068 .set_ringparam
= sky2_set_ringparam
,
4069 .get_pauseparam
= sky2_get_pauseparam
,
4070 .set_pauseparam
= sky2_set_pauseparam
,
4071 .phys_id
= sky2_phys_id
,
4072 .get_sset_count
= sky2_get_sset_count
,
4073 .get_ethtool_stats
= sky2_get_ethtool_stats
,
4076 #ifdef CONFIG_SKY2_DEBUG
4078 static struct dentry
*sky2_debug
;
4082 * Read and parse the first part of Vital Product Data
4084 #define VPD_SIZE 128
4085 #define VPD_MAGIC 0x82
4087 static const struct vpd_tag
{
4091 { "PN", "Part Number" },
4092 { "EC", "Engineering Level" },
4093 { "MN", "Manufacturer" },
4094 { "SN", "Serial Number" },
4095 { "YA", "Asset Tag" },
4096 { "VL", "First Error Log Message" },
4097 { "VF", "Second Error Log Message" },
4098 { "VB", "Boot Agent ROM Configuration" },
4099 { "VE", "EFI UNDI Configuration" },
4102 static void sky2_show_vpd(struct seq_file
*seq
, struct sky2_hw
*hw
)
4110 reg2
= sky2_pci_read16(hw
, PCI_DEV_REG2
);
4111 vpd_size
= 1 << ( ((reg2
& PCI_VPD_ROM_SZ
) >> 14) + 8);
4113 seq_printf(seq
, "%s Product Data\n", pci_name(hw
->pdev
));
4114 buf
= kmalloc(vpd_size
, GFP_KERNEL
);
4116 seq_puts(seq
, "no memory!\n");
4120 if (pci_read_vpd(hw
->pdev
, 0, vpd_size
, buf
) < 0) {
4121 seq_puts(seq
, "VPD read failed\n");
4125 if (buf
[0] != VPD_MAGIC
) {
4126 seq_printf(seq
, "VPD tag mismatch: %#x\n", buf
[0]);
4130 if (len
== 0 || len
> vpd_size
- 4) {
4131 seq_printf(seq
, "Invalid id length: %d\n", len
);
4135 seq_printf(seq
, "%.*s\n", len
, buf
+ 3);
4138 while (offs
< vpd_size
- 4) {
4141 if (!memcmp("RW", buf
+ offs
, 2)) /* end marker */
4143 len
= buf
[offs
+ 2];
4144 if (offs
+ len
+ 3 >= vpd_size
)
4147 for (i
= 0; i
< ARRAY_SIZE(vpd_tags
); i
++) {
4148 if (!memcmp(vpd_tags
[i
].tag
, buf
+ offs
, 2)) {
4149 seq_printf(seq
, " %s: %.*s\n",
4150 vpd_tags
[i
].label
, len
, buf
+ offs
+ 3);
4160 static int sky2_debug_show(struct seq_file
*seq
, void *v
)
4162 struct net_device
*dev
= seq
->private;
4163 const struct sky2_port
*sky2
= netdev_priv(dev
);
4164 struct sky2_hw
*hw
= sky2
->hw
;
4165 unsigned port
= sky2
->port
;
4169 sky2_show_vpd(seq
, hw
);
4171 seq_printf(seq
, "\nIRQ src=%x mask=%x control=%x\n",
4172 sky2_read32(hw
, B0_ISRC
),
4173 sky2_read32(hw
, B0_IMSK
),
4174 sky2_read32(hw
, B0_Y2_SP_ICR
));
4176 if (!netif_running(dev
)) {
4177 seq_printf(seq
, "network not running\n");
4181 napi_disable(&hw
->napi
);
4182 last
= sky2_read16(hw
, STAT_PUT_IDX
);
4184 if (hw
->st_idx
== last
)
4185 seq_puts(seq
, "Status ring (empty)\n");
4187 seq_puts(seq
, "Status ring\n");
4188 for (idx
= hw
->st_idx
; idx
!= last
&& idx
< STATUS_RING_SIZE
;
4189 idx
= RING_NEXT(idx
, STATUS_RING_SIZE
)) {
4190 const struct sky2_status_le
*le
= hw
->st_le
+ idx
;
4191 seq_printf(seq
, "[%d] %#x %d %#x\n",
4192 idx
, le
->opcode
, le
->length
, le
->status
);
4194 seq_puts(seq
, "\n");
4197 seq_printf(seq
, "Tx ring pending=%u...%u report=%d done=%d\n",
4198 sky2
->tx_cons
, sky2
->tx_prod
,
4199 sky2_read16(hw
, port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
),
4200 sky2_read16(hw
, Q_ADDR(txqaddr
[port
], Q_DONE
)));
4202 /* Dump contents of tx ring */
4204 for (idx
= sky2
->tx_next
; idx
!= sky2
->tx_prod
&& idx
< sky2
->tx_ring_size
;
4205 idx
= RING_NEXT(idx
, sky2
->tx_ring_size
)) {
4206 const struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
4207 u32 a
= le32_to_cpu(le
->addr
);
4210 seq_printf(seq
, "%u:", idx
);
4213 switch(le
->opcode
& ~HW_OWNER
) {
4215 seq_printf(seq
, " %#x:", a
);
4218 seq_printf(seq
, " mtu=%d", a
);
4221 seq_printf(seq
, " vlan=%d", be16_to_cpu(le
->length
));
4224 seq_printf(seq
, " csum=%#x", a
);
4227 seq_printf(seq
, " tso=%#x(%d)", a
, le16_to_cpu(le
->length
));
4230 seq_printf(seq
, " %#x(%d)", a
, le16_to_cpu(le
->length
));
4233 seq_printf(seq
, " frag=%#x(%d)", a
, le16_to_cpu(le
->length
));
4236 seq_printf(seq
, " op=%#x,%#x(%d)", le
->opcode
,
4237 a
, le16_to_cpu(le
->length
));
4240 if (le
->ctrl
& EOP
) {
4241 seq_putc(seq
, '\n');
4246 seq_printf(seq
, "\nRx ring hw get=%d put=%d last=%d\n",
4247 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_GET_IDX
)),
4248 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_PUT_IDX
)),
4249 sky2_read16(hw
, Y2_QADDR(rxqaddr
[port
], PREF_UNIT_LAST_IDX
)));
4251 sky2_read32(hw
, B0_Y2_SP_LISR
);
4252 napi_enable(&hw
->napi
);
4256 static int sky2_debug_open(struct inode
*inode
, struct file
*file
)
4258 return single_open(file
, sky2_debug_show
, inode
->i_private
);
4261 static const struct file_operations sky2_debug_fops
= {
4262 .owner
= THIS_MODULE
,
4263 .open
= sky2_debug_open
,
4265 .llseek
= seq_lseek
,
4266 .release
= single_release
,
4270 * Use network device events to create/remove/rename
4271 * debugfs file entries
4273 static int sky2_device_event(struct notifier_block
*unused
,
4274 unsigned long event
, void *ptr
)
4276 struct net_device
*dev
= ptr
;
4277 struct sky2_port
*sky2
= netdev_priv(dev
);
4279 if (dev
->netdev_ops
->ndo_open
!= sky2_up
|| !sky2_debug
)
4283 case NETDEV_CHANGENAME
:
4284 if (sky2
->debugfs
) {
4285 sky2
->debugfs
= debugfs_rename(sky2_debug
, sky2
->debugfs
,
4286 sky2_debug
, dev
->name
);
4290 case NETDEV_GOING_DOWN
:
4291 if (sky2
->debugfs
) {
4292 printk(KERN_DEBUG PFX
"%s: remove debugfs\n",
4294 debugfs_remove(sky2
->debugfs
);
4295 sky2
->debugfs
= NULL
;
4300 sky2
->debugfs
= debugfs_create_file(dev
->name
, S_IRUGO
,
4303 if (IS_ERR(sky2
->debugfs
))
4304 sky2
->debugfs
= NULL
;
4310 static struct notifier_block sky2_notifier
= {
4311 .notifier_call
= sky2_device_event
,
4315 static __init
void sky2_debug_init(void)
4319 ent
= debugfs_create_dir("sky2", NULL
);
4320 if (!ent
|| IS_ERR(ent
))
4324 register_netdevice_notifier(&sky2_notifier
);
4327 static __exit
void sky2_debug_cleanup(void)
4330 unregister_netdevice_notifier(&sky2_notifier
);
4331 debugfs_remove(sky2_debug
);
4337 #define sky2_debug_init()
4338 #define sky2_debug_cleanup()
4341 /* Two copies of network device operations to handle special case of
4342 not allowing netpoll on second port */
4343 static const struct net_device_ops sky2_netdev_ops
[2] = {
4345 .ndo_open
= sky2_up
,
4346 .ndo_stop
= sky2_down
,
4347 .ndo_start_xmit
= sky2_xmit_frame
,
4348 .ndo_do_ioctl
= sky2_ioctl
,
4349 .ndo_validate_addr
= eth_validate_addr
,
4350 .ndo_set_mac_address
= sky2_set_mac_address
,
4351 .ndo_set_multicast_list
= sky2_set_multicast
,
4352 .ndo_change_mtu
= sky2_change_mtu
,
4353 .ndo_tx_timeout
= sky2_tx_timeout
,
4354 #ifdef SKY2_VLAN_TAG_USED
4355 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4357 #ifdef CONFIG_NET_POLL_CONTROLLER
4358 .ndo_poll_controller
= sky2_netpoll
,
4362 .ndo_open
= sky2_up
,
4363 .ndo_stop
= sky2_down
,
4364 .ndo_start_xmit
= sky2_xmit_frame
,
4365 .ndo_do_ioctl
= sky2_ioctl
,
4366 .ndo_validate_addr
= eth_validate_addr
,
4367 .ndo_set_mac_address
= sky2_set_mac_address
,
4368 .ndo_set_multicast_list
= sky2_set_multicast
,
4369 .ndo_change_mtu
= sky2_change_mtu
,
4370 .ndo_tx_timeout
= sky2_tx_timeout
,
4371 #ifdef SKY2_VLAN_TAG_USED
4372 .ndo_vlan_rx_register
= sky2_vlan_rx_register
,
4377 /* Initialize network device */
4378 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
4380 int highmem
, int wol
)
4382 struct sky2_port
*sky2
;
4383 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
4386 dev_err(&hw
->pdev
->dev
, "etherdev alloc failed\n");
4390 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
4391 dev
->irq
= hw
->pdev
->irq
;
4392 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
4393 dev
->watchdog_timeo
= TX_WATCHDOG
;
4394 dev
->netdev_ops
= &sky2_netdev_ops
[port
];
4396 sky2
= netdev_priv(dev
);
4399 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
4401 /* Auto speed and flow control */
4402 sky2
->flags
= SKY2_FLAG_AUTO_SPEED
| SKY2_FLAG_AUTO_PAUSE
;
4403 if (hw
->chip_id
!= CHIP_ID_YUKON_XL
)
4404 sky2
->flags
|= SKY2_FLAG_RX_CHECKSUM
;
4406 sky2
->flow_mode
= FC_BOTH
;
4410 sky2
->advertising
= sky2_supported_modes(hw
);
4413 spin_lock_init(&sky2
->phy_lock
);
4415 sky2
->tx_pending
= TX_DEF_PENDING
;
4416 sky2
->tx_ring_size
= roundup_pow_of_two(TX_DEF_PENDING
+1);
4417 sky2
->rx_pending
= RX_DEF_PENDING
;
4419 hw
->dev
[port
] = dev
;
4423 dev
->features
|= NETIF_F_TSO
| NETIF_F_IP_CSUM
| NETIF_F_SG
;
4425 dev
->features
|= NETIF_F_HIGHDMA
;
4427 #ifdef SKY2_VLAN_TAG_USED
4428 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4429 if (!(sky2
->hw
->chip_id
== CHIP_ID_YUKON_FE_P
&&
4430 sky2
->hw
->chip_rev
== CHIP_REV_YU_FE2_A0
)) {
4431 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
4435 /* read the mac address */
4436 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
4437 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
4442 static void __devinit
sky2_show_addr(struct net_device
*dev
)
4444 const struct sky2_port
*sky2
= netdev_priv(dev
);
4446 if (netif_msg_probe(sky2
))
4447 printk(KERN_INFO PFX
"%s: addr %pM\n",
4448 dev
->name
, dev
->dev_addr
);
4451 /* Handle software interrupt used during MSI test */
4452 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
4454 struct sky2_hw
*hw
= dev_id
;
4455 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
4460 if (status
& Y2_IS_IRQ_SW
) {
4461 hw
->flags
|= SKY2_HW_USE_MSI
;
4462 wake_up(&hw
->msi_wait
);
4463 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4465 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
4470 /* Test interrupt path by forcing a a software IRQ */
4471 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
4473 struct pci_dev
*pdev
= hw
->pdev
;
4476 init_waitqueue_head (&hw
->msi_wait
);
4478 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
4480 err
= request_irq(pdev
->irq
, sky2_test_intr
, 0, DRV_NAME
, hw
);
4482 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4486 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
4487 sky2_read8(hw
, B0_CTST
);
4489 wait_event_timeout(hw
->msi_wait
, (hw
->flags
& SKY2_HW_USE_MSI
), HZ
/10);
4491 if (!(hw
->flags
& SKY2_HW_USE_MSI
)) {
4492 /* MSI test failed, go back to INTx mode */
4493 dev_info(&pdev
->dev
, "No interrupt generated using MSI, "
4494 "switching to INTx mode.\n");
4497 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
4500 sky2_write32(hw
, B0_IMSK
, 0);
4501 sky2_read32(hw
, B0_IMSK
);
4503 free_irq(pdev
->irq
, hw
);
4508 /* This driver supports yukon2 chipset only */
4509 static const char *sky2_name(u8 chipid
, char *buf
, int sz
)
4511 const char *name
[] = {
4513 "EC Ultra", /* 0xb4 */
4514 "Extreme", /* 0xb5 */
4518 "Supreme", /* 0xb9 */
4520 "Unknown", /* 0xbb */
4521 "Optima", /* 0xbc */
4524 if (chipid
>= CHIP_ID_YUKON_XL
&& chipid
< CHIP_ID_YUKON_OPT
)
4525 strncpy(buf
, name
[chipid
- CHIP_ID_YUKON_XL
], sz
);
4527 snprintf(buf
, sz
, "(chip %#x)", chipid
);
4531 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
4532 const struct pci_device_id
*ent
)
4534 struct net_device
*dev
;
4536 int err
, using_dac
= 0, wol_default
;
4540 err
= pci_enable_device(pdev
);
4542 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
4546 /* Get configuration information
4547 * Note: only regular PCI config access once to test for HW issues
4548 * other PCI access through shared memory for speed and to
4549 * avoid MMCONFIG problems.
4551 err
= pci_read_config_dword(pdev
, PCI_DEV_REG2
, ®
);
4553 dev_err(&pdev
->dev
, "PCI read config failed\n");
4558 dev_err(&pdev
->dev
, "PCI configuration read error\n");
4562 err
= pci_request_regions(pdev
, DRV_NAME
);
4564 dev_err(&pdev
->dev
, "cannot obtain PCI resources\n");
4565 goto err_out_disable
;
4568 pci_set_master(pdev
);
4570 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
4571 !(err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))) {
4573 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
4575 dev_err(&pdev
->dev
, "unable to obtain 64 bit DMA "
4576 "for consistent allocations\n");
4577 goto err_out_free_regions
;
4580 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
4582 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
4583 goto err_out_free_regions
;
4589 /* The sk98lin vendor driver uses hardware byte swapping but
4590 * this driver uses software swapping.
4592 reg
&= ~PCI_REV_DESC
;
4593 err
= pci_write_config_dword(pdev
,PCI_DEV_REG2
, reg
);
4595 dev_err(&pdev
->dev
, "PCI write config failed\n");
4596 goto err_out_free_regions
;
4600 wol_default
= device_may_wakeup(&pdev
->dev
) ? WAKE_MAGIC
: 0;
4604 hw
= kzalloc(sizeof(*hw
) + strlen(DRV_NAME
"@pci:")
4605 + strlen(pci_name(pdev
)) + 1, GFP_KERNEL
);
4607 dev_err(&pdev
->dev
, "cannot allocate hardware struct\n");
4608 goto err_out_free_regions
;
4612 sprintf(hw
->irq_name
, DRV_NAME
"@pci:%s", pci_name(pdev
));
4614 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
4616 dev_err(&pdev
->dev
, "cannot map device registers\n");
4617 goto err_out_free_hw
;
4620 /* ring for status responses */
4621 hw
->st_le
= pci_alloc_consistent(pdev
, STATUS_LE_BYTES
, &hw
->st_dma
);
4623 goto err_out_iounmap
;
4625 err
= sky2_init(hw
);
4627 goto err_out_iounmap
;
4629 dev_info(&pdev
->dev
, "Yukon-2 %s chip revision %d\n",
4630 sky2_name(hw
->chip_id
, buf1
, sizeof(buf1
)), hw
->chip_rev
);
4634 dev
= sky2_init_netdev(hw
, 0, using_dac
, wol_default
);
4637 goto err_out_free_pci
;
4640 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
4641 err
= sky2_test_msi(hw
);
4642 if (err
== -EOPNOTSUPP
)
4643 pci_disable_msi(pdev
);
4645 goto err_out_free_netdev
;
4648 err
= register_netdev(dev
);
4650 dev_err(&pdev
->dev
, "cannot register net device\n");
4651 goto err_out_free_netdev
;
4654 netif_carrier_off(dev
);
4656 netif_napi_add(dev
, &hw
->napi
, sky2_poll
, NAPI_WEIGHT
);
4658 err
= request_irq(pdev
->irq
, sky2_intr
,
4659 (hw
->flags
& SKY2_HW_USE_MSI
) ? 0 : IRQF_SHARED
,
4662 dev_err(&pdev
->dev
, "cannot assign irq %d\n", pdev
->irq
);
4663 goto err_out_unregister
;
4665 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4666 napi_enable(&hw
->napi
);
4668 sky2_show_addr(dev
);
4670 if (hw
->ports
> 1) {
4671 struct net_device
*dev1
;
4674 dev1
= sky2_init_netdev(hw
, 1, using_dac
, wol_default
);
4675 if (dev1
&& (err
= register_netdev(dev1
)) == 0)
4676 sky2_show_addr(dev1
);
4678 dev_warn(&pdev
->dev
,
4679 "register of second port failed (%d)\n", err
);
4687 setup_timer(&hw
->watchdog_timer
, sky2_watchdog
, (unsigned long) hw
);
4688 INIT_WORK(&hw
->restart_work
, sky2_restart
);
4690 pci_set_drvdata(pdev
, hw
);
4695 if (hw
->flags
& SKY2_HW_USE_MSI
)
4696 pci_disable_msi(pdev
);
4697 unregister_netdev(dev
);
4698 err_out_free_netdev
:
4701 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4702 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4707 err_out_free_regions
:
4708 pci_release_regions(pdev
);
4710 pci_disable_device(pdev
);
4712 pci_set_drvdata(pdev
, NULL
);
4716 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
4718 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4724 del_timer_sync(&hw
->watchdog_timer
);
4725 cancel_work_sync(&hw
->restart_work
);
4727 for (i
= hw
->ports
-1; i
>= 0; --i
)
4728 unregister_netdev(hw
->dev
[i
]);
4730 sky2_write32(hw
, B0_IMSK
, 0);
4734 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
4735 sky2_read8(hw
, B0_CTST
);
4737 free_irq(pdev
->irq
, hw
);
4738 if (hw
->flags
& SKY2_HW_USE_MSI
)
4739 pci_disable_msi(pdev
);
4740 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
4741 pci_release_regions(pdev
);
4742 pci_disable_device(pdev
);
4744 for (i
= hw
->ports
-1; i
>= 0; --i
)
4745 free_netdev(hw
->dev
[i
]);
4750 pci_set_drvdata(pdev
, NULL
);
4754 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4756 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4762 del_timer_sync(&hw
->watchdog_timer
);
4763 cancel_work_sync(&hw
->restart_work
);
4766 for (i
= 0; i
< hw
->ports
; i
++) {
4767 struct net_device
*dev
= hw
->dev
[i
];
4768 struct sky2_port
*sky2
= netdev_priv(dev
);
4773 sky2_wol_init(sky2
);
4778 sky2_write32(hw
, B0_IMSK
, 0);
4779 napi_disable(&hw
->napi
);
4783 pci_save_state(pdev
);
4784 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
), wol
);
4785 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
4790 static int sky2_resume(struct pci_dev
*pdev
)
4792 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4798 err
= pci_set_power_state(pdev
, PCI_D0
);
4802 err
= pci_restore_state(pdev
);
4806 pci_enable_wake(pdev
, PCI_D0
, 0);
4808 /* Re-enable all clocks */
4809 if (hw
->chip_id
== CHIP_ID_YUKON_EX
||
4810 hw
->chip_id
== CHIP_ID_YUKON_EC_U
||
4811 hw
->chip_id
== CHIP_ID_YUKON_FE_P
)
4812 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
4815 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
4816 napi_enable(&hw
->napi
);
4819 for (i
= 0; i
< hw
->ports
; i
++) {
4820 err
= sky2_reattach(hw
->dev
[i
]);
4830 dev_err(&pdev
->dev
, "resume failed (%d)\n", err
);
4831 pci_disable_device(pdev
);
4836 static void sky2_shutdown(struct pci_dev
*pdev
)
4838 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
4845 del_timer_sync(&hw
->watchdog_timer
);
4847 for (i
= 0; i
< hw
->ports
; i
++) {
4848 struct net_device
*dev
= hw
->dev
[i
];
4849 struct sky2_port
*sky2
= netdev_priv(dev
);
4853 sky2_wol_init(sky2
);
4861 pci_enable_wake(pdev
, PCI_D3hot
, wol
);
4862 pci_enable_wake(pdev
, PCI_D3cold
, wol
);
4864 pci_disable_device(pdev
);
4865 pci_set_power_state(pdev
, PCI_D3hot
);
4868 static struct pci_driver sky2_driver
= {
4870 .id_table
= sky2_id_table
,
4871 .probe
= sky2_probe
,
4872 .remove
= __devexit_p(sky2_remove
),
4874 .suspend
= sky2_suspend
,
4875 .resume
= sky2_resume
,
4877 .shutdown
= sky2_shutdown
,
4880 static int __init
sky2_init_module(void)
4882 pr_info(PFX
"driver version " DRV_VERSION
"\n");
4885 return pci_register_driver(&sky2_driver
);
4888 static void __exit
sky2_cleanup_module(void)
4890 pci_unregister_driver(&sky2_driver
);
4891 sky2_debug_cleanup();
4894 module_init(sky2_init_module
);
4895 module_exit(sky2_cleanup_module
);
4897 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4898 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4899 MODULE_LICENSE("GPL");
4900 MODULE_VERSION(DRV_VERSION
);