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Merge branch 'master' of git://git2.kernel.org/pub/scm/linux/kernel/git/torvalds...
[linux-2.6/linux-2.6-openrd.git] / drivers / net / sky2.c
blob67249c3c9f5046a471f1790745b2b0ccc83fb0c9
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
33 #include <linux/ip.h>
34 #include <net/ip.h>
35 #include <linux/tcp.h>
36 #include <linux/in.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3.
60 */
61
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
73
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
81
82
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
144 { 0 }
145 };
146
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
153
154 static void sky2_set_multicast(struct net_device *dev);
155
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
158 {
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
167 if (ctrl == 0xffff)
168 goto io_error;
169
170 if (!(ctrl & GM_SMI_CT_BUSY))
171 return 0;
172
173 udelay(10);
174 }
175
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
177 return -ETIMEDOUT;
178
179 io_error:
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
181 return -EIO;
182 }
183
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
185 {
186 int i;
187
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
193 if (ctrl == 0xffff)
194 goto io_error;
195
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
198 return 0;
199 }
200
201 udelay(10);
202 }
203
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
205 return -ETIMEDOUT;
206 io_error:
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
208 return -EIO;
209 }
210
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
212 {
213 u16 v;
214 __gm_phy_read(hw, port, reg, &v);
215 return v;
216 }
217
218
219 static void sky2_power_on(struct sky2_hw *hw)
220 {
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
224
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
227
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 else
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
238 u32 reg;
239
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
246
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
251
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
253
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg = sky2_read32(hw, B2_GP_IO);
256 reg |= GLB_GPIO_STAT_RACE_DIS;
257 sky2_write32(hw, B2_GP_IO, reg);
258
259 sky2_read32(hw, B2_GP_IO);
260 }
261
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
264 }
265
266 static void sky2_power_aux(struct sky2_hw *hw)
267 {
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
279 pci_pme_capable(hw->pdev, PCI_D3cold))
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
283
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
286 }
287
288 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
289 {
290 u16 reg;
291
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
294
295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
303 }
304
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv[] = {
307 [FC_NONE] = 0,
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
311 };
312
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv[] = {
315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
319 };
320
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
326 [FC_BOTH] = 0,
327 };
328
329
330 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331 {
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
334
335 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
340 PHY_M_EC_MAC_S_MSK);
341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw->chip_id == CHIP_ID_YUKON_EC)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 else
348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
350
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
352 }
353
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
355 if (sky2_is_copper(hw)) {
356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
359
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
362 u16 spec;
363
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
368 }
369 } else {
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
378 (hw->flags & SKY2_HW_NEWER_PHY)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
382 }
383 }
384 } else {
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
387
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
389 }
390
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
396
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403
404 if (hw->pmd_type == 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
407
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412 }
413
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
415 }
416
417 ctrl = PHY_CT_RESET;
418 ct1000 = 0;
419 adv = PHY_AN_CSMA;
420 reg = 0;
421
422 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
423 if (sky2_is_copper(hw)) {
424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
436
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
442 }
443
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
446 } else {
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
449
450 /* Disable auto update for duplex flow control and duplex */
451 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
452
453 switch (sky2->speed) {
454 case SPEED_1000:
455 ctrl |= PHY_CT_SP1000;
456 reg |= GM_GPCR_SPEED_1000;
457 break;
458 case SPEED_100:
459 ctrl |= PHY_CT_SP100;
460 reg |= GM_GPCR_SPEED_100;
461 break;
462 }
463
464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
469 }
470
471 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
472 if (sky2_is_copper(hw))
473 adv |= copper_fc_adv[sky2->flow_mode];
474 else
475 adv |= fiber_fc_adv[sky2->flow_mode];
476 } else {
477 reg |= GM_GPCR_AU_FCT_DIS;
478 reg |= gm_fc_disable[sky2->flow_mode];
479
480 /* Forward pause packets to GMAC? */
481 if (sky2->flow_mode & FC_RX)
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
483 else
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
485 }
486
487 gma_write16(hw, port, GM_GP_CTRL, reg);
488
489 if (hw->flags & SKY2_HW_GIGABIT)
490 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
491
492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
493 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
494
495 /* Setup Phy LED's */
496 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
497 ledover = 0;
498
499 switch (hw->chip_id) {
500 case CHIP_ID_YUKON_FE:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
503
504 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
505
506 /* delete ACT LED control bits */
507 ctrl &= ~PHY_M_FELP_LED1_MSK;
508 /* change ACT LED control to blink mode */
509 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
510 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
511 break;
512
513 case CHIP_ID_YUKON_FE_P:
514 /* Enable Link Partner Next Page */
515 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 ctrl |= PHY_M_PC_ENA_LIP_NP;
517
518 /* disable Energy Detect and enable scrambler */
519 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
521
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
526
527 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
528 break;
529
530 case CHIP_ID_YUKON_XL:
531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
532
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
535
536 /* set LED Function Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
542
543 /* set Polarity Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
551
552 /* restore page register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
554 break;
555
556 case CHIP_ID_YUKON_EC_U:
557 case CHIP_ID_YUKON_EX:
558 case CHIP_ID_YUKON_SUPR:
559 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
560
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
563
564 /* set LED Function Control register */
565 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
570
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
573 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
574 /* restore page register */
575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
576 break;
577
578 default:
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
581
582 /* turn off the Rx LED (LED_RX) */
583 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
584 }
585
586 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
587 /* apply fixes in PHY AFE */
588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
589
590 /* increase differential signal amplitude in 10BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xaa99);
592 gm_phy_write(hw, port, 0x17, 0x2011);
593
594 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw, port, 0x18, 0xa204);
597 gm_phy_write(hw, port, 0x17, 0x2002);
598 }
599
600 /* set page register to 0 */
601 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
602 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
603 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
606 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
607 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
610
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw, port, 24, 0x2800);
613 gm_phy_write(hw, port, 23, 0x2001);
614
615 /* set page register back to 0 */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
617 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
618 hw->chip_id < CHIP_ID_YUKON_SUPR) {
619 /* no effect on Yukon-XL */
620 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
621
622 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
623 sky2->speed == SPEED_100) {
624 /* turn on 100 Mbps LED (LED_LINK100) */
625 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
626 }
627
628 if (ledover)
629 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
630
631 }
632
633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
634 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
636 else
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
638 }
639
640 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
641 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
642
643 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
644 {
645 u32 reg1;
646
647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
648 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
649 reg1 &= ~phy_power[port];
650
651 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
652 reg1 |= coma_mode[port];
653
654 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
656 sky2_pci_read32(hw, PCI_DEV_REG1);
657
658 if (hw->chip_id == CHIP_ID_YUKON_FE)
659 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
660 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 }
663
664 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
665 {
666 u32 reg1;
667 u16 ctrl;
668
669 /* release GPHY Control reset */
670 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
671
672 /* release GMAC reset */
673 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
674
675 if (hw->flags & SKY2_HW_NEWER_PHY) {
676 /* select page 2 to access MAC control register */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
678
679 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
680 /* allow GMII Power Down */
681 ctrl &= ~PHY_M_MAC_GMIF_PUP;
682 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
683
684 /* set page register back to 0 */
685 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
686 }
687
688 /* setup General Purpose Control Register */
689 gma_write16(hw, port, GM_GP_CTRL,
690 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
691 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
692 GM_GPCR_AU_SPD_DIS);
693
694 if (hw->chip_id != CHIP_ID_YUKON_EC) {
695 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
696 /* select page 2 to access MAC control register */
697 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
698
699 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
700 /* enable Power Down */
701 ctrl |= PHY_M_PC_POW_D_ENA;
702 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
703
704 /* set page register back to 0 */
705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
706 }
707
708 /* set IEEE compatible Power Down Mode (dev. #4.99) */
709 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
710 }
711
712 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
713 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
714 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
715 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
717 }
718
719 /* Force a renegotiation */
720 static void sky2_phy_reinit(struct sky2_port *sky2)
721 {
722 spin_lock_bh(&sky2->phy_lock);
723 sky2_phy_init(sky2->hw, sky2->port);
724 spin_unlock_bh(&sky2->phy_lock);
725 }
726
727 /* Put device in state to listen for Wake On Lan */
728 static void sky2_wol_init(struct sky2_port *sky2)
729 {
730 struct sky2_hw *hw = sky2->hw;
731 unsigned port = sky2->port;
732 enum flow_control save_mode;
733 u16 ctrl;
734 u32 reg1;
735
736 /* Bring hardware out of reset */
737 sky2_write16(hw, B0_CTST, CS_RST_CLR);
738 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
739
740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
742
743 /* Force to 10/100
744 * sky2_reset will re-enable on resume
745 */
746 save_mode = sky2->flow_mode;
747 ctrl = sky2->advertising;
748
749 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
750 sky2->flow_mode = FC_NONE;
751
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_power_up(hw, port);
754 sky2_phy_init(hw, port);
755 spin_unlock_bh(&sky2->phy_lock);
756
757 sky2->flow_mode = save_mode;
758 sky2->advertising = ctrl;
759
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw, port, GM_GP_CTRL,
762 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
763 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
764
765 /* Set WOL address */
766 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
767 sky2->netdev->dev_addr, ETH_ALEN);
768
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
771 ctrl = 0;
772 if (sky2->wol & WAKE_PHY)
773 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
774 else
775 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
776
777 if (sky2->wol & WAKE_MAGIC)
778 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
779 else
780 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
781
782 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
784
785 /* Turn on legacy PCI-Express PME mode */
786 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
787 reg1 |= PCI_Y2_PME_LEGACY;
788 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
789
790 /* block receiver */
791 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
792
793 }
794
795 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
796 {
797 struct net_device *dev = hw->dev[port];
798
799 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
800 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
801 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
802 /* Yukon-Extreme B0 and further Extreme devices */
803 /* enable Store & Forward mode for TX */
804
805 if (dev->mtu <= ETH_DATA_LEN)
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
807 TX_JUMBO_DIS | TX_STFW_ENA);
808
809 else
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
811 TX_JUMBO_ENA| TX_STFW_ENA);
812 } else {
813 if (dev->mtu <= ETH_DATA_LEN)
814 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
815 else {
816 /* set Tx GMAC FIFO Almost Empty Threshold */
817 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
818 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
819
820 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
821
822 /* Can't do offload because of lack of store/forward */
823 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
824 }
825 }
826 }
827
828 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
829 {
830 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
831 u16 reg;
832 u32 rx_reg;
833 int i;
834 const u8 *addr = hw->dev[port]->dev_addr;
835
836 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
837 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
838
839 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
840
841 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
842 /* WA DEV_472 -- looks like crossed wires on port 2 */
843 /* clear GMAC 1 Control reset */
844 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
845 do {
846 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
847 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
848 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
849 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
850 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
851 }
852
853 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
854
855 /* Enable Transmit FIFO Underrun */
856 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
857
858 spin_lock_bh(&sky2->phy_lock);
859 sky2_phy_power_up(hw, port);
860 sky2_phy_init(hw, port);
861 spin_unlock_bh(&sky2->phy_lock);
862
863 /* MIB clear */
864 reg = gma_read16(hw, port, GM_PHY_ADDR);
865 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
866
867 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
868 gma_read16(hw, port, i);
869 gma_write16(hw, port, GM_PHY_ADDR, reg);
870
871 /* transmit control */
872 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
873
874 /* receive control reg: unicast + multicast + no FCS */
875 gma_write16(hw, port, GM_RX_CTRL,
876 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
877
878 /* transmit flow control */
879 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
880
881 /* transmit parameter */
882 gma_write16(hw, port, GM_TX_PARAM,
883 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
884 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
885 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
886 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
887
888 /* serial mode register */
889 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
890 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
891
892 if (hw->dev[port]->mtu > ETH_DATA_LEN)
893 reg |= GM_SMOD_JUMBO_ENA;
894
895 gma_write16(hw, port, GM_SERIAL_MODE, reg);
896
897 /* virtual address for data */
898 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
899
900 /* physical address: used for pause frames */
901 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
902
903 /* ignore counter overflows */
904 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
905 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
906 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
907
908 /* Configure Rx MAC FIFO */
909 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
910 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
911 if (hw->chip_id == CHIP_ID_YUKON_EX ||
912 hw->chip_id == CHIP_ID_YUKON_FE_P)
913 rx_reg |= GMF_RX_OVER_ON;
914
915 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
916
917 if (hw->chip_id == CHIP_ID_YUKON_XL) {
918 /* Hardware errata - clear flush mask */
919 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
920 } else {
921 /* Flush Rx MAC FIFO on any flow control or error */
922 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
923 }
924
925 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
926 reg = RX_GMF_FL_THR_DEF + 1;
927 /* Another magic mystery workaround from sk98lin */
928 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
929 hw->chip_rev == CHIP_REV_YU_FE2_A0)
930 reg = 0x178;
931 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
932
933 /* Configure Tx MAC FIFO */
934 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
935 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
936
937 /* On chips without ram buffer, pause is controled by MAC level */
938 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
939 /* Pause threshold is scaled by 8 in bytes */
940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0)
942 reg = 1568 / 8;
943 else
944 reg = 1024 / 8;
945 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
946 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
947
948 sky2_set_tx_stfwd(hw, port);
949 }
950
951 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
952 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
953 /* disable dynamic watermark */
954 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
955 reg &= ~TX_DYN_WM_ENA;
956 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
957 }
958 }
959
960 /* Assign Ram Buffer allocation to queue */
961 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
962 {
963 u32 end;
964
965 /* convert from K bytes to qwords used for hw register */
966 start *= 1024/8;
967 space *= 1024/8;
968 end = start + space - 1;
969
970 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
971 sky2_write32(hw, RB_ADDR(q, RB_START), start);
972 sky2_write32(hw, RB_ADDR(q, RB_END), end);
973 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
974 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
975
976 if (q == Q_R1 || q == Q_R2) {
977 u32 tp = space - space/4;
978
979 /* On receive queue's set the thresholds
980 * give receiver priority when > 3/4 full
981 * send pause when down to 2K
982 */
983 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
984 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
985
986 tp = space - 2048/8;
987 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
988 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
989 } else {
990 /* Enable store & forward on Tx queue's because
991 * Tx FIFO is only 1K on Yukon
992 */
993 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
994 }
995
996 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
997 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
998 }
999
1000 /* Setup Bus Memory Interface */
1001 static void sky2_qset(struct sky2_hw *hw, u16 q)
1002 {
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1004 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1005 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1006 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1007 }
1008
1009 /* Setup prefetch unit registers. This is the interface between
1010 * hardware and driver list elements
1011 */
1012 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1013 dma_addr_t addr, u32 last)
1014 {
1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1019 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1021
1022 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1023 }
1024
1025 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1026 {
1027 struct sky2_tx_le *le = sky2->tx_le + *slot;
1028
1029 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1030 le->ctrl = 0;
1031 return le;
1032 }
1033
1034 static void tx_init(struct sky2_port *sky2)
1035 {
1036 struct sky2_tx_le *le;
1037
1038 sky2->tx_prod = sky2->tx_cons = 0;
1039 sky2->tx_tcpsum = 0;
1040 sky2->tx_last_mss = 0;
1041
1042 le = get_tx_le(sky2, &sky2->tx_prod);
1043 le->addr = 0;
1044 le->opcode = OP_ADDR64 | HW_OWNER;
1045 sky2->tx_last_upper = 0;
1046 }
1047
1048 /* Update chip's next pointer */
1049 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1050 {
1051 /* Make sure write' to descriptors are complete before we tell hardware */
1052 wmb();
1053 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1054
1055 /* Synchronize I/O on since next processor may write to tail */
1056 mmiowb();
1057 }
1058
1059
1060 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1061 {
1062 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1063 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1064 le->ctrl = 0;
1065 return le;
1066 }
1067
1068 /* Build description to hardware for one receive segment */
1069 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1070 dma_addr_t map, unsigned len)
1071 {
1072 struct sky2_rx_le *le;
1073
1074 if (sizeof(dma_addr_t) > sizeof(u32)) {
1075 le = sky2_next_rx(sky2);
1076 le->addr = cpu_to_le32(upper_32_bits(map));
1077 le->opcode = OP_ADDR64 | HW_OWNER;
1078 }
1079
1080 le = sky2_next_rx(sky2);
1081 le->addr = cpu_to_le32(lower_32_bits(map));
1082 le->length = cpu_to_le16(len);
1083 le->opcode = op | HW_OWNER;
1084 }
1085
1086 /* Build description to hardware for one possibly fragmented skb */
1087 static void sky2_rx_submit(struct sky2_port *sky2,
1088 const struct rx_ring_info *re)
1089 {
1090 int i;
1091
1092 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1093
1094 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1095 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1096 }
1097
1098
1099 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1100 unsigned size)
1101 {
1102 struct sk_buff *skb = re->skb;
1103 int i;
1104
1105 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1106 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1107 return -EIO;
1108
1109 pci_unmap_len_set(re, data_size, size);
1110
1111 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1112 re->frag_addr[i] = pci_map_page(pdev,
1113 skb_shinfo(skb)->frags[i].page,
1114 skb_shinfo(skb)->frags[i].page_offset,
1115 skb_shinfo(skb)->frags[i].size,
1116 PCI_DMA_FROMDEVICE);
1117 return 0;
1118 }
1119
1120 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1121 {
1122 struct sk_buff *skb = re->skb;
1123 int i;
1124
1125 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1126 PCI_DMA_FROMDEVICE);
1127
1128 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1129 pci_unmap_page(pdev, re->frag_addr[i],
1130 skb_shinfo(skb)->frags[i].size,
1131 PCI_DMA_FROMDEVICE);
1132 }
1133
1134 /* Tell chip where to start receive checksum.
1135 * Actually has two checksums, but set both same to avoid possible byte
1136 * order problems.
1137 */
1138 static void rx_set_checksum(struct sky2_port *sky2)
1139 {
1140 struct sky2_rx_le *le = sky2_next_rx(sky2);
1141
1142 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1143 le->ctrl = 0;
1144 le->opcode = OP_TCPSTART | HW_OWNER;
1145
1146 sky2_write32(sky2->hw,
1147 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1148 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1149 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1150 }
1151
1152 /*
1153 * The RX Stop command will not work for Yukon-2 if the BMU does not
1154 * reach the end of packet and since we can't make sure that we have
1155 * incoming data, we must reset the BMU while it is not doing a DMA
1156 * transfer. Since it is possible that the RX path is still active,
1157 * the RX RAM buffer will be stopped first, so any possible incoming
1158 * data will not trigger a DMA. After the RAM buffer is stopped, the
1159 * BMU is polled until any DMA in progress is ended and only then it
1160 * will be reset.
1161 */
1162 static void sky2_rx_stop(struct sky2_port *sky2)
1163 {
1164 struct sky2_hw *hw = sky2->hw;
1165 unsigned rxq = rxqaddr[sky2->port];
1166 int i;
1167
1168 /* disable the RAM Buffer receive queue */
1169 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1170
1171 for (i = 0; i < 0xffff; i++)
1172 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1173 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1174 goto stopped;
1175
1176 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1177 sky2->netdev->name);
1178 stopped:
1179 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1180
1181 /* reset the Rx prefetch unit */
1182 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1183 mmiowb();
1184 }
1185
1186 /* Clean out receive buffer area, assumes receiver hardware stopped */
1187 static void sky2_rx_clean(struct sky2_port *sky2)
1188 {
1189 unsigned i;
1190
1191 memset(sky2->rx_le, 0, RX_LE_BYTES);
1192 for (i = 0; i < sky2->rx_pending; i++) {
1193 struct rx_ring_info *re = sky2->rx_ring + i;
1194
1195 if (re->skb) {
1196 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1197 kfree_skb(re->skb);
1198 re->skb = NULL;
1199 }
1200 }
1201 }
1202
1203 /* Basic MII support */
1204 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1205 {
1206 struct mii_ioctl_data *data = if_mii(ifr);
1207 struct sky2_port *sky2 = netdev_priv(dev);
1208 struct sky2_hw *hw = sky2->hw;
1209 int err = -EOPNOTSUPP;
1210
1211 if (!netif_running(dev))
1212 return -ENODEV; /* Phy still in reset */
1213
1214 switch (cmd) {
1215 case SIOCGMIIPHY:
1216 data->phy_id = PHY_ADDR_MARV;
1217
1218 /* fallthru */
1219 case SIOCGMIIREG: {
1220 u16 val = 0;
1221
1222 spin_lock_bh(&sky2->phy_lock);
1223 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1224 spin_unlock_bh(&sky2->phy_lock);
1225
1226 data->val_out = val;
1227 break;
1228 }
1229
1230 case SIOCSMIIREG:
1231 spin_lock_bh(&sky2->phy_lock);
1232 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1233 data->val_in);
1234 spin_unlock_bh(&sky2->phy_lock);
1235 break;
1236 }
1237 return err;
1238 }
1239
1240 #ifdef SKY2_VLAN_TAG_USED
1241 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1242 {
1243 if (onoff) {
1244 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1245 RX_VLAN_STRIP_ON);
1246 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1247 TX_VLAN_TAG_ON);
1248 } else {
1249 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1250 RX_VLAN_STRIP_OFF);
1251 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1252 TX_VLAN_TAG_OFF);
1253 }
1254 }
1255
1256 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1257 {
1258 struct sky2_port *sky2 = netdev_priv(dev);
1259 struct sky2_hw *hw = sky2->hw;
1260 u16 port = sky2->port;
1261
1262 netif_tx_lock_bh(dev);
1263 napi_disable(&hw->napi);
1264
1265 sky2->vlgrp = grp;
1266 sky2_set_vlan_mode(hw, port, grp != NULL);
1267
1268 sky2_read32(hw, B0_Y2_SP_LISR);
1269 napi_enable(&hw->napi);
1270 netif_tx_unlock_bh(dev);
1271 }
1272 #endif
1273
1274 /* Amount of required worst case padding in rx buffer */
1275 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1276 {
1277 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1278 }
1279
1280 /*
1281 * Allocate an skb for receiving. If the MTU is large enough
1282 * make the skb non-linear with a fragment list of pages.
1283 */
1284 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1285 {
1286 struct sk_buff *skb;
1287 int i;
1288
1289 skb = netdev_alloc_skb(sky2->netdev,
1290 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1291 if (!skb)
1292 goto nomem;
1293
1294 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1295 unsigned char *start;
1296 /*
1297 * Workaround for a bug in FIFO that cause hang
1298 * if the FIFO if the receive buffer is not 64 byte aligned.
1299 * The buffer returned from netdev_alloc_skb is
1300 * aligned except if slab debugging is enabled.
1301 */
1302 start = PTR_ALIGN(skb->data, 8);
1303 skb_reserve(skb, start - skb->data);
1304 } else
1305 skb_reserve(skb, NET_IP_ALIGN);
1306
1307 for (i = 0; i < sky2->rx_nfrags; i++) {
1308 struct page *page = alloc_page(GFP_ATOMIC);
1309
1310 if (!page)
1311 goto free_partial;
1312 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1313 }
1314
1315 return skb;
1316 free_partial:
1317 kfree_skb(skb);
1318 nomem:
1319 return NULL;
1320 }
1321
1322 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1323 {
1324 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1325 }
1326
1327 /*
1328 * Allocate and setup receiver buffer pool.
1329 * Normal case this ends up creating one list element for skb
1330 * in the receive ring. Worst case if using large MTU and each
1331 * allocation falls on a different 64 bit region, that results
1332 * in 6 list elements per ring entry.
1333 * One element is used for checksum enable/disable, and one
1334 * extra to avoid wrap.
1335 */
1336 static int sky2_rx_start(struct sky2_port *sky2)
1337 {
1338 struct sky2_hw *hw = sky2->hw;
1339 struct rx_ring_info *re;
1340 unsigned rxq = rxqaddr[sky2->port];
1341 unsigned i, size, thresh;
1342
1343 sky2->rx_put = sky2->rx_next = 0;
1344 sky2_qset(hw, rxq);
1345
1346 /* On PCI express lowering the watermark gives better performance */
1347 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1348 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1349
1350 /* These chips have no ram buffer?
1351 * MAC Rx RAM Read is controlled by hardware */
1352 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1353 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1354 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1355 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1356
1357 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1358
1359 if (!(hw->flags & SKY2_HW_NEW_LE))
1360 rx_set_checksum(sky2);
1361
1362 /* Space needed for frame data + headers rounded up */
1363 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1364
1365 /* Stopping point for hardware truncation */
1366 thresh = (size - 8) / sizeof(u32);
1367
1368 sky2->rx_nfrags = size >> PAGE_SHIFT;
1369 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1370
1371 /* Compute residue after pages */
1372 size -= sky2->rx_nfrags << PAGE_SHIFT;
1373
1374 /* Optimize to handle small packets and headers */
1375 if (size < copybreak)
1376 size = copybreak;
1377 if (size < ETH_HLEN)
1378 size = ETH_HLEN;
1379
1380 sky2->rx_data_size = size;
1381
1382 /* Fill Rx ring */
1383 for (i = 0; i < sky2->rx_pending; i++) {
1384 re = sky2->rx_ring + i;
1385
1386 re->skb = sky2_rx_alloc(sky2);
1387 if (!re->skb)
1388 goto nomem;
1389
1390 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1391 dev_kfree_skb(re->skb);
1392 re->skb = NULL;
1393 goto nomem;
1394 }
1395
1396 sky2_rx_submit(sky2, re);
1397 }
1398
1399 /*
1400 * The receiver hangs if it receives frames larger than the
1401 * packet buffer. As a workaround, truncate oversize frames, but
1402 * the register is limited to 9 bits, so if you do frames > 2052
1403 * you better get the MTU right!
1404 */
1405 if (thresh > 0x1ff)
1406 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1407 else {
1408 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1409 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1410 }
1411
1412 /* Tell chip about available buffers */
1413 sky2_rx_update(sky2, rxq);
1414
1415 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1416 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1417 /*
1418 * Disable flushing of non ASF packets;
1419 * must be done after initializing the BMUs;
1420 * drivers without ASF support should do this too, otherwise
1421 * it may happen that they cannot run on ASF devices;
1422 * remember that the MAC FIFO isn't reset during initialization.
1423 */
1424 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1425 }
1426
1427 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1428 /* Enable RX Home Address & Routing Header checksum fix */
1429 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1430 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1431
1432 /* Enable TX Home Address & Routing Header checksum fix */
1433 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1434 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1435 }
1436
1437
1438
1439 return 0;
1440 nomem:
1441 sky2_rx_clean(sky2);
1442 return -ENOMEM;
1443 }
1444
1445 static int sky2_alloc_buffers(struct sky2_port *sky2)
1446 {
1447 struct sky2_hw *hw = sky2->hw;
1448
1449 /* must be power of 2 */
1450 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1451 sky2->tx_ring_size *
1452 sizeof(struct sky2_tx_le),
1453 &sky2->tx_le_map);
1454 if (!sky2->tx_le)
1455 goto nomem;
1456
1457 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1458 GFP_KERNEL);
1459 if (!sky2->tx_ring)
1460 goto nomem;
1461
1462 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1463 &sky2->rx_le_map);
1464 if (!sky2->rx_le)
1465 goto nomem;
1466 memset(sky2->rx_le, 0, RX_LE_BYTES);
1467
1468 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1469 GFP_KERNEL);
1470 if (!sky2->rx_ring)
1471 goto nomem;
1472
1473 return 0;
1474 nomem:
1475 return -ENOMEM;
1476 }
1477
1478 static void sky2_free_buffers(struct sky2_port *sky2)
1479 {
1480 struct sky2_hw *hw = sky2->hw;
1481
1482 if (sky2->rx_le) {
1483 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1484 sky2->rx_le, sky2->rx_le_map);
1485 sky2->rx_le = NULL;
1486 }
1487 if (sky2->tx_le) {
1488 pci_free_consistent(hw->pdev,
1489 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1490 sky2->tx_le, sky2->tx_le_map);
1491 sky2->tx_le = NULL;
1492 }
1493 kfree(sky2->tx_ring);
1494 kfree(sky2->rx_ring);
1495
1496 sky2->tx_ring = NULL;
1497 sky2->rx_ring = NULL;
1498 }
1499
1500 /* Bring up network interface. */
1501 static int sky2_up(struct net_device *dev)
1502 {
1503 struct sky2_port *sky2 = netdev_priv(dev);
1504 struct sky2_hw *hw = sky2->hw;
1505 unsigned port = sky2->port;
1506 u32 imask, ramsize;
1507 int cap, err;
1508 struct net_device *otherdev = hw->dev[sky2->port^1];
1509
1510 /*
1511 * On dual port PCI-X card, there is an problem where status
1512 * can be received out of order due to split transactions
1513 */
1514 if (otherdev && netif_running(otherdev) &&
1515 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1516 u16 cmd;
1517
1518 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1519 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1520 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1521
1522 }
1523
1524 netif_carrier_off(dev);
1525
1526 err = sky2_alloc_buffers(sky2);
1527 if (err)
1528 goto err_out;
1529
1530 tx_init(sky2);
1531
1532 sky2_mac_init(hw, port);
1533
1534 /* Register is number of 4K blocks on internal RAM buffer. */
1535 ramsize = sky2_read8(hw, B2_E_0) * 4;
1536 if (ramsize > 0) {
1537 u32 rxspace;
1538
1539 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1540 if (ramsize < 16)
1541 rxspace = ramsize / 2;
1542 else
1543 rxspace = 8 + (2*(ramsize - 16))/3;
1544
1545 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1546 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1547
1548 /* Make sure SyncQ is disabled */
1549 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1550 RB_RST_SET);
1551 }
1552
1553 sky2_qset(hw, txqaddr[port]);
1554
1555 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1556 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1557 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1558
1559 /* Set almost empty threshold */
1560 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1561 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1562 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1563
1564 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1565 sky2->tx_ring_size - 1);
1566
1567 #ifdef SKY2_VLAN_TAG_USED
1568 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1569 #endif
1570
1571 err = sky2_rx_start(sky2);
1572 if (err)
1573 goto err_out;
1574
1575 /* Enable interrupts from phy/mac for port */
1576 imask = sky2_read32(hw, B0_IMSK);
1577 imask |= portirq_msk[port];
1578 sky2_write32(hw, B0_IMSK, imask);
1579 sky2_read32(hw, B0_IMSK);
1580
1581 if (netif_msg_ifup(sky2))
1582 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1583
1584 return 0;
1585
1586 err_out:
1587 sky2_free_buffers(sky2);
1588 return err;
1589 }
1590
1591 /* Modular subtraction in ring */
1592 static inline int tx_inuse(const struct sky2_port *sky2)
1593 {
1594 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1595 }
1596
1597 /* Number of list elements available for next tx */
1598 static inline int tx_avail(const struct sky2_port *sky2)
1599 {
1600 return sky2->tx_pending - tx_inuse(sky2);
1601 }
1602
1603 /* Estimate of number of transmit list elements required */
1604 static unsigned tx_le_req(const struct sk_buff *skb)
1605 {
1606 unsigned count;
1607
1608 count = (skb_shinfo(skb)->nr_frags + 1)
1609 * (sizeof(dma_addr_t) / sizeof(u32));
1610
1611 if (skb_is_gso(skb))
1612 ++count;
1613 else if (sizeof(dma_addr_t) == sizeof(u32))
1614 ++count; /* possible vlan */
1615
1616 if (skb->ip_summed == CHECKSUM_PARTIAL)
1617 ++count;
1618
1619 return count;
1620 }
1621
1622 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1623 {
1624 if (re->flags & TX_MAP_SINGLE)
1625 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1626 pci_unmap_len(re, maplen),
1627 PCI_DMA_TODEVICE);
1628 else if (re->flags & TX_MAP_PAGE)
1629 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1630 pci_unmap_len(re, maplen),
1631 PCI_DMA_TODEVICE);
1632 re->flags = 0;
1633 }
1634
1635 /*
1636 * Put one packet in ring for transmit.
1637 * A single packet can generate multiple list elements, and
1638 * the number of ring elements will probably be less than the number
1639 * of list elements used.
1640 */
1641 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1642 struct net_device *dev)
1643 {
1644 struct sky2_port *sky2 = netdev_priv(dev);
1645 struct sky2_hw *hw = sky2->hw;
1646 struct sky2_tx_le *le = NULL;
1647 struct tx_ring_info *re;
1648 unsigned i, len;
1649 dma_addr_t mapping;
1650 u32 upper;
1651 u16 slot;
1652 u16 mss;
1653 u8 ctrl;
1654
1655 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1656 return NETDEV_TX_BUSY;
1657
1658 len = skb_headlen(skb);
1659 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1660
1661 if (pci_dma_mapping_error(hw->pdev, mapping))
1662 goto mapping_error;
1663
1664 slot = sky2->tx_prod;
1665 if (unlikely(netif_msg_tx_queued(sky2)))
1666 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1667 dev->name, slot, skb->len);
1668
1669 /* Send high bits if needed */
1670 upper = upper_32_bits(mapping);
1671 if (upper != sky2->tx_last_upper) {
1672 le = get_tx_le(sky2, &slot);
1673 le->addr = cpu_to_le32(upper);
1674 sky2->tx_last_upper = upper;
1675 le->opcode = OP_ADDR64 | HW_OWNER;
1676 }
1677
1678 /* Check for TCP Segmentation Offload */
1679 mss = skb_shinfo(skb)->gso_size;
1680 if (mss != 0) {
1681
1682 if (!(hw->flags & SKY2_HW_NEW_LE))
1683 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1684
1685 if (mss != sky2->tx_last_mss) {
1686 le = get_tx_le(sky2, &slot);
1687 le->addr = cpu_to_le32(mss);
1688
1689 if (hw->flags & SKY2_HW_NEW_LE)
1690 le->opcode = OP_MSS | HW_OWNER;
1691 else
1692 le->opcode = OP_LRGLEN | HW_OWNER;
1693 sky2->tx_last_mss = mss;
1694 }
1695 }
1696
1697 ctrl = 0;
1698 #ifdef SKY2_VLAN_TAG_USED
1699 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1700 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1701 if (!le) {
1702 le = get_tx_le(sky2, &slot);
1703 le->addr = 0;
1704 le->opcode = OP_VLAN|HW_OWNER;
1705 } else
1706 le->opcode |= OP_VLAN;
1707 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1708 ctrl |= INS_VLAN;
1709 }
1710 #endif
1711
1712 /* Handle TCP checksum offload */
1713 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1714 /* On Yukon EX (some versions) encoding change. */
1715 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1716 ctrl |= CALSUM; /* auto checksum */
1717 else {
1718 const unsigned offset = skb_transport_offset(skb);
1719 u32 tcpsum;
1720
1721 tcpsum = offset << 16; /* sum start */
1722 tcpsum |= offset + skb->csum_offset; /* sum write */
1723
1724 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1725 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1726 ctrl |= UDPTCP;
1727
1728 if (tcpsum != sky2->tx_tcpsum) {
1729 sky2->tx_tcpsum = tcpsum;
1730
1731 le = get_tx_le(sky2, &slot);
1732 le->addr = cpu_to_le32(tcpsum);
1733 le->length = 0; /* initial checksum value */
1734 le->ctrl = 1; /* one packet */
1735 le->opcode = OP_TCPLISW | HW_OWNER;
1736 }
1737 }
1738 }
1739
1740 re = sky2->tx_ring + slot;
1741 re->flags = TX_MAP_SINGLE;
1742 pci_unmap_addr_set(re, mapaddr, mapping);
1743 pci_unmap_len_set(re, maplen, len);
1744
1745 le = get_tx_le(sky2, &slot);
1746 le->addr = cpu_to_le32(lower_32_bits(mapping));
1747 le->length = cpu_to_le16(len);
1748 le->ctrl = ctrl;
1749 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1750
1751
1752 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1753 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1754
1755 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1756 frag->size, PCI_DMA_TODEVICE);
1757
1758 if (pci_dma_mapping_error(hw->pdev, mapping))
1759 goto mapping_unwind;
1760
1761 upper = upper_32_bits(mapping);
1762 if (upper != sky2->tx_last_upper) {
1763 le = get_tx_le(sky2, &slot);
1764 le->addr = cpu_to_le32(upper);
1765 sky2->tx_last_upper = upper;
1766 le->opcode = OP_ADDR64 | HW_OWNER;
1767 }
1768
1769 re = sky2->tx_ring + slot;
1770 re->flags = TX_MAP_PAGE;
1771 pci_unmap_addr_set(re, mapaddr, mapping);
1772 pci_unmap_len_set(re, maplen, frag->size);
1773
1774 le = get_tx_le(sky2, &slot);
1775 le->addr = cpu_to_le32(lower_32_bits(mapping));
1776 le->length = cpu_to_le16(frag->size);
1777 le->ctrl = ctrl;
1778 le->opcode = OP_BUFFER | HW_OWNER;
1779 }
1780
1781 re->skb = skb;
1782 le->ctrl |= EOP;
1783
1784 sky2->tx_prod = slot;
1785
1786 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1787 netif_stop_queue(dev);
1788
1789 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1790
1791 return NETDEV_TX_OK;
1792
1793 mapping_unwind:
1794 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1795 re = sky2->tx_ring + i;
1796
1797 sky2_tx_unmap(hw->pdev, re);
1798 }
1799
1800 mapping_error:
1801 if (net_ratelimit())
1802 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1803 dev_kfree_skb(skb);
1804 return NETDEV_TX_OK;
1805 }
1806
1807 /*
1808 * Free ring elements from starting at tx_cons until "done"
1809 *
1810 * NB:
1811 * 1. The hardware will tell us about partial completion of multi-part
1812 * buffers so make sure not to free skb to early.
1813 * 2. This may run in parallel start_xmit because the it only
1814 * looks at the tail of the queue of FIFO (tx_cons), not
1815 * the head (tx_prod)
1816 */
1817 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1818 {
1819 struct net_device *dev = sky2->netdev;
1820 unsigned idx;
1821
1822 BUG_ON(done >= sky2->tx_ring_size);
1823
1824 for (idx = sky2->tx_cons; idx != done;
1825 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1826 struct tx_ring_info *re = sky2->tx_ring + idx;
1827 struct sk_buff *skb = re->skb;
1828
1829 sky2_tx_unmap(sky2->hw->pdev, re);
1830
1831 if (skb) {
1832 if (unlikely(netif_msg_tx_done(sky2)))
1833 printk(KERN_DEBUG "%s: tx done %u\n",
1834 dev->name, idx);
1835
1836 dev->stats.tx_packets++;
1837 dev->stats.tx_bytes += skb->len;
1838
1839 re->skb = NULL;
1840 dev_kfree_skb_any(skb);
1841
1842 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1843 }
1844 }
1845
1846 sky2->tx_cons = idx;
1847 smp_mb();
1848
1849 /* Wake unless it's detached, and called e.g. from sky2_down() */
1850 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
1851 netif_wake_queue(dev);
1852 }
1853
1854 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1855 {
1856 /* Disable Force Sync bit and Enable Alloc bit */
1857 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1858 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1859
1860 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1861 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1862 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1863
1864 /* Reset the PCI FIFO of the async Tx queue */
1865 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1866 BMU_RST_SET | BMU_FIFO_RST);
1867
1868 /* Reset the Tx prefetch units */
1869 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1870 PREF_UNIT_RST_SET);
1871
1872 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1873 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1874 }
1875
1876 /* Network shutdown */
1877 static int sky2_down(struct net_device *dev)
1878 {
1879 struct sky2_port *sky2 = netdev_priv(dev);
1880 struct sky2_hw *hw = sky2->hw;
1881 unsigned port = sky2->port;
1882 u16 ctrl;
1883 u32 imask;
1884
1885 /* Never really got started! */
1886 if (!sky2->tx_le)
1887 return 0;
1888
1889 if (netif_msg_ifdown(sky2))
1890 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1891
1892 /* Force flow control off */
1893 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1894
1895 /* Stop transmitter */
1896 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1897 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1898
1899 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1900 RB_RST_SET | RB_DIS_OP_MD);
1901
1902 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1903 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1904 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1905
1906 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1907
1908 /* Workaround shared GMAC reset */
1909 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1910 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1911 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1912
1913 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1914
1915 /* Force any delayed status interrrupt and NAPI */
1916 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1917 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1918 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1919 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1920
1921 sky2_rx_stop(sky2);
1922
1923 /* Disable port IRQ */
1924 imask = sky2_read32(hw, B0_IMSK);
1925 imask &= ~portirq_msk[port];
1926 sky2_write32(hw, B0_IMSK, imask);
1927 sky2_read32(hw, B0_IMSK);
1928
1929 synchronize_irq(hw->pdev->irq);
1930 napi_synchronize(&hw->napi);
1931
1932 spin_lock_bh(&sky2->phy_lock);
1933 sky2_phy_power_down(hw, port);
1934 spin_unlock_bh(&sky2->phy_lock);
1935
1936 sky2_tx_reset(hw, port);
1937
1938 /* Free any pending frames stuck in HW queue */
1939 sky2_tx_complete(sky2, sky2->tx_prod);
1940
1941 sky2_rx_clean(sky2);
1942
1943 sky2_free_buffers(sky2);
1944
1945 return 0;
1946 }
1947
1948 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1949 {
1950 if (hw->flags & SKY2_HW_FIBRE_PHY)
1951 return SPEED_1000;
1952
1953 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1954 if (aux & PHY_M_PS_SPEED_100)
1955 return SPEED_100;
1956 else
1957 return SPEED_10;
1958 }
1959
1960 switch (aux & PHY_M_PS_SPEED_MSK) {
1961 case PHY_M_PS_SPEED_1000:
1962 return SPEED_1000;
1963 case PHY_M_PS_SPEED_100:
1964 return SPEED_100;
1965 default:
1966 return SPEED_10;
1967 }
1968 }
1969
1970 static void sky2_link_up(struct sky2_port *sky2)
1971 {
1972 struct sky2_hw *hw = sky2->hw;
1973 unsigned port = sky2->port;
1974 u16 reg;
1975 static const char *fc_name[] = {
1976 [FC_NONE] = "none",
1977 [FC_TX] = "tx",
1978 [FC_RX] = "rx",
1979 [FC_BOTH] = "both",
1980 };
1981
1982 /* enable Rx/Tx */
1983 reg = gma_read16(hw, port, GM_GP_CTRL);
1984 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1985 gma_write16(hw, port, GM_GP_CTRL, reg);
1986
1987 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1988
1989 netif_carrier_on(sky2->netdev);
1990
1991 mod_timer(&hw->watchdog_timer, jiffies + 1);
1992
1993 /* Turn on link LED */
1994 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1995 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1996
1997 if (netif_msg_link(sky2))
1998 printk(KERN_INFO PFX
1999 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2000 sky2->netdev->name, sky2->speed,
2001 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2002 fc_name[sky2->flow_status]);
2003 }
2004
2005 static void sky2_link_down(struct sky2_port *sky2)
2006 {
2007 struct sky2_hw *hw = sky2->hw;
2008 unsigned port = sky2->port;
2009 u16 reg;
2010
2011 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2012
2013 reg = gma_read16(hw, port, GM_GP_CTRL);
2014 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2015 gma_write16(hw, port, GM_GP_CTRL, reg);
2016
2017 netif_carrier_off(sky2->netdev);
2018
2019 /* Turn off link LED */
2020 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2021
2022 if (netif_msg_link(sky2))
2023 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2024
2025 sky2_phy_init(hw, port);
2026 }
2027
2028 static enum flow_control sky2_flow(int rx, int tx)
2029 {
2030 if (rx)
2031 return tx ? FC_BOTH : FC_RX;
2032 else
2033 return tx ? FC_TX : FC_NONE;
2034 }
2035
2036 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2037 {
2038 struct sky2_hw *hw = sky2->hw;
2039 unsigned port = sky2->port;
2040 u16 advert, lpa;
2041
2042 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2043 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2044 if (lpa & PHY_M_AN_RF) {
2045 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2046 return -1;
2047 }
2048
2049 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2050 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2051 sky2->netdev->name);
2052 return -1;
2053 }
2054
2055 sky2->speed = sky2_phy_speed(hw, aux);
2056 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2057
2058 /* Since the pause result bits seem to in different positions on
2059 * different chips. look at registers.
2060 */
2061 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2062 /* Shift for bits in fiber PHY */
2063 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2064 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2065
2066 if (advert & ADVERTISE_1000XPAUSE)
2067 advert |= ADVERTISE_PAUSE_CAP;
2068 if (advert & ADVERTISE_1000XPSE_ASYM)
2069 advert |= ADVERTISE_PAUSE_ASYM;
2070 if (lpa & LPA_1000XPAUSE)
2071 lpa |= LPA_PAUSE_CAP;
2072 if (lpa & LPA_1000XPAUSE_ASYM)
2073 lpa |= LPA_PAUSE_ASYM;
2074 }
2075
2076 sky2->flow_status = FC_NONE;
2077 if (advert & ADVERTISE_PAUSE_CAP) {
2078 if (lpa & LPA_PAUSE_CAP)
2079 sky2->flow_status = FC_BOTH;
2080 else if (advert & ADVERTISE_PAUSE_ASYM)
2081 sky2->flow_status = FC_RX;
2082 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2083 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2084 sky2->flow_status = FC_TX;
2085 }
2086
2087 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2088 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2089 sky2->flow_status = FC_NONE;
2090
2091 if (sky2->flow_status & FC_TX)
2092 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2093 else
2094 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2095
2096 return 0;
2097 }
2098
2099 /* Interrupt from PHY */
2100 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2101 {
2102 struct net_device *dev = hw->dev[port];
2103 struct sky2_port *sky2 = netdev_priv(dev);
2104 u16 istatus, phystat;
2105
2106 if (!netif_running(dev))
2107 return;
2108
2109 spin_lock(&sky2->phy_lock);
2110 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2111 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2112
2113 if (netif_msg_intr(sky2))
2114 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2115 sky2->netdev->name, istatus, phystat);
2116
2117 if (istatus & PHY_M_IS_AN_COMPL) {
2118 if (sky2_autoneg_done(sky2, phystat) == 0)
2119 sky2_link_up(sky2);
2120 goto out;
2121 }
2122
2123 if (istatus & PHY_M_IS_LSP_CHANGE)
2124 sky2->speed = sky2_phy_speed(hw, phystat);
2125
2126 if (istatus & PHY_M_IS_DUP_CHANGE)
2127 sky2->duplex =
2128 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2129
2130 if (istatus & PHY_M_IS_LST_CHANGE) {
2131 if (phystat & PHY_M_PS_LINK_UP)
2132 sky2_link_up(sky2);
2133 else
2134 sky2_link_down(sky2);
2135 }
2136 out:
2137 spin_unlock(&sky2->phy_lock);
2138 }
2139
2140 /* Special quick link interrupt (Yukon-2 Optima only) */
2141 static void sky2_qlink_intr(struct sky2_hw *hw)
2142 {
2143 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2144 u32 imask;
2145 u16 phy;
2146
2147 /* disable irq */
2148 imask = sky2_read32(hw, B0_IMSK);
2149 imask &= ~Y2_IS_PHY_QLNK;
2150 sky2_write32(hw, B0_IMSK, imask);
2151
2152 /* reset PHY Link Detect */
2153 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2154 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2155 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2156 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2157
2158 sky2_link_up(sky2);
2159 }
2160
2161 /* Transmit timeout is only called if we are running, carrier is up
2162 * and tx queue is full (stopped).
2163 */
2164 static void sky2_tx_timeout(struct net_device *dev)
2165 {
2166 struct sky2_port *sky2 = netdev_priv(dev);
2167 struct sky2_hw *hw = sky2->hw;
2168
2169 if (netif_msg_timer(sky2))
2170 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2171
2172 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2173 dev->name, sky2->tx_cons, sky2->tx_prod,
2174 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2175 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2176
2177 /* can't restart safely under softirq */
2178 schedule_work(&hw->restart_work);
2179 }
2180
2181 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2182 {
2183 struct sky2_port *sky2 = netdev_priv(dev);
2184 struct sky2_hw *hw = sky2->hw;
2185 unsigned port = sky2->port;
2186 int err;
2187 u16 ctl, mode;
2188 u32 imask;
2189
2190 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2191 return -EINVAL;
2192
2193 if (new_mtu > ETH_DATA_LEN &&
2194 (hw->chip_id == CHIP_ID_YUKON_FE ||
2195 hw->chip_id == CHIP_ID_YUKON_FE_P))
2196 return -EINVAL;
2197
2198 if (!netif_running(dev)) {
2199 dev->mtu = new_mtu;
2200 return 0;
2201 }
2202
2203 imask = sky2_read32(hw, B0_IMSK);
2204 sky2_write32(hw, B0_IMSK, 0);
2205
2206 dev->trans_start = jiffies; /* prevent tx timeout */
2207 netif_stop_queue(dev);
2208 napi_disable(&hw->napi);
2209
2210 synchronize_irq(hw->pdev->irq);
2211
2212 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2213 sky2_set_tx_stfwd(hw, port);
2214
2215 ctl = gma_read16(hw, port, GM_GP_CTRL);
2216 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2217 sky2_rx_stop(sky2);
2218 sky2_rx_clean(sky2);
2219
2220 dev->mtu = new_mtu;
2221
2222 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2223 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2224
2225 if (dev->mtu > ETH_DATA_LEN)
2226 mode |= GM_SMOD_JUMBO_ENA;
2227
2228 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2229
2230 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2231
2232 err = sky2_rx_start(sky2);
2233 sky2_write32(hw, B0_IMSK, imask);
2234
2235 sky2_read32(hw, B0_Y2_SP_LISR);
2236 napi_enable(&hw->napi);
2237
2238 if (err)
2239 dev_close(dev);
2240 else {
2241 gma_write16(hw, port, GM_GP_CTRL, ctl);
2242
2243 netif_wake_queue(dev);
2244 }
2245
2246 return err;
2247 }
2248
2249 /* For small just reuse existing skb for next receive */
2250 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2251 const struct rx_ring_info *re,
2252 unsigned length)
2253 {
2254 struct sk_buff *skb;
2255
2256 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2257 if (likely(skb)) {
2258 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2259 length, PCI_DMA_FROMDEVICE);
2260 skb_copy_from_linear_data(re->skb, skb->data, length);
2261 skb->ip_summed = re->skb->ip_summed;
2262 skb->csum = re->skb->csum;
2263 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2264 length, PCI_DMA_FROMDEVICE);
2265 re->skb->ip_summed = CHECKSUM_NONE;
2266 skb_put(skb, length);
2267 }
2268 return skb;
2269 }
2270
2271 /* Adjust length of skb with fragments to match received data */
2272 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2273 unsigned int length)
2274 {
2275 int i, num_frags;
2276 unsigned int size;
2277
2278 /* put header into skb */
2279 size = min(length, hdr_space);
2280 skb->tail += size;
2281 skb->len += size;
2282 length -= size;
2283
2284 num_frags = skb_shinfo(skb)->nr_frags;
2285 for (i = 0; i < num_frags; i++) {
2286 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2287
2288 if (length == 0) {
2289 /* don't need this page */
2290 __free_page(frag->page);
2291 --skb_shinfo(skb)->nr_frags;
2292 } else {
2293 size = min(length, (unsigned) PAGE_SIZE);
2294
2295 frag->size = size;
2296 skb->data_len += size;
2297 skb->truesize += size;
2298 skb->len += size;
2299 length -= size;
2300 }
2301 }
2302 }
2303
2304 /* Normal packet - take skb from ring element and put in a new one */
2305 static struct sk_buff *receive_new(struct sky2_port *sky2,
2306 struct rx_ring_info *re,
2307 unsigned int length)
2308 {
2309 struct sk_buff *skb, *nskb;
2310 unsigned hdr_space = sky2->rx_data_size;
2311
2312 /* Don't be tricky about reusing pages (yet) */
2313 nskb = sky2_rx_alloc(sky2);
2314 if (unlikely(!nskb))
2315 return NULL;
2316
2317 skb = re->skb;
2318 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2319
2320 prefetch(skb->data);
2321 re->skb = nskb;
2322 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2323 dev_kfree_skb(nskb);
2324 re->skb = skb;
2325 return NULL;
2326 }
2327
2328 if (skb_shinfo(skb)->nr_frags)
2329 skb_put_frags(skb, hdr_space, length);
2330 else
2331 skb_put(skb, length);
2332 return skb;
2333 }
2334
2335 /*
2336 * Receive one packet.
2337 * For larger packets, get new buffer.
2338 */
2339 static struct sk_buff *sky2_receive(struct net_device *dev,
2340 u16 length, u32 status)
2341 {
2342 struct sky2_port *sky2 = netdev_priv(dev);
2343 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2344 struct sk_buff *skb = NULL;
2345 u16 count = (status & GMR_FS_LEN) >> 16;
2346
2347 #ifdef SKY2_VLAN_TAG_USED
2348 /* Account for vlan tag */
2349 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2350 count -= VLAN_HLEN;
2351 #endif
2352
2353 if (unlikely(netif_msg_rx_status(sky2)))
2354 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2355 dev->name, sky2->rx_next, status, length);
2356
2357 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2358 prefetch(sky2->rx_ring + sky2->rx_next);
2359
2360 /* This chip has hardware problems that generates bogus status.
2361 * So do only marginal checking and expect higher level protocols
2362 * to handle crap frames.
2363 */
2364 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2365 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2366 length != count)
2367 goto okay;
2368
2369 if (status & GMR_FS_ANY_ERR)
2370 goto error;
2371
2372 if (!(status & GMR_FS_RX_OK))
2373 goto resubmit;
2374
2375 /* if length reported by DMA does not match PHY, packet was truncated */
2376 if (length != count)
2377 goto len_error;
2378
2379 okay:
2380 if (length < copybreak)
2381 skb = receive_copy(sky2, re, length);
2382 else
2383 skb = receive_new(sky2, re, length);
2384 resubmit:
2385 sky2_rx_submit(sky2, re);
2386
2387 return skb;
2388
2389 len_error:
2390 /* Truncation of overlength packets
2391 causes PHY length to not match MAC length */
2392 ++dev->stats.rx_length_errors;
2393 if (netif_msg_rx_err(sky2) && net_ratelimit())
2394 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2395 dev->name, status, length);
2396 goto resubmit;
2397
2398 error:
2399 ++dev->stats.rx_errors;
2400 if (status & GMR_FS_RX_FF_OV) {
2401 dev->stats.rx_over_errors++;
2402 goto resubmit;
2403 }
2404
2405 if (netif_msg_rx_err(sky2) && net_ratelimit())
2406 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2407 dev->name, status, length);
2408
2409 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2410 dev->stats.rx_length_errors++;
2411 if (status & GMR_FS_FRAGMENT)
2412 dev->stats.rx_frame_errors++;
2413 if (status & GMR_FS_CRC_ERR)
2414 dev->stats.rx_crc_errors++;
2415
2416 goto resubmit;
2417 }
2418
2419 /* Transmit complete */
2420 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2421 {
2422 struct sky2_port *sky2 = netdev_priv(dev);
2423
2424 if (netif_running(dev))
2425 sky2_tx_complete(sky2, last);
2426 }
2427
2428 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2429 u32 status, struct sk_buff *skb)
2430 {
2431 #ifdef SKY2_VLAN_TAG_USED
2432 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2433 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2434 if (skb->ip_summed == CHECKSUM_NONE)
2435 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2436 else
2437 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2438 vlan_tag, skb);
2439 return;
2440 }
2441 #endif
2442 if (skb->ip_summed == CHECKSUM_NONE)
2443 netif_receive_skb(skb);
2444 else
2445 napi_gro_receive(&sky2->hw->napi, skb);
2446 }
2447
2448 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2449 unsigned packets, unsigned bytes)
2450 {
2451 if (packets) {
2452 struct net_device *dev = hw->dev[port];
2453
2454 dev->stats.rx_packets += packets;
2455 dev->stats.rx_bytes += bytes;
2456 dev->last_rx = jiffies;
2457 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2458 }
2459 }
2460
2461 /* Process status response ring */
2462 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2463 {
2464 int work_done = 0;
2465 unsigned int total_bytes[2] = { 0 };
2466 unsigned int total_packets[2] = { 0 };
2467
2468 rmb();
2469 do {
2470 struct sky2_port *sky2;
2471 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2472 unsigned port;
2473 struct net_device *dev;
2474 struct sk_buff *skb;
2475 u32 status;
2476 u16 length;
2477 u8 opcode = le->opcode;
2478
2479 if (!(opcode & HW_OWNER))
2480 break;
2481
2482 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2483
2484 port = le->css & CSS_LINK_BIT;
2485 dev = hw->dev[port];
2486 sky2 = netdev_priv(dev);
2487 length = le16_to_cpu(le->length);
2488 status = le32_to_cpu(le->status);
2489
2490 le->opcode = 0;
2491 switch (opcode & ~HW_OWNER) {
2492 case OP_RXSTAT:
2493 total_packets[port]++;
2494 total_bytes[port] += length;
2495 skb = sky2_receive(dev, length, status);
2496 if (unlikely(!skb)) {
2497 dev->stats.rx_dropped++;
2498 break;
2499 }
2500
2501 /* This chip reports checksum status differently */
2502 if (hw->flags & SKY2_HW_NEW_LE) {
2503 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2504 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2505 (le->css & CSS_TCPUDPCSOK))
2506 skb->ip_summed = CHECKSUM_UNNECESSARY;
2507 else
2508 skb->ip_summed = CHECKSUM_NONE;
2509 }
2510
2511 skb->protocol = eth_type_trans(skb, dev);
2512
2513 sky2_skb_rx(sky2, status, skb);
2514
2515 /* Stop after net poll weight */
2516 if (++work_done >= to_do)
2517 goto exit_loop;
2518 break;
2519
2520 #ifdef SKY2_VLAN_TAG_USED
2521 case OP_RXVLAN:
2522 sky2->rx_tag = length;
2523 break;
2524
2525 case OP_RXCHKSVLAN:
2526 sky2->rx_tag = length;
2527 /* fall through */
2528 #endif
2529 case OP_RXCHKS:
2530 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2531 break;
2532
2533 /* If this happens then driver assuming wrong format */
2534 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2535 if (net_ratelimit())
2536 printk(KERN_NOTICE "%s: unexpected"
2537 " checksum status\n",
2538 dev->name);
2539 break;
2540 }
2541
2542 /* Both checksum counters are programmed to start at
2543 * the same offset, so unless there is a problem they
2544 * should match. This failure is an early indication that
2545 * hardware receive checksumming won't work.
2546 */
2547 if (likely(status >> 16 == (status & 0xffff))) {
2548 skb = sky2->rx_ring[sky2->rx_next].skb;
2549 skb->ip_summed = CHECKSUM_COMPLETE;
2550 skb->csum = le16_to_cpu(status);
2551 } else {
2552 printk(KERN_NOTICE PFX "%s: hardware receive "
2553 "checksum problem (status = %#x)\n",
2554 dev->name, status);
2555 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2556
2557 sky2_write32(sky2->hw,
2558 Q_ADDR(rxqaddr[port], Q_CSR),
2559 BMU_DIS_RX_CHKSUM);
2560 }
2561 break;
2562
2563 case OP_TXINDEXLE:
2564 /* TX index reports status for both ports */
2565 sky2_tx_done(hw->dev[0], status & 0xfff);
2566 if (hw->dev[1])
2567 sky2_tx_done(hw->dev[1],
2568 ((status >> 24) & 0xff)
2569 | (u16)(length & 0xf) << 8);
2570 break;
2571
2572 default:
2573 if (net_ratelimit())
2574 printk(KERN_WARNING PFX
2575 "unknown status opcode 0x%x\n", opcode);
2576 }
2577 } while (hw->st_idx != idx);
2578
2579 /* Fully processed status ring so clear irq */
2580 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2581
2582 exit_loop:
2583 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2584 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2585
2586 return work_done;
2587 }
2588
2589 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2590 {
2591 struct net_device *dev = hw->dev[port];
2592
2593 if (net_ratelimit())
2594 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2595 dev->name, status);
2596
2597 if (status & Y2_IS_PAR_RD1) {
2598 if (net_ratelimit())
2599 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2600 dev->name);
2601 /* Clear IRQ */
2602 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2603 }
2604
2605 if (status & Y2_IS_PAR_WR1) {
2606 if (net_ratelimit())
2607 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2608 dev->name);
2609
2610 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2611 }
2612
2613 if (status & Y2_IS_PAR_MAC1) {
2614 if (net_ratelimit())
2615 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2616 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2617 }
2618
2619 if (status & Y2_IS_PAR_RX1) {
2620 if (net_ratelimit())
2621 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2622 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2623 }
2624
2625 if (status & Y2_IS_TCP_TXA1) {
2626 if (net_ratelimit())
2627 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2628 dev->name);
2629 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2630 }
2631 }
2632
2633 static void sky2_hw_intr(struct sky2_hw *hw)
2634 {
2635 struct pci_dev *pdev = hw->pdev;
2636 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2637 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2638
2639 status &= hwmsk;
2640
2641 if (status & Y2_IS_TIST_OV)
2642 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2643
2644 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2645 u16 pci_err;
2646
2647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2648 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2649 if (net_ratelimit())
2650 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2651 pci_err);
2652
2653 sky2_pci_write16(hw, PCI_STATUS,
2654 pci_err | PCI_STATUS_ERROR_BITS);
2655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2656 }
2657
2658 if (status & Y2_IS_PCI_EXP) {
2659 /* PCI-Express uncorrectable Error occurred */
2660 u32 err;
2661
2662 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2663 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2664 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2665 0xfffffffful);
2666 if (net_ratelimit())
2667 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2668
2669 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2670 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2671 }
2672
2673 if (status & Y2_HWE_L1_MASK)
2674 sky2_hw_error(hw, 0, status);
2675 status >>= 8;
2676 if (status & Y2_HWE_L1_MASK)
2677 sky2_hw_error(hw, 1, status);
2678 }
2679
2680 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2681 {
2682 struct net_device *dev = hw->dev[port];
2683 struct sky2_port *sky2 = netdev_priv(dev);
2684 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2685
2686 if (netif_msg_intr(sky2))
2687 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2688 dev->name, status);
2689
2690 if (status & GM_IS_RX_CO_OV)
2691 gma_read16(hw, port, GM_RX_IRQ_SRC);
2692
2693 if (status & GM_IS_TX_CO_OV)
2694 gma_read16(hw, port, GM_TX_IRQ_SRC);
2695
2696 if (status & GM_IS_RX_FF_OR) {
2697 ++dev->stats.rx_fifo_errors;
2698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2699 }
2700
2701 if (status & GM_IS_TX_FF_UR) {
2702 ++dev->stats.tx_fifo_errors;
2703 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2704 }
2705 }
2706
2707 /* This should never happen it is a bug. */
2708 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2709 {
2710 struct net_device *dev = hw->dev[port];
2711 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2712
2713 dev_err(&hw->pdev->dev, PFX
2714 "%s: descriptor error q=%#x get=%u put=%u\n",
2715 dev->name, (unsigned) q, (unsigned) idx,
2716 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2717
2718 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2719 }
2720
2721 static int sky2_rx_hung(struct net_device *dev)
2722 {
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 struct sky2_hw *hw = sky2->hw;
2725 unsigned port = sky2->port;
2726 unsigned rxq = rxqaddr[port];
2727 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2728 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2729 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2730 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2731
2732 /* If idle and MAC or PCI is stuck */
2733 if (sky2->check.last == dev->last_rx &&
2734 ((mac_rp == sky2->check.mac_rp &&
2735 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2736 /* Check if the PCI RX hang */
2737 (fifo_rp == sky2->check.fifo_rp &&
2738 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2739 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2740 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2741 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2742 return 1;
2743 } else {
2744 sky2->check.last = dev->last_rx;
2745 sky2->check.mac_rp = mac_rp;
2746 sky2->check.mac_lev = mac_lev;
2747 sky2->check.fifo_rp = fifo_rp;
2748 sky2->check.fifo_lev = fifo_lev;
2749 return 0;
2750 }
2751 }
2752
2753 static void sky2_watchdog(unsigned long arg)
2754 {
2755 struct sky2_hw *hw = (struct sky2_hw *) arg;
2756
2757 /* Check for lost IRQ once a second */
2758 if (sky2_read32(hw, B0_ISRC)) {
2759 napi_schedule(&hw->napi);
2760 } else {
2761 int i, active = 0;
2762
2763 for (i = 0; i < hw->ports; i++) {
2764 struct net_device *dev = hw->dev[i];
2765 if (!netif_running(dev))
2766 continue;
2767 ++active;
2768
2769 /* For chips with Rx FIFO, check if stuck */
2770 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2771 sky2_rx_hung(dev)) {
2772 pr_info(PFX "%s: receiver hang detected\n",
2773 dev->name);
2774 schedule_work(&hw->restart_work);
2775 return;
2776 }
2777 }
2778
2779 if (active == 0)
2780 return;
2781 }
2782
2783 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2784 }
2785
2786 /* Hardware/software error handling */
2787 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2788 {
2789 if (net_ratelimit())
2790 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2791
2792 if (status & Y2_IS_HW_ERR)
2793 sky2_hw_intr(hw);
2794
2795 if (status & Y2_IS_IRQ_MAC1)
2796 sky2_mac_intr(hw, 0);
2797
2798 if (status & Y2_IS_IRQ_MAC2)
2799 sky2_mac_intr(hw, 1);
2800
2801 if (status & Y2_IS_CHK_RX1)
2802 sky2_le_error(hw, 0, Q_R1);
2803
2804 if (status & Y2_IS_CHK_RX2)
2805 sky2_le_error(hw, 1, Q_R2);
2806
2807 if (status & Y2_IS_CHK_TXA1)
2808 sky2_le_error(hw, 0, Q_XA1);
2809
2810 if (status & Y2_IS_CHK_TXA2)
2811 sky2_le_error(hw, 1, Q_XA2);
2812 }
2813
2814 static int sky2_poll(struct napi_struct *napi, int work_limit)
2815 {
2816 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2817 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2818 int work_done = 0;
2819 u16 idx;
2820
2821 if (unlikely(status & Y2_IS_ERROR))
2822 sky2_err_intr(hw, status);
2823
2824 if (status & Y2_IS_IRQ_PHY1)
2825 sky2_phy_intr(hw, 0);
2826
2827 if (status & Y2_IS_IRQ_PHY2)
2828 sky2_phy_intr(hw, 1);
2829
2830 if (status & Y2_IS_PHY_QLNK)
2831 sky2_qlink_intr(hw);
2832
2833 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2834 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2835
2836 if (work_done >= work_limit)
2837 goto done;
2838 }
2839
2840 napi_complete(napi);
2841 sky2_read32(hw, B0_Y2_SP_LISR);
2842 done:
2843
2844 return work_done;
2845 }
2846
2847 static irqreturn_t sky2_intr(int irq, void *dev_id)
2848 {
2849 struct sky2_hw *hw = dev_id;
2850 u32 status;
2851
2852 /* Reading this mask interrupts as side effect */
2853 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2854 if (status == 0 || status == ~0)
2855 return IRQ_NONE;
2856
2857 prefetch(&hw->st_le[hw->st_idx]);
2858
2859 napi_schedule(&hw->napi);
2860
2861 return IRQ_HANDLED;
2862 }
2863
2864 #ifdef CONFIG_NET_POLL_CONTROLLER
2865 static void sky2_netpoll(struct net_device *dev)
2866 {
2867 struct sky2_port *sky2 = netdev_priv(dev);
2868
2869 napi_schedule(&sky2->hw->napi);
2870 }
2871 #endif
2872
2873 /* Chip internal frequency for clock calculations */
2874 static u32 sky2_mhz(const struct sky2_hw *hw)
2875 {
2876 switch (hw->chip_id) {
2877 case CHIP_ID_YUKON_EC:
2878 case CHIP_ID_YUKON_EC_U:
2879 case CHIP_ID_YUKON_EX:
2880 case CHIP_ID_YUKON_SUPR:
2881 case CHIP_ID_YUKON_UL_2:
2882 case CHIP_ID_YUKON_OPT:
2883 return 125;
2884
2885 case CHIP_ID_YUKON_FE:
2886 return 100;
2887
2888 case CHIP_ID_YUKON_FE_P:
2889 return 50;
2890
2891 case CHIP_ID_YUKON_XL:
2892 return 156;
2893
2894 default:
2895 BUG();
2896 }
2897 }
2898
2899 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2900 {
2901 return sky2_mhz(hw) * us;
2902 }
2903
2904 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2905 {
2906 return clk / sky2_mhz(hw);
2907 }
2908
2909
2910 static int __devinit sky2_init(struct sky2_hw *hw)
2911 {
2912 u8 t8;
2913
2914 /* Enable all clocks and check for bad PCI access */
2915 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2916
2917 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2918
2919 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2920 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2921
2922 switch(hw->chip_id) {
2923 case CHIP_ID_YUKON_XL:
2924 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2925 break;
2926
2927 case CHIP_ID_YUKON_EC_U:
2928 hw->flags = SKY2_HW_GIGABIT
2929 | SKY2_HW_NEWER_PHY
2930 | SKY2_HW_ADV_POWER_CTL;
2931 break;
2932
2933 case CHIP_ID_YUKON_EX:
2934 hw->flags = SKY2_HW_GIGABIT
2935 | SKY2_HW_NEWER_PHY
2936 | SKY2_HW_NEW_LE
2937 | SKY2_HW_ADV_POWER_CTL;
2938
2939 /* New transmit checksum */
2940 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2941 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2942 break;
2943
2944 case CHIP_ID_YUKON_EC:
2945 /* This rev is really old, and requires untested workarounds */
2946 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2947 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2948 return -EOPNOTSUPP;
2949 }
2950 hw->flags = SKY2_HW_GIGABIT;
2951 break;
2952
2953 case CHIP_ID_YUKON_FE:
2954 break;
2955
2956 case CHIP_ID_YUKON_FE_P:
2957 hw->flags = SKY2_HW_NEWER_PHY
2958 | SKY2_HW_NEW_LE
2959 | SKY2_HW_AUTO_TX_SUM
2960 | SKY2_HW_ADV_POWER_CTL;
2961 break;
2962
2963 case CHIP_ID_YUKON_SUPR:
2964 hw->flags = SKY2_HW_GIGABIT
2965 | SKY2_HW_NEWER_PHY
2966 | SKY2_HW_NEW_LE
2967 | SKY2_HW_AUTO_TX_SUM
2968 | SKY2_HW_ADV_POWER_CTL;
2969 break;
2970
2971 case CHIP_ID_YUKON_UL_2:
2972 hw->flags = SKY2_HW_GIGABIT
2973 | SKY2_HW_ADV_POWER_CTL;
2974 break;
2975
2976 case CHIP_ID_YUKON_OPT:
2977 hw->flags = SKY2_HW_GIGABIT
2978 | SKY2_HW_NEW_LE
2979 | SKY2_HW_ADV_POWER_CTL;
2980 break;
2981
2982 default:
2983 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2984 hw->chip_id);
2985 return -EOPNOTSUPP;
2986 }
2987
2988 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2989 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2990 hw->flags |= SKY2_HW_FIBRE_PHY;
2991
2992 hw->ports = 1;
2993 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2994 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2995 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2996 ++hw->ports;
2997 }
2998
2999 if (sky2_read8(hw, B2_E_0))
3000 hw->flags |= SKY2_HW_RAM_BUFFER;
3001
3002 return 0;
3003 }
3004
3005 static void sky2_reset(struct sky2_hw *hw)
3006 {
3007 struct pci_dev *pdev = hw->pdev;
3008 u16 status;
3009 int i, cap;
3010 u32 hwe_mask = Y2_HWE_ALL_MASK;
3011
3012 /* disable ASF */
3013 if (hw->chip_id == CHIP_ID_YUKON_EX) {
3014 status = sky2_read16(hw, HCU_CCSR);
3015 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3016 HCU_CCSR_UC_STATE_MSK);
3017 sky2_write16(hw, HCU_CCSR, status);
3018 } else
3019 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3020 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3021
3022 /* do a SW reset */
3023 sky2_write8(hw, B0_CTST, CS_RST_SET);
3024 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3025
3026 /* allow writes to PCI config */
3027 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3028
3029 /* clear PCI errors, if any */
3030 status = sky2_pci_read16(hw, PCI_STATUS);
3031 status |= PCI_STATUS_ERROR_BITS;
3032 sky2_pci_write16(hw, PCI_STATUS, status);
3033
3034 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3035
3036 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3037 if (cap) {
3038 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3039 0xfffffffful);
3040
3041 /* If error bit is stuck on ignore it */
3042 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3043 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3044 else
3045 hwe_mask |= Y2_IS_PCI_EXP;
3046 }
3047
3048 sky2_power_on(hw);
3049 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3050
3051 for (i = 0; i < hw->ports; i++) {
3052 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3053 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3054
3055 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3056 hw->chip_id == CHIP_ID_YUKON_SUPR)
3057 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3058 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3059 | GMC_BYP_RETR_ON);
3060
3061 }
3062
3063 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3064 /* enable MACSec clock gating */
3065 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3066 }
3067
3068 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3069 u16 reg;
3070 u32 msk;
3071
3072 if (hw->chip_rev == 0) {
3073 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3074 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3075
3076 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3077 reg = 10;
3078 } else {
3079 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3080 reg = 3;
3081 }
3082
3083 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3084
3085 /* reset PHY Link Detect */
3086 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3087 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3088 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3089 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3090
3091
3092 /* enable PHY Quick Link */
3093 msk = sky2_read32(hw, B0_IMSK);
3094 msk |= Y2_IS_PHY_QLNK;
3095 sky2_write32(hw, B0_IMSK, msk);
3096
3097 /* check if PSMv2 was running before */
3098 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3099 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3100 int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3101 /* restore the PCIe Link Control register */
3102 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3103 }
3104 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3105
3106 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3107 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3108 }
3109
3110 /* Clear I2C IRQ noise */
3111 sky2_write32(hw, B2_I2C_IRQ, 1);
3112
3113 /* turn off hardware timer (unused) */
3114 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3115 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3116
3117 /* Turn off descriptor polling */
3118 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3119
3120 /* Turn off receive timestamp */
3121 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3122 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3123
3124 /* enable the Tx Arbiters */
3125 for (i = 0; i < hw->ports; i++)
3126 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3127
3128 /* Initialize ram interface */
3129 for (i = 0; i < hw->ports; i++) {
3130 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3131
3132 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3133 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3134 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3135 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3136 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3138 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3144 }
3145
3146 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3147
3148 for (i = 0; i < hw->ports; i++)
3149 sky2_gmac_reset(hw, i);
3150
3151 memset(hw->st_le, 0, STATUS_LE_BYTES);
3152 hw->st_idx = 0;
3153
3154 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3155 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3156
3157 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3158 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3159
3160 /* Set the list last index */
3161 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3162
3163 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3164 sky2_write8(hw, STAT_FIFO_WM, 16);
3165
3166 /* set Status-FIFO ISR watermark */
3167 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3168 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3169 else
3170 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3171
3172 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3173 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3174 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3175
3176 /* enable status unit */
3177 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3178
3179 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3180 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3181 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3182 }
3183
3184 /* Take device down (offline).
3185 * Equivalent to doing dev_stop() but this does not
3186 * inform upper layers of the transistion.
3187 */
3188 static void sky2_detach(struct net_device *dev)
3189 {
3190 if (netif_running(dev)) {
3191 netif_device_detach(dev); /* stop txq */
3192 sky2_down(dev);
3193 }
3194 }
3195
3196 /* Bring device back after doing sky2_detach */
3197 static int sky2_reattach(struct net_device *dev)
3198 {
3199 int err = 0;
3200
3201 if (netif_running(dev)) {
3202 err = sky2_up(dev);
3203 if (err) {
3204 printk(KERN_INFO PFX "%s: could not restart %d\n",
3205 dev->name, err);
3206 dev_close(dev);
3207 } else {
3208 netif_device_attach(dev);
3209 sky2_set_multicast(dev);
3210 }
3211 }
3212
3213 return err;
3214 }
3215
3216 static void sky2_restart(struct work_struct *work)
3217 {
3218 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3219 int i;
3220
3221 rtnl_lock();
3222 for (i = 0; i < hw->ports; i++)
3223 sky2_detach(hw->dev[i]);
3224
3225 napi_disable(&hw->napi);
3226 sky2_write32(hw, B0_IMSK, 0);
3227 sky2_reset(hw);
3228 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3229 napi_enable(&hw->napi);
3230
3231 for (i = 0; i < hw->ports; i++)
3232 sky2_reattach(hw->dev[i]);
3233
3234 rtnl_unlock();
3235 }
3236
3237 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3238 {
3239 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3240 }
3241
3242 static void sky2_hw_set_wol(struct sky2_hw *hw)
3243 {
3244 int wol = 0;
3245 int i;
3246
3247 for (i = 0; i < hw->ports; i++) {
3248 struct net_device *dev = hw->dev[i];
3249 struct sky2_port *sky2 = netdev_priv(dev);
3250
3251 if (sky2->wol)
3252 wol = 1;
3253 }
3254
3255 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3256 hw->chip_id == CHIP_ID_YUKON_EX ||
3257 hw->chip_id == CHIP_ID_YUKON_FE_P)
3258 sky2_write32(hw, B0_CTST, wol ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3259
3260 device_set_wakeup_enable(&hw->pdev->dev, wol);
3261 }
3262
3263 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3264 {
3265 const struct sky2_port *sky2 = netdev_priv(dev);
3266
3267 wol->supported = sky2_wol_supported(sky2->hw);
3268 wol->wolopts = sky2->wol;
3269 }
3270
3271 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3272 {
3273 struct sky2_port *sky2 = netdev_priv(dev);
3274 struct sky2_hw *hw = sky2->hw;
3275
3276 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3277 !device_can_wakeup(&hw->pdev->dev))
3278 return -EOPNOTSUPP;
3279
3280 sky2->wol = wol->wolopts;
3281
3282 sky2_hw_set_wol(hw);
3283
3284 if (!netif_running(dev))
3285 sky2_wol_init(sky2);
3286 return 0;
3287 }
3288
3289 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3290 {
3291 if (sky2_is_copper(hw)) {
3292 u32 modes = SUPPORTED_10baseT_Half
3293 | SUPPORTED_10baseT_Full
3294 | SUPPORTED_100baseT_Half
3295 | SUPPORTED_100baseT_Full
3296 | SUPPORTED_Autoneg | SUPPORTED_TP;
3297
3298 if (hw->flags & SKY2_HW_GIGABIT)
3299 modes |= SUPPORTED_1000baseT_Half
3300 | SUPPORTED_1000baseT_Full;
3301 return modes;
3302 } else
3303 return SUPPORTED_1000baseT_Half
3304 | SUPPORTED_1000baseT_Full
3305 | SUPPORTED_Autoneg
3306 | SUPPORTED_FIBRE;
3307 }
3308
3309 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3310 {
3311 struct sky2_port *sky2 = netdev_priv(dev);
3312 struct sky2_hw *hw = sky2->hw;
3313
3314 ecmd->transceiver = XCVR_INTERNAL;
3315 ecmd->supported = sky2_supported_modes(hw);
3316 ecmd->phy_address = PHY_ADDR_MARV;
3317 if (sky2_is_copper(hw)) {
3318 ecmd->port = PORT_TP;
3319 ecmd->speed = sky2->speed;
3320 } else {
3321 ecmd->speed = SPEED_1000;
3322 ecmd->port = PORT_FIBRE;
3323 }
3324
3325 ecmd->advertising = sky2->advertising;
3326 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3327 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3328 ecmd->duplex = sky2->duplex;
3329 return 0;
3330 }
3331
3332 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3333 {
3334 struct sky2_port *sky2 = netdev_priv(dev);
3335 const struct sky2_hw *hw = sky2->hw;
3336 u32 supported = sky2_supported_modes(hw);
3337
3338 if (ecmd->autoneg == AUTONEG_ENABLE) {
3339 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3340 ecmd->advertising = supported;
3341 sky2->duplex = -1;
3342 sky2->speed = -1;
3343 } else {
3344 u32 setting;
3345
3346 switch (ecmd->speed) {
3347 case SPEED_1000:
3348 if (ecmd->duplex == DUPLEX_FULL)
3349 setting = SUPPORTED_1000baseT_Full;
3350 else if (ecmd->duplex == DUPLEX_HALF)
3351 setting = SUPPORTED_1000baseT_Half;
3352 else
3353 return -EINVAL;
3354 break;
3355 case SPEED_100:
3356 if (ecmd->duplex == DUPLEX_FULL)
3357 setting = SUPPORTED_100baseT_Full;
3358 else if (ecmd->duplex == DUPLEX_HALF)
3359 setting = SUPPORTED_100baseT_Half;
3360 else
3361 return -EINVAL;
3362 break;
3363
3364 case SPEED_10:
3365 if (ecmd->duplex == DUPLEX_FULL)
3366 setting = SUPPORTED_10baseT_Full;
3367 else if (ecmd->duplex == DUPLEX_HALF)
3368 setting = SUPPORTED_10baseT_Half;
3369 else
3370 return -EINVAL;
3371 break;
3372 default:
3373 return -EINVAL;
3374 }
3375
3376 if ((setting & supported) == 0)
3377 return -EINVAL;
3378
3379 sky2->speed = ecmd->speed;
3380 sky2->duplex = ecmd->duplex;
3381 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3382 }
3383
3384 sky2->advertising = ecmd->advertising;
3385
3386 if (netif_running(dev)) {
3387 sky2_phy_reinit(sky2);
3388 sky2_set_multicast(dev);
3389 }
3390
3391 return 0;
3392 }
3393
3394 static void sky2_get_drvinfo(struct net_device *dev,
3395 struct ethtool_drvinfo *info)
3396 {
3397 struct sky2_port *sky2 = netdev_priv(dev);
3398
3399 strcpy(info->driver, DRV_NAME);
3400 strcpy(info->version, DRV_VERSION);
3401 strcpy(info->fw_version, "N/A");
3402 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3403 }
3404
3405 static const struct sky2_stat {
3406 char name[ETH_GSTRING_LEN];
3407 u16 offset;
3408 } sky2_stats[] = {
3409 { "tx_bytes", GM_TXO_OK_HI },
3410 { "rx_bytes", GM_RXO_OK_HI },
3411 { "tx_broadcast", GM_TXF_BC_OK },
3412 { "rx_broadcast", GM_RXF_BC_OK },
3413 { "tx_multicast", GM_TXF_MC_OK },
3414 { "rx_multicast", GM_RXF_MC_OK },
3415 { "tx_unicast", GM_TXF_UC_OK },
3416 { "rx_unicast", GM_RXF_UC_OK },
3417 { "tx_mac_pause", GM_TXF_MPAUSE },
3418 { "rx_mac_pause", GM_RXF_MPAUSE },
3419 { "collisions", GM_TXF_COL },
3420 { "late_collision",GM_TXF_LAT_COL },
3421 { "aborted", GM_TXF_ABO_COL },
3422 { "single_collisions", GM_TXF_SNG_COL },
3423 { "multi_collisions", GM_TXF_MUL_COL },
3424
3425 { "rx_short", GM_RXF_SHT },
3426 { "rx_runt", GM_RXE_FRAG },
3427 { "rx_64_byte_packets", GM_RXF_64B },
3428 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3429 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3430 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3431 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3432 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3433 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3434 { "rx_too_long", GM_RXF_LNG_ERR },
3435 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3436 { "rx_jabber", GM_RXF_JAB_PKT },
3437 { "rx_fcs_error", GM_RXF_FCS_ERR },
3438
3439 { "tx_64_byte_packets", GM_TXF_64B },
3440 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3441 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3442 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3443 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3444 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3445 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3446 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3447 };
3448
3449 static u32 sky2_get_rx_csum(struct net_device *dev)
3450 {
3451 struct sky2_port *sky2 = netdev_priv(dev);
3452
3453 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3454 }
3455
3456 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3457 {
3458 struct sky2_port *sky2 = netdev_priv(dev);
3459
3460 if (data)
3461 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3462 else
3463 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3464
3465 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3466 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3467
3468 return 0;
3469 }
3470
3471 static u32 sky2_get_msglevel(struct net_device *netdev)
3472 {
3473 struct sky2_port *sky2 = netdev_priv(netdev);
3474 return sky2->msg_enable;
3475 }
3476
3477 static int sky2_nway_reset(struct net_device *dev)
3478 {
3479 struct sky2_port *sky2 = netdev_priv(dev);
3480
3481 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3482 return -EINVAL;
3483
3484 sky2_phy_reinit(sky2);
3485 sky2_set_multicast(dev);
3486
3487 return 0;
3488 }
3489
3490 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3491 {
3492 struct sky2_hw *hw = sky2->hw;
3493 unsigned port = sky2->port;
3494 int i;
3495
3496 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3497 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3498 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3499 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3500
3501 for (i = 2; i < count; i++)
3502 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3503 }
3504
3505 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3506 {
3507 struct sky2_port *sky2 = netdev_priv(netdev);
3508 sky2->msg_enable = value;
3509 }
3510
3511 static int sky2_get_sset_count(struct net_device *dev, int sset)
3512 {
3513 switch (sset) {
3514 case ETH_SS_STATS:
3515 return ARRAY_SIZE(sky2_stats);
3516 default:
3517 return -EOPNOTSUPP;
3518 }
3519 }
3520
3521 static void sky2_get_ethtool_stats(struct net_device *dev,
3522 struct ethtool_stats *stats, u64 * data)
3523 {
3524 struct sky2_port *sky2 = netdev_priv(dev);
3525
3526 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3527 }
3528
3529 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3530 {
3531 int i;
3532
3533 switch (stringset) {
3534 case ETH_SS_STATS:
3535 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3536 memcpy(data + i * ETH_GSTRING_LEN,
3537 sky2_stats[i].name, ETH_GSTRING_LEN);
3538 break;
3539 }
3540 }
3541
3542 static int sky2_set_mac_address(struct net_device *dev, void *p)
3543 {
3544 struct sky2_port *sky2 = netdev_priv(dev);
3545 struct sky2_hw *hw = sky2->hw;
3546 unsigned port = sky2->port;
3547 const struct sockaddr *addr = p;
3548
3549 if (!is_valid_ether_addr(addr->sa_data))
3550 return -EADDRNOTAVAIL;
3551
3552 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3553 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3554 dev->dev_addr, ETH_ALEN);
3555 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3556 dev->dev_addr, ETH_ALEN);
3557
3558 /* virtual address for data */
3559 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3560
3561 /* physical address: used for pause frames */
3562 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3563
3564 return 0;
3565 }
3566
3567 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3568 {
3569 u32 bit;
3570
3571 bit = ether_crc(ETH_ALEN, addr) & 63;
3572 filter[bit >> 3] |= 1 << (bit & 7);
3573 }
3574
3575 static void sky2_set_multicast(struct net_device *dev)
3576 {
3577 struct sky2_port *sky2 = netdev_priv(dev);
3578 struct sky2_hw *hw = sky2->hw;
3579 unsigned port = sky2->port;
3580 struct dev_mc_list *list = dev->mc_list;
3581 u16 reg;
3582 u8 filter[8];
3583 int rx_pause;
3584 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3585
3586 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3587 memset(filter, 0, sizeof(filter));
3588
3589 reg = gma_read16(hw, port, GM_RX_CTRL);
3590 reg |= GM_RXCR_UCF_ENA;
3591
3592 if (dev->flags & IFF_PROMISC) /* promiscuous */
3593 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3594 else if (dev->flags & IFF_ALLMULTI)
3595 memset(filter, 0xff, sizeof(filter));
3596 else if (dev->mc_count == 0 && !rx_pause)
3597 reg &= ~GM_RXCR_MCF_ENA;
3598 else {
3599 int i;
3600 reg |= GM_RXCR_MCF_ENA;
3601
3602 if (rx_pause)
3603 sky2_add_filter(filter, pause_mc_addr);
3604
3605 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3606 sky2_add_filter(filter, list->dmi_addr);
3607 }
3608
3609 gma_write16(hw, port, GM_MC_ADDR_H1,
3610 (u16) filter[0] | ((u16) filter[1] << 8));
3611 gma_write16(hw, port, GM_MC_ADDR_H2,
3612 (u16) filter[2] | ((u16) filter[3] << 8));
3613 gma_write16(hw, port, GM_MC_ADDR_H3,
3614 (u16) filter[4] | ((u16) filter[5] << 8));
3615 gma_write16(hw, port, GM_MC_ADDR_H4,
3616 (u16) filter[6] | ((u16) filter[7] << 8));
3617
3618 gma_write16(hw, port, GM_RX_CTRL, reg);
3619 }
3620
3621 /* Can have one global because blinking is controlled by
3622 * ethtool and that is always under RTNL mutex
3623 */
3624 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3625 {
3626 struct sky2_hw *hw = sky2->hw;
3627 unsigned port = sky2->port;
3628
3629 spin_lock_bh(&sky2->phy_lock);
3630 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3631 hw->chip_id == CHIP_ID_YUKON_EX ||
3632 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3633 u16 pg;
3634 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3635 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3636
3637 switch (mode) {
3638 case MO_LED_OFF:
3639 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3640 PHY_M_LEDC_LOS_CTRL(8) |
3641 PHY_M_LEDC_INIT_CTRL(8) |
3642 PHY_M_LEDC_STA1_CTRL(8) |
3643 PHY_M_LEDC_STA0_CTRL(8));
3644 break;
3645 case MO_LED_ON:
3646 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3647 PHY_M_LEDC_LOS_CTRL(9) |
3648 PHY_M_LEDC_INIT_CTRL(9) |
3649 PHY_M_LEDC_STA1_CTRL(9) |
3650 PHY_M_LEDC_STA0_CTRL(9));
3651 break;
3652 case MO_LED_BLINK:
3653 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3654 PHY_M_LEDC_LOS_CTRL(0xa) |
3655 PHY_M_LEDC_INIT_CTRL(0xa) |
3656 PHY_M_LEDC_STA1_CTRL(0xa) |
3657 PHY_M_LEDC_STA0_CTRL(0xa));
3658 break;
3659 case MO_LED_NORM:
3660 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3661 PHY_M_LEDC_LOS_CTRL(1) |
3662 PHY_M_LEDC_INIT_CTRL(8) |
3663 PHY_M_LEDC_STA1_CTRL(7) |
3664 PHY_M_LEDC_STA0_CTRL(7));
3665 }
3666
3667 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3668 } else
3669 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3670 PHY_M_LED_MO_DUP(mode) |
3671 PHY_M_LED_MO_10(mode) |
3672 PHY_M_LED_MO_100(mode) |
3673 PHY_M_LED_MO_1000(mode) |
3674 PHY_M_LED_MO_RX(mode) |
3675 PHY_M_LED_MO_TX(mode));
3676
3677 spin_unlock_bh(&sky2->phy_lock);
3678 }
3679
3680 /* blink LED's for finding board */
3681 static int sky2_phys_id(struct net_device *dev, u32 data)
3682 {
3683 struct sky2_port *sky2 = netdev_priv(dev);
3684 unsigned int i;
3685
3686 if (data == 0)
3687 data = UINT_MAX;
3688
3689 for (i = 0; i < data; i++) {
3690 sky2_led(sky2, MO_LED_ON);
3691 if (msleep_interruptible(500))
3692 break;
3693 sky2_led(sky2, MO_LED_OFF);
3694 if (msleep_interruptible(500))
3695 break;
3696 }
3697 sky2_led(sky2, MO_LED_NORM);
3698
3699 return 0;
3700 }
3701
3702 static void sky2_get_pauseparam(struct net_device *dev,
3703 struct ethtool_pauseparam *ecmd)
3704 {
3705 struct sky2_port *sky2 = netdev_priv(dev);
3706
3707 switch (sky2->flow_mode) {
3708 case FC_NONE:
3709 ecmd->tx_pause = ecmd->rx_pause = 0;
3710 break;
3711 case FC_TX:
3712 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3713 break;
3714 case FC_RX:
3715 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3716 break;
3717 case FC_BOTH:
3718 ecmd->tx_pause = ecmd->rx_pause = 1;
3719 }
3720
3721 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3722 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3723 }
3724
3725 static int sky2_set_pauseparam(struct net_device *dev,
3726 struct ethtool_pauseparam *ecmd)
3727 {
3728 struct sky2_port *sky2 = netdev_priv(dev);
3729
3730 if (ecmd->autoneg == AUTONEG_ENABLE)
3731 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3732 else
3733 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3734
3735 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3736
3737 if (netif_running(dev))
3738 sky2_phy_reinit(sky2);
3739
3740 return 0;
3741 }
3742
3743 static int sky2_get_coalesce(struct net_device *dev,
3744 struct ethtool_coalesce *ecmd)
3745 {
3746 struct sky2_port *sky2 = netdev_priv(dev);
3747 struct sky2_hw *hw = sky2->hw;
3748
3749 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3750 ecmd->tx_coalesce_usecs = 0;
3751 else {
3752 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3753 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3754 }
3755 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3756
3757 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3758 ecmd->rx_coalesce_usecs = 0;
3759 else {
3760 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3761 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3762 }
3763 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3764
3765 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3766 ecmd->rx_coalesce_usecs_irq = 0;
3767 else {
3768 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3769 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3770 }
3771
3772 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3773
3774 return 0;
3775 }
3776
3777 /* Note: this affect both ports */
3778 static int sky2_set_coalesce(struct net_device *dev,
3779 struct ethtool_coalesce *ecmd)
3780 {
3781 struct sky2_port *sky2 = netdev_priv(dev);
3782 struct sky2_hw *hw = sky2->hw;
3783 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3784
3785 if (ecmd->tx_coalesce_usecs > tmax ||
3786 ecmd->rx_coalesce_usecs > tmax ||
3787 ecmd->rx_coalesce_usecs_irq > tmax)
3788 return -EINVAL;
3789
3790 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3791 return -EINVAL;
3792 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3793 return -EINVAL;
3794 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3795 return -EINVAL;
3796
3797 if (ecmd->tx_coalesce_usecs == 0)
3798 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3799 else {
3800 sky2_write32(hw, STAT_TX_TIMER_INI,
3801 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3802 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3803 }
3804 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3805
3806 if (ecmd->rx_coalesce_usecs == 0)
3807 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3808 else {
3809 sky2_write32(hw, STAT_LEV_TIMER_INI,
3810 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3811 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3812 }
3813 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3814
3815 if (ecmd->rx_coalesce_usecs_irq == 0)
3816 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3817 else {
3818 sky2_write32(hw, STAT_ISR_TIMER_INI,
3819 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3820 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3821 }
3822 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3823 return 0;
3824 }
3825
3826 static void sky2_get_ringparam(struct net_device *dev,
3827 struct ethtool_ringparam *ering)
3828 {
3829 struct sky2_port *sky2 = netdev_priv(dev);
3830
3831 ering->rx_max_pending = RX_MAX_PENDING;
3832 ering->rx_mini_max_pending = 0;
3833 ering->rx_jumbo_max_pending = 0;
3834 ering->tx_max_pending = TX_MAX_PENDING;
3835
3836 ering->rx_pending = sky2->rx_pending;
3837 ering->rx_mini_pending = 0;
3838 ering->rx_jumbo_pending = 0;
3839 ering->tx_pending = sky2->tx_pending;
3840 }
3841
3842 static int sky2_set_ringparam(struct net_device *dev,
3843 struct ethtool_ringparam *ering)
3844 {
3845 struct sky2_port *sky2 = netdev_priv(dev);
3846
3847 if (ering->rx_pending > RX_MAX_PENDING ||
3848 ering->rx_pending < 8 ||
3849 ering->tx_pending < TX_MIN_PENDING ||
3850 ering->tx_pending > TX_MAX_PENDING)
3851 return -EINVAL;
3852
3853 sky2_detach(dev);
3854
3855 sky2->rx_pending = ering->rx_pending;
3856 sky2->tx_pending = ering->tx_pending;
3857 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3858
3859 return sky2_reattach(dev);
3860 }
3861
3862 static int sky2_get_regs_len(struct net_device *dev)
3863 {
3864 return 0x4000;
3865 }
3866
3867 /*
3868 * Returns copy of control register region
3869 * Note: ethtool_get_regs always provides full size (16k) buffer
3870 */
3871 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3872 void *p)
3873 {
3874 const struct sky2_port *sky2 = netdev_priv(dev);
3875 const void __iomem *io = sky2->hw->regs;
3876 unsigned int b;
3877
3878 regs->version = 1;
3879
3880 for (b = 0; b < 128; b++) {
3881 /* This complicated switch statement is to make sure and
3882 * only access regions that are unreserved.
3883 * Some blocks are only valid on dual port cards.
3884 * and block 3 has some special diagnostic registers that
3885 * are poison.
3886 */
3887 switch (b) {
3888 case 3:
3889 /* skip diagnostic ram region */
3890 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3891 break;
3892
3893 /* dual port cards only */
3894 case 5: /* Tx Arbiter 2 */
3895 case 9: /* RX2 */
3896 case 14 ... 15: /* TX2 */
3897 case 17: case 19: /* Ram Buffer 2 */
3898 case 22 ... 23: /* Tx Ram Buffer 2 */
3899 case 25: /* Rx MAC Fifo 1 */
3900 case 27: /* Tx MAC Fifo 2 */
3901 case 31: /* GPHY 2 */
3902 case 40 ... 47: /* Pattern Ram 2 */
3903 case 52: case 54: /* TCP Segmentation 2 */
3904 case 112 ... 116: /* GMAC 2 */
3905 if (sky2->hw->ports == 1)
3906 goto reserved;
3907 /* fall through */
3908 case 0: /* Control */
3909 case 2: /* Mac address */
3910 case 4: /* Tx Arbiter 1 */
3911 case 7: /* PCI express reg */
3912 case 8: /* RX1 */
3913 case 12 ... 13: /* TX1 */
3914 case 16: case 18:/* Rx Ram Buffer 1 */
3915 case 20 ... 21: /* Tx Ram Buffer 1 */
3916 case 24: /* Rx MAC Fifo 1 */
3917 case 26: /* Tx MAC Fifo 1 */
3918 case 28 ... 29: /* Descriptor and status unit */
3919 case 30: /* GPHY 1*/
3920 case 32 ... 39: /* Pattern Ram 1 */
3921 case 48: case 50: /* TCP Segmentation 1 */
3922 case 56 ... 60: /* PCI space */
3923 case 80 ... 84: /* GMAC 1 */
3924 memcpy_fromio(p, io, 128);
3925 break;
3926 default:
3927 reserved:
3928 memset(p, 0, 128);
3929 }
3930
3931 p += 128;
3932 io += 128;
3933 }
3934 }
3935
3936 /* In order to do Jumbo packets on these chips, need to turn off the
3937 * transmit store/forward. Therefore checksum offload won't work.
3938 */
3939 static int no_tx_offload(struct net_device *dev)
3940 {
3941 const struct sky2_port *sky2 = netdev_priv(dev);
3942 const struct sky2_hw *hw = sky2->hw;
3943
3944 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3945 }
3946
3947 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3948 {
3949 if (data && no_tx_offload(dev))
3950 return -EINVAL;
3951
3952 return ethtool_op_set_tx_csum(dev, data);
3953 }
3954
3955
3956 static int sky2_set_tso(struct net_device *dev, u32 data)
3957 {
3958 if (data && no_tx_offload(dev))
3959 return -EINVAL;
3960
3961 return ethtool_op_set_tso(dev, data);
3962 }
3963
3964 static int sky2_get_eeprom_len(struct net_device *dev)
3965 {
3966 struct sky2_port *sky2 = netdev_priv(dev);
3967 struct sky2_hw *hw = sky2->hw;
3968 u16 reg2;
3969
3970 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3971 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3972 }
3973
3974 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3975 {
3976 unsigned long start = jiffies;
3977
3978 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3979 /* Can take up to 10.6 ms for write */
3980 if (time_after(jiffies, start + HZ/4)) {
3981 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3982 return -ETIMEDOUT;
3983 }
3984 mdelay(1);
3985 }
3986
3987 return 0;
3988 }
3989
3990 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3991 u16 offset, size_t length)
3992 {
3993 int rc = 0;
3994
3995 while (length > 0) {
3996 u32 val;
3997
3998 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3999 rc = sky2_vpd_wait(hw, cap, 0);
4000 if (rc)
4001 break;
4002
4003 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4004
4005 memcpy(data, &val, min(sizeof(val), length));
4006 offset += sizeof(u32);
4007 data += sizeof(u32);
4008 length -= sizeof(u32);
4009 }
4010
4011 return rc;
4012 }
4013
4014 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4015 u16 offset, unsigned int length)
4016 {
4017 unsigned int i;
4018 int rc = 0;
4019
4020 for (i = 0; i < length; i += sizeof(u32)) {
4021 u32 val = *(u32 *)(data + i);
4022
4023 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4024 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4025
4026 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4027 if (rc)
4028 break;
4029 }
4030 return rc;
4031 }
4032
4033 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4034 u8 *data)
4035 {
4036 struct sky2_port *sky2 = netdev_priv(dev);
4037 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4038
4039 if (!cap)
4040 return -EINVAL;
4041
4042 eeprom->magic = SKY2_EEPROM_MAGIC;
4043
4044 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4045 }
4046
4047 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4048 u8 *data)
4049 {
4050 struct sky2_port *sky2 = netdev_priv(dev);
4051 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4052
4053 if (!cap)
4054 return -EINVAL;
4055
4056 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4057 return -EINVAL;
4058
4059 /* Partial writes not supported */
4060 if ((eeprom->offset & 3) || (eeprom->len & 3))
4061 return -EINVAL;
4062
4063 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4064 }
4065
4066
4067 static const struct ethtool_ops sky2_ethtool_ops = {
4068 .get_settings = sky2_get_settings,
4069 .set_settings = sky2_set_settings,
4070 .get_drvinfo = sky2_get_drvinfo,
4071 .get_wol = sky2_get_wol,
4072 .set_wol = sky2_set_wol,
4073 .get_msglevel = sky2_get_msglevel,
4074 .set_msglevel = sky2_set_msglevel,
4075 .nway_reset = sky2_nway_reset,
4076 .get_regs_len = sky2_get_regs_len,
4077 .get_regs = sky2_get_regs,
4078 .get_link = ethtool_op_get_link,
4079 .get_eeprom_len = sky2_get_eeprom_len,
4080 .get_eeprom = sky2_get_eeprom,
4081 .set_eeprom = sky2_set_eeprom,
4082 .set_sg = ethtool_op_set_sg,
4083 .set_tx_csum = sky2_set_tx_csum,
4084 .set_tso = sky2_set_tso,
4085 .get_rx_csum = sky2_get_rx_csum,
4086 .set_rx_csum = sky2_set_rx_csum,
4087 .get_strings = sky2_get_strings,
4088 .get_coalesce = sky2_get_coalesce,
4089 .set_coalesce = sky2_set_coalesce,
4090 .get_ringparam = sky2_get_ringparam,
4091 .set_ringparam = sky2_set_ringparam,
4092 .get_pauseparam = sky2_get_pauseparam,
4093 .set_pauseparam = sky2_set_pauseparam,
4094 .phys_id = sky2_phys_id,
4095 .get_sset_count = sky2_get_sset_count,
4096 .get_ethtool_stats = sky2_get_ethtool_stats,
4097 };
4098
4099 #ifdef CONFIG_SKY2_DEBUG
4100
4101 static struct dentry *sky2_debug;
4102
4103
4104 /*
4105 * Read and parse the first part of Vital Product Data
4106 */
4107 #define VPD_SIZE 128
4108 #define VPD_MAGIC 0x82
4109
4110 static const struct vpd_tag {
4111 char tag[2];
4112 char *label;
4113 } vpd_tags[] = {
4114 { "PN", "Part Number" },
4115 { "EC", "Engineering Level" },
4116 { "MN", "Manufacturer" },
4117 { "SN", "Serial Number" },
4118 { "YA", "Asset Tag" },
4119 { "VL", "First Error Log Message" },
4120 { "VF", "Second Error Log Message" },
4121 { "VB", "Boot Agent ROM Configuration" },
4122 { "VE", "EFI UNDI Configuration" },
4123 };
4124
4125 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4126 {
4127 size_t vpd_size;
4128 loff_t offs;
4129 u8 len;
4130 unsigned char *buf;
4131 u16 reg2;
4132
4133 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4134 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4135
4136 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4137 buf = kmalloc(vpd_size, GFP_KERNEL);
4138 if (!buf) {
4139 seq_puts(seq, "no memory!\n");
4140 return;
4141 }
4142
4143 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4144 seq_puts(seq, "VPD read failed\n");
4145 goto out;
4146 }
4147
4148 if (buf[0] != VPD_MAGIC) {
4149 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4150 goto out;
4151 }
4152 len = buf[1];
4153 if (len == 0 || len > vpd_size - 4) {
4154 seq_printf(seq, "Invalid id length: %d\n", len);
4155 goto out;
4156 }
4157
4158 seq_printf(seq, "%.*s\n", len, buf + 3);
4159 offs = len + 3;
4160
4161 while (offs < vpd_size - 4) {
4162 int i;
4163
4164 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4165 break;
4166 len = buf[offs + 2];
4167 if (offs + len + 3 >= vpd_size)
4168 break;
4169
4170 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4171 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4172 seq_printf(seq, " %s: %.*s\n",
4173 vpd_tags[i].label, len, buf + offs + 3);
4174 break;
4175 }
4176 }
4177 offs += len + 3;
4178 }
4179 out:
4180 kfree(buf);
4181 }
4182
4183 static int sky2_debug_show(struct seq_file *seq, void *v)
4184 {
4185 struct net_device *dev = seq->private;
4186 const struct sky2_port *sky2 = netdev_priv(dev);
4187 struct sky2_hw *hw = sky2->hw;
4188 unsigned port = sky2->port;
4189 unsigned idx, last;
4190 int sop;
4191
4192 sky2_show_vpd(seq, hw);
4193
4194 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4195 sky2_read32(hw, B0_ISRC),
4196 sky2_read32(hw, B0_IMSK),
4197 sky2_read32(hw, B0_Y2_SP_ICR));
4198
4199 if (!netif_running(dev)) {
4200 seq_printf(seq, "network not running\n");
4201 return 0;
4202 }
4203
4204 napi_disable(&hw->napi);
4205 last = sky2_read16(hw, STAT_PUT_IDX);
4206
4207 if (hw->st_idx == last)
4208 seq_puts(seq, "Status ring (empty)\n");
4209 else {
4210 seq_puts(seq, "Status ring\n");
4211 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4212 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4213 const struct sky2_status_le *le = hw->st_le + idx;
4214 seq_printf(seq, "[%d] %#x %d %#x\n",
4215 idx, le->opcode, le->length, le->status);
4216 }
4217 seq_puts(seq, "\n");
4218 }
4219
4220 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4221 sky2->tx_cons, sky2->tx_prod,
4222 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4223 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4224
4225 /* Dump contents of tx ring */
4226 sop = 1;
4227 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4228 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4229 const struct sky2_tx_le *le = sky2->tx_le + idx;
4230 u32 a = le32_to_cpu(le->addr);
4231
4232 if (sop)
4233 seq_printf(seq, "%u:", idx);
4234 sop = 0;
4235
4236 switch(le->opcode & ~HW_OWNER) {
4237 case OP_ADDR64:
4238 seq_printf(seq, " %#x:", a);
4239 break;
4240 case OP_LRGLEN:
4241 seq_printf(seq, " mtu=%d", a);
4242 break;
4243 case OP_VLAN:
4244 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4245 break;
4246 case OP_TCPLISW:
4247 seq_printf(seq, " csum=%#x", a);
4248 break;
4249 case OP_LARGESEND:
4250 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4251 break;
4252 case OP_PACKET:
4253 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4254 break;
4255 case OP_BUFFER:
4256 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4257 break;
4258 default:
4259 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4260 a, le16_to_cpu(le->length));
4261 }
4262
4263 if (le->ctrl & EOP) {
4264 seq_putc(seq, '\n');
4265 sop = 1;
4266 }
4267 }
4268
4269 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4270 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4271 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4272 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4273
4274 sky2_read32(hw, B0_Y2_SP_LISR);
4275 napi_enable(&hw->napi);
4276 return 0;
4277 }
4278
4279 static int sky2_debug_open(struct inode *inode, struct file *file)
4280 {
4281 return single_open(file, sky2_debug_show, inode->i_private);
4282 }
4283
4284 static const struct file_operations sky2_debug_fops = {
4285 .owner = THIS_MODULE,
4286 .open = sky2_debug_open,
4287 .read = seq_read,
4288 .llseek = seq_lseek,
4289 .release = single_release,
4290 };
4291
4292 /*
4293 * Use network device events to create/remove/rename
4294 * debugfs file entries
4295 */
4296 static int sky2_device_event(struct notifier_block *unused,
4297 unsigned long event, void *ptr)
4298 {
4299 struct net_device *dev = ptr;
4300 struct sky2_port *sky2 = netdev_priv(dev);
4301
4302 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4303 return NOTIFY_DONE;
4304
4305 switch(event) {
4306 case NETDEV_CHANGENAME:
4307 if (sky2->debugfs) {
4308 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4309 sky2_debug, dev->name);
4310 }
4311 break;
4312
4313 case NETDEV_GOING_DOWN:
4314 if (sky2->debugfs) {
4315 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4316 dev->name);
4317 debugfs_remove(sky2->debugfs);
4318 sky2->debugfs = NULL;
4319 }
4320 break;
4321
4322 case NETDEV_UP:
4323 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4324 sky2_debug, dev,
4325 &sky2_debug_fops);
4326 if (IS_ERR(sky2->debugfs))
4327 sky2->debugfs = NULL;
4328 }
4329
4330 return NOTIFY_DONE;
4331 }
4332
4333 static struct notifier_block sky2_notifier = {
4334 .notifier_call = sky2_device_event,
4335 };
4336
4337
4338 static __init void sky2_debug_init(void)
4339 {
4340 struct dentry *ent;
4341
4342 ent = debugfs_create_dir("sky2", NULL);
4343 if (!ent || IS_ERR(ent))
4344 return;
4345
4346 sky2_debug = ent;
4347 register_netdevice_notifier(&sky2_notifier);
4348 }
4349
4350 static __exit void sky2_debug_cleanup(void)
4351 {
4352 if (sky2_debug) {
4353 unregister_netdevice_notifier(&sky2_notifier);
4354 debugfs_remove(sky2_debug);
4355 sky2_debug = NULL;
4356 }
4357 }
4358
4359 #else
4360 #define sky2_debug_init()
4361 #define sky2_debug_cleanup()
4362 #endif
4363
4364 /* Two copies of network device operations to handle special case of
4365 not allowing netpoll on second port */
4366 static const struct net_device_ops sky2_netdev_ops[2] = {
4367 {
4368 .ndo_open = sky2_up,
4369 .ndo_stop = sky2_down,
4370 .ndo_start_xmit = sky2_xmit_frame,
4371 .ndo_do_ioctl = sky2_ioctl,
4372 .ndo_validate_addr = eth_validate_addr,
4373 .ndo_set_mac_address = sky2_set_mac_address,
4374 .ndo_set_multicast_list = sky2_set_multicast,
4375 .ndo_change_mtu = sky2_change_mtu,
4376 .ndo_tx_timeout = sky2_tx_timeout,
4377 #ifdef SKY2_VLAN_TAG_USED
4378 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4379 #endif
4380 #ifdef CONFIG_NET_POLL_CONTROLLER
4381 .ndo_poll_controller = sky2_netpoll,
4382 #endif
4383 },
4384 {
4385 .ndo_open = sky2_up,
4386 .ndo_stop = sky2_down,
4387 .ndo_start_xmit = sky2_xmit_frame,
4388 .ndo_do_ioctl = sky2_ioctl,
4389 .ndo_validate_addr = eth_validate_addr,
4390 .ndo_set_mac_address = sky2_set_mac_address,
4391 .ndo_set_multicast_list = sky2_set_multicast,
4392 .ndo_change_mtu = sky2_change_mtu,
4393 .ndo_tx_timeout = sky2_tx_timeout,
4394 #ifdef SKY2_VLAN_TAG_USED
4395 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4396 #endif
4397 },
4398 };
4399
4400 /* Initialize network device */
4401 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4402 unsigned port,
4403 int highmem, int wol)
4404 {
4405 struct sky2_port *sky2;
4406 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4407
4408 if (!dev) {
4409 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4410 return NULL;
4411 }
4412
4413 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4414 dev->irq = hw->pdev->irq;
4415 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4416 dev->watchdog_timeo = TX_WATCHDOG;
4417 dev->netdev_ops = &sky2_netdev_ops[port];
4418
4419 sky2 = netdev_priv(dev);
4420 sky2->netdev = dev;
4421 sky2->hw = hw;
4422 sky2->msg_enable = netif_msg_init(debug, default_msg);
4423
4424 /* Auto speed and flow control */
4425 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4426 if (hw->chip_id != CHIP_ID_YUKON_XL)
4427 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4428
4429 sky2->flow_mode = FC_BOTH;
4430
4431 sky2->duplex = -1;
4432 sky2->speed = -1;
4433 sky2->advertising = sky2_supported_modes(hw);
4434 sky2->wol = wol;
4435
4436 spin_lock_init(&sky2->phy_lock);
4437
4438 sky2->tx_pending = TX_DEF_PENDING;
4439 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4440 sky2->rx_pending = RX_DEF_PENDING;
4441
4442 hw->dev[port] = dev;
4443
4444 sky2->port = port;
4445
4446 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4447 if (highmem)
4448 dev->features |= NETIF_F_HIGHDMA;
4449
4450 #ifdef SKY2_VLAN_TAG_USED
4451 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4452 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4453 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4454 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4455 }
4456 #endif
4457
4458 /* read the mac address */
4459 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4460 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4461
4462 return dev;
4463 }
4464
4465 static void __devinit sky2_show_addr(struct net_device *dev)
4466 {
4467 const struct sky2_port *sky2 = netdev_priv(dev);
4468
4469 if (netif_msg_probe(sky2))
4470 printk(KERN_INFO PFX "%s: addr %pM\n",
4471 dev->name, dev->dev_addr);
4472 }
4473
4474 /* Handle software interrupt used during MSI test */
4475 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4476 {
4477 struct sky2_hw *hw = dev_id;
4478 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4479
4480 if (status == 0)
4481 return IRQ_NONE;
4482
4483 if (status & Y2_IS_IRQ_SW) {
4484 hw->flags |= SKY2_HW_USE_MSI;
4485 wake_up(&hw->msi_wait);
4486 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4487 }
4488 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4489
4490 return IRQ_HANDLED;
4491 }
4492
4493 /* Test interrupt path by forcing a a software IRQ */
4494 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4495 {
4496 struct pci_dev *pdev = hw->pdev;
4497 int err;
4498
4499 init_waitqueue_head (&hw->msi_wait);
4500
4501 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4502
4503 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4504 if (err) {
4505 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4506 return err;
4507 }
4508
4509 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4510 sky2_read8(hw, B0_CTST);
4511
4512 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4513
4514 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4515 /* MSI test failed, go back to INTx mode */
4516 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4517 "switching to INTx mode.\n");
4518
4519 err = -EOPNOTSUPP;
4520 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4521 }
4522
4523 sky2_write32(hw, B0_IMSK, 0);
4524 sky2_read32(hw, B0_IMSK);
4525
4526 free_irq(pdev->irq, hw);
4527
4528 return err;
4529 }
4530
4531 /* This driver supports yukon2 chipset only */
4532 static const char *sky2_name(u8 chipid, char *buf, int sz)
4533 {
4534 const char *name[] = {
4535 "XL", /* 0xb3 */
4536 "EC Ultra", /* 0xb4 */
4537 "Extreme", /* 0xb5 */
4538 "EC", /* 0xb6 */
4539 "FE", /* 0xb7 */
4540 "FE+", /* 0xb8 */
4541 "Supreme", /* 0xb9 */
4542 "UL 2", /* 0xba */
4543 "Unknown", /* 0xbb */
4544 "Optima", /* 0xbc */
4545 };
4546
4547 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4548 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4549 else
4550 snprintf(buf, sz, "(chip %#x)", chipid);
4551 return buf;
4552 }
4553
4554 static int __devinit sky2_probe(struct pci_dev *pdev,
4555 const struct pci_device_id *ent)
4556 {
4557 struct net_device *dev;
4558 struct sky2_hw *hw;
4559 int err, using_dac = 0, wol_default;
4560 u32 reg;
4561 char buf1[16];
4562
4563 err = pci_enable_device(pdev);
4564 if (err) {
4565 dev_err(&pdev->dev, "cannot enable PCI device\n");
4566 goto err_out;
4567 }
4568
4569 /* Get configuration information
4570 * Note: only regular PCI config access once to test for HW issues
4571 * other PCI access through shared memory for speed and to
4572 * avoid MMCONFIG problems.
4573 */
4574 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4575 if (err) {
4576 dev_err(&pdev->dev, "PCI read config failed\n");
4577 goto err_out;
4578 }
4579
4580 if (~reg == 0) {
4581 dev_err(&pdev->dev, "PCI configuration read error\n");
4582 goto err_out;
4583 }
4584
4585 err = pci_request_regions(pdev, DRV_NAME);
4586 if (err) {
4587 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4588 goto err_out_disable;
4589 }
4590
4591 pci_set_master(pdev);
4592
4593 if (sizeof(dma_addr_t) > sizeof(u32) &&
4594 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4595 using_dac = 1;
4596 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4597 if (err < 0) {
4598 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4599 "for consistent allocations\n");
4600 goto err_out_free_regions;
4601 }
4602 } else {
4603 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4604 if (err) {
4605 dev_err(&pdev->dev, "no usable DMA configuration\n");
4606 goto err_out_free_regions;
4607 }
4608 }
4609
4610
4611 #ifdef __BIG_ENDIAN
4612 /* The sk98lin vendor driver uses hardware byte swapping but
4613 * this driver uses software swapping.
4614 */
4615 reg &= ~PCI_REV_DESC;
4616 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4617 if (err) {
4618 dev_err(&pdev->dev, "PCI write config failed\n");
4619 goto err_out_free_regions;
4620 }
4621 #endif
4622
4623 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4624
4625 err = -ENOMEM;
4626
4627 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4628 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4629 if (!hw) {
4630 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4631 goto err_out_free_regions;
4632 }
4633
4634 hw->pdev = pdev;
4635 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4636
4637 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4638 if (!hw->regs) {
4639 dev_err(&pdev->dev, "cannot map device registers\n");
4640 goto err_out_free_hw;
4641 }
4642
4643 /* ring for status responses */
4644 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4645 if (!hw->st_le)
4646 goto err_out_iounmap;
4647
4648 err = sky2_init(hw);
4649 if (err)
4650 goto err_out_iounmap;
4651
4652 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4653 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4654
4655 sky2_reset(hw);
4656
4657 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4658 if (!dev) {
4659 err = -ENOMEM;
4660 goto err_out_free_pci;
4661 }
4662
4663 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4664 err = sky2_test_msi(hw);
4665 if (err == -EOPNOTSUPP)
4666 pci_disable_msi(pdev);
4667 else if (err)
4668 goto err_out_free_netdev;
4669 }
4670
4671 err = register_netdev(dev);
4672 if (err) {
4673 dev_err(&pdev->dev, "cannot register net device\n");
4674 goto err_out_free_netdev;
4675 }
4676
4677 netif_carrier_off(dev);
4678
4679 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4680
4681 err = request_irq(pdev->irq, sky2_intr,
4682 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4683 hw->irq_name, hw);
4684 if (err) {
4685 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4686 goto err_out_unregister;
4687 }
4688 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4689 napi_enable(&hw->napi);
4690
4691 sky2_show_addr(dev);
4692
4693 if (hw->ports > 1) {
4694 struct net_device *dev1;
4695
4696 err = -ENOMEM;
4697 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4698 if (dev1 && (err = register_netdev(dev1)) == 0)
4699 sky2_show_addr(dev1);
4700 else {
4701 dev_warn(&pdev->dev,
4702 "register of second port failed (%d)\n", err);
4703 hw->dev[1] = NULL;
4704 hw->ports = 1;
4705 if (dev1)
4706 free_netdev(dev1);
4707 }
4708 }
4709
4710 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4711 INIT_WORK(&hw->restart_work, sky2_restart);
4712
4713 pci_set_drvdata(pdev, hw);
4714 pdev->d3_delay = 150;
4715
4716 return 0;
4717
4718 err_out_unregister:
4719 if (hw->flags & SKY2_HW_USE_MSI)
4720 pci_disable_msi(pdev);
4721 unregister_netdev(dev);
4722 err_out_free_netdev:
4723 free_netdev(dev);
4724 err_out_free_pci:
4725 sky2_write8(hw, B0_CTST, CS_RST_SET);
4726 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4727 err_out_iounmap:
4728 iounmap(hw->regs);
4729 err_out_free_hw:
4730 kfree(hw);
4731 err_out_free_regions:
4732 pci_release_regions(pdev);
4733 err_out_disable:
4734 pci_disable_device(pdev);
4735 err_out:
4736 pci_set_drvdata(pdev, NULL);
4737 return err;
4738 }
4739
4740 static void __devexit sky2_remove(struct pci_dev *pdev)
4741 {
4742 struct sky2_hw *hw = pci_get_drvdata(pdev);
4743 int i;
4744
4745 if (!hw)
4746 return;
4747
4748 del_timer_sync(&hw->watchdog_timer);
4749 cancel_work_sync(&hw->restart_work);
4750
4751 for (i = hw->ports-1; i >= 0; --i)
4752 unregister_netdev(hw->dev[i]);
4753
4754 sky2_write32(hw, B0_IMSK, 0);
4755
4756 sky2_power_aux(hw);
4757
4758 sky2_write8(hw, B0_CTST, CS_RST_SET);
4759 sky2_read8(hw, B0_CTST);
4760
4761 free_irq(pdev->irq, hw);
4762 if (hw->flags & SKY2_HW_USE_MSI)
4763 pci_disable_msi(pdev);
4764 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4765 pci_release_regions(pdev);
4766 pci_disable_device(pdev);
4767
4768 for (i = hw->ports-1; i >= 0; --i)
4769 free_netdev(hw->dev[i]);
4770
4771 iounmap(hw->regs);
4772 kfree(hw);
4773
4774 pci_set_drvdata(pdev, NULL);
4775 }
4776
4777 #ifdef CONFIG_PM
4778 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4779 {
4780 struct sky2_hw *hw = pci_get_drvdata(pdev);
4781 int i, wol = 0;
4782
4783 if (!hw)
4784 return 0;
4785
4786 del_timer_sync(&hw->watchdog_timer);
4787 cancel_work_sync(&hw->restart_work);
4788
4789 rtnl_lock();
4790 for (i = 0; i < hw->ports; i++) {
4791 struct net_device *dev = hw->dev[i];
4792 struct sky2_port *sky2 = netdev_priv(dev);
4793
4794 sky2_detach(dev);
4795
4796 if (sky2->wol)
4797 sky2_wol_init(sky2);
4798
4799 wol |= sky2->wol;
4800 }
4801
4802 sky2_write32(hw, B0_IMSK, 0);
4803 napi_disable(&hw->napi);
4804 sky2_power_aux(hw);
4805 rtnl_unlock();
4806
4807 pci_save_state(pdev);
4808 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4809 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4810
4811 return 0;
4812 }
4813
4814 static int sky2_resume(struct pci_dev *pdev)
4815 {
4816 struct sky2_hw *hw = pci_get_drvdata(pdev);
4817 int i, err;
4818
4819 if (!hw)
4820 return 0;
4821
4822 err = pci_set_power_state(pdev, PCI_D0);
4823 if (err)
4824 goto out;
4825
4826 err = pci_restore_state(pdev);
4827 if (err)
4828 goto out;
4829
4830 pci_enable_wake(pdev, PCI_D0, 0);
4831
4832 /* Re-enable all clocks */
4833 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4834 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4835 hw->chip_id == CHIP_ID_YUKON_FE_P)
4836 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4837
4838 sky2_reset(hw);
4839 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4840 napi_enable(&hw->napi);
4841
4842 rtnl_lock();
4843 for (i = 0; i < hw->ports; i++) {
4844 err = sky2_reattach(hw->dev[i]);
4845 if (err)
4846 goto out;
4847 }
4848 rtnl_unlock();
4849
4850 return 0;
4851 out:
4852 rtnl_unlock();
4853
4854 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4855 pci_disable_device(pdev);
4856 return err;
4857 }
4858 #endif
4859
4860 static void sky2_shutdown(struct pci_dev *pdev)
4861 {
4862 struct sky2_hw *hw = pci_get_drvdata(pdev);
4863 int i, wol = 0;
4864
4865 if (!hw)
4866 return;
4867
4868 rtnl_lock();
4869 del_timer_sync(&hw->watchdog_timer);
4870
4871 for (i = 0; i < hw->ports; i++) {
4872 struct net_device *dev = hw->dev[i];
4873 struct sky2_port *sky2 = netdev_priv(dev);
4874
4875 if (sky2->wol) {
4876 wol = 1;
4877 sky2_wol_init(sky2);
4878 }
4879 }
4880
4881 if (wol)
4882 sky2_power_aux(hw);
4883 rtnl_unlock();
4884
4885 pci_enable_wake(pdev, PCI_D3hot, wol);
4886 pci_enable_wake(pdev, PCI_D3cold, wol);
4887
4888 pci_disable_device(pdev);
4889 pci_set_power_state(pdev, PCI_D3hot);
4890 }
4891
4892 static struct pci_driver sky2_driver = {
4893 .name = DRV_NAME,
4894 .id_table = sky2_id_table,
4895 .probe = sky2_probe,
4896 .remove = __devexit_p(sky2_remove),
4897 #ifdef CONFIG_PM
4898 .suspend = sky2_suspend,
4899 .resume = sky2_resume,
4900 #endif
4901 .shutdown = sky2_shutdown,
4902 };
4903
4904 static int __init sky2_init_module(void)
4905 {
4906 pr_info(PFX "driver version " DRV_VERSION "\n");
4907
4908 sky2_debug_init();
4909 return pci_register_driver(&sky2_driver);
4910 }
4911
4912 static void __exit sky2_cleanup_module(void)
4913 {
4914 pci_unregister_driver(&sky2_driver);
4915 sky2_debug_cleanup();
4916 }
4917
4918 module_init(sky2_init_module);
4919 module_exit(sky2_cleanup_module);
4920
4921 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4922 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4923 MODULE_LICENSE("GPL");
4924 MODULE_VERSION(DRV_VERSION);
linux 2.6 git repository for openrd