arch/ia64/pci/pci.c

   1 /*
   2  * pci.c - Low-Level PCI Access in IA-64
   3  *
   4  * Derived from bios32.c of i386 tree.
   5  *
   6  * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
   7  *      David Mosberger-Tang <davidm@hpl.hp.com>
   8  *      Bjorn Helgaas <bjorn.helgaas@hp.com>
   9  * Copyright (C) 2004 Silicon Graphics, Inc.
  10  *
  11  * Note: Above list of copyright holders is incomplete...
  12  */
  13
  14 #include <linux/acpi.h>
  15 #include <linux/types.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pci.h>
  18 #include <linux/init.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/bootmem.h>
  23 #include <linux/export.h>
  24
  25 #include <asm/machvec.h>
  26 #include <asm/page.h>
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/sal.h>
  30 #include <asm/smp.h>
  31 #include <asm/irq.h>
  32 #include <asm/hw_irq.h>
  33
  34 /*
  35  * Low-level SAL-based PCI configuration access functions. Note that SAL
  36  * calls are already serialized (via sal_lock), so we don't need another
  37  * synchronization mechanism here.
  38  */
  39
  40 #define PCI_SAL_ADDRESS(seg, bus, devfn, reg)           \
  41         (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  42
  43 /* SAL 3.2 adds support for extended config space. */
  44
  45 #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg)       \
  46         (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  47
  48 int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
  49               int reg, int len, u32 *value)
  50 {
  51         u64 addr, data = 0;
  52         int mode, result;
  53
  54         if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  55                 return -EINVAL;
  56
  57         if ((seg | reg) <= 255) {
  58                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  59                 mode = 0;
  60         } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
  61                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  62                 mode = 1;
  63         } else {
  64                 return -EINVAL;
  65         }
  66
  67         result = ia64_sal_pci_config_read(addr, mode, len, &data);
  68         if (result != 0)
  69                 return -EINVAL;
  70
  71         *value = (u32) data;
  72         return 0;
  73 }
  74
  75 int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
  76                int reg, int len, u32 value)
  77 {
  78         u64 addr;
  79         int mode, result;
  80
  81         if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  82                 return -EINVAL;
  83
  84         if ((seg | reg) <= 255) {
  85                 addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  86                 mode = 0;
  87         } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
  88                 addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  89                 mode = 1;
  90         } else {
  91                 return -EINVAL;
  92         }
  93         result = ia64_sal_pci_config_write(addr, mode, len, value);
  94         if (result != 0)
  95                 return -EINVAL;
  96         return 0;
  97 }
  98
  99 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
 100                                                         int size, u32 *value)
 101 {
 102         return raw_pci_read(pci_domain_nr(bus), bus->number,
 103                                  devfn, where, size, value);
 104 }
 105
 106 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
 107                                                         int size, u32 value)
 108 {
 109         return raw_pci_write(pci_domain_nr(bus), bus->number,
 110                                   devfn, where, size, value);
 111 }
 112
 113 struct pci_ops pci_root_ops = {
 114         .read = pci_read,
 115         .write = pci_write,
 116 };
 117
 118 /* Called by ACPI when it finds a new root bus.  */
 119
 120 static struct pci_controller * __devinit
 121 alloc_pci_controller (int seg)
 122 {
 123         struct pci_controller *controller;
 124
 125         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 126         if (!controller)
 127                 return NULL;
 128
 129         controller->segment = seg;
 130         controller->node = -1;
 131         return controller;
 132 }
 133
 134 struct pci_root_info {
 135         struct acpi_device *bridge;
 136         struct pci_controller *controller;
 137         char *name;
 138 };
 139
 140 static unsigned int
 141 new_space (u64 phys_base, int sparse)
 142 {
 143         u64 mmio_base;
 144         int i;
 145
 146         if (phys_base == 0)
 147                 return 0;       /* legacy I/O port space */
 148
 149         mmio_base = (u64) ioremap(phys_base, 0);
 150         for (i = 0; i < num_io_spaces; i++)
 151                 if (io_space[i].mmio_base == mmio_base &&
 152                     io_space[i].sparse == sparse)
 153                         return i;
 154
 155         if (num_io_spaces == MAX_IO_SPACES) {
 156                 printk(KERN_ERR "PCI: Too many IO port spaces "
 157                         "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
 158                 return ~0;
 159         }
 160
 161         i = num_io_spaces++;
 162         io_space[i].mmio_base = mmio_base;
 163         io_space[i].sparse = sparse;
 164
 165         return i;
 166 }
 167
 168 static u64 __devinit
 169 add_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr)
 170 {
 171         struct resource *resource;
 172         char *name;
 173         unsigned long base, min, max, base_port;
 174         unsigned int sparse = 0, space_nr, len;
 175
 176         resource = kzalloc(sizeof(*resource), GFP_KERNEL);
 177         if (!resource) {
 178                 printk(KERN_ERR "PCI: No memory for %s I/O port space\n",
 179                         info->name);
 180                 goto out;
 181         }
 182
 183         len = strlen(info->name) + 32;
 184         name = kzalloc(len, GFP_KERNEL);
 185         if (!name) {
 186                 printk(KERN_ERR "PCI: No memory for %s I/O port space name\n",
 187                         info->name);
 188                 goto free_resource;
 189         }
 190
 191         min = addr->minimum;
 192         max = min + addr->address_length - 1;
 193         if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
 194                 sparse = 1;
 195
 196         space_nr = new_space(addr->translation_offset, sparse);
 197         if (space_nr == ~0)
 198                 goto free_name;
 199
 200         base = __pa(io_space[space_nr].mmio_base);
 201         base_port = IO_SPACE_BASE(space_nr);
 202         snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
 203                 base_port + min, base_port + max);
 204
 205         /*
 206          * The SDM guarantees the legacy 0-64K space is sparse, but if the
 207          * mapping is done by the processor (not the bridge), ACPI may not
 208          * mark it as sparse.
 209          */
 210         if (space_nr == 0)
 211                 sparse = 1;
 212
 213         resource->name  = name;
 214         resource->flags = IORESOURCE_MEM;
 215         resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
 216         resource->end   = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
 217         insert_resource(&iomem_resource, resource);
 218
 219         return base_port;
 220
 221 free_name:
 222         kfree(name);
 223 free_resource:
 224         kfree(resource);
 225 out:
 226         return ~0;
 227 }
 228
 229 static acpi_status __devinit resource_to_window(struct acpi_resource *resource,
 230         struct acpi_resource_address64 *addr)
 231 {
 232         acpi_status status;
 233
 234         /*
 235          * We're only interested in _CRS descriptors that are
 236          *      - address space descriptors for memory or I/O space
 237          *      - non-zero size
 238          *      - producers, i.e., the address space is routed downstream,
 239          *        not consumed by the bridge itself
 240          */
 241         status = acpi_resource_to_address64(resource, addr);
 242         if (ACPI_SUCCESS(status) &&
 243             (addr->resource_type == ACPI_MEMORY_RANGE ||
 244              addr->resource_type == ACPI_IO_RANGE) &&
 245             addr->address_length &&
 246             addr->producer_consumer == ACPI_PRODUCER)
 247                 return AE_OK;
 248
 249         return AE_ERROR;
 250 }
 251
 252 static acpi_status __devinit
 253 count_window (struct acpi_resource *resource, void *data)
 254 {
 255         unsigned int *windows = (unsigned int *) data;
 256         struct acpi_resource_address64 addr;
 257         acpi_status status;
 258
 259         status = resource_to_window(resource, &addr);
 260         if (ACPI_SUCCESS(status))
 261                 (*windows)++;
 262
 263         return AE_OK;
 264 }
 265
 266 static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
 267 {
 268         struct pci_root_info *info = data;
 269         struct pci_window *window;
 270         struct acpi_resource_address64 addr;
 271         acpi_status status;
 272         unsigned long flags, offset = 0;
 273         struct resource *root;
 274
 275         /* Return AE_OK for non-window resources to keep scanning for more */
 276         status = resource_to_window(res, &addr);
 277         if (!ACPI_SUCCESS(status))
 278                 return AE_OK;
 279
 280         if (addr.resource_type == ACPI_MEMORY_RANGE) {
 281                 flags = IORESOURCE_MEM;
 282                 root = &iomem_resource;
 283                 offset = addr.translation_offset;
 284         } else if (addr.resource_type == ACPI_IO_RANGE) {
 285                 flags = IORESOURCE_IO;
 286                 root = &ioport_resource;
 287                 offset = add_io_space(info, &addr);
 288                 if (offset == ~0)
 289                         return AE_OK;
 290         } else
 291                 return AE_OK;
 292
 293         window = &info->controller->window[info->controller->windows++];
 294         window->resource.name = info->name;
 295         window->resource.flags = flags;
 296         window->resource.start = addr.minimum + offset;
 297         window->resource.end = window->resource.start + addr.address_length - 1;
 298         window->resource.child = NULL;
 299         window->offset = offset;
 300
 301         if (insert_resource(root, &window->resource)) {
 302                 dev_err(&info->bridge->dev,
 303                         "can't allocate host bridge window %pR\n",
 304                         &window->resource);
 305         } else {
 306                 if (offset)
 307                         dev_info(&info->bridge->dev, "host bridge window %pR "
 308                                  "(PCI address [%#llx-%#llx])\n",
 309                                  &window->resource,
 310                                  window->resource.start - offset,
 311                                  window->resource.end - offset);
 312                 else
 313                         dev_info(&info->bridge->dev,
 314                                  "host bridge window %pR\n",
 315                                  &window->resource);
 316         }
 317
 318         return AE_OK;
 319 }
 320
 321 static void __devinit
 322 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
 323 {
 324         int i;
 325
 326         pci_bus_remove_resources(bus);
 327         for (i = 0; i < ctrl->windows; i++) {
 328                 struct resource *res = &ctrl->window[i].resource;
 329                 /* HP's firmware has a hack to work around a Windows bug.
 330                  * Ignore these tiny memory ranges */
 331                 if ((res->flags & IORESOURCE_MEM) &&
 332                     (res->end - res->start < 16))
 333                         continue;
 334                 pci_bus_add_resource(bus, res, 0);
 335         }
 336 }
 337
 338 struct pci_bus * __devinit
 339 pci_acpi_scan_root(struct acpi_pci_root *root)
 340 {
 341         struct acpi_device *device = root->device;
 342         int domain = root->segment;
 343         int bus = root->secondary.start;
 344         struct pci_controller *controller;
 345         unsigned int windows = 0;
 346         struct pci_bus *pbus;
 347         char *name;
 348         int pxm;
 349
 350         controller = alloc_pci_controller(domain);
 351         if (!controller)
 352                 goto out1;
 353
 354         controller->acpi_handle = device->handle;
 355
 356         pxm = acpi_get_pxm(controller->acpi_handle);
 357 #ifdef CONFIG_NUMA
 358         if (pxm >= 0)
 359                 controller->node = pxm_to_node(pxm);
 360 #endif
 361
 362         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
 363                         &windows);
 364         if (windows) {
 365                 struct pci_root_info info;
 366
 367                 controller->window =
 368                         kmalloc_node(sizeof(*controller->window) * windows,
 369                                      GFP_KERNEL, controller->node);
 370                 if (!controller->window)
 371                         goto out2;
 372
 373                 name = kmalloc(16, GFP_KERNEL);
 374                 if (!name)
 375                         goto out3;
 376
 377                 sprintf(name, "PCI Bus %04x:%02x", domain, bus);
 378                 info.bridge = device;
 379                 info.controller = controller;
 380                 info.name = name;
 381                 acpi_walk_resources(device->handle, METHOD_NAME__CRS,
 382                         add_window, &info);
 383         }
 384         /*
 385          * See arch/x86/pci/acpi.c.
 386          * The desired pci bus might already be scanned in a quirk. We
 387          * should handle the case here, but it appears that IA64 hasn't
 388          * such quirk. So we just ignore the case now.
 389          */
 390         pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller);
 391
 392         return pbus;
 393
 394 out3:
 395         kfree(controller->window);
 396 out2:
 397         kfree(controller);
 398 out1:
 399         return NULL;
 400 }
 401
 402 void pcibios_resource_to_bus(struct pci_dev *dev,
 403                 struct pci_bus_region *region, struct resource *res)
 404 {
 405         struct pci_controller *controller = PCI_CONTROLLER(dev);
 406         unsigned long offset = 0;
 407         int i;
 408
 409         for (i = 0; i < controller->windows; i++) {
 410                 struct pci_window *window = &controller->window[i];
 411                 if (!(window->resource.flags & res->flags))
 412                         continue;
 413                 if (window->resource.start > res->start)
 414                         continue;
 415                 if (window->resource.end < res->end)
 416                         continue;
 417                 offset = window->offset;
 418                 break;
 419         }
 420
 421         region->start = res->start - offset;
 422         region->end = res->end - offset;
 423 }
 424 EXPORT_SYMBOL(pcibios_resource_to_bus);
 425
 426 void pcibios_bus_to_resource(struct pci_dev *dev,
 427                 struct resource *res, struct pci_bus_region *region)
 428 {
 429         struct pci_controller *controller = PCI_CONTROLLER(dev);
 430         unsigned long offset = 0;
 431         int i;
 432
 433         for (i = 0; i < controller->windows; i++) {
 434                 struct pci_window *window = &controller->window[i];
 435                 if (!(window->resource.flags & res->flags))
 436                         continue;
 437                 if (window->resource.start - window->offset > region->start)
 438                         continue;
 439                 if (window->resource.end - window->offset < region->end)
 440                         continue;
 441                 offset = window->offset;
 442                 break;
 443         }
 444
 445         res->start = region->start + offset;
 446         res->end = region->end + offset;
 447 }
 448 EXPORT_SYMBOL(pcibios_bus_to_resource);
 449
 450 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 451 {
 452         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
 453         struct resource *devr = &dev->resource[idx], *busr;
 454
 455         if (!dev->bus)
 456                 return 0;
 457
 458         pci_bus_for_each_resource(dev->bus, busr, i) {
 459                 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
 460                         continue;
 461                 if ((devr->start) && (devr->start >= busr->start) &&
 462                                 (devr->end <= busr->end))
 463                         return 1;
 464         }
 465         return 0;
 466 }
 467
 468 static void __devinit
 469 pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
 470 {
 471         struct pci_bus_region region;
 472         int i;
 473
 474         for (i = start; i < limit; i++) {
 475                 if (!dev->resource[i].flags)
 476                         continue;
 477                 region.start = dev->resource[i].start;
 478                 region.end = dev->resource[i].end;
 479                 pcibios_bus_to_resource(dev, &dev->resource[i], &region);
 480                 if ((is_valid_resource(dev, i)))
 481                         pci_claim_resource(dev, i);
 482         }
 483 }
 484
 485 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 486 {
 487         pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
 488 }
 489 EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
 490
 491 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
 492 {
 493         pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
 494 }
 495
 496 /*
 497  *  Called after each bus is probed, but before its children are examined.
 498  */
 499 void __devinit
 500 pcibios_fixup_bus (struct pci_bus *b)
 501 {
 502         struct pci_dev *dev;
 503
 504         if (b->self) {
 505                 pci_read_bridge_bases(b);
 506                 pcibios_fixup_bridge_resources(b->self);
 507         } else {
 508                 pcibios_setup_root_windows(b, b->sysdata);
 509         }
 510         list_for_each_entry(dev, &b->devices, bus_list)
 511                 pcibios_fixup_device_resources(dev);
 512         platform_pci_fixup_bus(b);
 513
 514         return;
 515 }
 516
 517 void __devinit
 518 pcibios_update_irq (struct pci_dev *dev, int irq)
 519 {
 520         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 521
 522         /* ??? FIXME -- record old value for shutdown.  */
 523 }
 524
 525 int
 526 pcibios_enable_device (struct pci_dev *dev, int mask)
 527 {
 528         int ret;
 529
 530         ret = pci_enable_resources(dev, mask);
 531         if (ret < 0)
 532                 return ret;
 533
 534         if (!dev->msi_enabled)
 535                 return acpi_pci_irq_enable(dev);
 536         return 0;
 537 }
 538
 539 void
 540 pcibios_disable_device (struct pci_dev *dev)
 541 {
 542         BUG_ON(atomic_read(&dev->enable_cnt));
 543         if (!dev->msi_enabled)
 544                 acpi_pci_irq_disable(dev);
 545 }
 546
 547 resource_size_t
 548 pcibios_align_resource (void *data, const struct resource *res,
 549                         resource_size_t size, resource_size_t align)
 550 {
 551         return res->start;
 552 }
 553
 554 /*
 555  * PCI BIOS setup, always defaults to SAL interface
 556  */
 557 char * __init
 558 pcibios_setup (char *str)
 559 {
 560         return str;
 561 }
 562
 563 int
 564 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
 565                      enum pci_mmap_state mmap_state, int write_combine)
 566 {
 567         unsigned long size = vma->vm_end - vma->vm_start;
 568         pgprot_t prot;
 569
 570         /*
 571          * I/O space cannot be accessed via normal processor loads and
 572          * stores on this platform.
 573          */
 574         if (mmap_state == pci_mmap_io)
 575                 /*
 576                  * XXX we could relax this for I/O spaces for which ACPI
 577                  * indicates that the space is 1-to-1 mapped.  But at the
 578                  * moment, we don't support multiple PCI address spaces and
 579                  * the legacy I/O space is not 1-to-1 mapped, so this is moot.
 580                  */
 581                 return -EINVAL;
 582
 583         if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
 584                 return -EINVAL;
 585
 586         prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
 587                                     vma->vm_page_prot);
 588
 589         /*
 590          * If the user requested WC, the kernel uses UC or WC for this region,
 591          * and the chipset supports WC, we can use WC. Otherwise, we have to
 592          * use the same attribute the kernel uses.
 593          */
 594         if (write_combine &&
 595             ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC ||
 596              (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) &&
 597             efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
 598                 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
 599         else
 600                 vma->vm_page_prot = prot;
 601
 602         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 603                              vma->vm_end - vma->vm_start, vma->vm_page_prot))
 604                 return -EAGAIN;
 605
 606         return 0;
 607 }
 608
 609 /**
 610  * ia64_pci_get_legacy_mem - generic legacy mem routine
 611  * @bus: bus to get legacy memory base address for
 612  *
 613  * Find the base of legacy memory for @bus.  This is typically the first
 614  * megabyte of bus address space for @bus or is simply 0 on platforms whose
 615  * chipsets support legacy I/O and memory routing.  Returns the base address
 616  * or an error pointer if an error occurred.
 617  *
 618  * This is the ia64 generic version of this routine.  Other platforms
 619  * are free to override it with a machine vector.
 620  */
 621 char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
 622 {
 623         return (char *)__IA64_UNCACHED_OFFSET;
 624 }
 625
 626 /**
 627  * pci_mmap_legacy_page_range - map legacy memory space to userland
 628  * @bus: bus whose legacy space we're mapping
 629  * @vma: vma passed in by mmap
 630  *
 631  * Map legacy memory space for this device back to userspace using a machine
 632  * vector to get the base address.
 633  */
 634 int
 635 pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
 636                            enum pci_mmap_state mmap_state)
 637 {
 638         unsigned long size = vma->vm_end - vma->vm_start;
 639         pgprot_t prot;
 640         char *addr;
 641
 642         /* We only support mmap'ing of legacy memory space */
 643         if (mmap_state != pci_mmap_mem)
 644                 return -ENOSYS;
 645
 646         /*
 647          * Avoid attribute aliasing.  See Documentation/ia64/aliasing.txt
 648          * for more details.
 649          */
 650         if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
 651                 return -EINVAL;
 652         prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
 653                                     vma->vm_page_prot);
 654
 655         addr = pci_get_legacy_mem(bus);
 656         if (IS_ERR(addr))
 657                 return PTR_ERR(addr);
 658
 659         vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
 660         vma->vm_page_prot = prot;
 661
 662         if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
 663                             size, vma->vm_page_prot))
 664                 return -EAGAIN;
 665
 666         return 0;
 667 }
 668
 669 /**
 670  * ia64_pci_legacy_read - read from legacy I/O space
 671  * @bus: bus to read
 672  * @port: legacy port value
 673  * @val: caller allocated storage for returned value
 674  * @size: number of bytes to read
 675  *
 676  * Simply reads @size bytes from @port and puts the result in @val.
 677  *
 678  * Again, this (and the write routine) are generic versions that can be
 679  * overridden by the platform.  This is necessary on platforms that don't
 680  * support legacy I/O routing or that hard fail on legacy I/O timeouts.
 681  */
 682 int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
 683 {
 684         int ret = size;
 685
 686         switch (size) {
 687         case 1:
 688                 *val = inb(port);
 689                 break;
 690         case 2:
 691                 *val = inw(port);
 692                 break;
 693         case 4:
 694                 *val = inl(port);
 695                 break;
 696         default:
 697                 ret = -EINVAL;
 698                 break;
 699         }
 700
 701         return ret;
 702 }
 703
 704 /**
 705  * ia64_pci_legacy_write - perform a legacy I/O write
 706  * @bus: bus pointer
 707  * @port: port to write
 708  * @val: value to write
 709  * @size: number of bytes to write from @val
 710  *
 711  * Simply writes @size bytes of @val to @port.
 712  */
 713 int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
 714 {
 715         int ret = size;
 716
 717         switch (size) {
 718         case 1:
 719                 outb(val, port);
 720                 break;
 721         case 2:
 722                 outw(val, port);
 723                 break;
 724         case 4:
 725                 outl(val, port);
 726                 break;
 727         default:
 728                 ret = -EINVAL;
 729                 break;
 730         }
 731
 732         return ret;
 733 }
 734
 735 /**
 736  * set_pci_cacheline_size - determine cacheline size for PCI devices
 737  *
 738  * We want to use the line-size of the outer-most cache.  We assume
 739  * that this line-size is the same for all CPUs.
 740  *
 741  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
 742  */
 743 static void __init set_pci_dfl_cacheline_size(void)
 744 {
 745         unsigned long levels, unique_caches;
 746         long status;
 747         pal_cache_config_info_t cci;
 748
 749         status = ia64_pal_cache_summary(&levels, &unique_caches);
 750         if (status != 0) {
 751                 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
 752                         "(status=%ld)\n", __func__, status);
 753                 return;
 754         }
 755
 756         status = ia64_pal_cache_config_info(levels - 1,
 757                                 /* cache_type (data_or_unified)= */ 2, &cci);
 758         if (status != 0) {
 759                 printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
 760                         "(status=%ld)\n", __func__, status);
 761                 return;
 762         }
 763         pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
 764 }
 765
 766 u64 ia64_dma_get_required_mask(struct device *dev)
 767 {
 768         u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);
 769         u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));
 770         u64 mask;
 771
 772         if (!high_totalram) {
 773                 /* convert to mask just covering totalram */
 774                 low_totalram = (1 << (fls(low_totalram) - 1));
 775                 low_totalram += low_totalram - 1;
 776                 mask = low_totalram;
 777         } else {
 778                 high_totalram = (1 << (fls(high_totalram) - 1));
 779                 high_totalram += high_totalram - 1;
 780                 mask = (((u64)high_totalram) << 32) + 0xffffffff;
 781         }
 782         return mask;
 783 }
 784 EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask);
 785
 786 u64 dma_get_required_mask(struct device *dev)
 787 {
 788         return platform_dma_get_required_mask(dev);
 789 }
 790 EXPORT_SYMBOL_GPL(dma_get_required_mask);
 791
 792 static int __init pcibios_init(void)
 793 {
 794         set_pci_dfl_cacheline_size();
 795         return 0;
 796 }
 797
 798 subsys_initcall(pcibios_init);