arch/arm/mach-imx/time.c

   1 /*
   2  *  linux/arch/arm/mach-imx/time.c
   3  *
   4  *  Copyright (C) 2000-2001 Deep Blue Solutions
   5  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   6  *  Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/sched.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/time.h>
  18 #include <linux/clocksource.h>
  19 #include <linux/clockchips.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <asm/leds.h>
  25 #include <asm/irq.h>
  26 #include <asm/mach/time.h>
  27
  28 /* Use timer 1 as system timer */
  29 #define TIMER_BASE IMX_TIM1_BASE
  30
  31 static struct clock_event_device clockevent_imx;
  32 static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
  33
  34 /*
  35  * IRQ handler for the timer
  36  */
  37 static irqreturn_t
  38 imx_timer_interrupt(int irq, void *dev_id)
  39 {
  40         struct clock_event_device *evt = &clockevent_imx;
  41         uint32_t tstat;
  42         irqreturn_t ret = IRQ_NONE;
  43
  44         /* clear the interrupt */
  45         tstat = IMX_TSTAT(TIMER_BASE);
  46         IMX_TSTAT(TIMER_BASE) = 0;
  47
  48         if (tstat & TSTAT_COMP) {
  49                 evt->event_handler(evt);
  50                 ret = IRQ_HANDLED;
  51         }
  52
  53         return ret;
  54 }
  55
  56 static struct irqaction imx_timer_irq = {
  57         .name           = "i.MX Timer Tick",
  58         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  59         .handler        = imx_timer_interrupt,
  60 };
  61
  62 /*
  63  * Set up timer hardware into expected mode and state.
  64  */
  65 static void __init imx_timer_hardware_init(void)
  66 {
  67         /*
  68          * Initialise to a known state (all timers off, and timing reset)
  69          */
  70         IMX_TCTL(TIMER_BASE) = 0;
  71         IMX_TPRER(TIMER_BASE) = 0;
  72
  73         IMX_TCTL(TIMER_BASE) = TCTL_FRR | TCTL_CLK_PCLK1 | TCTL_TEN;
  74 }
  75
  76 cycle_t imx_get_cycles(void)
  77 {
  78         return IMX_TCN(TIMER_BASE);
  79 }
  80
  81 static struct clocksource clocksource_imx = {
  82         .name           = "imx_timer1",
  83         .rating         = 200,
  84         .read           = imx_get_cycles,
  85         .mask           = 0xFFFFFFFF,
  86         .shift          = 20,
  87         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  88 };
  89
  90 static int __init imx_clocksource_init(unsigned long rate)
  91 {
  92         clocksource_imx.mult =
  93                 clocksource_hz2mult(rate, clocksource_imx.shift);
  94         clocksource_register(&clocksource_imx);
  95
  96         return 0;
  97 }
  98
  99 static int imx_set_next_event(unsigned long evt,
 100                                   struct clock_event_device *unused)
 101 {
 102         unsigned long tcmp;
 103
 104         tcmp = IMX_TCN(TIMER_BASE) + evt;
 105         IMX_TCMP(TIMER_BASE) = tcmp;
 106
 107         return (int32_t)(tcmp - IMX_TCN(TIMER_BASE)) < 0 ? -ETIME : 0;
 108 }
 109
 110 #ifdef DEBUG
 111 static const char *clock_event_mode_label[]={
 112         [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
 113         [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
 114         [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
 115         [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
 116 };
 117 #endif /*DEBUG*/
 118
 119 static void imx_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 120 {
 121         unsigned long flags;
 122
 123         /*
 124          * The timer interrupt generation is disabled at least
 125          * for enough time to call imx_set_next_event()
 126          */
 127         local_irq_save(flags);
 128         /* Disable interrupt in GPT module */
 129         IMX_TCTL(TIMER_BASE) &= ~TCTL_IRQEN;
 130         if (mode != clockevent_mode) {
 131                 /* Set event time into far-far future */
 132                 IMX_TCMP(TIMER_BASE) = IMX_TCN(TIMER_BASE) - 3;
 133                 /* Clear pending interrupt */
 134                 IMX_TSTAT(TIMER_BASE) &= ~TSTAT_COMP;
 135         }
 136
 137 #ifdef DEBUG
 138         printk(KERN_INFO "imx_set_mode: changing mode from %s to %s\n",
 139                 clock_event_mode_label[clockevent_mode], clock_event_mode_label[mode]);
 140 #endif /*DEBUG*/
 141
 142         /* Remember timer mode */
 143         clockevent_mode = mode;
 144         local_irq_restore(flags);
 145
 146         switch (mode) {
 147         case CLOCK_EVT_MODE_PERIODIC:
 148                 printk(KERN_ERR "imx_set_mode: Periodic mode is not supported for i.MX\n");
 149                 break;
 150         case CLOCK_EVT_MODE_ONESHOT:
 151                 /*
 152                  * Do not put overhead of interrupt enable/disable into
 153                  * imx_set_next_event(), the core has about 4 minutes
 154                  * to call imx_set_next_event() or shutdown clock after
 155                  * mode switching
 156                  */
 157                 local_irq_save(flags);
 158                 IMX_TCTL(TIMER_BASE) |= TCTL_IRQEN;
 159                 local_irq_restore(flags);
 160                 break;
 161         case CLOCK_EVT_MODE_SHUTDOWN:
 162         case CLOCK_EVT_MODE_UNUSED:
 163         case CLOCK_EVT_MODE_RESUME:
 164                 /* Left event sources disabled, no more interrupts appears */
 165                 break;
 166         }
 167 }
 168
 169 static struct clock_event_device clockevent_imx = {
 170         .name           = "imx_timer1",
 171         .features       = CLOCK_EVT_FEAT_ONESHOT,
 172         .shift          = 32,
 173         .set_mode       = imx_set_mode,
 174         .set_next_event = imx_set_next_event,
 175         .rating         = 200,
 176 };
 177
 178 static int __init imx_clockevent_init(unsigned long rate)
 179 {
 180         clockevent_imx.mult = div_sc(rate, NSEC_PER_SEC,
 181                                         clockevent_imx.shift);
 182         clockevent_imx.max_delta_ns =
 183                 clockevent_delta2ns(0xfffffffe, &clockevent_imx);
 184         clockevent_imx.min_delta_ns =
 185                 clockevent_delta2ns(0xf, &clockevent_imx);
 186
 187         clockevent_imx.cpumask = cpumask_of(0);
 188
 189         clockevents_register_device(&clockevent_imx);
 190
 191         return 0;
 192 }
 193
 194 extern int imx_clocks_init(void);
 195
 196 static void __init imx_timer_init(void)
 197 {
 198         struct clk *clk;
 199         unsigned long rate;
 200
 201         imx_clocks_init();
 202
 203         clk = clk_get(NULL, "perclk1");
 204         clk_enable(clk);
 205         rate = clk_get_rate(clk);
 206
 207         imx_timer_hardware_init();
 208         imx_clocksource_init(rate);
 209
 210         imx_clockevent_init(rate);
 211
 212         /*
 213          * Make irqs happen for the system timer
 214          */
 215         setup_irq(TIM1_INT, &imx_timer_irq);
 216 }
 217
 218 struct sys_timer imx_timer = {
 219         .init           = imx_timer_init,
 220 };