drivers/net/can/flexcan.c

   1 /*
   2  * flexcan.c - FLEXCAN CAN controller driver
   3  *
   4  * Copyright (c) 2005-2006 Varma Electronics Oy
   5  * Copyright (c) 2009 Sascha Hauer, Pengutronix
   6  * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
   7  *
   8  * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
   9  *
  10  * LICENCE:
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation version 2.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  */
  21
  22 #include <linux/netdevice.h>
  23 #include <linux/can.h>
  24 #include <linux/can/dev.h>
  25 #include <linux/can/error.h>
  26 #include <linux/can/platform/flexcan.h>
  27 #include <linux/clk.h>
  28 #include <linux/delay.h>
  29 #include <linux/if_arp.h>
  30 #include <linux/if_ether.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/io.h>
  33 #include <linux/kernel.h>
  34 #include <linux/list.h>
  35 #include <linux/module.h>
  36 #include <linux/of.h>
  37 #include <linux/platform_device.h>
  38
  39 #define DRV_NAME                        "flexcan"
  40
  41 /* 8 for RX fifo and 2 error handling */
  42 #define FLEXCAN_NAPI_WEIGHT             (8 + 2)
  43
  44 /* FLEXCAN module configuration register (CANMCR) bits */
  45 #define FLEXCAN_MCR_MDIS                BIT(31)
  46 #define FLEXCAN_MCR_FRZ                 BIT(30)
  47 #define FLEXCAN_MCR_FEN                 BIT(29)
  48 #define FLEXCAN_MCR_HALT                BIT(28)
  49 #define FLEXCAN_MCR_NOT_RDY             BIT(27)
  50 #define FLEXCAN_MCR_WAK_MSK             BIT(26)
  51 #define FLEXCAN_MCR_SOFTRST             BIT(25)
  52 #define FLEXCAN_MCR_FRZ_ACK             BIT(24)
  53 #define FLEXCAN_MCR_SUPV                BIT(23)
  54 #define FLEXCAN_MCR_SLF_WAK             BIT(22)
  55 #define FLEXCAN_MCR_WRN_EN              BIT(21)
  56 #define FLEXCAN_MCR_LPM_ACK             BIT(20)
  57 #define FLEXCAN_MCR_WAK_SRC             BIT(19)
  58 #define FLEXCAN_MCR_DOZE                BIT(18)
  59 #define FLEXCAN_MCR_SRX_DIS             BIT(17)
  60 #define FLEXCAN_MCR_BCC                 BIT(16)
  61 #define FLEXCAN_MCR_LPRIO_EN            BIT(13)
  62 #define FLEXCAN_MCR_AEN                 BIT(12)
  63 #define FLEXCAN_MCR_MAXMB(x)            ((x) & 0xf)
  64 #define FLEXCAN_MCR_IDAM_A              (0 << 8)
  65 #define FLEXCAN_MCR_IDAM_B              (1 << 8)
  66 #define FLEXCAN_MCR_IDAM_C              (2 << 8)
  67 #define FLEXCAN_MCR_IDAM_D              (3 << 8)
  68
  69 /* FLEXCAN control register (CANCTRL) bits */
  70 #define FLEXCAN_CTRL_PRESDIV(x)         (((x) & 0xff) << 24)
  71 #define FLEXCAN_CTRL_RJW(x)             (((x) & 0x03) << 22)
  72 #define FLEXCAN_CTRL_PSEG1(x)           (((x) & 0x07) << 19)
  73 #define FLEXCAN_CTRL_PSEG2(x)           (((x) & 0x07) << 16)
  74 #define FLEXCAN_CTRL_BOFF_MSK           BIT(15)
  75 #define FLEXCAN_CTRL_ERR_MSK            BIT(14)
  76 #define FLEXCAN_CTRL_CLK_SRC            BIT(13)
  77 #define FLEXCAN_CTRL_LPB                BIT(12)
  78 #define FLEXCAN_CTRL_TWRN_MSK           BIT(11)
  79 #define FLEXCAN_CTRL_RWRN_MSK           BIT(10)
  80 #define FLEXCAN_CTRL_SMP                BIT(7)
  81 #define FLEXCAN_CTRL_BOFF_REC           BIT(6)
  82 #define FLEXCAN_CTRL_TSYN               BIT(5)
  83 #define FLEXCAN_CTRL_LBUF               BIT(4)
  84 #define FLEXCAN_CTRL_LOM                BIT(3)
  85 #define FLEXCAN_CTRL_PROPSEG(x)         ((x) & 0x07)
  86 #define FLEXCAN_CTRL_ERR_BUS            (FLEXCAN_CTRL_ERR_MSK)
  87 #define FLEXCAN_CTRL_ERR_STATE \
  88         (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
  89          FLEXCAN_CTRL_BOFF_MSK)
  90 #define FLEXCAN_CTRL_ERR_ALL \
  91         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
  92
  93 /* FLEXCAN error and status register (ESR) bits */
  94 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
  95 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
  96 #define FLEXCAN_ESR_BIT1_ERR            BIT(15)
  97 #define FLEXCAN_ESR_BIT0_ERR            BIT(14)
  98 #define FLEXCAN_ESR_ACK_ERR             BIT(13)
  99 #define FLEXCAN_ESR_CRC_ERR             BIT(12)
 100 #define FLEXCAN_ESR_FRM_ERR             BIT(11)
 101 #define FLEXCAN_ESR_STF_ERR             BIT(10)
 102 #define FLEXCAN_ESR_TX_WRN              BIT(9)
 103 #define FLEXCAN_ESR_RX_WRN              BIT(8)
 104 #define FLEXCAN_ESR_IDLE                BIT(7)
 105 #define FLEXCAN_ESR_TXRX                BIT(6)
 106 #define FLEXCAN_EST_FLT_CONF_SHIFT      (4)
 107 #define FLEXCAN_ESR_FLT_CONF_MASK       (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
 108 #define FLEXCAN_ESR_FLT_CONF_ACTIVE     (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
 109 #define FLEXCAN_ESR_FLT_CONF_PASSIVE    (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
 110 #define FLEXCAN_ESR_BOFF_INT            BIT(2)
 111 #define FLEXCAN_ESR_ERR_INT             BIT(1)
 112 #define FLEXCAN_ESR_WAK_INT             BIT(0)
 113 #define FLEXCAN_ESR_ERR_BUS \
 114         (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
 115          FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
 116          FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
 117 #define FLEXCAN_ESR_ERR_STATE \
 118         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
 119 #define FLEXCAN_ESR_ERR_ALL \
 120         (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
 121 #define FLEXCAN_ESR_ALL_INT \
 122         (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
 123          FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
 124
 125 /* FLEXCAN interrupt flag register (IFLAG) bits */
 126 #define FLEXCAN_TX_BUF_ID               8
 127 #define FLEXCAN_IFLAG_BUF(x)            BIT(x)
 128 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW  BIT(7)
 129 #define FLEXCAN_IFLAG_RX_FIFO_WARN      BIT(6)
 130 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
 131 #define FLEXCAN_IFLAG_DEFAULT \
 132         (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
 133          FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
 134
 135 /* FLEXCAN message buffers */
 136 #define FLEXCAN_MB_CNT_CODE(x)          (((x) & 0xf) << 24)
 137 #define FLEXCAN_MB_CNT_SRR              BIT(22)
 138 #define FLEXCAN_MB_CNT_IDE              BIT(21)
 139 #define FLEXCAN_MB_CNT_RTR              BIT(20)
 140 #define FLEXCAN_MB_CNT_LENGTH(x)        (((x) & 0xf) << 16)
 141 #define FLEXCAN_MB_CNT_TIMESTAMP(x)     ((x) & 0xffff)
 142
 143 #define FLEXCAN_MB_CODE_MASK            (0xf0ffffff)
 144
 145 /* Structure of the message buffer */
 146 struct flexcan_mb {
 147         u32 can_ctrl;
 148         u32 can_id;
 149         u32 data[2];
 150 };
 151
 152 /* Structure of the hardware registers */
 153 struct flexcan_regs {
 154         u32 mcr;                /* 0x00 */
 155         u32 ctrl;               /* 0x04 */
 156         u32 timer;              /* 0x08 */
 157         u32 _reserved1;         /* 0x0c */
 158         u32 rxgmask;            /* 0x10 */
 159         u32 rx14mask;           /* 0x14 */
 160         u32 rx15mask;           /* 0x18 */
 161         u32 ecr;                /* 0x1c */
 162         u32 esr;                /* 0x20 */
 163         u32 imask2;             /* 0x24 */
 164         u32 imask1;             /* 0x28 */
 165         u32 iflag2;             /* 0x2c */
 166         u32 iflag1;             /* 0x30 */
 167         u32 _reserved2[19];
 168         struct flexcan_mb cantxfg[64];
 169 };
 170
 171 struct flexcan_priv {
 172         struct can_priv can;
 173         struct net_device *dev;
 174         struct napi_struct napi;
 175
 176         void __iomem *base;
 177         u32 reg_esr;
 178         u32 reg_ctrl_default;
 179
 180         struct clk *clk;
 181         struct flexcan_platform_data *pdata;
 182 };
 183
 184 static struct can_bittiming_const flexcan_bittiming_const = {
 185         .name = DRV_NAME,
 186         .tseg1_min = 4,
 187         .tseg1_max = 16,
 188         .tseg2_min = 2,
 189         .tseg2_max = 8,
 190         .sjw_max = 4,
 191         .brp_min = 1,
 192         .brp_max = 256,
 193         .brp_inc = 1,
 194 };
 195
 196 /*
 197  * Abstract off the read/write for arm versus ppc.
 198  */
 199 #if defined(__BIG_ENDIAN)
 200 static inline u32 flexcan_read(void __iomem *addr)
 201 {
 202         return in_be32(addr);
 203 }
 204
 205 static inline void flexcan_write(u32 val, void __iomem *addr)
 206 {
 207         out_be32(addr, val);
 208 }
 209 #else
 210 static inline u32 flexcan_read(void __iomem *addr)
 211 {
 212         return readl(addr);
 213 }
 214
 215 static inline void flexcan_write(u32 val, void __iomem *addr)
 216 {
 217         writel(val, addr);
 218 }
 219 #endif
 220
 221 /*
 222  * Swtich transceiver on or off
 223  */
 224 static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
 225 {
 226         if (priv->pdata && priv->pdata->transceiver_switch)
 227                 priv->pdata->transceiver_switch(on);
 228 }
 229
 230 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
 231                                               u32 reg_esr)
 232 {
 233         return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
 234                 (reg_esr & FLEXCAN_ESR_ERR_BUS);
 235 }
 236
 237 static inline void flexcan_chip_enable(struct flexcan_priv *priv)
 238 {
 239         struct flexcan_regs __iomem *regs = priv->base;
 240         u32 reg;
 241
 242         reg = flexcan_read(&regs->mcr);
 243         reg &= ~FLEXCAN_MCR_MDIS;
 244         flexcan_write(reg, &regs->mcr);
 245
 246         udelay(10);
 247 }
 248
 249 static inline void flexcan_chip_disable(struct flexcan_priv *priv)
 250 {
 251         struct flexcan_regs __iomem *regs = priv->base;
 252         u32 reg;
 253
 254         reg = flexcan_read(&regs->mcr);
 255         reg |= FLEXCAN_MCR_MDIS;
 256         flexcan_write(reg, &regs->mcr);
 257 }
 258
 259 static int flexcan_get_berr_counter(const struct net_device *dev,
 260                                     struct can_berr_counter *bec)
 261 {
 262         const struct flexcan_priv *priv = netdev_priv(dev);
 263         struct flexcan_regs __iomem *regs = priv->base;
 264         u32 reg = flexcan_read(&regs->ecr);
 265
 266         bec->txerr = (reg >> 0) & 0xff;
 267         bec->rxerr = (reg >> 8) & 0xff;
 268
 269         return 0;
 270 }
 271
 272 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 273 {
 274         const struct flexcan_priv *priv = netdev_priv(dev);
 275         struct net_device_stats *stats = &dev->stats;
 276         struct flexcan_regs __iomem *regs = priv->base;
 277         struct can_frame *cf = (struct can_frame *)skb->data;
 278         u32 can_id;
 279         u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
 280
 281         if (can_dropped_invalid_skb(dev, skb))
 282                 return NETDEV_TX_OK;
 283
 284         netif_stop_queue(dev);
 285
 286         if (cf->can_id & CAN_EFF_FLAG) {
 287                 can_id = cf->can_id & CAN_EFF_MASK;
 288                 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
 289         } else {
 290                 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
 291         }
 292
 293         if (cf->can_id & CAN_RTR_FLAG)
 294                 ctrl |= FLEXCAN_MB_CNT_RTR;
 295
 296         if (cf->can_dlc > 0) {
 297                 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
 298                 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
 299         }
 300         if (cf->can_dlc > 3) {
 301                 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
 302                 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
 303         }
 304
 305         flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
 306         flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
 307
 308         kfree_skb(skb);
 309
 310         /* tx_packets is incremented in flexcan_irq */
 311         stats->tx_bytes += cf->can_dlc;
 312
 313         return NETDEV_TX_OK;
 314 }
 315
 316 static void do_bus_err(struct net_device *dev,
 317                        struct can_frame *cf, u32 reg_esr)
 318 {
 319         struct flexcan_priv *priv = netdev_priv(dev);
 320         int rx_errors = 0, tx_errors = 0;
 321
 322         cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 323
 324         if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
 325                 dev_dbg(dev->dev.parent, "BIT1_ERR irq\n");
 326                 cf->data[2] |= CAN_ERR_PROT_BIT1;
 327                 tx_errors = 1;
 328         }
 329         if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
 330                 dev_dbg(dev->dev.parent, "BIT0_ERR irq\n");
 331                 cf->data[2] |= CAN_ERR_PROT_BIT0;
 332                 tx_errors = 1;
 333         }
 334         if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
 335                 dev_dbg(dev->dev.parent, "ACK_ERR irq\n");
 336                 cf->can_id |= CAN_ERR_ACK;
 337                 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
 338                 tx_errors = 1;
 339         }
 340         if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
 341                 dev_dbg(dev->dev.parent, "CRC_ERR irq\n");
 342                 cf->data[2] |= CAN_ERR_PROT_BIT;
 343                 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
 344                 rx_errors = 1;
 345         }
 346         if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
 347                 dev_dbg(dev->dev.parent, "FRM_ERR irq\n");
 348                 cf->data[2] |= CAN_ERR_PROT_FORM;
 349                 rx_errors = 1;
 350         }
 351         if (reg_esr & FLEXCAN_ESR_STF_ERR) {
 352                 dev_dbg(dev->dev.parent, "STF_ERR irq\n");
 353                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 354                 rx_errors = 1;
 355         }
 356
 357         priv->can.can_stats.bus_error++;
 358         if (rx_errors)
 359                 dev->stats.rx_errors++;
 360         if (tx_errors)
 361                 dev->stats.tx_errors++;
 362 }
 363
 364 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
 365 {
 366         struct sk_buff *skb;
 367         struct can_frame *cf;
 368
 369         skb = alloc_can_err_skb(dev, &cf);
 370         if (unlikely(!skb))
 371                 return 0;
 372
 373         do_bus_err(dev, cf, reg_esr);
 374         netif_receive_skb(skb);
 375
 376         dev->stats.rx_packets++;
 377         dev->stats.rx_bytes += cf->can_dlc;
 378
 379         return 1;
 380 }
 381
 382 static void do_state(struct net_device *dev,
 383                      struct can_frame *cf, enum can_state new_state)
 384 {
 385         struct flexcan_priv *priv = netdev_priv(dev);
 386         struct can_berr_counter bec;
 387
 388         flexcan_get_berr_counter(dev, &bec);
 389
 390         switch (priv->can.state) {
 391         case CAN_STATE_ERROR_ACTIVE:
 392                 /*
 393                  * from: ERROR_ACTIVE
 394                  * to  : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
 395                  * =>  : there was a warning int
 396                  */
 397                 if (new_state >= CAN_STATE_ERROR_WARNING &&
 398                     new_state <= CAN_STATE_BUS_OFF) {
 399                         dev_dbg(dev->dev.parent, "Error Warning IRQ\n");
 400                         priv->can.can_stats.error_warning++;
 401
 402                         cf->can_id |= CAN_ERR_CRTL;
 403                         cf->data[1] = (bec.txerr > bec.rxerr) ?
 404                                 CAN_ERR_CRTL_TX_WARNING :
 405                                 CAN_ERR_CRTL_RX_WARNING;
 406                 }
 407         case CAN_STATE_ERROR_WARNING:   /* fallthrough */
 408                 /*
 409                  * from: ERROR_ACTIVE, ERROR_WARNING
 410                  * to  : ERROR_PASSIVE, BUS_OFF
 411                  * =>  : error passive int
 412                  */
 413                 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
 414                     new_state <= CAN_STATE_BUS_OFF) {
 415                         dev_dbg(dev->dev.parent, "Error Passive IRQ\n");
 416                         priv->can.can_stats.error_passive++;
 417
 418                         cf->can_id |= CAN_ERR_CRTL;
 419                         cf->data[1] = (bec.txerr > bec.rxerr) ?
 420                                 CAN_ERR_CRTL_TX_PASSIVE :
 421                                 CAN_ERR_CRTL_RX_PASSIVE;
 422                 }
 423                 break;
 424         case CAN_STATE_BUS_OFF:
 425                 dev_err(dev->dev.parent,
 426                         "BUG! hardware recovered automatically from BUS_OFF\n");
 427                 break;
 428         default:
 429                 break;
 430         }
 431
 432         /* process state changes depending on the new state */
 433         switch (new_state) {
 434         case CAN_STATE_ERROR_ACTIVE:
 435                 dev_dbg(dev->dev.parent, "Error Active\n");
 436                 cf->can_id |= CAN_ERR_PROT;
 437                 cf->data[2] = CAN_ERR_PROT_ACTIVE;
 438                 break;
 439         case CAN_STATE_BUS_OFF:
 440                 cf->can_id |= CAN_ERR_BUSOFF;
 441                 can_bus_off(dev);
 442                 break;
 443         default:
 444                 break;
 445         }
 446 }
 447
 448 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
 449 {
 450         struct flexcan_priv *priv = netdev_priv(dev);
 451         struct sk_buff *skb;
 452         struct can_frame *cf;
 453         enum can_state new_state;
 454         int flt;
 455
 456         flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
 457         if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
 458                 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
 459                                         FLEXCAN_ESR_RX_WRN))))
 460                         new_state = CAN_STATE_ERROR_ACTIVE;
 461                 else
 462                         new_state = CAN_STATE_ERROR_WARNING;
 463         } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
 464                 new_state = CAN_STATE_ERROR_PASSIVE;
 465         else
 466                 new_state = CAN_STATE_BUS_OFF;
 467
 468         /* state hasn't changed */
 469         if (likely(new_state == priv->can.state))
 470                 return 0;
 471
 472         skb = alloc_can_err_skb(dev, &cf);
 473         if (unlikely(!skb))
 474                 return 0;
 475
 476         do_state(dev, cf, new_state);
 477         priv->can.state = new_state;
 478         netif_receive_skb(skb);
 479
 480         dev->stats.rx_packets++;
 481         dev->stats.rx_bytes += cf->can_dlc;
 482
 483         return 1;
 484 }
 485
 486 static void flexcan_read_fifo(const struct net_device *dev,
 487                               struct can_frame *cf)
 488 {
 489         const struct flexcan_priv *priv = netdev_priv(dev);
 490         struct flexcan_regs __iomem *regs = priv->base;
 491         struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
 492         u32 reg_ctrl, reg_id;
 493
 494         reg_ctrl = flexcan_read(&mb->can_ctrl);
 495         reg_id = flexcan_read(&mb->can_id);
 496         if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
 497                 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
 498         else
 499                 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
 500
 501         if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
 502                 cf->can_id |= CAN_RTR_FLAG;
 503         cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
 504
 505         *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
 506         *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
 507
 508         /* mark as read */
 509         flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
 510         flexcan_read(&regs->timer);
 511 }
 512
 513 static int flexcan_read_frame(struct net_device *dev)
 514 {
 515         struct net_device_stats *stats = &dev->stats;
 516         struct can_frame *cf;
 517         struct sk_buff *skb;
 518
 519         skb = alloc_can_skb(dev, &cf);
 520         if (unlikely(!skb)) {
 521                 stats->rx_dropped++;
 522                 return 0;
 523         }
 524
 525         flexcan_read_fifo(dev, cf);
 526         netif_receive_skb(skb);
 527
 528         stats->rx_packets++;
 529         stats->rx_bytes += cf->can_dlc;
 530
 531         return 1;
 532 }
 533
 534 static int flexcan_poll(struct napi_struct *napi, int quota)
 535 {
 536         struct net_device *dev = napi->dev;
 537         const struct flexcan_priv *priv = netdev_priv(dev);
 538         struct flexcan_regs __iomem *regs = priv->base;
 539         u32 reg_iflag1, reg_esr;
 540         int work_done = 0;
 541
 542         /*
 543          * The error bits are cleared on read,
 544          * use saved value from irq handler.
 545          */
 546         reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
 547
 548         /* handle state changes */
 549         work_done += flexcan_poll_state(dev, reg_esr);
 550
 551         /* handle RX-FIFO */
 552         reg_iflag1 = flexcan_read(&regs->iflag1);
 553         while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
 554                work_done < quota) {
 555                 work_done += flexcan_read_frame(dev);
 556                 reg_iflag1 = flexcan_read(&regs->iflag1);
 557         }
 558
 559         /* report bus errors */
 560         if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
 561                 work_done += flexcan_poll_bus_err(dev, reg_esr);
 562
 563         if (work_done < quota) {
 564                 napi_complete(napi);
 565                 /* enable IRQs */
 566                 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 567                 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
 568         }
 569
 570         return work_done;
 571 }
 572
 573 static irqreturn_t flexcan_irq(int irq, void *dev_id)
 574 {
 575         struct net_device *dev = dev_id;
 576         struct net_device_stats *stats = &dev->stats;
 577         struct flexcan_priv *priv = netdev_priv(dev);
 578         struct flexcan_regs __iomem *regs = priv->base;
 579         u32 reg_iflag1, reg_esr;
 580
 581         reg_iflag1 = flexcan_read(&regs->iflag1);
 582         reg_esr = flexcan_read(&regs->esr);
 583         /* ACK all bus error and state change IRQ sources */
 584         if (reg_esr & FLEXCAN_ESR_ALL_INT)
 585                 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
 586
 587         /*
 588          * schedule NAPI in case of:
 589          * - rx IRQ
 590          * - state change IRQ
 591          * - bus error IRQ and bus error reporting is activated
 592          */
 593         if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
 594             (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
 595             flexcan_has_and_handle_berr(priv, reg_esr)) {
 596                 /*
 597                  * The error bits are cleared on read,
 598                  * save them for later use.
 599                  */
 600                 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
 601                 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
 602                         ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
 603                 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
 604                        &regs->ctrl);
 605                 napi_schedule(&priv->napi);
 606         }
 607
 608         /* FIFO overflow */
 609         if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
 610                 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
 611                 dev->stats.rx_over_errors++;
 612                 dev->stats.rx_errors++;
 613         }
 614
 615         /* transmission complete interrupt */
 616         if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
 617                 /* tx_bytes is incremented in flexcan_start_xmit */
 618                 stats->tx_packets++;
 619                 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
 620                 netif_wake_queue(dev);
 621         }
 622
 623         return IRQ_HANDLED;
 624 }
 625
 626 static void flexcan_set_bittiming(struct net_device *dev)
 627 {
 628         const struct flexcan_priv *priv = netdev_priv(dev);
 629         const struct can_bittiming *bt = &priv->can.bittiming;
 630         struct flexcan_regs __iomem *regs = priv->base;
 631         u32 reg;
 632
 633         reg = flexcan_read(&regs->ctrl);
 634         reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
 635                  FLEXCAN_CTRL_RJW(0x3) |
 636                  FLEXCAN_CTRL_PSEG1(0x7) |
 637                  FLEXCAN_CTRL_PSEG2(0x7) |
 638                  FLEXCAN_CTRL_PROPSEG(0x7) |
 639                  FLEXCAN_CTRL_LPB |
 640                  FLEXCAN_CTRL_SMP |
 641                  FLEXCAN_CTRL_LOM);
 642
 643         reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
 644                 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
 645                 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
 646                 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
 647                 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
 648
 649         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 650                 reg |= FLEXCAN_CTRL_LPB;
 651         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 652                 reg |= FLEXCAN_CTRL_LOM;
 653         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
 654                 reg |= FLEXCAN_CTRL_SMP;
 655
 656         dev_info(dev->dev.parent, "writing ctrl=0x%08x\n", reg);
 657         flexcan_write(reg, &regs->ctrl);
 658
 659         /* print chip status */
 660         dev_dbg(dev->dev.parent, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
 661                 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
 662 }
 663
 664 /*
 665  * flexcan_chip_start
 666  *
 667  * this functions is entered with clocks enabled
 668  *
 669  */
 670 static int flexcan_chip_start(struct net_device *dev)
 671 {
 672         struct flexcan_priv *priv = netdev_priv(dev);
 673         struct flexcan_regs __iomem *regs = priv->base;
 674         unsigned int i;
 675         int err;
 676         u32 reg_mcr, reg_ctrl;
 677
 678         /* enable module */
 679         flexcan_chip_enable(priv);
 680
 681         /* soft reset */
 682         flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
 683         udelay(10);
 684
 685         reg_mcr = flexcan_read(&regs->mcr);
 686         if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
 687                 dev_err(dev->dev.parent,
 688                         "Failed to softreset can module (mcr=0x%08x)\n",
 689                         reg_mcr);
 690                 err = -ENODEV;
 691                 goto out;
 692         }
 693
 694         flexcan_set_bittiming(dev);
 695
 696         /*
 697          * MCR
 698          *
 699          * enable freeze
 700          * enable fifo
 701          * halt now
 702          * only supervisor access
 703          * enable warning int
 704          * choose format C
 705          *
 706          */
 707         reg_mcr = flexcan_read(&regs->mcr);
 708         reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
 709                 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
 710                 FLEXCAN_MCR_IDAM_C;
 711         dev_dbg(dev->dev.parent, "%s: writing mcr=0x%08x", __func__, reg_mcr);
 712         flexcan_write(reg_mcr, &regs->mcr);
 713
 714         /*
 715          * CTRL
 716          *
 717          * disable timer sync feature
 718          *
 719          * disable auto busoff recovery
 720          * transmit lowest buffer first
 721          *
 722          * enable tx and rx warning interrupt
 723          * enable bus off interrupt
 724          * (== FLEXCAN_CTRL_ERR_STATE)
 725          *
 726          * _note_: we enable the "error interrupt"
 727          * (FLEXCAN_CTRL_ERR_MSK), too. Otherwise we don't get any
 728          * warning or bus passive interrupts.
 729          */
 730         reg_ctrl = flexcan_read(&regs->ctrl);
 731         reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
 732         reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
 733                 FLEXCAN_CTRL_ERR_STATE | FLEXCAN_CTRL_ERR_MSK;
 734
 735         /* save for later use */
 736         priv->reg_ctrl_default = reg_ctrl;
 737         dev_dbg(dev->dev.parent, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
 738         flexcan_write(reg_ctrl, &regs->ctrl);
 739
 740         for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
 741                 flexcan_write(0, &regs->cantxfg[i].can_ctrl);
 742                 flexcan_write(0, &regs->cantxfg[i].can_id);
 743                 flexcan_write(0, &regs->cantxfg[i].data[0]);
 744                 flexcan_write(0, &regs->cantxfg[i].data[1]);
 745
 746                 /* put MB into rx queue */
 747                 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
 748                         &regs->cantxfg[i].can_ctrl);
 749         }
 750
 751         /* acceptance mask/acceptance code (accept everything) */
 752         flexcan_write(0x0, &regs->rxgmask);
 753         flexcan_write(0x0, &regs->rx14mask);
 754         flexcan_write(0x0, &regs->rx15mask);
 755
 756         flexcan_transceiver_switch(priv, 1);
 757
 758         /* synchronize with the can bus */
 759         reg_mcr = flexcan_read(&regs->mcr);
 760         reg_mcr &= ~FLEXCAN_MCR_HALT;
 761         flexcan_write(reg_mcr, &regs->mcr);
 762
 763         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 764
 765         /* enable FIFO interrupts */
 766         flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
 767
 768         /* print chip status */
 769         dev_dbg(dev->dev.parent, "%s: reading mcr=0x%08x ctrl=0x%08x\n",
 770                 __func__, flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
 771
 772         return 0;
 773
 774  out:
 775         flexcan_chip_disable(priv);
 776         return err;
 777 }
 778
 779 /*
 780  * flexcan_chip_stop
 781  *
 782  * this functions is entered with clocks enabled
 783  *
 784  */
 785 static void flexcan_chip_stop(struct net_device *dev)
 786 {
 787         struct flexcan_priv *priv = netdev_priv(dev);
 788         struct flexcan_regs __iomem *regs = priv->base;
 789         u32 reg;
 790
 791         /* Disable all interrupts */
 792         flexcan_write(0, &regs->imask1);
 793
 794         /* Disable + halt module */
 795         reg = flexcan_read(&regs->mcr);
 796         reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
 797         flexcan_write(reg, &regs->mcr);
 798
 799         flexcan_transceiver_switch(priv, 0);
 800         priv->can.state = CAN_STATE_STOPPED;
 801
 802         return;
 803 }
 804
 805 static int flexcan_open(struct net_device *dev)
 806 {
 807         struct flexcan_priv *priv = netdev_priv(dev);
 808         int err;
 809
 810         clk_prepare_enable(priv->clk);
 811
 812         err = open_candev(dev);
 813         if (err)
 814                 goto out;
 815
 816         err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
 817         if (err)
 818                 goto out_close;
 819
 820         /* start chip and queuing */
 821         err = flexcan_chip_start(dev);
 822         if (err)
 823                 goto out_close;
 824         napi_enable(&priv->napi);
 825         netif_start_queue(dev);
 826
 827         return 0;
 828
 829  out_close:
 830         close_candev(dev);
 831  out:
 832         clk_disable_unprepare(priv->clk);
 833
 834         return err;
 835 }
 836
 837 static int flexcan_close(struct net_device *dev)
 838 {
 839         struct flexcan_priv *priv = netdev_priv(dev);
 840
 841         netif_stop_queue(dev);
 842         napi_disable(&priv->napi);
 843         flexcan_chip_stop(dev);
 844
 845         free_irq(dev->irq, dev);
 846         clk_disable_unprepare(priv->clk);
 847
 848         close_candev(dev);
 849
 850         return 0;
 851 }
 852
 853 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
 854 {
 855         int err;
 856
 857         switch (mode) {
 858         case CAN_MODE_START:
 859                 err = flexcan_chip_start(dev);
 860                 if (err)
 861                         return err;
 862
 863                 netif_wake_queue(dev);
 864                 break;
 865
 866         default:
 867                 return -EOPNOTSUPP;
 868         }
 869
 870         return 0;
 871 }
 872
 873 static const struct net_device_ops flexcan_netdev_ops = {
 874         .ndo_open       = flexcan_open,
 875         .ndo_stop       = flexcan_close,
 876         .ndo_start_xmit = flexcan_start_xmit,
 877 };
 878
 879 static int __devinit register_flexcandev(struct net_device *dev)
 880 {
 881         struct flexcan_priv *priv = netdev_priv(dev);
 882         struct flexcan_regs __iomem *regs = priv->base;
 883         u32 reg, err;
 884
 885         clk_prepare_enable(priv->clk);
 886
 887         /* select "bus clock", chip must be disabled */
 888         flexcan_chip_disable(priv);
 889         reg = flexcan_read(&regs->ctrl);
 890         reg |= FLEXCAN_CTRL_CLK_SRC;
 891         flexcan_write(reg, &regs->ctrl);
 892
 893         flexcan_chip_enable(priv);
 894
 895         /* set freeze, halt and activate FIFO, restrict register access */
 896         reg = flexcan_read(&regs->mcr);
 897         reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
 898                 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
 899         flexcan_write(reg, &regs->mcr);
 900
 901         /*
 902          * Currently we only support newer versions of this core
 903          * featuring a RX FIFO. Older cores found on some Coldfire
 904          * derivates are not yet supported.
 905          */
 906         reg = flexcan_read(&regs->mcr);
 907         if (!(reg & FLEXCAN_MCR_FEN)) {
 908                 dev_err(dev->dev.parent,
 909                         "Could not enable RX FIFO, unsupported core\n");
 910                 err = -ENODEV;
 911                 goto out;
 912         }
 913
 914         err = register_candev(dev);
 915
 916  out:
 917         /* disable core and turn off clocks */
 918         flexcan_chip_disable(priv);
 919         clk_disable_unprepare(priv->clk);
 920
 921         return err;
 922 }
 923
 924 static void __devexit unregister_flexcandev(struct net_device *dev)
 925 {
 926         unregister_candev(dev);
 927 }
 928
 929 static int __devinit flexcan_probe(struct platform_device *pdev)
 930 {
 931         struct net_device *dev;
 932         struct flexcan_priv *priv;
 933         struct resource *mem;
 934         struct clk *clk = NULL;
 935         void __iomem *base;
 936         resource_size_t mem_size;
 937         int err, irq;
 938         u32 clock_freq = 0;
 939
 940         if (pdev->dev.of_node) {
 941                 const u32 *clock_freq_p;
 942
 943                 clock_freq_p = of_get_property(pdev->dev.of_node,
 944                                                 "clock-frequency", NULL);
 945                 if (clock_freq_p)
 946                         clock_freq = *clock_freq_p;
 947         }
 948
 949         if (!clock_freq) {
 950                 clk = clk_get(&pdev->dev, NULL);
 951                 if (IS_ERR(clk)) {
 952                         dev_err(&pdev->dev, "no clock defined\n");
 953                         err = PTR_ERR(clk);
 954                         goto failed_clock;
 955                 }
 956                 clock_freq = clk_get_rate(clk);
 957         }
 958
 959         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 960         irq = platform_get_irq(pdev, 0);
 961         if (!mem || irq <= 0) {
 962                 err = -ENODEV;
 963                 goto failed_get;
 964         }
 965
 966         mem_size = resource_size(mem);
 967         if (!request_mem_region(mem->start, mem_size, pdev->name)) {
 968                 err = -EBUSY;
 969                 goto failed_get;
 970         }
 971
 972         base = ioremap(mem->start, mem_size);
 973         if (!base) {
 974                 err = -ENOMEM;
 975                 goto failed_map;
 976         }
 977
 978         dev = alloc_candev(sizeof(struct flexcan_priv), 0);
 979         if (!dev) {
 980                 err = -ENOMEM;
 981                 goto failed_alloc;
 982         }
 983
 984         dev->netdev_ops = &flexcan_netdev_ops;
 985         dev->irq = irq;
 986         dev->flags |= IFF_ECHO; /* we support local echo in hardware */
 987
 988         priv = netdev_priv(dev);
 989         priv->can.clock.freq = clock_freq;
 990         priv->can.bittiming_const = &flexcan_bittiming_const;
 991         priv->can.do_set_mode = flexcan_set_mode;
 992         priv->can.do_get_berr_counter = flexcan_get_berr_counter;
 993         priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
 994                 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
 995                 CAN_CTRLMODE_BERR_REPORTING;
 996         priv->base = base;
 997         priv->dev = dev;
 998         priv->clk = clk;
 999         priv->pdata = pdev->dev.platform_data;
1000
1001         netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1002
1003         dev_set_drvdata(&pdev->dev, dev);
1004         SET_NETDEV_DEV(dev, &pdev->dev);
1005
1006         err = register_flexcandev(dev);
1007         if (err) {
1008                 dev_err(&pdev->dev, "registering netdev failed\n");
1009                 goto failed_register;
1010         }
1011
1012         dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1013                  priv->base, dev->irq);
1014
1015         return 0;
1016
1017  failed_register:
1018         free_candev(dev);
1019  failed_alloc:
1020         iounmap(base);
1021  failed_map:
1022         release_mem_region(mem->start, mem_size);
1023  failed_get:
1024         if (clk)
1025                 clk_put(clk);
1026  failed_clock:
1027         return err;
1028 }
1029
1030 static int __devexit flexcan_remove(struct platform_device *pdev)
1031 {
1032         struct net_device *dev = platform_get_drvdata(pdev);
1033         struct flexcan_priv *priv = netdev_priv(dev);
1034         struct resource *mem;
1035
1036         unregister_flexcandev(dev);
1037         platform_set_drvdata(pdev, NULL);
1038         iounmap(priv->base);
1039
1040         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1041         release_mem_region(mem->start, resource_size(mem));
1042
1043         if (priv->clk)
1044                 clk_put(priv->clk);
1045
1046         free_candev(dev);
1047
1048         return 0;
1049 }
1050
1051 static struct of_device_id flexcan_of_match[] = {
1052         {
1053                 .compatible = "fsl,p1010-flexcan",
1054         },
1055         {},
1056 };
1057
1058 static struct platform_driver flexcan_driver = {
1059         .driver = {
1060                 .name = DRV_NAME,
1061                 .owner = THIS_MODULE,
1062                 .of_match_table = flexcan_of_match,
1063         },
1064         .probe = flexcan_probe,
1065         .remove = __devexit_p(flexcan_remove),
1066 };
1067
1068 module_platform_driver(flexcan_driver);
1069
1070 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1071               "Marc Kleine-Budde <kernel@pengutronix.de>");
1072 MODULE_LICENSE("GPL v2");
1073 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");