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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6/libata-dev.git] / drivers / net / can / flexcan.c
blob769d29ed106dbb1336745510b7fa2ff60f387bf7
1 /*
2 * flexcan.c - FLEXCAN CAN controller driver
3 *
4 * Copyright (c) 2005-2006 Varma Electronics Oy
5 * Copyright (c) 2009 Sascha Hauer, Pengutronix
6 * Copyright (c) 2010 Marc Kleine-Budde, Pengutronix
7 *
8 * Based on code originally by Andrey Volkov <avolkov@varma-el.com>
9 *
10 * LICENCE:
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 */
21
22 #include <linux/netdevice.h>
23 #include <linux/can.h>
24 #include <linux/can/dev.h>
25 #include <linux/can/error.h>
26 #include <linux/can/led.h>
27 #include <linux/can/platform/flexcan.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/if_arp.h>
31 #include <linux/if_ether.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/kernel.h>
35 #include <linux/list.h>
36 #include <linux/module.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/platform_device.h>
40 #include <linux/pinctrl/consumer.h>
41
42 #define DRV_NAME "flexcan"
43
44 /* 8 for RX fifo and 2 error handling */
45 #define FLEXCAN_NAPI_WEIGHT (8 + 2)
46
47 /* FLEXCAN module configuration register (CANMCR) bits */
48 #define FLEXCAN_MCR_MDIS BIT(31)
49 #define FLEXCAN_MCR_FRZ BIT(30)
50 #define FLEXCAN_MCR_FEN BIT(29)
51 #define FLEXCAN_MCR_HALT BIT(28)
52 #define FLEXCAN_MCR_NOT_RDY BIT(27)
53 #define FLEXCAN_MCR_WAK_MSK BIT(26)
54 #define FLEXCAN_MCR_SOFTRST BIT(25)
55 #define FLEXCAN_MCR_FRZ_ACK BIT(24)
56 #define FLEXCAN_MCR_SUPV BIT(23)
57 #define FLEXCAN_MCR_SLF_WAK BIT(22)
58 #define FLEXCAN_MCR_WRN_EN BIT(21)
59 #define FLEXCAN_MCR_LPM_ACK BIT(20)
60 #define FLEXCAN_MCR_WAK_SRC BIT(19)
61 #define FLEXCAN_MCR_DOZE BIT(18)
62 #define FLEXCAN_MCR_SRX_DIS BIT(17)
63 #define FLEXCAN_MCR_BCC BIT(16)
64 #define FLEXCAN_MCR_LPRIO_EN BIT(13)
65 #define FLEXCAN_MCR_AEN BIT(12)
66 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf)
67 #define FLEXCAN_MCR_IDAM_A (0 << 8)
68 #define FLEXCAN_MCR_IDAM_B (1 << 8)
69 #define FLEXCAN_MCR_IDAM_C (2 << 8)
70 #define FLEXCAN_MCR_IDAM_D (3 << 8)
71
72 /* FLEXCAN control register (CANCTRL) bits */
73 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
74 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
75 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
76 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
77 #define FLEXCAN_CTRL_BOFF_MSK BIT(15)
78 #define FLEXCAN_CTRL_ERR_MSK BIT(14)
79 #define FLEXCAN_CTRL_CLK_SRC BIT(13)
80 #define FLEXCAN_CTRL_LPB BIT(12)
81 #define FLEXCAN_CTRL_TWRN_MSK BIT(11)
82 #define FLEXCAN_CTRL_RWRN_MSK BIT(10)
83 #define FLEXCAN_CTRL_SMP BIT(7)
84 #define FLEXCAN_CTRL_BOFF_REC BIT(6)
85 #define FLEXCAN_CTRL_TSYN BIT(5)
86 #define FLEXCAN_CTRL_LBUF BIT(4)
87 #define FLEXCAN_CTRL_LOM BIT(3)
88 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
89 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK)
90 #define FLEXCAN_CTRL_ERR_STATE \
91 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \
92 FLEXCAN_CTRL_BOFF_MSK)
93 #define FLEXCAN_CTRL_ERR_ALL \
94 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
95
96 /* FLEXCAN error and status register (ESR) bits */
97 #define FLEXCAN_ESR_TWRN_INT BIT(17)
98 #define FLEXCAN_ESR_RWRN_INT BIT(16)
99 #define FLEXCAN_ESR_BIT1_ERR BIT(15)
100 #define FLEXCAN_ESR_BIT0_ERR BIT(14)
101 #define FLEXCAN_ESR_ACK_ERR BIT(13)
102 #define FLEXCAN_ESR_CRC_ERR BIT(12)
103 #define FLEXCAN_ESR_FRM_ERR BIT(11)
104 #define FLEXCAN_ESR_STF_ERR BIT(10)
105 #define FLEXCAN_ESR_TX_WRN BIT(9)
106 #define FLEXCAN_ESR_RX_WRN BIT(8)
107 #define FLEXCAN_ESR_IDLE BIT(7)
108 #define FLEXCAN_ESR_TXRX BIT(6)
109 #define FLEXCAN_EST_FLT_CONF_SHIFT (4)
110 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
111 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
112 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
113 #define FLEXCAN_ESR_BOFF_INT BIT(2)
114 #define FLEXCAN_ESR_ERR_INT BIT(1)
115 #define FLEXCAN_ESR_WAK_INT BIT(0)
116 #define FLEXCAN_ESR_ERR_BUS \
117 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \
118 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \
119 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR)
120 #define FLEXCAN_ESR_ERR_STATE \
121 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT)
122 #define FLEXCAN_ESR_ERR_ALL \
123 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE)
124 #define FLEXCAN_ESR_ALL_INT \
125 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \
126 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
127
128 /* FLEXCAN interrupt flag register (IFLAG) bits */
129 #define FLEXCAN_TX_BUF_ID 8
130 #define FLEXCAN_IFLAG_BUF(x) BIT(x)
131 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
132 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
133 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5)
134 #define FLEXCAN_IFLAG_DEFAULT \
135 (FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | FLEXCAN_IFLAG_RX_FIFO_AVAILABLE | \
136 FLEXCAN_IFLAG_BUF(FLEXCAN_TX_BUF_ID))
137
138 /* FLEXCAN message buffers */
139 #define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
140 #define FLEXCAN_MB_CNT_SRR BIT(22)
141 #define FLEXCAN_MB_CNT_IDE BIT(21)
142 #define FLEXCAN_MB_CNT_RTR BIT(20)
143 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
144 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
145
146 #define FLEXCAN_MB_CODE_MASK (0xf0ffffff)
147
148 /*
149 * FLEXCAN hardware feature flags
150 *
151 * Below is some version info we got:
152 * SOC Version IP-Version Glitch- [TR]WRN_INT
153 * Filter? connected?
154 * MX25 FlexCAN2 03.00.00.00 no no
155 * MX28 FlexCAN2 03.00.04.00 yes yes
156 * MX35 FlexCAN2 03.00.00.00 no no
157 * MX53 FlexCAN2 03.00.00.00 yes no
158 * MX6s FlexCAN3 10.00.12.00 yes yes
159 *
160 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
161 */
162 #define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
163 #define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
164
165 /* Structure of the message buffer */
166 struct flexcan_mb {
167 u32 can_ctrl;
168 u32 can_id;
169 u32 data[2];
170 };
171
172 /* Structure of the hardware registers */
173 struct flexcan_regs {
174 u32 mcr; /* 0x00 */
175 u32 ctrl; /* 0x04 */
176 u32 timer; /* 0x08 */
177 u32 _reserved1; /* 0x0c */
178 u32 rxgmask; /* 0x10 */
179 u32 rx14mask; /* 0x14 */
180 u32 rx15mask; /* 0x18 */
181 u32 ecr; /* 0x1c */
182 u32 esr; /* 0x20 */
183 u32 imask2; /* 0x24 */
184 u32 imask1; /* 0x28 */
185 u32 iflag2; /* 0x2c */
186 u32 iflag1; /* 0x30 */
187 u32 crl2; /* 0x34 */
188 u32 esr2; /* 0x38 */
189 u32 imeur; /* 0x3c */
190 u32 lrfr; /* 0x40 */
191 u32 crcr; /* 0x44 */
192 u32 rxfgmask; /* 0x48 */
193 u32 rxfir; /* 0x4c */
194 u32 _reserved3[12];
195 struct flexcan_mb cantxfg[64];
196 };
197
198 struct flexcan_devtype_data {
199 u32 features; /* hardware controller features */
200 };
201
202 struct flexcan_priv {
203 struct can_priv can;
204 struct net_device *dev;
205 struct napi_struct napi;
206
207 void __iomem *base;
208 u32 reg_esr;
209 u32 reg_ctrl_default;
210
211 struct clk *clk_ipg;
212 struct clk *clk_per;
213 struct flexcan_platform_data *pdata;
214 const struct flexcan_devtype_data *devtype_data;
215 };
216
217 static struct flexcan_devtype_data fsl_p1010_devtype_data = {
218 .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
219 };
220 static struct flexcan_devtype_data fsl_imx28_devtype_data;
221 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
222 .features = FLEXCAN_HAS_V10_FEATURES,
223 };
224
225 static const struct can_bittiming_const flexcan_bittiming_const = {
226 .name = DRV_NAME,
227 .tseg1_min = 4,
228 .tseg1_max = 16,
229 .tseg2_min = 2,
230 .tseg2_max = 8,
231 .sjw_max = 4,
232 .brp_min = 1,
233 .brp_max = 256,
234 .brp_inc = 1,
235 };
236
237 /*
238 * Abstract off the read/write for arm versus ppc.
239 */
240 #if defined(__BIG_ENDIAN)
241 static inline u32 flexcan_read(void __iomem *addr)
242 {
243 return in_be32(addr);
244 }
245
246 static inline void flexcan_write(u32 val, void __iomem *addr)
247 {
248 out_be32(addr, val);
249 }
250 #else
251 static inline u32 flexcan_read(void __iomem *addr)
252 {
253 return readl(addr);
254 }
255
256 static inline void flexcan_write(u32 val, void __iomem *addr)
257 {
258 writel(val, addr);
259 }
260 #endif
261
262 /*
263 * Swtich transceiver on or off
264 */
265 static void flexcan_transceiver_switch(const struct flexcan_priv *priv, int on)
266 {
267 if (priv->pdata && priv->pdata->transceiver_switch)
268 priv->pdata->transceiver_switch(on);
269 }
270
271 static inline int flexcan_has_and_handle_berr(const struct flexcan_priv *priv,
272 u32 reg_esr)
273 {
274 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
275 (reg_esr & FLEXCAN_ESR_ERR_BUS);
276 }
277
278 static inline void flexcan_chip_enable(struct flexcan_priv *priv)
279 {
280 struct flexcan_regs __iomem *regs = priv->base;
281 u32 reg;
282
283 reg = flexcan_read(&regs->mcr);
284 reg &= ~FLEXCAN_MCR_MDIS;
285 flexcan_write(reg, &regs->mcr);
286
287 udelay(10);
288 }
289
290 static inline void flexcan_chip_disable(struct flexcan_priv *priv)
291 {
292 struct flexcan_regs __iomem *regs = priv->base;
293 u32 reg;
294
295 reg = flexcan_read(&regs->mcr);
296 reg |= FLEXCAN_MCR_MDIS;
297 flexcan_write(reg, &regs->mcr);
298 }
299
300 static int flexcan_get_berr_counter(const struct net_device *dev,
301 struct can_berr_counter *bec)
302 {
303 const struct flexcan_priv *priv = netdev_priv(dev);
304 struct flexcan_regs __iomem *regs = priv->base;
305 u32 reg = flexcan_read(&regs->ecr);
306
307 bec->txerr = (reg >> 0) & 0xff;
308 bec->rxerr = (reg >> 8) & 0xff;
309
310 return 0;
311 }
312
313 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
314 {
315 const struct flexcan_priv *priv = netdev_priv(dev);
316 struct flexcan_regs __iomem *regs = priv->base;
317 struct can_frame *cf = (struct can_frame *)skb->data;
318 u32 can_id;
319 u32 ctrl = FLEXCAN_MB_CNT_CODE(0xc) | (cf->can_dlc << 16);
320
321 if (can_dropped_invalid_skb(dev, skb))
322 return NETDEV_TX_OK;
323
324 netif_stop_queue(dev);
325
326 if (cf->can_id & CAN_EFF_FLAG) {
327 can_id = cf->can_id & CAN_EFF_MASK;
328 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR;
329 } else {
330 can_id = (cf->can_id & CAN_SFF_MASK) << 18;
331 }
332
333 if (cf->can_id & CAN_RTR_FLAG)
334 ctrl |= FLEXCAN_MB_CNT_RTR;
335
336 if (cf->can_dlc > 0) {
337 u32 data = be32_to_cpup((__be32 *)&cf->data[0]);
338 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[0]);
339 }
340 if (cf->can_dlc > 3) {
341 u32 data = be32_to_cpup((__be32 *)&cf->data[4]);
342 flexcan_write(data, &regs->cantxfg[FLEXCAN_TX_BUF_ID].data[1]);
343 }
344
345 can_put_echo_skb(skb, dev, 0);
346
347 flexcan_write(can_id, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
348 flexcan_write(ctrl, &regs->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
349
350 return NETDEV_TX_OK;
351 }
352
353 static void do_bus_err(struct net_device *dev,
354 struct can_frame *cf, u32 reg_esr)
355 {
356 struct flexcan_priv *priv = netdev_priv(dev);
357 int rx_errors = 0, tx_errors = 0;
358
359 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
360
361 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) {
362 netdev_dbg(dev, "BIT1_ERR irq\n");
363 cf->data[2] |= CAN_ERR_PROT_BIT1;
364 tx_errors = 1;
365 }
366 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) {
367 netdev_dbg(dev, "BIT0_ERR irq\n");
368 cf->data[2] |= CAN_ERR_PROT_BIT0;
369 tx_errors = 1;
370 }
371 if (reg_esr & FLEXCAN_ESR_ACK_ERR) {
372 netdev_dbg(dev, "ACK_ERR irq\n");
373 cf->can_id |= CAN_ERR_ACK;
374 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
375 tx_errors = 1;
376 }
377 if (reg_esr & FLEXCAN_ESR_CRC_ERR) {
378 netdev_dbg(dev, "CRC_ERR irq\n");
379 cf->data[2] |= CAN_ERR_PROT_BIT;
380 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
381 rx_errors = 1;
382 }
383 if (reg_esr & FLEXCAN_ESR_FRM_ERR) {
384 netdev_dbg(dev, "FRM_ERR irq\n");
385 cf->data[2] |= CAN_ERR_PROT_FORM;
386 rx_errors = 1;
387 }
388 if (reg_esr & FLEXCAN_ESR_STF_ERR) {
389 netdev_dbg(dev, "STF_ERR irq\n");
390 cf->data[2] |= CAN_ERR_PROT_STUFF;
391 rx_errors = 1;
392 }
393
394 priv->can.can_stats.bus_error++;
395 if (rx_errors)
396 dev->stats.rx_errors++;
397 if (tx_errors)
398 dev->stats.tx_errors++;
399 }
400
401 static int flexcan_poll_bus_err(struct net_device *dev, u32 reg_esr)
402 {
403 struct sk_buff *skb;
404 struct can_frame *cf;
405
406 skb = alloc_can_err_skb(dev, &cf);
407 if (unlikely(!skb))
408 return 0;
409
410 do_bus_err(dev, cf, reg_esr);
411 netif_receive_skb(skb);
412
413 dev->stats.rx_packets++;
414 dev->stats.rx_bytes += cf->can_dlc;
415
416 return 1;
417 }
418
419 static void do_state(struct net_device *dev,
420 struct can_frame *cf, enum can_state new_state)
421 {
422 struct flexcan_priv *priv = netdev_priv(dev);
423 struct can_berr_counter bec;
424
425 flexcan_get_berr_counter(dev, &bec);
426
427 switch (priv->can.state) {
428 case CAN_STATE_ERROR_ACTIVE:
429 /*
430 * from: ERROR_ACTIVE
431 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF
432 * => : there was a warning int
433 */
434 if (new_state >= CAN_STATE_ERROR_WARNING &&
435 new_state <= CAN_STATE_BUS_OFF) {
436 netdev_dbg(dev, "Error Warning IRQ\n");
437 priv->can.can_stats.error_warning++;
438
439 cf->can_id |= CAN_ERR_CRTL;
440 cf->data[1] = (bec.txerr > bec.rxerr) ?
441 CAN_ERR_CRTL_TX_WARNING :
442 CAN_ERR_CRTL_RX_WARNING;
443 }
444 case CAN_STATE_ERROR_WARNING: /* fallthrough */
445 /*
446 * from: ERROR_ACTIVE, ERROR_WARNING
447 * to : ERROR_PASSIVE, BUS_OFF
448 * => : error passive int
449 */
450 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
451 new_state <= CAN_STATE_BUS_OFF) {
452 netdev_dbg(dev, "Error Passive IRQ\n");
453 priv->can.can_stats.error_passive++;
454
455 cf->can_id |= CAN_ERR_CRTL;
456 cf->data[1] = (bec.txerr > bec.rxerr) ?
457 CAN_ERR_CRTL_TX_PASSIVE :
458 CAN_ERR_CRTL_RX_PASSIVE;
459 }
460 break;
461 case CAN_STATE_BUS_OFF:
462 netdev_err(dev, "BUG! "
463 "hardware recovered automatically from BUS_OFF\n");
464 break;
465 default:
466 break;
467 }
468
469 /* process state changes depending on the new state */
470 switch (new_state) {
471 case CAN_STATE_ERROR_ACTIVE:
472 netdev_dbg(dev, "Error Active\n");
473 cf->can_id |= CAN_ERR_PROT;
474 cf->data[2] = CAN_ERR_PROT_ACTIVE;
475 break;
476 case CAN_STATE_BUS_OFF:
477 cf->can_id |= CAN_ERR_BUSOFF;
478 can_bus_off(dev);
479 break;
480 default:
481 break;
482 }
483 }
484
485 static int flexcan_poll_state(struct net_device *dev, u32 reg_esr)
486 {
487 struct flexcan_priv *priv = netdev_priv(dev);
488 struct sk_buff *skb;
489 struct can_frame *cf;
490 enum can_state new_state;
491 int flt;
492
493 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK;
494 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) {
495 if (likely(!(reg_esr & (FLEXCAN_ESR_TX_WRN |
496 FLEXCAN_ESR_RX_WRN))))
497 new_state = CAN_STATE_ERROR_ACTIVE;
498 else
499 new_state = CAN_STATE_ERROR_WARNING;
500 } else if (unlikely(flt == FLEXCAN_ESR_FLT_CONF_PASSIVE))
501 new_state = CAN_STATE_ERROR_PASSIVE;
502 else
503 new_state = CAN_STATE_BUS_OFF;
504
505 /* state hasn't changed */
506 if (likely(new_state == priv->can.state))
507 return 0;
508
509 skb = alloc_can_err_skb(dev, &cf);
510 if (unlikely(!skb))
511 return 0;
512
513 do_state(dev, cf, new_state);
514 priv->can.state = new_state;
515 netif_receive_skb(skb);
516
517 dev->stats.rx_packets++;
518 dev->stats.rx_bytes += cf->can_dlc;
519
520 return 1;
521 }
522
523 static void flexcan_read_fifo(const struct net_device *dev,
524 struct can_frame *cf)
525 {
526 const struct flexcan_priv *priv = netdev_priv(dev);
527 struct flexcan_regs __iomem *regs = priv->base;
528 struct flexcan_mb __iomem *mb = &regs->cantxfg[0];
529 u32 reg_ctrl, reg_id;
530
531 reg_ctrl = flexcan_read(&mb->can_ctrl);
532 reg_id = flexcan_read(&mb->can_id);
533 if (reg_ctrl & FLEXCAN_MB_CNT_IDE)
534 cf->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG;
535 else
536 cf->can_id = (reg_id >> 18) & CAN_SFF_MASK;
537
538 if (reg_ctrl & FLEXCAN_MB_CNT_RTR)
539 cf->can_id |= CAN_RTR_FLAG;
540 cf->can_dlc = get_can_dlc((reg_ctrl >> 16) & 0xf);
541
542 *(__be32 *)(cf->data + 0) = cpu_to_be32(flexcan_read(&mb->data[0]));
543 *(__be32 *)(cf->data + 4) = cpu_to_be32(flexcan_read(&mb->data[1]));
544
545 /* mark as read */
546 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->iflag1);
547 flexcan_read(&regs->timer);
548 }
549
550 static int flexcan_read_frame(struct net_device *dev)
551 {
552 struct net_device_stats *stats = &dev->stats;
553 struct can_frame *cf;
554 struct sk_buff *skb;
555
556 skb = alloc_can_skb(dev, &cf);
557 if (unlikely(!skb)) {
558 stats->rx_dropped++;
559 return 0;
560 }
561
562 flexcan_read_fifo(dev, cf);
563 netif_receive_skb(skb);
564
565 stats->rx_packets++;
566 stats->rx_bytes += cf->can_dlc;
567
568 can_led_event(dev, CAN_LED_EVENT_RX);
569
570 return 1;
571 }
572
573 static int flexcan_poll(struct napi_struct *napi, int quota)
574 {
575 struct net_device *dev = napi->dev;
576 const struct flexcan_priv *priv = netdev_priv(dev);
577 struct flexcan_regs __iomem *regs = priv->base;
578 u32 reg_iflag1, reg_esr;
579 int work_done = 0;
580
581 /*
582 * The error bits are cleared on read,
583 * use saved value from irq handler.
584 */
585 reg_esr = flexcan_read(&regs->esr) | priv->reg_esr;
586
587 /* handle state changes */
588 work_done += flexcan_poll_state(dev, reg_esr);
589
590 /* handle RX-FIFO */
591 reg_iflag1 = flexcan_read(&regs->iflag1);
592 while (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE &&
593 work_done < quota) {
594 work_done += flexcan_read_frame(dev);
595 reg_iflag1 = flexcan_read(&regs->iflag1);
596 }
597
598 /* report bus errors */
599 if (flexcan_has_and_handle_berr(priv, reg_esr) && work_done < quota)
600 work_done += flexcan_poll_bus_err(dev, reg_esr);
601
602 if (work_done < quota) {
603 napi_complete(napi);
604 /* enable IRQs */
605 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
606 flexcan_write(priv->reg_ctrl_default, &regs->ctrl);
607 }
608
609 return work_done;
610 }
611
612 static irqreturn_t flexcan_irq(int irq, void *dev_id)
613 {
614 struct net_device *dev = dev_id;
615 struct net_device_stats *stats = &dev->stats;
616 struct flexcan_priv *priv = netdev_priv(dev);
617 struct flexcan_regs __iomem *regs = priv->base;
618 u32 reg_iflag1, reg_esr;
619
620 reg_iflag1 = flexcan_read(&regs->iflag1);
621 reg_esr = flexcan_read(&regs->esr);
622 /* ACK all bus error and state change IRQ sources */
623 if (reg_esr & FLEXCAN_ESR_ALL_INT)
624 flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, &regs->esr);
625
626 /*
627 * schedule NAPI in case of:
628 * - rx IRQ
629 * - state change IRQ
630 * - bus error IRQ and bus error reporting is activated
631 */
632 if ((reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) ||
633 (reg_esr & FLEXCAN_ESR_ERR_STATE) ||
634 flexcan_has_and_handle_berr(priv, reg_esr)) {
635 /*
636 * The error bits are cleared on read,
637 * save them for later use.
638 */
639 priv->reg_esr = reg_esr & FLEXCAN_ESR_ERR_BUS;
640 flexcan_write(FLEXCAN_IFLAG_DEFAULT &
641 ~FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, &regs->imask1);
642 flexcan_write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL,
643 &regs->ctrl);
644 napi_schedule(&priv->napi);
645 }
646
647 /* FIFO overflow */
648 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) {
649 flexcan_write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, &regs->iflag1);
650 dev->stats.rx_over_errors++;
651 dev->stats.rx_errors++;
652 }
653
654 /* transmission complete interrupt */
655 if (reg_iflag1 & (1 << FLEXCAN_TX_BUF_ID)) {
656 stats->tx_bytes += can_get_echo_skb(dev, 0);
657 stats->tx_packets++;
658 can_led_event(dev, CAN_LED_EVENT_TX);
659 flexcan_write((1 << FLEXCAN_TX_BUF_ID), &regs->iflag1);
660 netif_wake_queue(dev);
661 }
662
663 return IRQ_HANDLED;
664 }
665
666 static void flexcan_set_bittiming(struct net_device *dev)
667 {
668 const struct flexcan_priv *priv = netdev_priv(dev);
669 const struct can_bittiming *bt = &priv->can.bittiming;
670 struct flexcan_regs __iomem *regs = priv->base;
671 u32 reg;
672
673 reg = flexcan_read(&regs->ctrl);
674 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) |
675 FLEXCAN_CTRL_RJW(0x3) |
676 FLEXCAN_CTRL_PSEG1(0x7) |
677 FLEXCAN_CTRL_PSEG2(0x7) |
678 FLEXCAN_CTRL_PROPSEG(0x7) |
679 FLEXCAN_CTRL_LPB |
680 FLEXCAN_CTRL_SMP |
681 FLEXCAN_CTRL_LOM);
682
683 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) |
684 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) |
685 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) |
686 FLEXCAN_CTRL_RJW(bt->sjw - 1) |
687 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1);
688
689 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
690 reg |= FLEXCAN_CTRL_LPB;
691 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
692 reg |= FLEXCAN_CTRL_LOM;
693 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
694 reg |= FLEXCAN_CTRL_SMP;
695
696 netdev_info(dev, "writing ctrl=0x%08x\n", reg);
697 flexcan_write(reg, &regs->ctrl);
698
699 /* print chip status */
700 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__,
701 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
702 }
703
704 /*
705 * flexcan_chip_start
706 *
707 * this functions is entered with clocks enabled
708 *
709 */
710 static int flexcan_chip_start(struct net_device *dev)
711 {
712 struct flexcan_priv *priv = netdev_priv(dev);
713 struct flexcan_regs __iomem *regs = priv->base;
714 unsigned int i;
715 int err;
716 u32 reg_mcr, reg_ctrl;
717
718 /* enable module */
719 flexcan_chip_enable(priv);
720
721 /* soft reset */
722 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr);
723 udelay(10);
724
725 reg_mcr = flexcan_read(&regs->mcr);
726 if (reg_mcr & FLEXCAN_MCR_SOFTRST) {
727 netdev_err(dev, "Failed to softreset can module (mcr=0x%08x)\n",
728 reg_mcr);
729 err = -ENODEV;
730 goto out;
731 }
732
733 flexcan_set_bittiming(dev);
734
735 /*
736 * MCR
737 *
738 * enable freeze
739 * enable fifo
740 * halt now
741 * only supervisor access
742 * enable warning int
743 * choose format C
744 * disable local echo
745 *
746 */
747 reg_mcr = flexcan_read(&regs->mcr);
748 reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
749 FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
750 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS;
751 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
752 flexcan_write(reg_mcr, &regs->mcr);
753
754 /*
755 * CTRL
756 *
757 * disable timer sync feature
758 *
759 * disable auto busoff recovery
760 * transmit lowest buffer first
761 *
762 * enable tx and rx warning interrupt
763 * enable bus off interrupt
764 * (== FLEXCAN_CTRL_ERR_STATE)
765 */
766 reg_ctrl = flexcan_read(&regs->ctrl);
767 reg_ctrl &= ~FLEXCAN_CTRL_TSYN;
768 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF |
769 FLEXCAN_CTRL_ERR_STATE;
770 /*
771 * enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK),
772 * on most Flexcan cores, too. Otherwise we don't get
773 * any error warning or passive interrupts.
774 */
775 if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
776 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
777 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
778
779 /* save for later use */
780 priv->reg_ctrl_default = reg_ctrl;
781 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
782 flexcan_write(reg_ctrl, &regs->ctrl);
783
784 for (i = 0; i < ARRAY_SIZE(regs->cantxfg); i++) {
785 flexcan_write(0, &regs->cantxfg[i].can_ctrl);
786 flexcan_write(0, &regs->cantxfg[i].can_id);
787 flexcan_write(0, &regs->cantxfg[i].data[0]);
788 flexcan_write(0, &regs->cantxfg[i].data[1]);
789
790 /* put MB into rx queue */
791 flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
792 &regs->cantxfg[i].can_ctrl);
793 }
794
795 /* acceptance mask/acceptance code (accept everything) */
796 flexcan_write(0x0, &regs->rxgmask);
797 flexcan_write(0x0, &regs->rx14mask);
798 flexcan_write(0x0, &regs->rx15mask);
799
800 if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
801 flexcan_write(0x0, &regs->rxfgmask);
802
803 flexcan_transceiver_switch(priv, 1);
804
805 /* synchronize with the can bus */
806 reg_mcr = flexcan_read(&regs->mcr);
807 reg_mcr &= ~FLEXCAN_MCR_HALT;
808 flexcan_write(reg_mcr, &regs->mcr);
809
810 priv->can.state = CAN_STATE_ERROR_ACTIVE;
811
812 /* enable FIFO interrupts */
813 flexcan_write(FLEXCAN_IFLAG_DEFAULT, &regs->imask1);
814
815 /* print chip status */
816 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__,
817 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl));
818
819 return 0;
820
821 out:
822 flexcan_chip_disable(priv);
823 return err;
824 }
825
826 /*
827 * flexcan_chip_stop
828 *
829 * this functions is entered with clocks enabled
830 *
831 */
832 static void flexcan_chip_stop(struct net_device *dev)
833 {
834 struct flexcan_priv *priv = netdev_priv(dev);
835 struct flexcan_regs __iomem *regs = priv->base;
836 u32 reg;
837
838 /* Disable all interrupts */
839 flexcan_write(0, &regs->imask1);
840
841 /* Disable + halt module */
842 reg = flexcan_read(&regs->mcr);
843 reg |= FLEXCAN_MCR_MDIS | FLEXCAN_MCR_HALT;
844 flexcan_write(reg, &regs->mcr);
845
846 flexcan_transceiver_switch(priv, 0);
847 priv->can.state = CAN_STATE_STOPPED;
848
849 return;
850 }
851
852 static int flexcan_open(struct net_device *dev)
853 {
854 struct flexcan_priv *priv = netdev_priv(dev);
855 int err;
856
857 clk_prepare_enable(priv->clk_ipg);
858 clk_prepare_enable(priv->clk_per);
859
860 err = open_candev(dev);
861 if (err)
862 goto out;
863
864 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev);
865 if (err)
866 goto out_close;
867
868 /* start chip and queuing */
869 err = flexcan_chip_start(dev);
870 if (err)
871 goto out_close;
872
873 can_led_event(dev, CAN_LED_EVENT_OPEN);
874
875 napi_enable(&priv->napi);
876 netif_start_queue(dev);
877
878 return 0;
879
880 out_close:
881 close_candev(dev);
882 out:
883 clk_disable_unprepare(priv->clk_per);
884 clk_disable_unprepare(priv->clk_ipg);
885
886 return err;
887 }
888
889 static int flexcan_close(struct net_device *dev)
890 {
891 struct flexcan_priv *priv = netdev_priv(dev);
892
893 netif_stop_queue(dev);
894 napi_disable(&priv->napi);
895 flexcan_chip_stop(dev);
896
897 free_irq(dev->irq, dev);
898 clk_disable_unprepare(priv->clk_per);
899 clk_disable_unprepare(priv->clk_ipg);
900
901 close_candev(dev);
902
903 can_led_event(dev, CAN_LED_EVENT_STOP);
904
905 return 0;
906 }
907
908 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode)
909 {
910 int err;
911
912 switch (mode) {
913 case CAN_MODE_START:
914 err = flexcan_chip_start(dev);
915 if (err)
916 return err;
917
918 netif_wake_queue(dev);
919 break;
920
921 default:
922 return -EOPNOTSUPP;
923 }
924
925 return 0;
926 }
927
928 static const struct net_device_ops flexcan_netdev_ops = {
929 .ndo_open = flexcan_open,
930 .ndo_stop = flexcan_close,
931 .ndo_start_xmit = flexcan_start_xmit,
932 };
933
934 static int register_flexcandev(struct net_device *dev)
935 {
936 struct flexcan_priv *priv = netdev_priv(dev);
937 struct flexcan_regs __iomem *regs = priv->base;
938 u32 reg, err;
939
940 clk_prepare_enable(priv->clk_ipg);
941 clk_prepare_enable(priv->clk_per);
942
943 /* select "bus clock", chip must be disabled */
944 flexcan_chip_disable(priv);
945 reg = flexcan_read(&regs->ctrl);
946 reg |= FLEXCAN_CTRL_CLK_SRC;
947 flexcan_write(reg, &regs->ctrl);
948
949 flexcan_chip_enable(priv);
950
951 /* set freeze, halt and activate FIFO, restrict register access */
952 reg = flexcan_read(&regs->mcr);
953 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT |
954 FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
955 flexcan_write(reg, &regs->mcr);
956
957 /*
958 * Currently we only support newer versions of this core
959 * featuring a RX FIFO. Older cores found on some Coldfire
960 * derivates are not yet supported.
961 */
962 reg = flexcan_read(&regs->mcr);
963 if (!(reg & FLEXCAN_MCR_FEN)) {
964 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
965 err = -ENODEV;
966 goto out;
967 }
968
969 err = register_candev(dev);
970
971 out:
972 /* disable core and turn off clocks */
973 flexcan_chip_disable(priv);
974 clk_disable_unprepare(priv->clk_per);
975 clk_disable_unprepare(priv->clk_ipg);
976
977 return err;
978 }
979
980 static void unregister_flexcandev(struct net_device *dev)
981 {
982 unregister_candev(dev);
983 }
984
985 static const struct of_device_id flexcan_of_match[] = {
986 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
987 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
988 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
989 { /* sentinel */ },
990 };
991 MODULE_DEVICE_TABLE(of, flexcan_of_match);
992
993 static const struct platform_device_id flexcan_id_table[] = {
994 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
995 { /* sentinel */ },
996 };
997 MODULE_DEVICE_TABLE(platform, flexcan_id_table);
998
999 static int flexcan_probe(struct platform_device *pdev)
1000 {
1001 const struct of_device_id *of_id;
1002 const struct flexcan_devtype_data *devtype_data;
1003 struct net_device *dev;
1004 struct flexcan_priv *priv;
1005 struct resource *mem;
1006 struct clk *clk_ipg = NULL, *clk_per = NULL;
1007 struct pinctrl *pinctrl;
1008 void __iomem *base;
1009 resource_size_t mem_size;
1010 int err, irq;
1011 u32 clock_freq = 0;
1012
1013 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1014 if (IS_ERR(pinctrl))
1015 return PTR_ERR(pinctrl);
1016
1017 if (pdev->dev.of_node)
1018 of_property_read_u32(pdev->dev.of_node,
1019 "clock-frequency", &clock_freq);
1020
1021 if (!clock_freq) {
1022 clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1023 if (IS_ERR(clk_ipg)) {
1024 dev_err(&pdev->dev, "no ipg clock defined\n");
1025 err = PTR_ERR(clk_ipg);
1026 goto failed_clock;
1027 }
1028 clock_freq = clk_get_rate(clk_ipg);
1029
1030 clk_per = devm_clk_get(&pdev->dev, "per");
1031 if (IS_ERR(clk_per)) {
1032 dev_err(&pdev->dev, "no per clock defined\n");
1033 err = PTR_ERR(clk_per);
1034 goto failed_clock;
1035 }
1036 }
1037
1038 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1039 irq = platform_get_irq(pdev, 0);
1040 if (!mem || irq <= 0) {
1041 err = -ENODEV;
1042 goto failed_get;
1043 }
1044
1045 mem_size = resource_size(mem);
1046 if (!request_mem_region(mem->start, mem_size, pdev->name)) {
1047 err = -EBUSY;
1048 goto failed_get;
1049 }
1050
1051 base = ioremap(mem->start, mem_size);
1052 if (!base) {
1053 err = -ENOMEM;
1054 goto failed_map;
1055 }
1056
1057 dev = alloc_candev(sizeof(struct flexcan_priv), 1);
1058 if (!dev) {
1059 err = -ENOMEM;
1060 goto failed_alloc;
1061 }
1062
1063 of_id = of_match_device(flexcan_of_match, &pdev->dev);
1064 if (of_id) {
1065 devtype_data = of_id->data;
1066 } else if (pdev->id_entry->driver_data) {
1067 devtype_data = (struct flexcan_devtype_data *)
1068 pdev->id_entry->driver_data;
1069 } else {
1070 err = -ENODEV;
1071 goto failed_devtype;
1072 }
1073
1074 dev->netdev_ops = &flexcan_netdev_ops;
1075 dev->irq = irq;
1076 dev->flags |= IFF_ECHO;
1077
1078 priv = netdev_priv(dev);
1079 priv->can.clock.freq = clock_freq;
1080 priv->can.bittiming_const = &flexcan_bittiming_const;
1081 priv->can.do_set_mode = flexcan_set_mode;
1082 priv->can.do_get_berr_counter = flexcan_get_berr_counter;
1083 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
1084 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES |
1085 CAN_CTRLMODE_BERR_REPORTING;
1086 priv->base = base;
1087 priv->dev = dev;
1088 priv->clk_ipg = clk_ipg;
1089 priv->clk_per = clk_per;
1090 priv->pdata = pdev->dev.platform_data;
1091 priv->devtype_data = devtype_data;
1092
1093 netif_napi_add(dev, &priv->napi, flexcan_poll, FLEXCAN_NAPI_WEIGHT);
1094
1095 dev_set_drvdata(&pdev->dev, dev);
1096 SET_NETDEV_DEV(dev, &pdev->dev);
1097
1098 err = register_flexcandev(dev);
1099 if (err) {
1100 dev_err(&pdev->dev, "registering netdev failed\n");
1101 goto failed_register;
1102 }
1103
1104 devm_can_led_init(dev);
1105
1106 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n",
1107 priv->base, dev->irq);
1108
1109 return 0;
1110
1111 failed_register:
1112 failed_devtype:
1113 free_candev(dev);
1114 failed_alloc:
1115 iounmap(base);
1116 failed_map:
1117 release_mem_region(mem->start, mem_size);
1118 failed_get:
1119 failed_clock:
1120 return err;
1121 }
1122
1123 static int flexcan_remove(struct platform_device *pdev)
1124 {
1125 struct net_device *dev = platform_get_drvdata(pdev);
1126 struct flexcan_priv *priv = netdev_priv(dev);
1127 struct resource *mem;
1128
1129 unregister_flexcandev(dev);
1130 platform_set_drvdata(pdev, NULL);
1131 iounmap(priv->base);
1132
1133 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1134 release_mem_region(mem->start, resource_size(mem));
1135
1136 free_candev(dev);
1137
1138 return 0;
1139 }
1140
1141 #ifdef CONFIG_PM
1142 static int flexcan_suspend(struct platform_device *pdev, pm_message_t state)
1143 {
1144 struct net_device *dev = platform_get_drvdata(pdev);
1145 struct flexcan_priv *priv = netdev_priv(dev);
1146
1147 flexcan_chip_disable(priv);
1148
1149 if (netif_running(dev)) {
1150 netif_stop_queue(dev);
1151 netif_device_detach(dev);
1152 }
1153 priv->can.state = CAN_STATE_SLEEPING;
1154
1155 return 0;
1156 }
1157
1158 static int flexcan_resume(struct platform_device *pdev)
1159 {
1160 struct net_device *dev = platform_get_drvdata(pdev);
1161 struct flexcan_priv *priv = netdev_priv(dev);
1162
1163 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1164 if (netif_running(dev)) {
1165 netif_device_attach(dev);
1166 netif_start_queue(dev);
1167 }
1168 flexcan_chip_enable(priv);
1169
1170 return 0;
1171 }
1172 #else
1173 #define flexcan_suspend NULL
1174 #define flexcan_resume NULL
1175 #endif
1176
1177 static struct platform_driver flexcan_driver = {
1178 .driver = {
1179 .name = DRV_NAME,
1180 .owner = THIS_MODULE,
1181 .of_match_table = flexcan_of_match,
1182 },
1183 .probe = flexcan_probe,
1184 .remove = flexcan_remove,
1185 .suspend = flexcan_suspend,
1186 .resume = flexcan_resume,
1187 .id_table = flexcan_id_table,
1188 };
1189
1190 module_platform_driver(flexcan_driver);
1191
1192 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, "
1193 "Marc Kleine-Budde <kernel@pengutronix.de>");
1194 MODULE_LICENSE("GPL v2");
1195 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");
Linux 2.6 libata-dev (mirror)