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V4L/DVB (10075): pxa-camera: setup the FIFO inactivity time-out register
[linux-2.6/kvm.git] / drivers / media / video / pxa_camera.c
blob28ea13f7b2b039a007bfe2f362b75b922bfb99a1
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/mutex.h>
29 #include <linux/clk.h>
30
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/videobuf-dma-sg.h>
34 #include <media/soc_camera.h>
35
36 #include <linux/videodev2.h>
37
38 #include <asm/dma.h>
39 #include <mach/pxa-regs.h>
40 #include <mach/camera.h>
41
42 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
43 #define PXA_CAM_DRV_NAME "pxa27x-camera"
44
45 /* Camera Interface */
46 #define CICR0 0x0000
47 #define CICR1 0x0004
48 #define CICR2 0x0008
49 #define CICR3 0x000C
50 #define CICR4 0x0010
51 #define CISR 0x0014
52 #define CIFR 0x0018
53 #define CITOR 0x001C
54 #define CIBR0 0x0028
55 #define CIBR1 0x0030
56 #define CIBR2 0x0038
57
58 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
59 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
60 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
61 #define CICR0_ENB (1 << 28) /* Camera interface enable */
62 #define CICR0_DIS (1 << 27) /* Camera interface disable */
63 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
64 #define CICR0_TOM (1 << 9) /* Time-out mask */
65 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
66 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
67 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
68 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
69 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
70 #define CICR0_CDM (1 << 3) /* Disable-done mask */
71 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
72 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
73 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
74
75 #define CICR1_TBIT (1 << 31) /* Transparency bit */
76 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
77 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
78 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
79 #define CICR1_RGB_F (1 << 11) /* RGB format */
80 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
81 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
82 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
83 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
84 #define CICR1_DW (0x7 << 0) /* Data width mask */
85
86 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
87 wait count mask */
88 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
89 wait count mask */
90 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
91 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
92 wait count mask */
93 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
94 wait count mask */
95
96 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
97 wait count mask */
98 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
99 wait count mask */
100 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
101 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
102 wait count mask */
103 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
104
105 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
106 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
107 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
108 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
109 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
110 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
111 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
112 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
113
114 #define CISR_FTO (1 << 15) /* FIFO time-out */
115 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
116 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
117 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
118 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
119 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
120 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
121 #define CISR_EOL (1 << 8) /* End of line */
122 #define CISR_PAR_ERR (1 << 7) /* Parity error */
123 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
124 #define CISR_CDD (1 << 5) /* Camera interface disable done */
125 #define CISR_SOF (1 << 4) /* Start of frame */
126 #define CISR_EOF (1 << 3) /* End of frame */
127 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
128 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
129 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
130
131 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
132 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
133 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
134 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
135 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
136 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
137 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
138 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
139
140 #define CICR0_SIM_MP (0 << 24)
141 #define CICR0_SIM_SP (1 << 24)
142 #define CICR0_SIM_MS (2 << 24)
143 #define CICR0_SIM_EP (3 << 24)
144 #define CICR0_SIM_ES (4 << 24)
145
146 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
147 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
148 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
149 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
150 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
151
152 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
153 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
154 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
155 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
156 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
157
158 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
159 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
160 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
161 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
162
163 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
164 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
165 CICR0_EOFM | CICR0_FOM)
166
167 static DEFINE_MUTEX(camera_lock);
168
169 /*
170 * Structures
171 */
172 enum pxa_camera_active_dma {
173 DMA_Y = 0x1,
174 DMA_U = 0x2,
175 DMA_V = 0x4,
176 };
177
178 /* descriptor needed for the PXA DMA engine */
179 struct pxa_cam_dma {
180 dma_addr_t sg_dma;
181 struct pxa_dma_desc *sg_cpu;
182 size_t sg_size;
183 int sglen;
184 };
185
186 /* buffer for one video frame */
187 struct pxa_buffer {
188 /* common v4l buffer stuff -- must be first */
189 struct videobuf_buffer vb;
190
191 const struct soc_camera_data_format *fmt;
192
193 /* our descriptor lists for Y, U and V channels */
194 struct pxa_cam_dma dmas[3];
195
196 int inwork;
197
198 enum pxa_camera_active_dma active_dma;
199 };
200
201 struct pxa_camera_dev {
202 struct device *dev;
203 /* PXA27x is only supposed to handle one camera on its Quick Capture
204 * interface. If anyone ever builds hardware to enable more than
205 * one camera, they will have to modify this driver too */
206 struct soc_camera_device *icd;
207 struct clk *clk;
208
209 unsigned int irq;
210 void __iomem *base;
211
212 int channels;
213 unsigned int dma_chans[3];
214
215 struct pxacamera_platform_data *pdata;
216 struct resource *res;
217 unsigned long platform_flags;
218 unsigned long ciclk;
219 unsigned long mclk;
220 u32 mclk_divisor;
221
222 struct list_head capture;
223
224 spinlock_t lock;
225
226 struct pxa_buffer *active;
227 struct pxa_dma_desc *sg_tail[3];
228
229 u32 save_cicr[5];
230 };
231
232 static const char *pxa_cam_driver_description = "PXA_Camera";
233
234 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
235
236 /*
237 * Videobuf operations
238 */
239 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
240 unsigned int *size)
241 {
242 struct soc_camera_device *icd = vq->priv_data;
243 struct soc_camera_host *ici =
244 to_soc_camera_host(icd->dev.parent);
245 struct pxa_camera_dev *pcdev = ici->priv;
246
247 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
248
249 /* planar capture requires Y, U and V buffers to be page aligned */
250 if (pcdev->channels == 3) {
251 *size = PAGE_ALIGN(icd->width * icd->height); /* Y pages */
252 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* U pages */
253 *size += PAGE_ALIGN(icd->width * icd->height / 2); /* V pages */
254 } else {
255 *size = icd->width * icd->height *
256 ((icd->current_fmt->depth + 7) >> 3);
257 }
258
259 if (0 == *count)
260 *count = 32;
261 while (*size * *count > vid_limit * 1024 * 1024)
262 (*count)--;
263
264 return 0;
265 }
266
267 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
268 {
269 struct soc_camera_device *icd = vq->priv_data;
270 struct soc_camera_host *ici =
271 to_soc_camera_host(icd->dev.parent);
272 struct pxa_camera_dev *pcdev = ici->priv;
273 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
274 int i;
275
276 BUG_ON(in_interrupt());
277
278 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
279 &buf->vb, buf->vb.baddr, buf->vb.bsize);
280
281 /* This waits until this buffer is out of danger, i.e., until it is no
282 * longer in STATE_QUEUED or STATE_ACTIVE */
283 videobuf_waiton(&buf->vb, 0, 0);
284 videobuf_dma_unmap(vq, dma);
285 videobuf_dma_free(dma);
286
287 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
288 if (buf->dmas[i].sg_cpu)
289 dma_free_coherent(pcdev->dev, buf->dmas[i].sg_size,
290 buf->dmas[i].sg_cpu,
291 buf->dmas[i].sg_dma);
292 buf->dmas[i].sg_cpu = NULL;
293 }
294
295 buf->vb.state = VIDEOBUF_NEEDS_INIT;
296 }
297
298 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
299 struct pxa_buffer *buf,
300 struct videobuf_dmabuf *dma, int channel,
301 int sglen, int sg_start, int cibr,
302 unsigned int size)
303 {
304 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
305 int i;
306
307 if (pxa_dma->sg_cpu)
308 dma_free_coherent(pcdev->dev, pxa_dma->sg_size,
309 pxa_dma->sg_cpu, pxa_dma->sg_dma);
310
311 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
312 pxa_dma->sg_cpu = dma_alloc_coherent(pcdev->dev, pxa_dma->sg_size,
313 &pxa_dma->sg_dma, GFP_KERNEL);
314 if (!pxa_dma->sg_cpu)
315 return -ENOMEM;
316
317 pxa_dma->sglen = sglen;
318
319 for (i = 0; i < sglen; i++) {
320 int sg_i = sg_start + i;
321 struct scatterlist *sg = dma->sglist;
322 unsigned int dma_len = sg_dma_len(&sg[sg_i]), xfer_len;
323
324 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
325 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(&sg[sg_i]);
326
327 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
328 xfer_len = (min(dma_len, size) + 7) & ~7;
329
330 pxa_dma->sg_cpu[i].dcmd =
331 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
332 size -= dma_len;
333 pxa_dma->sg_cpu[i].ddadr =
334 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
335 }
336
337 pxa_dma->sg_cpu[sglen - 1].ddadr = DDADR_STOP;
338 pxa_dma->sg_cpu[sglen - 1].dcmd |= DCMD_ENDIRQEN;
339
340 return 0;
341 }
342
343 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
344 struct videobuf_buffer *vb, enum v4l2_field field)
345 {
346 struct soc_camera_device *icd = vq->priv_data;
347 struct soc_camera_host *ici =
348 to_soc_camera_host(icd->dev.parent);
349 struct pxa_camera_dev *pcdev = ici->priv;
350 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
351 int ret;
352 int sglen_y, sglen_yu = 0, sglen_u = 0, sglen_v = 0;
353 int size_y, size_u = 0, size_v = 0;
354
355 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
356 vb, vb->baddr, vb->bsize);
357
358 /* Added list head initialization on alloc */
359 WARN_ON(!list_empty(&vb->queue));
360
361 #ifdef DEBUG
362 /* This can be useful if you want to see if we actually fill
363 * the buffer with something */
364 memset((void *)vb->baddr, 0xaa, vb->bsize);
365 #endif
366
367 BUG_ON(NULL == icd->current_fmt);
368
369 /* I think, in buf_prepare you only have to protect global data,
370 * the actual buffer is yours */
371 buf->inwork = 1;
372
373 if (buf->fmt != icd->current_fmt ||
374 vb->width != icd->width ||
375 vb->height != icd->height ||
376 vb->field != field) {
377 buf->fmt = icd->current_fmt;
378 vb->width = icd->width;
379 vb->height = icd->height;
380 vb->field = field;
381 vb->state = VIDEOBUF_NEEDS_INIT;
382 }
383
384 vb->size = vb->width * vb->height * ((buf->fmt->depth + 7) >> 3);
385 if (0 != vb->baddr && vb->bsize < vb->size) {
386 ret = -EINVAL;
387 goto out;
388 }
389
390 if (vb->state == VIDEOBUF_NEEDS_INIT) {
391 unsigned int size = vb->size;
392 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
393
394 ret = videobuf_iolock(vq, vb, NULL);
395 if (ret)
396 goto fail;
397
398 if (pcdev->channels == 3) {
399 /* FIXME the calculations should be more precise */
400 sglen_y = dma->sglen / 2;
401 sglen_u = sglen_v = dma->sglen / 4 + 1;
402 sglen_yu = sglen_y + sglen_u;
403 size_y = size / 2;
404 size_u = size_v = size / 4;
405 } else {
406 sglen_y = dma->sglen;
407 size_y = size;
408 }
409
410 /* init DMA for Y channel */
411 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, sglen_y,
412 0, 0x28, size_y);
413
414 if (ret) {
415 dev_err(pcdev->dev,
416 "DMA initialization for Y/RGB failed\n");
417 goto fail;
418 }
419
420 if (pcdev->channels == 3) {
421 /* init DMA for U channel */
422 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, sglen_u,
423 sglen_y, 0x30, size_u);
424 if (ret) {
425 dev_err(pcdev->dev,
426 "DMA initialization for U failed\n");
427 goto fail_u;
428 }
429
430 /* init DMA for V channel */
431 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, sglen_v,
432 sglen_yu, 0x38, size_v);
433 if (ret) {
434 dev_err(pcdev->dev,
435 "DMA initialization for V failed\n");
436 goto fail_v;
437 }
438 }
439
440 vb->state = VIDEOBUF_PREPARED;
441 }
442
443 buf->inwork = 0;
444 buf->active_dma = DMA_Y;
445 if (pcdev->channels == 3)
446 buf->active_dma |= DMA_U | DMA_V;
447
448 return 0;
449
450 fail_v:
451 dma_free_coherent(pcdev->dev, buf->dmas[1].sg_size,
452 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
453 fail_u:
454 dma_free_coherent(pcdev->dev, buf->dmas[0].sg_size,
455 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
456 fail:
457 free_buffer(vq, buf);
458 out:
459 buf->inwork = 0;
460 return ret;
461 }
462
463 static void pxa_videobuf_queue(struct videobuf_queue *vq,
464 struct videobuf_buffer *vb)
465 {
466 struct soc_camera_device *icd = vq->priv_data;
467 struct soc_camera_host *ici =
468 to_soc_camera_host(icd->dev.parent);
469 struct pxa_camera_dev *pcdev = ici->priv;
470 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
471 struct pxa_buffer *active;
472 unsigned long flags;
473 int i;
474
475 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
476 vb, vb->baddr, vb->bsize);
477 spin_lock_irqsave(&pcdev->lock, flags);
478
479 list_add_tail(&vb->queue, &pcdev->capture);
480
481 vb->state = VIDEOBUF_ACTIVE;
482 active = pcdev->active;
483
484 if (!active) {
485 unsigned long cifr, cicr0;
486
487 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
488 __raw_writel(cifr, pcdev->base + CIFR);
489
490 for (i = 0; i < pcdev->channels; i++) {
491 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
492 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
493 pcdev->sg_tail[i] = buf->dmas[i].sg_cpu + buf->dmas[i].sglen - 1;
494 }
495
496 pcdev->active = buf;
497
498 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
499 __raw_writel(cicr0, pcdev->base + CICR0);
500 } else {
501 struct pxa_cam_dma *buf_dma;
502 struct pxa_cam_dma *act_dma;
503 int nents;
504
505 for (i = 0; i < pcdev->channels; i++) {
506 buf_dma = &buf->dmas[i];
507 act_dma = &active->dmas[i];
508 nents = buf_dma->sglen;
509
510 /* Stop DMA engine */
511 DCSR(pcdev->dma_chans[i]) = 0;
512
513 /* Add the descriptors we just initialized to
514 the currently running chain */
515 pcdev->sg_tail[i]->ddadr = buf_dma->sg_dma;
516 pcdev->sg_tail[i] = buf_dma->sg_cpu + buf_dma->sglen - 1;
517
518 /* Setup a dummy descriptor with the DMA engines current
519 * state
520 */
521 buf_dma->sg_cpu[nents].dsadr =
522 pcdev->res->start + 0x28 + i*8; /* CIBRx */
523 buf_dma->sg_cpu[nents].dtadr =
524 DTADR(pcdev->dma_chans[i]);
525 buf_dma->sg_cpu[nents].dcmd =
526 DCMD(pcdev->dma_chans[i]);
527
528 if (DDADR(pcdev->dma_chans[i]) == DDADR_STOP) {
529 /* The DMA engine is on the last
530 descriptor, set the next descriptors
531 address to the descriptors we just
532 initialized */
533 buf_dma->sg_cpu[nents].ddadr = buf_dma->sg_dma;
534 } else {
535 buf_dma->sg_cpu[nents].ddadr =
536 DDADR(pcdev->dma_chans[i]);
537 }
538
539 /* The next descriptor is the dummy descriptor */
540 DDADR(pcdev->dma_chans[i]) = buf_dma->sg_dma + nents *
541 sizeof(struct pxa_dma_desc);
542
543 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
544 }
545 }
546
547 spin_unlock_irqrestore(&pcdev->lock, flags);
548 }
549
550 static void pxa_videobuf_release(struct videobuf_queue *vq,
551 struct videobuf_buffer *vb)
552 {
553 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
554 #ifdef DEBUG
555 struct soc_camera_device *icd = vq->priv_data;
556
557 dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
558 vb, vb->baddr, vb->bsize);
559
560 switch (vb->state) {
561 case VIDEOBUF_ACTIVE:
562 dev_dbg(&icd->dev, "%s (active)\n", __func__);
563 break;
564 case VIDEOBUF_QUEUED:
565 dev_dbg(&icd->dev, "%s (queued)\n", __func__);
566 break;
567 case VIDEOBUF_PREPARED:
568 dev_dbg(&icd->dev, "%s (prepared)\n", __func__);
569 break;
570 default:
571 dev_dbg(&icd->dev, "%s (unknown)\n", __func__);
572 break;
573 }
574 #endif
575
576 free_buffer(vq, buf);
577 }
578
579 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
580 struct videobuf_buffer *vb,
581 struct pxa_buffer *buf)
582 {
583 unsigned long cicr0;
584
585 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
586 list_del_init(&vb->queue);
587 vb->state = VIDEOBUF_DONE;
588 do_gettimeofday(&vb->ts);
589 vb->field_count++;
590 wake_up(&vb->done);
591
592 if (list_empty(&pcdev->capture)) {
593 pcdev->active = NULL;
594 DCSR(pcdev->dma_chans[0]) = 0;
595 DCSR(pcdev->dma_chans[1]) = 0;
596 DCSR(pcdev->dma_chans[2]) = 0;
597
598 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
599 __raw_writel(cicr0, pcdev->base + CICR0);
600 return;
601 }
602
603 pcdev->active = list_entry(pcdev->capture.next,
604 struct pxa_buffer, vb.queue);
605 }
606
607 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
608 enum pxa_camera_active_dma act_dma)
609 {
610 struct pxa_buffer *buf;
611 unsigned long flags;
612 u32 status, camera_status, overrun;
613 struct videobuf_buffer *vb;
614 unsigned long cifr, cicr0;
615
616 spin_lock_irqsave(&pcdev->lock, flags);
617
618 status = DCSR(channel);
619 DCSR(channel) = status | DCSR_ENDINTR;
620
621 if (status & DCSR_BUSERR) {
622 dev_err(pcdev->dev, "DMA Bus Error IRQ!\n");
623 goto out;
624 }
625
626 if (!(status & DCSR_ENDINTR)) {
627 dev_err(pcdev->dev, "Unknown DMA IRQ source, "
628 "status: 0x%08x\n", status);
629 goto out;
630 }
631
632 if (!pcdev->active) {
633 dev_err(pcdev->dev, "DMA End IRQ with no active buffer!\n");
634 goto out;
635 }
636
637 camera_status = __raw_readl(pcdev->base + CISR);
638 overrun = CISR_IFO_0;
639 if (pcdev->channels == 3)
640 overrun |= CISR_IFO_1 | CISR_IFO_2;
641 if (camera_status & overrun) {
642 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
643 /* Stop the Capture Interface */
644 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
645 __raw_writel(cicr0, pcdev->base + CICR0);
646
647 /* Stop DMA */
648 DCSR(channel) = 0;
649 /* Reset the FIFOs */
650 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
651 __raw_writel(cifr, pcdev->base + CIFR);
652 /* Enable End-Of-Frame Interrupt */
653 cicr0 &= ~CICR0_EOFM;
654 __raw_writel(cicr0, pcdev->base + CICR0);
655 /* Restart the Capture Interface */
656 __raw_writel(cicr0 | CICR0_ENB, pcdev->base + CICR0);
657 goto out;
658 }
659
660 vb = &pcdev->active->vb;
661 buf = container_of(vb, struct pxa_buffer, vb);
662 WARN_ON(buf->inwork || list_empty(&vb->queue));
663 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
664 vb, vb->baddr, vb->bsize);
665
666 buf->active_dma &= ~act_dma;
667 if (!buf->active_dma)
668 pxa_camera_wakeup(pcdev, vb, buf);
669
670 out:
671 spin_unlock_irqrestore(&pcdev->lock, flags);
672 }
673
674 static void pxa_camera_dma_irq_y(int channel, void *data)
675 {
676 struct pxa_camera_dev *pcdev = data;
677 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
678 }
679
680 static void pxa_camera_dma_irq_u(int channel, void *data)
681 {
682 struct pxa_camera_dev *pcdev = data;
683 pxa_camera_dma_irq(channel, pcdev, DMA_U);
684 }
685
686 static void pxa_camera_dma_irq_v(int channel, void *data)
687 {
688 struct pxa_camera_dev *pcdev = data;
689 pxa_camera_dma_irq(channel, pcdev, DMA_V);
690 }
691
692 static struct videobuf_queue_ops pxa_videobuf_ops = {
693 .buf_setup = pxa_videobuf_setup,
694 .buf_prepare = pxa_videobuf_prepare,
695 .buf_queue = pxa_videobuf_queue,
696 .buf_release = pxa_videobuf_release,
697 };
698
699 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
700 struct soc_camera_device *icd)
701 {
702 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
703 struct pxa_camera_dev *pcdev = ici->priv;
704
705 /* We must pass NULL as dev pointer, then all pci_* dma operations
706 * transform to normal dma_* ones. */
707 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
708 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
709 sizeof(struct pxa_buffer), icd);
710 }
711
712 static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
713 {
714 unsigned long mclk = pcdev->mclk;
715 u32 div;
716 unsigned long lcdclk;
717
718 lcdclk = clk_get_rate(pcdev->clk);
719 pcdev->ciclk = lcdclk;
720
721 /* mclk <= ciclk / 4 (27.4.2) */
722 if (mclk > lcdclk / 4) {
723 mclk = lcdclk / 4;
724 dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk);
725 }
726
727 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
728 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
729
730 /* If we're not supplying MCLK, leave it at 0 */
731 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
732 pcdev->mclk = lcdclk / (2 * (div + 1));
733
734 dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, "
735 "divisor %u\n", lcdclk, mclk, div);
736
737 return div;
738 }
739
740 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
741 unsigned long pclk)
742 {
743 /* We want a timeout > 1 pixel time, not ">=" */
744 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
745
746 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
747 }
748
749 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
750 {
751 struct pxacamera_platform_data *pdata = pcdev->pdata;
752 u32 cicr4 = 0;
753
754 dev_dbg(pcdev->dev, "Registered platform device at %p data %p\n",
755 pcdev, pdata);
756
757 if (pdata && pdata->init) {
758 dev_dbg(pcdev->dev, "%s: Init gpios\n", __func__);
759 pdata->init(pcdev->dev);
760 }
761
762 /* disable all interrupts */
763 __raw_writel(0x3ff, pcdev->base + CICR0);
764
765 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
766 cicr4 |= CICR4_PCLK_EN;
767 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
768 cicr4 |= CICR4_MCLK_EN;
769 if (pcdev->platform_flags & PXA_CAMERA_PCP)
770 cicr4 |= CICR4_PCP;
771 if (pcdev->platform_flags & PXA_CAMERA_HSP)
772 cicr4 |= CICR4_HSP;
773 if (pcdev->platform_flags & PXA_CAMERA_VSP)
774 cicr4 |= CICR4_VSP;
775
776 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
777
778 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
779 /* Initialise the timeout under the assumption pclk = mclk */
780 recalculate_fifo_timeout(pcdev, pcdev->mclk);
781 else
782 /* "Safe default" - 13MHz */
783 recalculate_fifo_timeout(pcdev, 13000000);
784
785 clk_enable(pcdev->clk);
786 }
787
788 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
789 {
790 clk_disable(pcdev->clk);
791 }
792
793 static irqreturn_t pxa_camera_irq(int irq, void *data)
794 {
795 struct pxa_camera_dev *pcdev = data;
796 unsigned long status, cicr0;
797
798 status = __raw_readl(pcdev->base + CISR);
799 dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status);
800
801 if (!status)
802 return IRQ_NONE;
803
804 __raw_writel(status, pcdev->base + CISR);
805
806 if (status & CISR_EOF) {
807 int i;
808 for (i = 0; i < pcdev->channels; i++) {
809 DDADR(pcdev->dma_chans[i]) =
810 pcdev->active->dmas[i].sg_dma;
811 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
812 }
813 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
814 __raw_writel(cicr0, pcdev->base + CICR0);
815 }
816
817 return IRQ_HANDLED;
818 }
819
820 /* The following two functions absolutely depend on the fact, that
821 * there can be only one camera on PXA quick capture interface */
822 static int pxa_camera_add_device(struct soc_camera_device *icd)
823 {
824 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
825 struct pxa_camera_dev *pcdev = ici->priv;
826 int ret;
827
828 mutex_lock(&camera_lock);
829
830 if (pcdev->icd) {
831 ret = -EBUSY;
832 goto ebusy;
833 }
834
835 dev_info(&icd->dev, "PXA Camera driver attached to camera %d\n",
836 icd->devnum);
837
838 pxa_camera_activate(pcdev);
839 ret = icd->ops->init(icd);
840
841 if (!ret)
842 pcdev->icd = icd;
843
844 ebusy:
845 mutex_unlock(&camera_lock);
846
847 return ret;
848 }
849
850 static void pxa_camera_remove_device(struct soc_camera_device *icd)
851 {
852 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
853 struct pxa_camera_dev *pcdev = ici->priv;
854
855 BUG_ON(icd != pcdev->icd);
856
857 dev_info(&icd->dev, "PXA Camera driver detached from camera %d\n",
858 icd->devnum);
859
860 /* disable capture, disable interrupts */
861 __raw_writel(0x3ff, pcdev->base + CICR0);
862
863 /* Stop DMA engine */
864 DCSR(pcdev->dma_chans[0]) = 0;
865 DCSR(pcdev->dma_chans[1]) = 0;
866 DCSR(pcdev->dma_chans[2]) = 0;
867
868 icd->ops->release(icd);
869
870 pxa_camera_deactivate(pcdev);
871
872 pcdev->icd = NULL;
873 }
874
875 static int test_platform_param(struct pxa_camera_dev *pcdev,
876 unsigned char buswidth, unsigned long *flags)
877 {
878 /*
879 * Platform specified synchronization and pixel clock polarities are
880 * only a recommendation and are only used during probing. The PXA270
881 * quick capture interface supports both.
882 */
883 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
884 SOCAM_MASTER : SOCAM_SLAVE) |
885 SOCAM_HSYNC_ACTIVE_HIGH |
886 SOCAM_HSYNC_ACTIVE_LOW |
887 SOCAM_VSYNC_ACTIVE_HIGH |
888 SOCAM_VSYNC_ACTIVE_LOW |
889 SOCAM_PCLK_SAMPLE_RISING |
890 SOCAM_PCLK_SAMPLE_FALLING;
891
892 /* If requested data width is supported by the platform, use it */
893 switch (buswidth) {
894 case 10:
895 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
896 return -EINVAL;
897 *flags |= SOCAM_DATAWIDTH_10;
898 break;
899 case 9:
900 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
901 return -EINVAL;
902 *flags |= SOCAM_DATAWIDTH_9;
903 break;
904 case 8:
905 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
906 return -EINVAL;
907 *flags |= SOCAM_DATAWIDTH_8;
908 break;
909 default:
910 return -EINVAL;
911 }
912
913 return 0;
914 }
915
916 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
917 {
918 struct soc_camera_host *ici =
919 to_soc_camera_host(icd->dev.parent);
920 struct pxa_camera_dev *pcdev = ici->priv;
921 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
922 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
923 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
924
925 if (ret < 0)
926 return ret;
927
928 camera_flags = icd->ops->query_bus_param(icd);
929
930 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
931 if (!common_flags)
932 return -EINVAL;
933
934 pcdev->channels = 1;
935
936 /* Make choises, based on platform preferences */
937 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
938 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
939 if (pcdev->platform_flags & PXA_CAMERA_HSP)
940 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
941 else
942 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
943 }
944
945 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
946 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
947 if (pcdev->platform_flags & PXA_CAMERA_VSP)
948 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
949 else
950 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
951 }
952
953 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
954 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
955 if (pcdev->platform_flags & PXA_CAMERA_PCP)
956 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
957 else
958 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
959 }
960
961 ret = icd->ops->set_bus_param(icd, common_flags);
962 if (ret < 0)
963 return ret;
964
965 /* Datawidth is now guaranteed to be equal to one of the three values.
966 * We fix bit-per-pixel equal to data-width... */
967 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
968 case SOCAM_DATAWIDTH_10:
969 dw = 4;
970 bpp = 0x40;
971 break;
972 case SOCAM_DATAWIDTH_9:
973 dw = 3;
974 bpp = 0x20;
975 break;
976 default:
977 /* Actually it can only be 8 now,
978 * default is just to silence compiler warnings */
979 case SOCAM_DATAWIDTH_8:
980 dw = 2;
981 bpp = 0;
982 }
983
984 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
985 cicr4 |= CICR4_PCLK_EN;
986 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
987 cicr4 |= CICR4_MCLK_EN;
988 if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
989 cicr4 |= CICR4_PCP;
990 if (common_flags & SOCAM_HSYNC_ACTIVE_LOW)
991 cicr4 |= CICR4_HSP;
992 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
993 cicr4 |= CICR4_VSP;
994
995 cicr0 = __raw_readl(pcdev->base + CICR0);
996 if (cicr0 & CICR0_ENB)
997 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
998
999 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
1000
1001 switch (pixfmt) {
1002 case V4L2_PIX_FMT_YUV422P:
1003 pcdev->channels = 3;
1004 cicr1 |= CICR1_YCBCR_F;
1005 /*
1006 * Normally, pxa bus wants as input UYVY format. We allow all
1007 * reorderings of the YUV422 format, as no processing is done,
1008 * and the YUV stream is just passed through without any
1009 * transformation. Note that UYVY is the only format that
1010 * should be used if pxa framebuffer Overlay2 is used.
1011 */
1012 case V4L2_PIX_FMT_UYVY:
1013 case V4L2_PIX_FMT_VYUY:
1014 case V4L2_PIX_FMT_YUYV:
1015 case V4L2_PIX_FMT_YVYU:
1016 cicr1 |= CICR1_COLOR_SP_VAL(2);
1017 break;
1018 case V4L2_PIX_FMT_RGB555:
1019 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1020 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1021 break;
1022 case V4L2_PIX_FMT_RGB565:
1023 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1024 break;
1025 }
1026
1027 cicr2 = 0;
1028 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
1029 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
1030 cicr4 |= pcdev->mclk_divisor;
1031
1032 __raw_writel(cicr1, pcdev->base + CICR1);
1033 __raw_writel(cicr2, pcdev->base + CICR2);
1034 __raw_writel(cicr3, pcdev->base + CICR3);
1035 __raw_writel(cicr4, pcdev->base + CICR4);
1036
1037 /* CIF interrupts are not used, only DMA */
1038 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1039 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1040 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1041 __raw_writel(cicr0, pcdev->base + CICR0);
1042
1043 return 0;
1044 }
1045
1046 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1047 unsigned char buswidth)
1048 {
1049 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1050 struct pxa_camera_dev *pcdev = ici->priv;
1051 unsigned long bus_flags, camera_flags;
1052 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1053
1054 if (ret < 0)
1055 return ret;
1056
1057 camera_flags = icd->ops->query_bus_param(icd);
1058
1059 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1060 }
1061
1062 static const struct soc_camera_data_format pxa_camera_formats[] = {
1063 {
1064 .name = "Planar YUV422 16 bit",
1065 .depth = 16,
1066 .fourcc = V4L2_PIX_FMT_YUV422P,
1067 .colorspace = V4L2_COLORSPACE_JPEG,
1068 },
1069 };
1070
1071 static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1072 {
1073 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1074 struct pxa_camera_dev *pcdev = ici->priv;
1075
1076 switch (depth) {
1077 case 8:
1078 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1079 case 9:
1080 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1081 case 10:
1082 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1083 }
1084 return false;
1085 }
1086
1087 static int required_buswidth(const struct soc_camera_data_format *fmt)
1088 {
1089 switch (fmt->fourcc) {
1090 case V4L2_PIX_FMT_UYVY:
1091 case V4L2_PIX_FMT_VYUY:
1092 case V4L2_PIX_FMT_YUYV:
1093 case V4L2_PIX_FMT_YVYU:
1094 case V4L2_PIX_FMT_RGB565:
1095 case V4L2_PIX_FMT_RGB555:
1096 return 8;
1097 default:
1098 return fmt->depth;
1099 }
1100 }
1101
1102 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1103 struct soc_camera_format_xlate *xlate)
1104 {
1105 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1106 int formats = 0, buswidth, ret;
1107
1108 buswidth = required_buswidth(icd->formats + idx);
1109
1110 if (!buswidth_supported(icd, buswidth))
1111 return 0;
1112
1113 ret = pxa_camera_try_bus_param(icd, buswidth);
1114 if (ret < 0)
1115 return 0;
1116
1117 switch (icd->formats[idx].fourcc) {
1118 case V4L2_PIX_FMT_UYVY:
1119 formats++;
1120 if (xlate) {
1121 xlate->host_fmt = &pxa_camera_formats[0];
1122 xlate->cam_fmt = icd->formats + idx;
1123 xlate->buswidth = buswidth;
1124 xlate++;
1125 dev_dbg(&ici->dev, "Providing format %s using %s\n",
1126 pxa_camera_formats[0].name,
1127 icd->formats[idx].name);
1128 }
1129 case V4L2_PIX_FMT_VYUY:
1130 case V4L2_PIX_FMT_YUYV:
1131 case V4L2_PIX_FMT_YVYU:
1132 case V4L2_PIX_FMT_RGB565:
1133 case V4L2_PIX_FMT_RGB555:
1134 formats++;
1135 if (xlate) {
1136 xlate->host_fmt = icd->formats + idx;
1137 xlate->cam_fmt = icd->formats + idx;
1138 xlate->buswidth = buswidth;
1139 xlate++;
1140 dev_dbg(&ici->dev, "Providing format %s packed\n",
1141 icd->formats[idx].name);
1142 }
1143 break;
1144 default:
1145 /* Generic pass-through */
1146 formats++;
1147 if (xlate) {
1148 xlate->host_fmt = icd->formats + idx;
1149 xlate->cam_fmt = icd->formats + idx;
1150 xlate->buswidth = icd->formats[idx].depth;
1151 xlate++;
1152 dev_dbg(&ici->dev,
1153 "Providing format %s in pass-through mode\n",
1154 icd->formats[idx].name);
1155 }
1156 }
1157
1158 return formats;
1159 }
1160
1161 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1162 __u32 pixfmt, struct v4l2_rect *rect)
1163 {
1164 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1165 struct pxa_camera_dev *pcdev = ici->priv;
1166 const struct soc_camera_data_format *host_fmt, *cam_fmt = NULL;
1167 const struct soc_camera_format_xlate *xlate;
1168 struct soc_camera_sense sense = {
1169 .master_clock = pcdev->mclk,
1170 .pixel_clock_max = pcdev->ciclk / 4,
1171 };
1172 int ret, buswidth;
1173
1174 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1175 if (!xlate) {
1176 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1177 return -EINVAL;
1178 }
1179
1180 buswidth = xlate->buswidth;
1181 host_fmt = xlate->host_fmt;
1182 cam_fmt = xlate->cam_fmt;
1183
1184 /* If PCLK is used to latch data from the sensor, check sense */
1185 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1186 icd->sense = &sense;
1187
1188 switch (pixfmt) {
1189 case 0: /* Only geometry change */
1190 ret = icd->ops->set_fmt(icd, pixfmt, rect);
1191 break;
1192 default:
1193 ret = icd->ops->set_fmt(icd, cam_fmt->fourcc, rect);
1194 }
1195
1196 icd->sense = NULL;
1197
1198 if (ret < 0) {
1199 dev_warn(&ici->dev, "Failed to configure for format %x\n",
1200 pixfmt);
1201 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1202 if (sense.pixel_clock > sense.pixel_clock_max) {
1203 dev_err(&ici->dev,
1204 "pixel clock %lu set by the camera too high!",
1205 sense.pixel_clock);
1206 return -EIO;
1207 }
1208 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1209 }
1210
1211 if (pixfmt && !ret) {
1212 icd->buswidth = buswidth;
1213 icd->current_fmt = host_fmt;
1214 }
1215
1216 return ret;
1217 }
1218
1219 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1220 struct v4l2_format *f)
1221 {
1222 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1223 const struct soc_camera_format_xlate *xlate;
1224 struct v4l2_pix_format *pix = &f->fmt.pix;
1225 __u32 pixfmt = pix->pixelformat;
1226
1227 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1228 if (!xlate) {
1229 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1230 return -EINVAL;
1231 }
1232
1233 /* limit to pxa hardware capabilities */
1234 if (pix->height < 32)
1235 pix->height = 32;
1236 if (pix->height > 2048)
1237 pix->height = 2048;
1238 if (pix->width < 48)
1239 pix->width = 48;
1240 if (pix->width > 2048)
1241 pix->width = 2048;
1242 pix->width &= ~0x01;
1243
1244 pix->bytesperline = pix->width *
1245 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1246 pix->sizeimage = pix->height * pix->bytesperline;
1247
1248 /* limit to sensor capabilities */
1249 return icd->ops->try_fmt(icd, f);
1250 }
1251
1252 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1253 struct v4l2_requestbuffers *p)
1254 {
1255 int i;
1256
1257 /* This is for locking debugging only. I removed spinlocks and now I
1258 * check whether .prepare is ever called on a linked buffer, or whether
1259 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1260 * it hadn't triggered */
1261 for (i = 0; i < p->count; i++) {
1262 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1263 struct pxa_buffer, vb);
1264 buf->inwork = 0;
1265 INIT_LIST_HEAD(&buf->vb.queue);
1266 }
1267
1268 return 0;
1269 }
1270
1271 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1272 {
1273 struct soc_camera_file *icf = file->private_data;
1274 struct pxa_buffer *buf;
1275
1276 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1277 vb.stream);
1278
1279 poll_wait(file, &buf->vb.done, pt);
1280
1281 if (buf->vb.state == VIDEOBUF_DONE ||
1282 buf->vb.state == VIDEOBUF_ERROR)
1283 return POLLIN|POLLRDNORM;
1284
1285 return 0;
1286 }
1287
1288 static int pxa_camera_querycap(struct soc_camera_host *ici,
1289 struct v4l2_capability *cap)
1290 {
1291 /* cap->name is set by the firendly caller:-> */
1292 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1293 cap->version = PXA_CAM_VERSION_CODE;
1294 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1295
1296 return 0;
1297 }
1298
1299 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1300 {
1301 struct soc_camera_host *ici =
1302 to_soc_camera_host(icd->dev.parent);
1303 struct pxa_camera_dev *pcdev = ici->priv;
1304 int i = 0, ret = 0;
1305
1306 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1307 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1308 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1309 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1310 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1311
1312 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1313 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1314
1315 return ret;
1316 }
1317
1318 static int pxa_camera_resume(struct soc_camera_device *icd)
1319 {
1320 struct soc_camera_host *ici =
1321 to_soc_camera_host(icd->dev.parent);
1322 struct pxa_camera_dev *pcdev = ici->priv;
1323 int i = 0, ret = 0;
1324
1325 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1326 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1327 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1328
1329 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1330 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1331 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1332 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1333 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1334
1335 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1336 ret = pcdev->icd->ops->resume(pcdev->icd);
1337
1338 /* Restart frame capture if active buffer exists */
1339 if (!ret && pcdev->active) {
1340 unsigned long cifr, cicr0;
1341
1342 /* Reset the FIFOs */
1343 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1344 __raw_writel(cifr, pcdev->base + CIFR);
1345
1346 cicr0 = __raw_readl(pcdev->base + CICR0);
1347 cicr0 &= ~CICR0_EOFM; /* Enable End-Of-Frame Interrupt */
1348 cicr0 |= CICR0_ENB; /* Restart the Capture Interface */
1349 __raw_writel(cicr0, pcdev->base + CICR0);
1350 }
1351
1352 return ret;
1353 }
1354
1355 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1356 .owner = THIS_MODULE,
1357 .add = pxa_camera_add_device,
1358 .remove = pxa_camera_remove_device,
1359 .suspend = pxa_camera_suspend,
1360 .resume = pxa_camera_resume,
1361 .get_formats = pxa_camera_get_formats,
1362 .set_fmt = pxa_camera_set_fmt,
1363 .try_fmt = pxa_camera_try_fmt,
1364 .init_videobuf = pxa_camera_init_videobuf,
1365 .reqbufs = pxa_camera_reqbufs,
1366 .poll = pxa_camera_poll,
1367 .querycap = pxa_camera_querycap,
1368 .set_bus_param = pxa_camera_set_bus_param,
1369 };
1370
1371 /* Should be allocated dynamically too, but we have only one. */
1372 static struct soc_camera_host pxa_soc_camera_host = {
1373 .drv_name = PXA_CAM_DRV_NAME,
1374 .ops = &pxa_soc_camera_host_ops,
1375 };
1376
1377 static int pxa_camera_probe(struct platform_device *pdev)
1378 {
1379 struct pxa_camera_dev *pcdev;
1380 struct resource *res;
1381 void __iomem *base;
1382 int irq;
1383 int err = 0;
1384
1385 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386 irq = platform_get_irq(pdev, 0);
1387 if (!res || irq < 0) {
1388 err = -ENODEV;
1389 goto exit;
1390 }
1391
1392 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1393 if (!pcdev) {
1394 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1395 err = -ENOMEM;
1396 goto exit;
1397 }
1398
1399 pcdev->clk = clk_get(&pdev->dev, "CAMCLK");
1400 if (IS_ERR(pcdev->clk)) {
1401 err = PTR_ERR(pcdev->clk);
1402 goto exit_kfree;
1403 }
1404
1405 dev_set_drvdata(&pdev->dev, pcdev);
1406 pcdev->res = res;
1407
1408 pcdev->pdata = pdev->dev.platform_data;
1409 pcdev->platform_flags = pcdev->pdata->flags;
1410 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1411 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1412 /* Platform hasn't set available data widths. This is bad.
1413 * Warn and use a default. */
1414 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1415 "data widths, using default 10 bit\n");
1416 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1417 }
1418 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1419 if (!pcdev->mclk) {
1420 dev_warn(&pdev->dev,
1421 "mclk == 0! Please, fix your platform data. "
1422 "Using default 20MHz\n");
1423 pcdev->mclk = 20000000;
1424 }
1425
1426 pcdev->dev = &pdev->dev;
1427 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1428
1429 INIT_LIST_HEAD(&pcdev->capture);
1430 spin_lock_init(&pcdev->lock);
1431
1432 /*
1433 * Request the regions.
1434 */
1435 if (!request_mem_region(res->start, res->end - res->start + 1,
1436 PXA_CAM_DRV_NAME)) {
1437 err = -EBUSY;
1438 goto exit_clk;
1439 }
1440
1441 base = ioremap(res->start, res->end - res->start + 1);
1442 if (!base) {
1443 err = -ENOMEM;
1444 goto exit_release;
1445 }
1446 pcdev->irq = irq;
1447 pcdev->base = base;
1448
1449 /* request dma */
1450 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1451 pxa_camera_dma_irq_y, pcdev);
1452 if (err < 0) {
1453 dev_err(pcdev->dev, "Can't request DMA for Y\n");
1454 goto exit_iounmap;
1455 }
1456 pcdev->dma_chans[0] = err;
1457 dev_dbg(pcdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1458
1459 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1460 pxa_camera_dma_irq_u, pcdev);
1461 if (err < 0) {
1462 dev_err(pcdev->dev, "Can't request DMA for U\n");
1463 goto exit_free_dma_y;
1464 }
1465 pcdev->dma_chans[1] = err;
1466 dev_dbg(pcdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1467
1468 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1469 pxa_camera_dma_irq_v, pcdev);
1470 if (err < 0) {
1471 dev_err(pcdev->dev, "Can't request DMA for V\n");
1472 goto exit_free_dma_u;
1473 }
1474 pcdev->dma_chans[2] = err;
1475 dev_dbg(pcdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1476
1477 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1478 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1479 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1480
1481 /* request irq */
1482 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1483 pcdev);
1484 if (err) {
1485 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1486 goto exit_free_dma;
1487 }
1488
1489 pxa_soc_camera_host.priv = pcdev;
1490 pxa_soc_camera_host.dev.parent = &pdev->dev;
1491 pxa_soc_camera_host.nr = pdev->id;
1492 err = soc_camera_host_register(&pxa_soc_camera_host);
1493 if (err)
1494 goto exit_free_irq;
1495
1496 return 0;
1497
1498 exit_free_irq:
1499 free_irq(pcdev->irq, pcdev);
1500 exit_free_dma:
1501 pxa_free_dma(pcdev->dma_chans[2]);
1502 exit_free_dma_u:
1503 pxa_free_dma(pcdev->dma_chans[1]);
1504 exit_free_dma_y:
1505 pxa_free_dma(pcdev->dma_chans[0]);
1506 exit_iounmap:
1507 iounmap(base);
1508 exit_release:
1509 release_mem_region(res->start, res->end - res->start + 1);
1510 exit_clk:
1511 clk_put(pcdev->clk);
1512 exit_kfree:
1513 kfree(pcdev);
1514 exit:
1515 return err;
1516 }
1517
1518 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1519 {
1520 struct pxa_camera_dev *pcdev = platform_get_drvdata(pdev);
1521 struct resource *res;
1522
1523 clk_put(pcdev->clk);
1524
1525 pxa_free_dma(pcdev->dma_chans[0]);
1526 pxa_free_dma(pcdev->dma_chans[1]);
1527 pxa_free_dma(pcdev->dma_chans[2]);
1528 free_irq(pcdev->irq, pcdev);
1529
1530 soc_camera_host_unregister(&pxa_soc_camera_host);
1531
1532 iounmap(pcdev->base);
1533
1534 res = pcdev->res;
1535 release_mem_region(res->start, res->end - res->start + 1);
1536
1537 kfree(pcdev);
1538
1539 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1540
1541 return 0;
1542 }
1543
1544 static struct platform_driver pxa_camera_driver = {
1545 .driver = {
1546 .name = PXA_CAM_DRV_NAME,
1547 },
1548 .probe = pxa_camera_probe,
1549 .remove = __exit_p(pxa_camera_remove),
1550 };
1551
1552
1553 static int __devinit pxa_camera_init(void)
1554 {
1555 return platform_driver_register(&pxa_camera_driver);
1556 }
1557
1558 static void __exit pxa_camera_exit(void)
1559 {
1560 platform_driver_unregister(&pxa_camera_driver);
1561 }
1562
1563 module_init(pxa_camera_init);
1564 module_exit(pxa_camera_exit);
1565
1566 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1567 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1568 MODULE_LICENSE("GPL");
kernel-based virtual machine