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mmc: block: inline command abortions
[linux-2.6/btrfs-unstable.git] / arch / arm / mach-davinci / devices-da8xx.c
blobc2457b3fdb5f0c2639d893379c1ed1b49d3b0296
1 /*
2 * DA8XX/OMAP L1XX platform device data
3 *
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13 #include <linux/init.h>
14 #include <linux/platform_data/syscon.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-contiguous.h>
17 #include <linux/serial_8250.h>
18 #include <linux/ahci_platform.h>
19 #include <linux/clk.h>
20 #include <linux/reboot.h>
21 #include <linux/dmaengine.h>
22
23 #include <mach/cputype.h>
24 #include <mach/common.h>
25 #include <mach/time.h>
26 #include <mach/da8xx.h>
27 #include "cpuidle.h"
28 #include "sram.h"
29
30 #include "clock.h"
31 #include "asp.h"
32
33 #define DA8XX_TPCC_BASE 0x01c00000
34 #define DA8XX_TPTC0_BASE 0x01c08000
35 #define DA8XX_TPTC1_BASE 0x01c08400
36 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
37 #define DA8XX_I2C0_BASE 0x01c22000
38 #define DA8XX_RTC_BASE 0x01c23000
39 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
40 #define DA8XX_MMCSD0_BASE 0x01c40000
41 #define DA8XX_SPI0_BASE 0x01c41000
42 #define DA830_SPI1_BASE 0x01e12000
43 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
44 #define DA850_SATA_BASE 0x01e18000
45 #define DA850_MMCSD1_BASE 0x01e1b000
46 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
47 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
48 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
49 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
50 #define DA8XX_I2C1_BASE 0x01e28000
51 #define DA850_TPCC1_BASE 0x01e30000
52 #define DA850_TPTC2_BASE 0x01e38000
53 #define DA850_SPI1_BASE 0x01f0e000
54 #define DA8XX_DDR2_CTL_BASE 0xb0000000
55
56 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
57 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
58 #define DA8XX_EMAC_RAM_OFFSET 0x0000
59 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
60
61 void __iomem *da8xx_syscfg0_base;
62 void __iomem *da8xx_syscfg1_base;
63
64 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
65 {
66 .mapbase = DA8XX_UART0_BASE,
67 .irq = IRQ_DA8XX_UARTINT0,
68 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
69 UPF_IOREMAP,
70 .iotype = UPIO_MEM,
71 .regshift = 2,
72 },
73 {
74 .flags = 0,
75 }
76 };
77 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
78 {
79 .mapbase = DA8XX_UART1_BASE,
80 .irq = IRQ_DA8XX_UARTINT1,
81 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
82 UPF_IOREMAP,
83 .iotype = UPIO_MEM,
84 .regshift = 2,
85 },
86 {
87 .flags = 0,
88 }
89 };
90 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
91 {
92 .mapbase = DA8XX_UART2_BASE,
93 .irq = IRQ_DA8XX_UARTINT2,
94 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
95 UPF_IOREMAP,
96 .iotype = UPIO_MEM,
97 .regshift = 2,
98 },
99 {
100 .flags = 0,
101 }
102 };
103
104 struct platform_device da8xx_serial_device[] = {
105 {
106 .name = "serial8250",
107 .id = PLAT8250_DEV_PLATFORM,
108 .dev = {
109 .platform_data = da8xx_serial0_pdata,
110 }
111 },
112 {
113 .name = "serial8250",
114 .id = PLAT8250_DEV_PLATFORM1,
115 .dev = {
116 .platform_data = da8xx_serial1_pdata,
117 }
118 },
119 {
120 .name = "serial8250",
121 .id = PLAT8250_DEV_PLATFORM2,
122 .dev = {
123 .platform_data = da8xx_serial2_pdata,
124 }
125 },
126 {
127 }
128 };
129
130 static s8 da8xx_queue_priority_mapping[][2] = {
131 /* {event queue no, Priority} */
132 {0, 3},
133 {1, 7},
134 {-1, -1}
135 };
136
137 static s8 da850_queue_priority_mapping[][2] = {
138 /* {event queue no, Priority} */
139 {0, 3},
140 {-1, -1}
141 };
142
143 static struct edma_soc_info da8xx_edma0_pdata = {
144 .queue_priority_mapping = da8xx_queue_priority_mapping,
145 .default_queue = EVENTQ_1,
146 };
147
148 static struct edma_soc_info da850_edma1_pdata = {
149 .queue_priority_mapping = da850_queue_priority_mapping,
150 .default_queue = EVENTQ_0,
151 };
152
153 static struct resource da8xx_edma0_resources[] = {
154 {
155 .name = "edma3_cc",
156 .start = DA8XX_TPCC_BASE,
157 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
158 .flags = IORESOURCE_MEM,
159 },
160 {
161 .name = "edma3_tc0",
162 .start = DA8XX_TPTC0_BASE,
163 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
164 .flags = IORESOURCE_MEM,
165 },
166 {
167 .name = "edma3_tc1",
168 .start = DA8XX_TPTC1_BASE,
169 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
170 .flags = IORESOURCE_MEM,
171 },
172 {
173 .name = "edma3_ccint",
174 .start = IRQ_DA8XX_CCINT0,
175 .flags = IORESOURCE_IRQ,
176 },
177 {
178 .name = "edma3_ccerrint",
179 .start = IRQ_DA8XX_CCERRINT,
180 .flags = IORESOURCE_IRQ,
181 },
182 };
183
184 static struct resource da850_edma1_resources[] = {
185 {
186 .name = "edma3_cc",
187 .start = DA850_TPCC1_BASE,
188 .end = DA850_TPCC1_BASE + SZ_32K - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .name = "edma3_tc0",
193 .start = DA850_TPTC2_BASE,
194 .end = DA850_TPTC2_BASE + SZ_1K - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 {
198 .name = "edma3_ccint",
199 .start = IRQ_DA850_CCINT1,
200 .flags = IORESOURCE_IRQ,
201 },
202 {
203 .name = "edma3_ccerrint",
204 .start = IRQ_DA850_CCERRINT1,
205 .flags = IORESOURCE_IRQ,
206 },
207 };
208
209 static const struct platform_device_info da8xx_edma0_device __initconst = {
210 .name = "edma",
211 .id = 0,
212 .dma_mask = DMA_BIT_MASK(32),
213 .res = da8xx_edma0_resources,
214 .num_res = ARRAY_SIZE(da8xx_edma0_resources),
215 .data = &da8xx_edma0_pdata,
216 .size_data = sizeof(da8xx_edma0_pdata),
217 };
218
219 static const struct platform_device_info da850_edma1_device __initconst = {
220 .name = "edma",
221 .id = 1,
222 .dma_mask = DMA_BIT_MASK(32),
223 .res = da850_edma1_resources,
224 .num_res = ARRAY_SIZE(da850_edma1_resources),
225 .data = &da850_edma1_pdata,
226 .size_data = sizeof(da850_edma1_pdata),
227 };
228
229 static const struct dma_slave_map da830_edma_map[] = {
230 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
231 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
232 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
233 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
234 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
235 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
236 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
237 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
238 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
239 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
240 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
241 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
242 };
243
244 int __init da830_register_edma(struct edma_rsv_info *rsv)
245 {
246 struct platform_device *edma_pdev;
247
248 da8xx_edma0_pdata.rsv = rsv;
249
250 da8xx_edma0_pdata.slave_map = da830_edma_map;
251 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
252
253 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
254 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
255 }
256
257 static const struct dma_slave_map da850_edma0_map[] = {
258 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
259 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
260 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
261 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
262 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
263 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
264 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
265 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
266 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
267 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
268 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
269 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
270 };
271
272 static const struct dma_slave_map da850_edma1_map[] = {
273 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
274 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
275 };
276
277 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
278 {
279 struct platform_device *edma_pdev;
280
281 if (rsv) {
282 da8xx_edma0_pdata.rsv = rsv[0];
283 da850_edma1_pdata.rsv = rsv[1];
284 }
285
286 da8xx_edma0_pdata.slave_map = da850_edma0_map;
287 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
288
289 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
290 if (IS_ERR(edma_pdev)) {
291 pr_warn("%s: Failed to register eDMA0\n", __func__);
292 return PTR_ERR(edma_pdev);
293 }
294
295 da850_edma1_pdata.slave_map = da850_edma1_map;
296 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
297
298 edma_pdev = platform_device_register_full(&da850_edma1_device);
299 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
300 }
301
302 static struct resource da8xx_i2c_resources0[] = {
303 {
304 .start = DA8XX_I2C0_BASE,
305 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = IRQ_DA8XX_I2CINT0,
310 .end = IRQ_DA8XX_I2CINT0,
311 .flags = IORESOURCE_IRQ,
312 },
313 };
314
315 static struct platform_device da8xx_i2c_device0 = {
316 .name = "i2c_davinci",
317 .id = 1,
318 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
319 .resource = da8xx_i2c_resources0,
320 };
321
322 static struct resource da8xx_i2c_resources1[] = {
323 {
324 .start = DA8XX_I2C1_BASE,
325 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
326 .flags = IORESOURCE_MEM,
327 },
328 {
329 .start = IRQ_DA8XX_I2CINT1,
330 .end = IRQ_DA8XX_I2CINT1,
331 .flags = IORESOURCE_IRQ,
332 },
333 };
334
335 static struct platform_device da8xx_i2c_device1 = {
336 .name = "i2c_davinci",
337 .id = 2,
338 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
339 .resource = da8xx_i2c_resources1,
340 };
341
342 int __init da8xx_register_i2c(int instance,
343 struct davinci_i2c_platform_data *pdata)
344 {
345 struct platform_device *pdev;
346
347 if (instance == 0)
348 pdev = &da8xx_i2c_device0;
349 else if (instance == 1)
350 pdev = &da8xx_i2c_device1;
351 else
352 return -EINVAL;
353
354 pdev->dev.platform_data = pdata;
355 return platform_device_register(pdev);
356 }
357
358 static struct resource da8xx_watchdog_resources[] = {
359 {
360 .start = DA8XX_WDOG_BASE,
361 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
362 .flags = IORESOURCE_MEM,
363 },
364 };
365
366 static struct platform_device da8xx_wdt_device = {
367 .name = "davinci-wdt",
368 .id = -1,
369 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
370 .resource = da8xx_watchdog_resources,
371 };
372
373 void da8xx_restart(enum reboot_mode mode, const char *cmd)
374 {
375 struct device *dev;
376
377 dev = bus_find_device_by_name(&platform_bus_type, NULL, "davinci-wdt");
378 if (!dev) {
379 pr_err("%s: failed to find watchdog device\n", __func__);
380 return;
381 }
382
383 davinci_watchdog_reset(to_platform_device(dev));
384 }
385
386 int __init da8xx_register_watchdog(void)
387 {
388 return platform_device_register(&da8xx_wdt_device);
389 }
390
391 static struct resource da8xx_emac_resources[] = {
392 {
393 .start = DA8XX_EMAC_CPPI_PORT_BASE,
394 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
395 .flags = IORESOURCE_MEM,
396 },
397 {
398 .start = IRQ_DA8XX_C0_RX_THRESH_PULSE,
399 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
400 .flags = IORESOURCE_IRQ,
401 },
402 {
403 .start = IRQ_DA8XX_C0_RX_PULSE,
404 .end = IRQ_DA8XX_C0_RX_PULSE,
405 .flags = IORESOURCE_IRQ,
406 },
407 {
408 .start = IRQ_DA8XX_C0_TX_PULSE,
409 .end = IRQ_DA8XX_C0_TX_PULSE,
410 .flags = IORESOURCE_IRQ,
411 },
412 {
413 .start = IRQ_DA8XX_C0_MISC_PULSE,
414 .end = IRQ_DA8XX_C0_MISC_PULSE,
415 .flags = IORESOURCE_IRQ,
416 },
417 };
418
419 struct emac_platform_data da8xx_emac_pdata = {
420 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
421 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
422 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
423 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
424 .version = EMAC_VERSION_2,
425 };
426
427 static struct platform_device da8xx_emac_device = {
428 .name = "davinci_emac",
429 .id = 1,
430 .dev = {
431 .platform_data = &da8xx_emac_pdata,
432 },
433 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
434 .resource = da8xx_emac_resources,
435 };
436
437 static struct resource da8xx_mdio_resources[] = {
438 {
439 .start = DA8XX_EMAC_MDIO_BASE,
440 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
441 .flags = IORESOURCE_MEM,
442 },
443 };
444
445 static struct platform_device da8xx_mdio_device = {
446 .name = "davinci_mdio",
447 .id = 0,
448 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
449 .resource = da8xx_mdio_resources,
450 };
451
452 int __init da8xx_register_emac(void)
453 {
454 int ret;
455
456 ret = platform_device_register(&da8xx_mdio_device);
457 if (ret < 0)
458 return ret;
459
460 return platform_device_register(&da8xx_emac_device);
461 }
462
463 static struct resource da830_mcasp1_resources[] = {
464 {
465 .name = "mpu",
466 .start = DAVINCI_DA830_MCASP1_REG_BASE,
467 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
468 .flags = IORESOURCE_MEM,
469 },
470 /* TX event */
471 {
472 .name = "tx",
473 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
474 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
475 .flags = IORESOURCE_DMA,
476 },
477 /* RX event */
478 {
479 .name = "rx",
480 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
481 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
482 .flags = IORESOURCE_DMA,
483 },
484 {
485 .name = "common",
486 .start = IRQ_DA8XX_MCASPINT,
487 .flags = IORESOURCE_IRQ,
488 },
489 };
490
491 static struct platform_device da830_mcasp1_device = {
492 .name = "davinci-mcasp",
493 .id = 1,
494 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
495 .resource = da830_mcasp1_resources,
496 };
497
498 static struct resource da830_mcasp2_resources[] = {
499 {
500 .name = "mpu",
501 .start = DAVINCI_DA830_MCASP2_REG_BASE,
502 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
503 .flags = IORESOURCE_MEM,
504 },
505 /* TX event */
506 {
507 .name = "tx",
508 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
509 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
510 .flags = IORESOURCE_DMA,
511 },
512 /* RX event */
513 {
514 .name = "rx",
515 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
516 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
517 .flags = IORESOURCE_DMA,
518 },
519 {
520 .name = "common",
521 .start = IRQ_DA8XX_MCASPINT,
522 .flags = IORESOURCE_IRQ,
523 },
524 };
525
526 static struct platform_device da830_mcasp2_device = {
527 .name = "davinci-mcasp",
528 .id = 2,
529 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
530 .resource = da830_mcasp2_resources,
531 };
532
533 static struct resource da850_mcasp_resources[] = {
534 {
535 .name = "mpu",
536 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
537 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
538 .flags = IORESOURCE_MEM,
539 },
540 /* TX event */
541 {
542 .name = "tx",
543 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
544 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
545 .flags = IORESOURCE_DMA,
546 },
547 /* RX event */
548 {
549 .name = "rx",
550 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
551 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
552 .flags = IORESOURCE_DMA,
553 },
554 {
555 .name = "common",
556 .start = IRQ_DA8XX_MCASPINT,
557 .flags = IORESOURCE_IRQ,
558 },
559 };
560
561 static struct platform_device da850_mcasp_device = {
562 .name = "davinci-mcasp",
563 .id = 0,
564 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
565 .resource = da850_mcasp_resources,
566 };
567
568 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
569 {
570 struct platform_device *pdev;
571
572 switch (id) {
573 case 0:
574 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
575 pdev = &da850_mcasp_device;
576 break;
577 case 1:
578 /* Valid for DA830/OMAP-L137 only */
579 if (!cpu_is_davinci_da830())
580 return;
581 pdev = &da830_mcasp1_device;
582 break;
583 case 2:
584 /* Valid for DA830/OMAP-L137 only */
585 if (!cpu_is_davinci_da830())
586 return;
587 pdev = &da830_mcasp2_device;
588 break;
589 default:
590 return;
591 }
592
593 pdev->dev.platform_data = pdata;
594 platform_device_register(pdev);
595 }
596
597 static struct resource da8xx_pruss_resources[] = {
598 {
599 .start = DA8XX_PRUSS_MEM_BASE,
600 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
601 .flags = IORESOURCE_MEM,
602 },
603 {
604 .start = IRQ_DA8XX_EVTOUT0,
605 .end = IRQ_DA8XX_EVTOUT0,
606 .flags = IORESOURCE_IRQ,
607 },
608 {
609 .start = IRQ_DA8XX_EVTOUT1,
610 .end = IRQ_DA8XX_EVTOUT1,
611 .flags = IORESOURCE_IRQ,
612 },
613 {
614 .start = IRQ_DA8XX_EVTOUT2,
615 .end = IRQ_DA8XX_EVTOUT2,
616 .flags = IORESOURCE_IRQ,
617 },
618 {
619 .start = IRQ_DA8XX_EVTOUT3,
620 .end = IRQ_DA8XX_EVTOUT3,
621 .flags = IORESOURCE_IRQ,
622 },
623 {
624 .start = IRQ_DA8XX_EVTOUT4,
625 .end = IRQ_DA8XX_EVTOUT4,
626 .flags = IORESOURCE_IRQ,
627 },
628 {
629 .start = IRQ_DA8XX_EVTOUT5,
630 .end = IRQ_DA8XX_EVTOUT5,
631 .flags = IORESOURCE_IRQ,
632 },
633 {
634 .start = IRQ_DA8XX_EVTOUT6,
635 .end = IRQ_DA8XX_EVTOUT6,
636 .flags = IORESOURCE_IRQ,
637 },
638 {
639 .start = IRQ_DA8XX_EVTOUT7,
640 .end = IRQ_DA8XX_EVTOUT7,
641 .flags = IORESOURCE_IRQ,
642 },
643 };
644
645 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
646 .pintc_base = 0x4000,
647 };
648
649 static struct platform_device da8xx_uio_pruss_dev = {
650 .name = "pruss_uio",
651 .id = -1,
652 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
653 .resource = da8xx_pruss_resources,
654 .dev = {
655 .coherent_dma_mask = DMA_BIT_MASK(32),
656 .platform_data = &da8xx_uio_pruss_pdata,
657 }
658 };
659
660 int __init da8xx_register_uio_pruss(void)
661 {
662 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
663 return platform_device_register(&da8xx_uio_pruss_dev);
664 }
665
666 static struct lcd_ctrl_config lcd_cfg = {
667 .panel_shade = COLOR_ACTIVE,
668 .bpp = 16,
669 };
670
671 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
672 .manu_name = "sharp",
673 .controller_data = &lcd_cfg,
674 .type = "Sharp_LCD035Q3DG01",
675 };
676
677 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
678 .manu_name = "sharp",
679 .controller_data = &lcd_cfg,
680 .type = "Sharp_LK043T1DG01",
681 };
682
683 static struct resource da8xx_lcdc_resources[] = {
684 [0] = { /* registers */
685 .start = DA8XX_LCD_CNTRL_BASE,
686 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
687 .flags = IORESOURCE_MEM,
688 },
689 [1] = { /* interrupt */
690 .start = IRQ_DA8XX_LCDINT,
691 .end = IRQ_DA8XX_LCDINT,
692 .flags = IORESOURCE_IRQ,
693 },
694 };
695
696 static struct platform_device da8xx_lcdc_device = {
697 .name = "da8xx_lcdc",
698 .id = 0,
699 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
700 .resource = da8xx_lcdc_resources,
701 };
702
703 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
704 {
705 da8xx_lcdc_device.dev.platform_data = pdata;
706 return platform_device_register(&da8xx_lcdc_device);
707 }
708
709 static struct resource da8xx_gpio_resources[] = {
710 { /* registers */
711 .start = DA8XX_GPIO_BASE,
712 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
713 .flags = IORESOURCE_MEM,
714 },
715 { /* interrupt */
716 .start = IRQ_DA8XX_GPIO0,
717 .end = IRQ_DA8XX_GPIO8,
718 .flags = IORESOURCE_IRQ,
719 },
720 };
721
722 static struct platform_device da8xx_gpio_device = {
723 .name = "davinci_gpio",
724 .id = -1,
725 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
726 .resource = da8xx_gpio_resources,
727 };
728
729 int __init da8xx_register_gpio(void *pdata)
730 {
731 da8xx_gpio_device.dev.platform_data = pdata;
732 return platform_device_register(&da8xx_gpio_device);
733 }
734
735 static struct resource da8xx_mmcsd0_resources[] = {
736 { /* registers */
737 .start = DA8XX_MMCSD0_BASE,
738 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
739 .flags = IORESOURCE_MEM,
740 },
741 { /* interrupt */
742 .start = IRQ_DA8XX_MMCSDINT0,
743 .end = IRQ_DA8XX_MMCSDINT0,
744 .flags = IORESOURCE_IRQ,
745 },
746 };
747
748 static struct platform_device da8xx_mmcsd0_device = {
749 .name = "da830-mmc",
750 .id = 0,
751 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
752 .resource = da8xx_mmcsd0_resources,
753 };
754
755 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
756 {
757 da8xx_mmcsd0_device.dev.platform_data = config;
758 return platform_device_register(&da8xx_mmcsd0_device);
759 }
760
761 #ifdef CONFIG_ARCH_DAVINCI_DA850
762 static struct resource da850_mmcsd1_resources[] = {
763 { /* registers */
764 .start = DA850_MMCSD1_BASE,
765 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
766 .flags = IORESOURCE_MEM,
767 },
768 { /* interrupt */
769 .start = IRQ_DA850_MMCSDINT0_1,
770 .end = IRQ_DA850_MMCSDINT0_1,
771 .flags = IORESOURCE_IRQ,
772 },
773 };
774
775 static struct platform_device da850_mmcsd1_device = {
776 .name = "da830-mmc",
777 .id = 1,
778 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
779 .resource = da850_mmcsd1_resources,
780 };
781
782 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
783 {
784 da850_mmcsd1_device.dev.platform_data = config;
785 return platform_device_register(&da850_mmcsd1_device);
786 }
787 #endif
788
789 static struct resource da8xx_rproc_resources[] = {
790 { /* DSP boot address */
791 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
792 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
793 .flags = IORESOURCE_MEM,
794 },
795 { /* DSP interrupt registers */
796 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
797 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
798 .flags = IORESOURCE_MEM,
799 },
800 { /* dsp irq */
801 .start = IRQ_DA8XX_CHIPINT0,
802 .end = IRQ_DA8XX_CHIPINT0,
803 .flags = IORESOURCE_IRQ,
804 },
805 };
806
807 static struct platform_device da8xx_dsp = {
808 .name = "davinci-rproc",
809 .dev = {
810 .coherent_dma_mask = DMA_BIT_MASK(32),
811 },
812 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
813 .resource = da8xx_rproc_resources,
814 };
815
816 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
817
818 static phys_addr_t rproc_base __initdata;
819 static unsigned long rproc_size __initdata;
820
821 static int __init early_rproc_mem(char *p)
822 {
823 char *endp;
824
825 if (p == NULL)
826 return 0;
827
828 rproc_size = memparse(p, &endp);
829 if (*endp == '@')
830 rproc_base = memparse(endp + 1, NULL);
831
832 return 0;
833 }
834 early_param("rproc_mem", early_rproc_mem);
835
836 void __init da8xx_rproc_reserve_cma(void)
837 {
838 int ret;
839
840 if (!rproc_base || !rproc_size) {
841 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
842 " 'nn' and 'address' must both be non-zero\n",
843 __func__);
844
845 return;
846 }
847
848 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
849 __func__, rproc_size, (unsigned long)rproc_base);
850
851 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
852 if (ret)
853 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
854 }
855
856 #else
857
858 void __init da8xx_rproc_reserve_cma(void)
859 {
860 }
861
862 #endif
863
864 int __init da8xx_register_rproc(void)
865 {
866 int ret;
867
868 ret = platform_device_register(&da8xx_dsp);
869 if (ret)
870 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
871
872 return ret;
873 };
874
875 static struct resource da8xx_rtc_resources[] = {
876 {
877 .start = DA8XX_RTC_BASE,
878 .end = DA8XX_RTC_BASE + SZ_4K - 1,
879 .flags = IORESOURCE_MEM,
880 },
881 { /* timer irq */
882 .start = IRQ_DA8XX_RTC,
883 .end = IRQ_DA8XX_RTC,
884 .flags = IORESOURCE_IRQ,
885 },
886 { /* alarm irq */
887 .start = IRQ_DA8XX_RTC,
888 .end = IRQ_DA8XX_RTC,
889 .flags = IORESOURCE_IRQ,
890 },
891 };
892
893 static struct platform_device da8xx_rtc_device = {
894 .name = "da830-rtc",
895 .id = -1,
896 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
897 .resource = da8xx_rtc_resources,
898 };
899
900 int da8xx_register_rtc(void)
901 {
902 return platform_device_register(&da8xx_rtc_device);
903 }
904
905 static void __iomem *da8xx_ddr2_ctlr_base;
906 void __iomem * __init da8xx_get_mem_ctlr(void)
907 {
908 if (da8xx_ddr2_ctlr_base)
909 return da8xx_ddr2_ctlr_base;
910
911 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
912 if (!da8xx_ddr2_ctlr_base)
913 pr_warn("%s: Unable to map DDR2 controller", __func__);
914
915 return da8xx_ddr2_ctlr_base;
916 }
917
918 static struct resource da8xx_cpuidle_resources[] = {
919 {
920 .start = DA8XX_DDR2_CTL_BASE,
921 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
922 .flags = IORESOURCE_MEM,
923 },
924 };
925
926 /* DA8XX devices support DDR2 power down */
927 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
928 .ddr2_pdown = 1,
929 };
930
931
932 static struct platform_device da8xx_cpuidle_device = {
933 .name = "cpuidle-davinci",
934 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
935 .resource = da8xx_cpuidle_resources,
936 .dev = {
937 .platform_data = &da8xx_cpuidle_pdata,
938 },
939 };
940
941 int __init da8xx_register_cpuidle(void)
942 {
943 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
944
945 return platform_device_register(&da8xx_cpuidle_device);
946 }
947
948 static struct resource da8xx_spi0_resources[] = {
949 [0] = {
950 .start = DA8XX_SPI0_BASE,
951 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
952 .flags = IORESOURCE_MEM,
953 },
954 [1] = {
955 .start = IRQ_DA8XX_SPINT0,
956 .end = IRQ_DA8XX_SPINT0,
957 .flags = IORESOURCE_IRQ,
958 },
959 };
960
961 static struct resource da8xx_spi1_resources[] = {
962 [0] = {
963 .start = DA830_SPI1_BASE,
964 .end = DA830_SPI1_BASE + SZ_4K - 1,
965 .flags = IORESOURCE_MEM,
966 },
967 [1] = {
968 .start = IRQ_DA8XX_SPINT1,
969 .end = IRQ_DA8XX_SPINT1,
970 .flags = IORESOURCE_IRQ,
971 },
972 };
973
974 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
975 [0] = {
976 .version = SPI_VERSION_2,
977 .intr_line = 1,
978 .dma_event_q = EVENTQ_0,
979 .prescaler_limit = 2,
980 },
981 [1] = {
982 .version = SPI_VERSION_2,
983 .intr_line = 1,
984 .dma_event_q = EVENTQ_0,
985 .prescaler_limit = 2,
986 },
987 };
988
989 static struct platform_device da8xx_spi_device[] = {
990 [0] = {
991 .name = "spi_davinci",
992 .id = 0,
993 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
994 .resource = da8xx_spi0_resources,
995 .dev = {
996 .platform_data = &da8xx_spi_pdata[0],
997 },
998 },
999 [1] = {
1000 .name = "spi_davinci",
1001 .id = 1,
1002 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1003 .resource = da8xx_spi1_resources,
1004 .dev = {
1005 .platform_data = &da8xx_spi_pdata[1],
1006 },
1007 },
1008 };
1009
1010 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1011 {
1012 if (instance < 0 || instance > 1)
1013 return -EINVAL;
1014
1015 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1016
1017 if (instance == 1 && cpu_is_davinci_da850()) {
1018 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1019 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1020 }
1021
1022 return platform_device_register(&da8xx_spi_device[instance]);
1023 }
1024
1025 #ifdef CONFIG_ARCH_DAVINCI_DA850
1026 static struct resource da850_sata_resources[] = {
1027 {
1028 .start = DA850_SATA_BASE,
1029 .end = DA850_SATA_BASE + 0x1fff,
1030 .flags = IORESOURCE_MEM,
1031 },
1032 {
1033 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1034 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1035 .flags = IORESOURCE_MEM,
1036 },
1037 {
1038 .start = IRQ_DA850_SATAINT,
1039 .flags = IORESOURCE_IRQ,
1040 },
1041 };
1042
1043 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1044
1045 static struct platform_device da850_sata_device = {
1046 .name = "ahci_da850",
1047 .id = -1,
1048 .dev = {
1049 .dma_mask = &da850_sata_dmamask,
1050 .coherent_dma_mask = DMA_BIT_MASK(32),
1051 },
1052 .num_resources = ARRAY_SIZE(da850_sata_resources),
1053 .resource = da850_sata_resources,
1054 };
1055
1056 int __init da850_register_sata(unsigned long refclkpn)
1057 {
1058 /* please see comment in drivers/ata/ahci_da850.c */
1059 BUG_ON(refclkpn != 100 * 1000 * 1000);
1060
1061 return platform_device_register(&da850_sata_device);
1062 }
1063 #endif
1064
1065 static struct syscon_platform_data da8xx_cfgchip_platform_data = {
1066 .label = "cfgchip",
1067 };
1068
1069 static struct resource da8xx_cfgchip_resources[] = {
1070 {
1071 .start = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP0_REG,
1072 .end = DA8XX_SYSCFG0_BASE + DA8XX_CFGCHIP4_REG + 3,
1073 .flags = IORESOURCE_MEM,
1074 },
1075 };
1076
1077 static struct platform_device da8xx_cfgchip_device = {
1078 .name = "syscon",
1079 .id = -1,
1080 .dev = {
1081 .platform_data = &da8xx_cfgchip_platform_data,
1082 },
1083 .num_resources = ARRAY_SIZE(da8xx_cfgchip_resources),
1084 .resource = da8xx_cfgchip_resources,
1085 };
1086
1087 int __init da8xx_register_cfgchip(void)
1088 {
1089 return platform_device_register(&da8xx_cfgchip_device);
1090 }
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