2 * DA8XX/OMAP L1XX platform device data
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/ahci_platform.h>
14 #include <linux/clk-provider.h>
15 #include <linux/clk.h>
16 #include <linux/clkdev.h>
17 #include <linux/dma-contiguous.h>
18 #include <linux/dmaengine.h>
19 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/reboot.h>
22 #include <linux/serial_8250.h>
24 #include <mach/common.h>
25 #include <mach/cputype.h>
26 #include <mach/da8xx.h>
27 #include <mach/time.h>
33 #define DA8XX_TPCC_BASE 0x01c00000
34 #define DA8XX_TPTC0_BASE 0x01c08000
35 #define DA8XX_TPTC1_BASE 0x01c08400
36 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
37 #define DA8XX_I2C0_BASE 0x01c22000
38 #define DA8XX_RTC_BASE 0x01c23000
39 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
40 #define DA8XX_MMCSD0_BASE 0x01c40000
41 #define DA8XX_SPI0_BASE 0x01c41000
42 #define DA830_SPI1_BASE 0x01e12000
43 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
44 #define DA850_SATA_BASE 0x01e18000
45 #define DA850_MMCSD1_BASE 0x01e1b000
46 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
47 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
48 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
49 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
50 #define DA8XX_I2C1_BASE 0x01e28000
51 #define DA850_TPCC1_BASE 0x01e30000
52 #define DA850_TPTC2_BASE 0x01e38000
53 #define DA850_SPI1_BASE 0x01f0e000
54 #define DA8XX_DDR2_CTL_BASE 0xb0000000
56 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
57 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
58 #define DA8XX_EMAC_RAM_OFFSET 0x0000
59 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
61 void __iomem
*da8xx_syscfg0_base
;
62 void __iomem
*da8xx_syscfg1_base
;
64 static struct plat_serial8250_port da8xx_serial0_pdata
[] = {
66 .mapbase
= DA8XX_UART0_BASE
,
67 .irq
= IRQ_DA8XX_UARTINT0
,
68 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
77 static struct plat_serial8250_port da8xx_serial1_pdata
[] = {
79 .mapbase
= DA8XX_UART1_BASE
,
80 .irq
= IRQ_DA8XX_UARTINT1
,
81 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
90 static struct plat_serial8250_port da8xx_serial2_pdata
[] = {
92 .mapbase
= DA8XX_UART2_BASE
,
93 .irq
= IRQ_DA8XX_UARTINT2
,
94 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
104 struct platform_device da8xx_serial_device
[] = {
106 .name
= "serial8250",
107 .id
= PLAT8250_DEV_PLATFORM
,
109 .platform_data
= da8xx_serial0_pdata
,
113 .name
= "serial8250",
114 .id
= PLAT8250_DEV_PLATFORM1
,
116 .platform_data
= da8xx_serial1_pdata
,
120 .name
= "serial8250",
121 .id
= PLAT8250_DEV_PLATFORM2
,
123 .platform_data
= da8xx_serial2_pdata
,
130 static s8 da8xx_queue_priority_mapping
[][2] = {
131 /* {event queue no, Priority} */
137 static s8 da850_queue_priority_mapping
[][2] = {
138 /* {event queue no, Priority} */
143 static struct edma_soc_info da8xx_edma0_pdata
= {
144 .queue_priority_mapping
= da8xx_queue_priority_mapping
,
145 .default_queue
= EVENTQ_1
,
148 static struct edma_soc_info da850_edma1_pdata
= {
149 .queue_priority_mapping
= da850_queue_priority_mapping
,
150 .default_queue
= EVENTQ_0
,
153 static struct resource da8xx_edma0_resources
[] = {
156 .start
= DA8XX_TPCC_BASE
,
157 .end
= DA8XX_TPCC_BASE
+ SZ_32K
- 1,
158 .flags
= IORESOURCE_MEM
,
162 .start
= DA8XX_TPTC0_BASE
,
163 .end
= DA8XX_TPTC0_BASE
+ SZ_1K
- 1,
164 .flags
= IORESOURCE_MEM
,
168 .start
= DA8XX_TPTC1_BASE
,
169 .end
= DA8XX_TPTC1_BASE
+ SZ_1K
- 1,
170 .flags
= IORESOURCE_MEM
,
173 .name
= "edma3_ccint",
174 .start
= IRQ_DA8XX_CCINT0
,
175 .flags
= IORESOURCE_IRQ
,
178 .name
= "edma3_ccerrint",
179 .start
= IRQ_DA8XX_CCERRINT
,
180 .flags
= IORESOURCE_IRQ
,
184 static struct resource da850_edma1_resources
[] = {
187 .start
= DA850_TPCC1_BASE
,
188 .end
= DA850_TPCC1_BASE
+ SZ_32K
- 1,
189 .flags
= IORESOURCE_MEM
,
193 .start
= DA850_TPTC2_BASE
,
194 .end
= DA850_TPTC2_BASE
+ SZ_1K
- 1,
195 .flags
= IORESOURCE_MEM
,
198 .name
= "edma3_ccint",
199 .start
= IRQ_DA850_CCINT1
,
200 .flags
= IORESOURCE_IRQ
,
203 .name
= "edma3_ccerrint",
204 .start
= IRQ_DA850_CCERRINT1
,
205 .flags
= IORESOURCE_IRQ
,
209 static const struct platform_device_info da8xx_edma0_device __initconst
= {
212 .dma_mask
= DMA_BIT_MASK(32),
213 .res
= da8xx_edma0_resources
,
214 .num_res
= ARRAY_SIZE(da8xx_edma0_resources
),
215 .data
= &da8xx_edma0_pdata
,
216 .size_data
= sizeof(da8xx_edma0_pdata
),
219 static const struct platform_device_info da850_edma1_device __initconst
= {
222 .dma_mask
= DMA_BIT_MASK(32),
223 .res
= da850_edma1_resources
,
224 .num_res
= ARRAY_SIZE(da850_edma1_resources
),
225 .data
= &da850_edma1_pdata
,
226 .size_data
= sizeof(da850_edma1_pdata
),
229 static const struct dma_slave_map da830_edma_map
[] = {
230 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
231 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
232 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
233 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
234 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
235 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
236 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
237 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
238 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
239 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
240 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
241 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
244 int __init
da830_register_edma(struct edma_rsv_info
*rsv
)
246 struct platform_device
*edma_pdev
;
248 da8xx_edma0_pdata
.rsv
= rsv
;
250 da8xx_edma0_pdata
.slave_map
= da830_edma_map
;
251 da8xx_edma0_pdata
.slavecnt
= ARRAY_SIZE(da830_edma_map
);
253 edma_pdev
= platform_device_register_full(&da8xx_edma0_device
);
254 return PTR_ERR_OR_ZERO(edma_pdev
);
257 static const struct dma_slave_map da850_edma0_map
[] = {
258 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
259 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
260 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
261 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
262 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
263 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
264 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
265 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
266 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
267 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
268 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
269 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
272 static const struct dma_slave_map da850_edma1_map
[] = {
273 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
274 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
277 int __init
da850_register_edma(struct edma_rsv_info
*rsv
[2])
279 struct platform_device
*edma_pdev
;
282 da8xx_edma0_pdata
.rsv
= rsv
[0];
283 da850_edma1_pdata
.rsv
= rsv
[1];
286 da8xx_edma0_pdata
.slave_map
= da850_edma0_map
;
287 da8xx_edma0_pdata
.slavecnt
= ARRAY_SIZE(da850_edma0_map
);
289 edma_pdev
= platform_device_register_full(&da8xx_edma0_device
);
290 if (IS_ERR(edma_pdev
)) {
291 pr_warn("%s: Failed to register eDMA0\n", __func__
);
292 return PTR_ERR(edma_pdev
);
295 da850_edma1_pdata
.slave_map
= da850_edma1_map
;
296 da850_edma1_pdata
.slavecnt
= ARRAY_SIZE(da850_edma1_map
);
298 edma_pdev
= platform_device_register_full(&da850_edma1_device
);
299 return PTR_ERR_OR_ZERO(edma_pdev
);
302 static struct resource da8xx_i2c_resources0
[] = {
304 .start
= DA8XX_I2C0_BASE
,
305 .end
= DA8XX_I2C0_BASE
+ SZ_4K
- 1,
306 .flags
= IORESOURCE_MEM
,
309 .start
= IRQ_DA8XX_I2CINT0
,
310 .end
= IRQ_DA8XX_I2CINT0
,
311 .flags
= IORESOURCE_IRQ
,
315 static struct platform_device da8xx_i2c_device0
= {
316 .name
= "i2c_davinci",
318 .num_resources
= ARRAY_SIZE(da8xx_i2c_resources0
),
319 .resource
= da8xx_i2c_resources0
,
322 static struct resource da8xx_i2c_resources1
[] = {
324 .start
= DA8XX_I2C1_BASE
,
325 .end
= DA8XX_I2C1_BASE
+ SZ_4K
- 1,
326 .flags
= IORESOURCE_MEM
,
329 .start
= IRQ_DA8XX_I2CINT1
,
330 .end
= IRQ_DA8XX_I2CINT1
,
331 .flags
= IORESOURCE_IRQ
,
335 static struct platform_device da8xx_i2c_device1
= {
336 .name
= "i2c_davinci",
338 .num_resources
= ARRAY_SIZE(da8xx_i2c_resources1
),
339 .resource
= da8xx_i2c_resources1
,
342 int __init
da8xx_register_i2c(int instance
,
343 struct davinci_i2c_platform_data
*pdata
)
345 struct platform_device
*pdev
;
348 pdev
= &da8xx_i2c_device0
;
349 else if (instance
== 1)
350 pdev
= &da8xx_i2c_device1
;
354 pdev
->dev
.platform_data
= pdata
;
355 return platform_device_register(pdev
);
358 static struct resource da8xx_watchdog_resources
[] = {
360 .start
= DA8XX_WDOG_BASE
,
361 .end
= DA8XX_WDOG_BASE
+ SZ_4K
- 1,
362 .flags
= IORESOURCE_MEM
,
366 static struct platform_device da8xx_wdt_device
= {
367 .name
= "davinci-wdt",
369 .num_resources
= ARRAY_SIZE(da8xx_watchdog_resources
),
370 .resource
= da8xx_watchdog_resources
,
373 int __init
da8xx_register_watchdog(void)
375 return platform_device_register(&da8xx_wdt_device
);
378 static struct resource da8xx_emac_resources
[] = {
380 .start
= DA8XX_EMAC_CPPI_PORT_BASE
,
381 .end
= DA8XX_EMAC_CPPI_PORT_BASE
+ SZ_16K
- 1,
382 .flags
= IORESOURCE_MEM
,
385 .start
= IRQ_DA8XX_C0_RX_THRESH_PULSE
,
386 .end
= IRQ_DA8XX_C0_RX_THRESH_PULSE
,
387 .flags
= IORESOURCE_IRQ
,
390 .start
= IRQ_DA8XX_C0_RX_PULSE
,
391 .end
= IRQ_DA8XX_C0_RX_PULSE
,
392 .flags
= IORESOURCE_IRQ
,
395 .start
= IRQ_DA8XX_C0_TX_PULSE
,
396 .end
= IRQ_DA8XX_C0_TX_PULSE
,
397 .flags
= IORESOURCE_IRQ
,
400 .start
= IRQ_DA8XX_C0_MISC_PULSE
,
401 .end
= IRQ_DA8XX_C0_MISC_PULSE
,
402 .flags
= IORESOURCE_IRQ
,
406 struct emac_platform_data da8xx_emac_pdata
= {
407 .ctrl_reg_offset
= DA8XX_EMAC_CTRL_REG_OFFSET
,
408 .ctrl_mod_reg_offset
= DA8XX_EMAC_MOD_REG_OFFSET
,
409 .ctrl_ram_offset
= DA8XX_EMAC_RAM_OFFSET
,
410 .ctrl_ram_size
= DA8XX_EMAC_CTRL_RAM_SIZE
,
411 .version
= EMAC_VERSION_2
,
414 static struct platform_device da8xx_emac_device
= {
415 .name
= "davinci_emac",
418 .platform_data
= &da8xx_emac_pdata
,
420 .num_resources
= ARRAY_SIZE(da8xx_emac_resources
),
421 .resource
= da8xx_emac_resources
,
424 static struct resource da8xx_mdio_resources
[] = {
426 .start
= DA8XX_EMAC_MDIO_BASE
,
427 .end
= DA8XX_EMAC_MDIO_BASE
+ SZ_4K
- 1,
428 .flags
= IORESOURCE_MEM
,
432 static struct platform_device da8xx_mdio_device
= {
433 .name
= "davinci_mdio",
435 .num_resources
= ARRAY_SIZE(da8xx_mdio_resources
),
436 .resource
= da8xx_mdio_resources
,
439 int __init
da8xx_register_emac(void)
443 ret
= platform_device_register(&da8xx_mdio_device
);
447 return platform_device_register(&da8xx_emac_device
);
450 static struct resource da830_mcasp1_resources
[] = {
453 .start
= DAVINCI_DA830_MCASP1_REG_BASE
,
454 .end
= DAVINCI_DA830_MCASP1_REG_BASE
+ (SZ_1K
* 12) - 1,
455 .flags
= IORESOURCE_MEM
,
460 .start
= DAVINCI_DA830_DMA_MCASP1_AXEVT
,
461 .end
= DAVINCI_DA830_DMA_MCASP1_AXEVT
,
462 .flags
= IORESOURCE_DMA
,
467 .start
= DAVINCI_DA830_DMA_MCASP1_AREVT
,
468 .end
= DAVINCI_DA830_DMA_MCASP1_AREVT
,
469 .flags
= IORESOURCE_DMA
,
473 .start
= IRQ_DA8XX_MCASPINT
,
474 .flags
= IORESOURCE_IRQ
,
478 static struct platform_device da830_mcasp1_device
= {
479 .name
= "davinci-mcasp",
481 .num_resources
= ARRAY_SIZE(da830_mcasp1_resources
),
482 .resource
= da830_mcasp1_resources
,
485 static struct resource da830_mcasp2_resources
[] = {
488 .start
= DAVINCI_DA830_MCASP2_REG_BASE
,
489 .end
= DAVINCI_DA830_MCASP2_REG_BASE
+ (SZ_1K
* 12) - 1,
490 .flags
= IORESOURCE_MEM
,
495 .start
= DAVINCI_DA830_DMA_MCASP2_AXEVT
,
496 .end
= DAVINCI_DA830_DMA_MCASP2_AXEVT
,
497 .flags
= IORESOURCE_DMA
,
502 .start
= DAVINCI_DA830_DMA_MCASP2_AREVT
,
503 .end
= DAVINCI_DA830_DMA_MCASP2_AREVT
,
504 .flags
= IORESOURCE_DMA
,
508 .start
= IRQ_DA8XX_MCASPINT
,
509 .flags
= IORESOURCE_IRQ
,
513 static struct platform_device da830_mcasp2_device
= {
514 .name
= "davinci-mcasp",
516 .num_resources
= ARRAY_SIZE(da830_mcasp2_resources
),
517 .resource
= da830_mcasp2_resources
,
520 static struct resource da850_mcasp_resources
[] = {
523 .start
= DAVINCI_DA8XX_MCASP0_REG_BASE
,
524 .end
= DAVINCI_DA8XX_MCASP0_REG_BASE
+ (SZ_1K
* 12) - 1,
525 .flags
= IORESOURCE_MEM
,
530 .start
= DAVINCI_DA8XX_DMA_MCASP0_AXEVT
,
531 .end
= DAVINCI_DA8XX_DMA_MCASP0_AXEVT
,
532 .flags
= IORESOURCE_DMA
,
537 .start
= DAVINCI_DA8XX_DMA_MCASP0_AREVT
,
538 .end
= DAVINCI_DA8XX_DMA_MCASP0_AREVT
,
539 .flags
= IORESOURCE_DMA
,
543 .start
= IRQ_DA8XX_MCASPINT
,
544 .flags
= IORESOURCE_IRQ
,
548 static struct platform_device da850_mcasp_device
= {
549 .name
= "davinci-mcasp",
551 .num_resources
= ARRAY_SIZE(da850_mcasp_resources
),
552 .resource
= da850_mcasp_resources
,
555 void __init
da8xx_register_mcasp(int id
, struct snd_platform_data
*pdata
)
557 struct platform_device
*pdev
;
561 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
562 pdev
= &da850_mcasp_device
;
565 /* Valid for DA830/OMAP-L137 only */
566 if (!cpu_is_davinci_da830())
568 pdev
= &da830_mcasp1_device
;
571 /* Valid for DA830/OMAP-L137 only */
572 if (!cpu_is_davinci_da830())
574 pdev
= &da830_mcasp2_device
;
580 pdev
->dev
.platform_data
= pdata
;
581 platform_device_register(pdev
);
584 static struct resource da8xx_pruss_resources
[] = {
586 .start
= DA8XX_PRUSS_MEM_BASE
,
587 .end
= DA8XX_PRUSS_MEM_BASE
+ 0xFFFF,
588 .flags
= IORESOURCE_MEM
,
591 .start
= IRQ_DA8XX_EVTOUT0
,
592 .end
= IRQ_DA8XX_EVTOUT0
,
593 .flags
= IORESOURCE_IRQ
,
596 .start
= IRQ_DA8XX_EVTOUT1
,
597 .end
= IRQ_DA8XX_EVTOUT1
,
598 .flags
= IORESOURCE_IRQ
,
601 .start
= IRQ_DA8XX_EVTOUT2
,
602 .end
= IRQ_DA8XX_EVTOUT2
,
603 .flags
= IORESOURCE_IRQ
,
606 .start
= IRQ_DA8XX_EVTOUT3
,
607 .end
= IRQ_DA8XX_EVTOUT3
,
608 .flags
= IORESOURCE_IRQ
,
611 .start
= IRQ_DA8XX_EVTOUT4
,
612 .end
= IRQ_DA8XX_EVTOUT4
,
613 .flags
= IORESOURCE_IRQ
,
616 .start
= IRQ_DA8XX_EVTOUT5
,
617 .end
= IRQ_DA8XX_EVTOUT5
,
618 .flags
= IORESOURCE_IRQ
,
621 .start
= IRQ_DA8XX_EVTOUT6
,
622 .end
= IRQ_DA8XX_EVTOUT6
,
623 .flags
= IORESOURCE_IRQ
,
626 .start
= IRQ_DA8XX_EVTOUT7
,
627 .end
= IRQ_DA8XX_EVTOUT7
,
628 .flags
= IORESOURCE_IRQ
,
632 static struct uio_pruss_pdata da8xx_uio_pruss_pdata
= {
633 .pintc_base
= 0x4000,
636 static struct platform_device da8xx_uio_pruss_dev
= {
639 .num_resources
= ARRAY_SIZE(da8xx_pruss_resources
),
640 .resource
= da8xx_pruss_resources
,
642 .coherent_dma_mask
= DMA_BIT_MASK(32),
643 .platform_data
= &da8xx_uio_pruss_pdata
,
647 int __init
da8xx_register_uio_pruss(void)
649 da8xx_uio_pruss_pdata
.sram_pool
= sram_get_gen_pool();
650 return platform_device_register(&da8xx_uio_pruss_dev
);
653 static struct lcd_ctrl_config lcd_cfg
= {
654 .panel_shade
= COLOR_ACTIVE
,
658 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata
= {
659 .manu_name
= "sharp",
660 .controller_data
= &lcd_cfg
,
661 .type
= "Sharp_LCD035Q3DG01",
664 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata
= {
665 .manu_name
= "sharp",
666 .controller_data
= &lcd_cfg
,
667 .type
= "Sharp_LK043T1DG01",
670 static struct resource da8xx_lcdc_resources
[] = {
671 [0] = { /* registers */
672 .start
= DA8XX_LCD_CNTRL_BASE
,
673 .end
= DA8XX_LCD_CNTRL_BASE
+ SZ_4K
- 1,
674 .flags
= IORESOURCE_MEM
,
676 [1] = { /* interrupt */
677 .start
= IRQ_DA8XX_LCDINT
,
678 .end
= IRQ_DA8XX_LCDINT
,
679 .flags
= IORESOURCE_IRQ
,
683 static struct platform_device da8xx_lcdc_device
= {
684 .name
= "da8xx_lcdc",
686 .num_resources
= ARRAY_SIZE(da8xx_lcdc_resources
),
687 .resource
= da8xx_lcdc_resources
,
690 int __init
da8xx_register_lcdc(struct da8xx_lcdc_platform_data
*pdata
)
692 da8xx_lcdc_device
.dev
.platform_data
= pdata
;
693 return platform_device_register(&da8xx_lcdc_device
);
696 static struct resource da8xx_gpio_resources
[] = {
698 .start
= DA8XX_GPIO_BASE
,
699 .end
= DA8XX_GPIO_BASE
+ SZ_4K
- 1,
700 .flags
= IORESOURCE_MEM
,
703 .start
= IRQ_DA8XX_GPIO0
,
704 .end
= IRQ_DA8XX_GPIO8
,
705 .flags
= IORESOURCE_IRQ
,
709 static struct platform_device da8xx_gpio_device
= {
710 .name
= "davinci_gpio",
712 .num_resources
= ARRAY_SIZE(da8xx_gpio_resources
),
713 .resource
= da8xx_gpio_resources
,
716 int __init
da8xx_register_gpio(void *pdata
)
718 da8xx_gpio_device
.dev
.platform_data
= pdata
;
719 return platform_device_register(&da8xx_gpio_device
);
722 static struct resource da8xx_mmcsd0_resources
[] = {
724 .start
= DA8XX_MMCSD0_BASE
,
725 .end
= DA8XX_MMCSD0_BASE
+ SZ_4K
- 1,
726 .flags
= IORESOURCE_MEM
,
729 .start
= IRQ_DA8XX_MMCSDINT0
,
730 .end
= IRQ_DA8XX_MMCSDINT0
,
731 .flags
= IORESOURCE_IRQ
,
735 static struct platform_device da8xx_mmcsd0_device
= {
738 .num_resources
= ARRAY_SIZE(da8xx_mmcsd0_resources
),
739 .resource
= da8xx_mmcsd0_resources
,
742 int __init
da8xx_register_mmcsd0(struct davinci_mmc_config
*config
)
744 da8xx_mmcsd0_device
.dev
.platform_data
= config
;
745 return platform_device_register(&da8xx_mmcsd0_device
);
748 #ifdef CONFIG_ARCH_DAVINCI_DA850
749 static struct resource da850_mmcsd1_resources
[] = {
751 .start
= DA850_MMCSD1_BASE
,
752 .end
= DA850_MMCSD1_BASE
+ SZ_4K
- 1,
753 .flags
= IORESOURCE_MEM
,
756 .start
= IRQ_DA850_MMCSDINT0_1
,
757 .end
= IRQ_DA850_MMCSDINT0_1
,
758 .flags
= IORESOURCE_IRQ
,
762 static struct platform_device da850_mmcsd1_device
= {
765 .num_resources
= ARRAY_SIZE(da850_mmcsd1_resources
),
766 .resource
= da850_mmcsd1_resources
,
769 int __init
da850_register_mmcsd1(struct davinci_mmc_config
*config
)
771 da850_mmcsd1_device
.dev
.platform_data
= config
;
772 return platform_device_register(&da850_mmcsd1_device
);
776 static struct resource da8xx_rproc_resources
[] = {
777 { /* DSP boot address */
779 .start
= DA8XX_SYSCFG0_BASE
+ DA8XX_HOST1CFG_REG
,
780 .end
= DA8XX_SYSCFG0_BASE
+ DA8XX_HOST1CFG_REG
+ 3,
781 .flags
= IORESOURCE_MEM
,
783 { /* DSP interrupt registers */
785 .start
= DA8XX_SYSCFG0_BASE
+ DA8XX_CHIPSIG_REG
,
786 .end
= DA8XX_SYSCFG0_BASE
+ DA8XX_CHIPSIG_REG
+ 7,
787 .flags
= IORESOURCE_MEM
,
791 .start
= DA8XX_DSP_L2_RAM_BASE
,
792 .end
= DA8XX_DSP_L2_RAM_BASE
+ SZ_256K
- 1,
793 .flags
= IORESOURCE_MEM
,
797 .start
= DA8XX_DSP_L1P_RAM_BASE
,
798 .end
= DA8XX_DSP_L1P_RAM_BASE
+ SZ_32K
- 1,
799 .flags
= IORESOURCE_MEM
,
803 .start
= DA8XX_DSP_L1D_RAM_BASE
,
804 .end
= DA8XX_DSP_L1D_RAM_BASE
+ SZ_32K
- 1,
805 .flags
= IORESOURCE_MEM
,
808 .start
= IRQ_DA8XX_CHIPINT0
,
809 .end
= IRQ_DA8XX_CHIPINT0
,
810 .flags
= IORESOURCE_IRQ
,
814 static struct platform_device da8xx_dsp
= {
815 .name
= "davinci-rproc",
817 .coherent_dma_mask
= DMA_BIT_MASK(32),
819 .num_resources
= ARRAY_SIZE(da8xx_rproc_resources
),
820 .resource
= da8xx_rproc_resources
,
823 static bool rproc_mem_inited __initdata
;
825 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
827 static phys_addr_t rproc_base __initdata
;
828 static unsigned long rproc_size __initdata
;
830 static int __init
early_rproc_mem(char *p
)
837 rproc_size
= memparse(p
, &endp
);
839 rproc_base
= memparse(endp
+ 1, NULL
);
843 early_param("rproc_mem", early_rproc_mem
);
845 void __init
da8xx_rproc_reserve_cma(void)
849 if (!rproc_base
|| !rproc_size
) {
850 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
851 " 'nn' and 'address' must both be non-zero\n",
857 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
858 __func__
, rproc_size
, (unsigned long)rproc_base
);
860 ret
= dma_declare_contiguous(&da8xx_dsp
.dev
, rproc_size
, rproc_base
, 0);
862 pr_err("%s: dma_declare_contiguous failed %d\n", __func__
, ret
);
864 rproc_mem_inited
= true;
869 void __init
da8xx_rproc_reserve_cma(void)
875 int __init
da8xx_register_rproc(void)
879 if (!rproc_mem_inited
) {
880 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
885 ret
= platform_device_register(&da8xx_dsp
);
887 pr_err("%s: can't register DSP device: %d\n", __func__
, ret
);
892 static struct resource da8xx_rtc_resources
[] = {
894 .start
= DA8XX_RTC_BASE
,
895 .end
= DA8XX_RTC_BASE
+ SZ_4K
- 1,
896 .flags
= IORESOURCE_MEM
,
899 .start
= IRQ_DA8XX_RTC
,
900 .end
= IRQ_DA8XX_RTC
,
901 .flags
= IORESOURCE_IRQ
,
904 .start
= IRQ_DA8XX_RTC
,
905 .end
= IRQ_DA8XX_RTC
,
906 .flags
= IORESOURCE_IRQ
,
910 static struct platform_device da8xx_rtc_device
= {
913 .num_resources
= ARRAY_SIZE(da8xx_rtc_resources
),
914 .resource
= da8xx_rtc_resources
,
917 int da8xx_register_rtc(void)
919 return platform_device_register(&da8xx_rtc_device
);
922 static void __iomem
*da8xx_ddr2_ctlr_base
;
923 void __iomem
* __init
da8xx_get_mem_ctlr(void)
925 if (da8xx_ddr2_ctlr_base
)
926 return da8xx_ddr2_ctlr_base
;
928 da8xx_ddr2_ctlr_base
= ioremap(DA8XX_DDR2_CTL_BASE
, SZ_32K
);
929 if (!da8xx_ddr2_ctlr_base
)
930 pr_warn("%s: Unable to map DDR2 controller", __func__
);
932 return da8xx_ddr2_ctlr_base
;
935 static struct resource da8xx_cpuidle_resources
[] = {
937 .start
= DA8XX_DDR2_CTL_BASE
,
938 .end
= DA8XX_DDR2_CTL_BASE
+ SZ_32K
- 1,
939 .flags
= IORESOURCE_MEM
,
943 /* DA8XX devices support DDR2 power down */
944 static struct davinci_cpuidle_config da8xx_cpuidle_pdata
= {
949 static struct platform_device da8xx_cpuidle_device
= {
950 .name
= "cpuidle-davinci",
951 .num_resources
= ARRAY_SIZE(da8xx_cpuidle_resources
),
952 .resource
= da8xx_cpuidle_resources
,
954 .platform_data
= &da8xx_cpuidle_pdata
,
958 int __init
da8xx_register_cpuidle(void)
960 da8xx_cpuidle_pdata
.ddr2_ctlr_base
= da8xx_get_mem_ctlr();
962 return platform_device_register(&da8xx_cpuidle_device
);
965 static struct resource da8xx_spi0_resources
[] = {
967 .start
= DA8XX_SPI0_BASE
,
968 .end
= DA8XX_SPI0_BASE
+ SZ_4K
- 1,
969 .flags
= IORESOURCE_MEM
,
972 .start
= IRQ_DA8XX_SPINT0
,
973 .end
= IRQ_DA8XX_SPINT0
,
974 .flags
= IORESOURCE_IRQ
,
978 static struct resource da8xx_spi1_resources
[] = {
980 .start
= DA830_SPI1_BASE
,
981 .end
= DA830_SPI1_BASE
+ SZ_4K
- 1,
982 .flags
= IORESOURCE_MEM
,
985 .start
= IRQ_DA8XX_SPINT1
,
986 .end
= IRQ_DA8XX_SPINT1
,
987 .flags
= IORESOURCE_IRQ
,
991 static struct davinci_spi_platform_data da8xx_spi_pdata
[] = {
993 .version
= SPI_VERSION_2
,
995 .dma_event_q
= EVENTQ_0
,
996 .prescaler_limit
= 2,
999 .version
= SPI_VERSION_2
,
1001 .dma_event_q
= EVENTQ_0
,
1002 .prescaler_limit
= 2,
1006 static struct platform_device da8xx_spi_device
[] = {
1008 .name
= "spi_davinci",
1010 .num_resources
= ARRAY_SIZE(da8xx_spi0_resources
),
1011 .resource
= da8xx_spi0_resources
,
1013 .platform_data
= &da8xx_spi_pdata
[0],
1017 .name
= "spi_davinci",
1019 .num_resources
= ARRAY_SIZE(da8xx_spi1_resources
),
1020 .resource
= da8xx_spi1_resources
,
1022 .platform_data
= &da8xx_spi_pdata
[1],
1027 int __init
da8xx_register_spi_bus(int instance
, unsigned num_chipselect
)
1029 if (instance
< 0 || instance
> 1)
1032 da8xx_spi_pdata
[instance
].num_chipselect
= num_chipselect
;
1034 if (instance
== 1 && cpu_is_davinci_da850()) {
1035 da8xx_spi1_resources
[0].start
= DA850_SPI1_BASE
;
1036 da8xx_spi1_resources
[0].end
= DA850_SPI1_BASE
+ SZ_4K
- 1;
1039 return platform_device_register(&da8xx_spi_device
[instance
]);
1042 #ifdef CONFIG_ARCH_DAVINCI_DA850
1043 int __init
da850_register_sata_refclk(int rate
)
1047 clk
= clk_register_fixed_rate(NULL
, "sata_refclk", NULL
, 0, rate
);
1049 return PTR_ERR(clk
);
1051 return clk_register_clkdev(clk
, "refclk", "ahci_da850");
1054 static struct resource da850_sata_resources
[] = {
1056 .start
= DA850_SATA_BASE
,
1057 .end
= DA850_SATA_BASE
+ 0x1fff,
1058 .flags
= IORESOURCE_MEM
,
1061 .start
= DA8XX_SYSCFG1_BASE
+ DA8XX_PWRDN_REG
,
1062 .end
= DA8XX_SYSCFG1_BASE
+ DA8XX_PWRDN_REG
+ 0x3,
1063 .flags
= IORESOURCE_MEM
,
1066 .start
= IRQ_DA850_SATAINT
,
1067 .flags
= IORESOURCE_IRQ
,
1071 static u64 da850_sata_dmamask
= DMA_BIT_MASK(32);
1073 static struct platform_device da850_sata_device
= {
1074 .name
= "ahci_da850",
1077 .dma_mask
= &da850_sata_dmamask
,
1078 .coherent_dma_mask
= DMA_BIT_MASK(32),
1080 .num_resources
= ARRAY_SIZE(da850_sata_resources
),
1081 .resource
= da850_sata_resources
,
1084 int __init
da850_register_sata(unsigned long refclkpn
)
1088 ret
= da850_register_sata_refclk(refclkpn
);
1092 return platform_device_register(&da850_sata_device
);
1096 static struct regmap
*da8xx_cfgchip
;
1098 static const struct regmap_config da8xx_cfgchip_config __initconst
= {
1103 .max_register
= DA8XX_CFGCHIP4_REG
- DA8XX_CFGCHIP0_REG
,
1107 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
1109 * This is for use on non-DT boards only. For DT boards, use
1110 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
1112 * Returns: Pointer to the CFGCHIP regmap or negative error code.
1114 struct regmap
* __init
da8xx_get_cfgchip(void)
1116 if (IS_ERR_OR_NULL(da8xx_cfgchip
))
1117 da8xx_cfgchip
= regmap_init_mmio(NULL
,
1118 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG
),
1119 &da8xx_cfgchip_config
);
1121 return da8xx_cfgchip
;