2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
32 #include <asm/virtext.h>
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
52 /* Turn on to get debugging output*/
53 /* #define NESTED_DEBUG */
56 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
58 #define nsvm_printk(fmt, args...) do {} while(0)
61 static const u32 host_save_user_msrs
[] = {
63 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
66 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
69 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
76 unsigned long vmcb_pa
;
77 struct svm_cpu_data
*svm_data
;
78 uint64_t asid_generation
;
79 uint64_t sysenter_esp
;
80 uint64_t sysenter_eip
;
84 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
93 /* These are the merged vectors */
96 /* gpa pointers to the real vectors */
97 u64 nested_vmcb_msrpm
;
100 /* enable NPT for AMD64 and X86 with PAE */
101 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
102 static bool npt_enabled
= true;
104 static bool npt_enabled
= false;
108 module_param(npt
, int, S_IRUGO
);
110 static int nested
= 0;
111 module_param(nested
, int, S_IRUGO
);
113 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
115 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
);
116 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
117 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
118 void *arg2
, void *opaque
);
119 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
120 bool has_error_code
, u32 error_code
);
122 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
124 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
127 static inline bool is_nested(struct vcpu_svm
*svm
)
129 return svm
->nested_vmcb
;
132 static unsigned long iopm_base
;
134 struct kvm_ldttss_desc
{
137 unsigned base1
: 8, type
: 5, dpl
: 2, p
: 1;
138 unsigned limit1
: 4, zero0
: 3, g
: 1, base2
: 8;
141 } __attribute__((packed
));
143 struct svm_cpu_data
{
149 struct kvm_ldttss_desc
*tss_desc
;
151 struct page
*save_area
;
154 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
155 static uint32_t svm_features
;
157 struct svm_init_data
{
162 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
164 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
165 #define MSRS_RANGE_SIZE 2048
166 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
168 #define MAX_INST_SIZE 15
170 static inline u32
svm_has(u32 feat
)
172 return svm_features
& feat
;
175 static inline void clgi(void)
177 asm volatile (__ex(SVM_CLGI
));
180 static inline void stgi(void)
182 asm volatile (__ex(SVM_STGI
));
185 static inline void invlpga(unsigned long addr
, u32 asid
)
187 asm volatile (__ex(SVM_INVLPGA
) :: "a"(addr
), "c"(asid
));
190 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
192 to_svm(vcpu
)->asid_generation
--;
195 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
197 force_new_asid(vcpu
);
200 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
202 if (!npt_enabled
&& !(efer
& EFER_LMA
))
205 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
206 vcpu
->arch
.shadow_efer
= efer
;
209 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
210 bool has_error_code
, u32 error_code
)
212 struct vcpu_svm
*svm
= to_svm(vcpu
);
214 /* If we are within a nested VM we'd better #VMEXIT and let the
215 guest handle the exception */
216 if (nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
219 svm
->vmcb
->control
.event_inj
= nr
221 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
222 | SVM_EVTINJ_TYPE_EXEPT
;
223 svm
->vmcb
->control
.event_inj_err
= error_code
;
226 static int is_external_interrupt(u32 info
)
228 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
229 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
232 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
234 struct vcpu_svm
*svm
= to_svm(vcpu
);
237 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
238 ret
|= X86_SHADOW_INT_STI
| X86_SHADOW_INT_MOV_SS
;
242 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
244 struct vcpu_svm
*svm
= to_svm(vcpu
);
247 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
249 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
253 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
255 struct vcpu_svm
*svm
= to_svm(vcpu
);
257 if (!svm
->next_rip
) {
258 if (emulate_instruction(vcpu
, vcpu
->run
, 0, 0, EMULTYPE_SKIP
) !=
260 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
263 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
264 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
265 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
267 kvm_rip_write(vcpu
, svm
->next_rip
);
268 svm_set_interrupt_shadow(vcpu
, 0);
271 static int has_svm(void)
275 if (!cpu_has_svm(&msg
)) {
276 printk(KERN_INFO
"has_svm: %s\n", msg
);
283 static void svm_hardware_disable(void *garbage
)
288 static void svm_hardware_enable(void *garbage
)
291 struct svm_cpu_data
*svm_data
;
293 struct descriptor_table gdt_descr
;
294 struct desc_struct
*gdt
;
295 int me
= raw_smp_processor_id();
298 printk(KERN_ERR
"svm_cpu_init: err EOPNOTSUPP on %d\n", me
);
301 svm_data
= per_cpu(svm_data
, me
);
304 printk(KERN_ERR
"svm_cpu_init: svm_data is NULL on %d\n",
309 svm_data
->asid_generation
= 1;
310 svm_data
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
311 svm_data
->next_asid
= svm_data
->max_asid
+ 1;
313 kvm_get_gdt(&gdt_descr
);
314 gdt
= (struct desc_struct
*)gdt_descr
.base
;
315 svm_data
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
317 rdmsrl(MSR_EFER
, efer
);
318 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
320 wrmsrl(MSR_VM_HSAVE_PA
,
321 page_to_pfn(svm_data
->save_area
) << PAGE_SHIFT
);
324 static void svm_cpu_uninit(int cpu
)
326 struct svm_cpu_data
*svm_data
327 = per_cpu(svm_data
, raw_smp_processor_id());
332 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
333 __free_page(svm_data
->save_area
);
337 static int svm_cpu_init(int cpu
)
339 struct svm_cpu_data
*svm_data
;
342 svm_data
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
346 svm_data
->save_area
= alloc_page(GFP_KERNEL
);
348 if (!svm_data
->save_area
)
351 per_cpu(svm_data
, cpu
) = svm_data
;
361 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
366 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
367 if (msr
>= msrpm_ranges
[i
] &&
368 msr
< msrpm_ranges
[i
] + MSRS_IN_RANGE
) {
369 u32 msr_offset
= (i
* MSRS_IN_RANGE
+ msr
-
370 msrpm_ranges
[i
]) * 2;
372 u32
*base
= msrpm
+ (msr_offset
/ 32);
373 u32 msr_shift
= msr_offset
% 32;
374 u32 mask
= ((write
) ? 0 : 2) | ((read
) ? 0 : 1);
375 *base
= (*base
& ~(0x3 << msr_shift
)) |
383 static void svm_vcpu_init_msrpm(u32
*msrpm
)
385 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
388 set_msr_interception(msrpm
, MSR_GS_BASE
, 1, 1);
389 set_msr_interception(msrpm
, MSR_FS_BASE
, 1, 1);
390 set_msr_interception(msrpm
, MSR_KERNEL_GS_BASE
, 1, 1);
391 set_msr_interception(msrpm
, MSR_LSTAR
, 1, 1);
392 set_msr_interception(msrpm
, MSR_CSTAR
, 1, 1);
393 set_msr_interception(msrpm
, MSR_SYSCALL_MASK
, 1, 1);
395 set_msr_interception(msrpm
, MSR_K6_STAR
, 1, 1);
396 set_msr_interception(msrpm
, MSR_IA32_SYSENTER_CS
, 1, 1);
399 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
401 u32
*msrpm
= svm
->msrpm
;
403 svm
->vmcb
->control
.lbr_ctl
= 1;
404 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
405 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
406 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
407 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
410 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
412 u32
*msrpm
= svm
->msrpm
;
414 svm
->vmcb
->control
.lbr_ctl
= 0;
415 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
416 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
417 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
418 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
421 static __init
int svm_hardware_setup(void)
424 struct page
*iopm_pages
;
428 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
433 iopm_va
= page_address(iopm_pages
);
434 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
435 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
437 if (boot_cpu_has(X86_FEATURE_NX
))
438 kvm_enable_efer_bits(EFER_NX
);
440 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
441 kvm_enable_efer_bits(EFER_FFXSR
);
444 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
445 kvm_enable_efer_bits(EFER_SVME
);
448 for_each_online_cpu(cpu
) {
449 r
= svm_cpu_init(cpu
);
454 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
456 if (!svm_has(SVM_FEATURE_NPT
))
459 if (npt_enabled
&& !npt
) {
460 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
465 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
473 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
478 static __exit
void svm_hardware_unsetup(void)
482 for_each_online_cpu(cpu
)
485 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
489 static void init_seg(struct vmcb_seg
*seg
)
492 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
493 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
498 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
501 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
506 static void init_vmcb(struct vcpu_svm
*svm
)
508 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
509 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
511 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
515 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
520 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
525 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
532 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
537 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
538 (1ULL << INTERCEPT_NMI
) |
539 (1ULL << INTERCEPT_SMI
) |
540 (1ULL << INTERCEPT_CPUID
) |
541 (1ULL << INTERCEPT_INVD
) |
542 (1ULL << INTERCEPT_HLT
) |
543 (1ULL << INTERCEPT_INVLPG
) |
544 (1ULL << INTERCEPT_INVLPGA
) |
545 (1ULL << INTERCEPT_IOIO_PROT
) |
546 (1ULL << INTERCEPT_MSR_PROT
) |
547 (1ULL << INTERCEPT_TASK_SWITCH
) |
548 (1ULL << INTERCEPT_SHUTDOWN
) |
549 (1ULL << INTERCEPT_VMRUN
) |
550 (1ULL << INTERCEPT_VMMCALL
) |
551 (1ULL << INTERCEPT_VMLOAD
) |
552 (1ULL << INTERCEPT_VMSAVE
) |
553 (1ULL << INTERCEPT_STGI
) |
554 (1ULL << INTERCEPT_CLGI
) |
555 (1ULL << INTERCEPT_SKINIT
) |
556 (1ULL << INTERCEPT_WBINVD
) |
557 (1ULL << INTERCEPT_MONITOR
) |
558 (1ULL << INTERCEPT_MWAIT
);
560 control
->iopm_base_pa
= iopm_base
;
561 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
562 control
->tsc_offset
= 0;
563 control
->int_ctl
= V_INTR_MASKING_MASK
;
571 save
->cs
.selector
= 0xf000;
572 /* Executable/Readable Code Segment */
573 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
574 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
575 save
->cs
.limit
= 0xffff;
577 * cs.base should really be 0xffff0000, but vmx can't handle that, so
578 * be consistent with it.
580 * Replace when we have real mode working for vmx.
582 save
->cs
.base
= 0xf0000;
584 save
->gdtr
.limit
= 0xffff;
585 save
->idtr
.limit
= 0xffff;
587 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
588 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
590 save
->efer
= EFER_SVME
;
591 save
->dr6
= 0xffff0ff0;
594 save
->rip
= 0x0000fff0;
595 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
598 * cr0 val on cpu init should be 0x60000010, we enable cpu
599 * cache by default. the orderly way is to enable cache in bios.
601 save
->cr0
= 0x00000010 | X86_CR0_PG
| X86_CR0_WP
;
602 save
->cr4
= X86_CR4_PAE
;
606 /* Setup VMCB for Nested Paging */
607 control
->nested_ctl
= 1;
608 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
609 (1ULL << INTERCEPT_INVLPG
));
610 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
611 control
->intercept_cr_read
&= ~(INTERCEPT_CR0_MASK
|
613 control
->intercept_cr_write
&= ~(INTERCEPT_CR0_MASK
|
615 save
->g_pat
= 0x0007040600070406ULL
;
616 /* enable caching because the QEMU Bios doesn't enable it */
617 save
->cr0
= X86_CR0_ET
;
621 force_new_asid(&svm
->vcpu
);
623 svm
->nested_vmcb
= 0;
624 svm
->vcpu
.arch
.hflags
= HF_GIF_MASK
;
627 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
629 struct vcpu_svm
*svm
= to_svm(vcpu
);
633 if (!kvm_vcpu_is_bsp(vcpu
)) {
634 kvm_rip_write(vcpu
, 0);
635 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
636 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
638 vcpu
->arch
.regs_avail
= ~0;
639 vcpu
->arch
.regs_dirty
= ~0;
644 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
646 struct vcpu_svm
*svm
;
648 struct page
*msrpm_pages
;
649 struct page
*hsave_page
;
650 struct page
*nested_msrpm_pages
;
653 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
659 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
663 page
= alloc_page(GFP_KERNEL
);
670 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
674 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
675 if (!nested_msrpm_pages
)
678 svm
->msrpm
= page_address(msrpm_pages
);
679 svm_vcpu_init_msrpm(svm
->msrpm
);
681 hsave_page
= alloc_page(GFP_KERNEL
);
684 svm
->hsave
= page_address(hsave_page
);
686 svm
->nested_msrpm
= page_address(nested_msrpm_pages
);
688 svm
->vmcb
= page_address(page
);
689 clear_page(svm
->vmcb
);
690 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
691 svm
->asid_generation
= 0;
695 svm
->vcpu
.fpu_active
= 1;
696 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
697 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
698 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
703 kvm_vcpu_uninit(&svm
->vcpu
);
705 kmem_cache_free(kvm_vcpu_cache
, svm
);
710 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
712 struct vcpu_svm
*svm
= to_svm(vcpu
);
714 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
715 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
716 __free_page(virt_to_page(svm
->hsave
));
717 __free_pages(virt_to_page(svm
->nested_msrpm
), MSRPM_ALLOC_ORDER
);
718 kvm_vcpu_uninit(vcpu
);
719 kmem_cache_free(kvm_vcpu_cache
, svm
);
722 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
724 struct vcpu_svm
*svm
= to_svm(vcpu
);
727 if (unlikely(cpu
!= vcpu
->cpu
)) {
731 * Make sure that the guest sees a monotonically
735 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
736 svm
->vmcb
->control
.tsc_offset
+= delta
;
738 kvm_migrate_timers(vcpu
);
739 svm
->asid_generation
= 0;
742 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
743 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
746 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
748 struct vcpu_svm
*svm
= to_svm(vcpu
);
751 ++vcpu
->stat
.host_state_reload
;
752 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
753 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
755 rdtscll(vcpu
->arch
.host_tsc
);
758 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
760 return to_svm(vcpu
)->vmcb
->save
.rflags
;
763 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
765 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
768 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
771 case VCPU_EXREG_PDPTR
:
772 BUG_ON(!npt_enabled
);
773 load_pdptrs(vcpu
, vcpu
->arch
.cr3
);
780 static void svm_set_vintr(struct vcpu_svm
*svm
)
782 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
785 static void svm_clear_vintr(struct vcpu_svm
*svm
)
787 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
790 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
792 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
795 case VCPU_SREG_CS
: return &save
->cs
;
796 case VCPU_SREG_DS
: return &save
->ds
;
797 case VCPU_SREG_ES
: return &save
->es
;
798 case VCPU_SREG_FS
: return &save
->fs
;
799 case VCPU_SREG_GS
: return &save
->gs
;
800 case VCPU_SREG_SS
: return &save
->ss
;
801 case VCPU_SREG_TR
: return &save
->tr
;
802 case VCPU_SREG_LDTR
: return &save
->ldtr
;
808 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
810 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
815 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
816 struct kvm_segment
*var
, int seg
)
818 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
821 var
->limit
= s
->limit
;
822 var
->selector
= s
->selector
;
823 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
824 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
825 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
826 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
827 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
828 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
829 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
830 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
832 /* AMD's VMCB does not have an explicit unusable field, so emulate it
833 * for cross vendor migration purposes by "not present"
835 var
->unusable
= !var
->present
|| (var
->type
== 0);
840 * SVM always stores 0 for the 'G' bit in the CS selector in
841 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
842 * Intel's VMENTRY has a check on the 'G' bit.
844 var
->g
= s
->limit
> 0xfffff;
848 * Work around a bug where the busy flag in the tr selector
858 * The accessed bit must always be set in the segment
859 * descriptor cache, although it can be cleared in the
860 * descriptor, the cached bit always remains at 1. Since
861 * Intel has a check on this, set it here to support
862 * cross-vendor migration.
868 /* On AMD CPUs sometimes the DB bit in the segment
869 * descriptor is left as 1, although the whole segment has
870 * been made unusable. Clear it here to pass an Intel VMX
871 * entry check when cross vendor migrating.
879 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
881 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
886 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
888 struct vcpu_svm
*svm
= to_svm(vcpu
);
890 dt
->limit
= svm
->vmcb
->save
.idtr
.limit
;
891 dt
->base
= svm
->vmcb
->save
.idtr
.base
;
894 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
896 struct vcpu_svm
*svm
= to_svm(vcpu
);
898 svm
->vmcb
->save
.idtr
.limit
= dt
->limit
;
899 svm
->vmcb
->save
.idtr
.base
= dt
->base
;
902 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
904 struct vcpu_svm
*svm
= to_svm(vcpu
);
906 dt
->limit
= svm
->vmcb
->save
.gdtr
.limit
;
907 dt
->base
= svm
->vmcb
->save
.gdtr
.base
;
910 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
912 struct vcpu_svm
*svm
= to_svm(vcpu
);
914 svm
->vmcb
->save
.gdtr
.limit
= dt
->limit
;
915 svm
->vmcb
->save
.gdtr
.base
= dt
->base
;
918 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
922 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
924 struct vcpu_svm
*svm
= to_svm(vcpu
);
927 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
928 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
929 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
930 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
933 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
934 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
935 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
942 if ((vcpu
->arch
.cr0
& X86_CR0_TS
) && !(cr0
& X86_CR0_TS
)) {
943 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
944 vcpu
->fpu_active
= 1;
947 vcpu
->arch
.cr0
= cr0
;
948 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
949 if (!vcpu
->fpu_active
) {
950 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
955 * re-enable caching here because the QEMU bios
956 * does not do it - this results in some delay at
959 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
960 svm
->vmcb
->save
.cr0
= cr0
;
963 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
965 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
966 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
968 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
969 force_new_asid(vcpu
);
971 vcpu
->arch
.cr4
= cr4
;
975 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
978 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
979 struct kvm_segment
*var
, int seg
)
981 struct vcpu_svm
*svm
= to_svm(vcpu
);
982 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
985 s
->limit
= var
->limit
;
986 s
->selector
= var
->selector
;
990 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
991 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
992 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
993 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
994 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
995 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
996 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
997 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
999 if (seg
== VCPU_SREG_CS
)
1001 = (svm
->vmcb
->save
.cs
.attrib
1002 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1006 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1008 struct vcpu_svm
*svm
= to_svm(vcpu
);
1010 svm
->vmcb
->control
.intercept_exceptions
&=
1011 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1013 if (vcpu
->arch
.singlestep
)
1014 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1016 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1017 if (vcpu
->guest_debug
&
1018 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1019 svm
->vmcb
->control
.intercept_exceptions
|=
1021 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1022 svm
->vmcb
->control
.intercept_exceptions
|=
1025 vcpu
->guest_debug
= 0;
1028 static int svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1030 int old_debug
= vcpu
->guest_debug
;
1031 struct vcpu_svm
*svm
= to_svm(vcpu
);
1033 vcpu
->guest_debug
= dbg
->control
;
1035 update_db_intercept(vcpu
);
1037 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1038 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1040 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1042 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
1043 svm
->vmcb
->save
.rflags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1044 else if (old_debug
& KVM_GUESTDBG_SINGLESTEP
)
1045 svm
->vmcb
->save
.rflags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1050 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1052 #ifdef CONFIG_X86_64
1053 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1057 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1059 #ifdef CONFIG_X86_64
1060 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1064 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*svm_data
)
1066 if (svm_data
->next_asid
> svm_data
->max_asid
) {
1067 ++svm_data
->asid_generation
;
1068 svm_data
->next_asid
= 1;
1069 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1072 svm
->asid_generation
= svm_data
->asid_generation
;
1073 svm
->vmcb
->control
.asid
= svm_data
->next_asid
++;
1076 static unsigned long svm_get_dr(struct kvm_vcpu
*vcpu
, int dr
)
1078 struct vcpu_svm
*svm
= to_svm(vcpu
);
1083 val
= vcpu
->arch
.db
[dr
];
1086 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1087 val
= vcpu
->arch
.dr6
;
1089 val
= svm
->vmcb
->save
.dr6
;
1092 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1093 val
= vcpu
->arch
.dr7
;
1095 val
= svm
->vmcb
->save
.dr7
;
1104 static void svm_set_dr(struct kvm_vcpu
*vcpu
, int dr
, unsigned long value
,
1107 struct vcpu_svm
*svm
= to_svm(vcpu
);
1113 vcpu
->arch
.db
[dr
] = value
;
1114 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
1115 vcpu
->arch
.eff_db
[dr
] = value
;
1118 if (vcpu
->arch
.cr4
& X86_CR4_DE
)
1119 *exception
= UD_VECTOR
;
1122 if (value
& 0xffffffff00000000ULL
) {
1123 *exception
= GP_VECTOR
;
1126 vcpu
->arch
.dr6
= (value
& DR6_VOLATILE
) | DR6_FIXED_1
;
1129 if (value
& 0xffffffff00000000ULL
) {
1130 *exception
= GP_VECTOR
;
1133 vcpu
->arch
.dr7
= (value
& DR7_VOLATILE
) | DR7_FIXED_1
;
1134 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
1135 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1136 vcpu
->arch
.switch_db_regs
= (value
& DR7_BP_EN_MASK
);
1140 /* FIXME: Possible case? */
1141 printk(KERN_DEBUG
"%s: unexpected dr %u\n",
1143 *exception
= UD_VECTOR
;
1148 static int pf_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1153 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1154 error_code
= svm
->vmcb
->control
.exit_info_1
;
1156 trace_kvm_page_fault(fault_address
, error_code
);
1158 * FIXME: Tis shouldn't be necessary here, but there is a flush
1159 * missing in the MMU code. Until we find this bug, flush the
1160 * complete TLB here on an NPF
1163 svm_flush_tlb(&svm
->vcpu
);
1165 if (kvm_event_needs_reinjection(&svm
->vcpu
))
1166 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1168 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1171 static int db_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1173 if (!(svm
->vcpu
.guest_debug
&
1174 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1175 !svm
->vcpu
.arch
.singlestep
) {
1176 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1180 if (svm
->vcpu
.arch
.singlestep
) {
1181 svm
->vcpu
.arch
.singlestep
= false;
1182 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1183 svm
->vmcb
->save
.rflags
&=
1184 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1185 update_db_intercept(&svm
->vcpu
);
1188 if (svm
->vcpu
.guest_debug
&
1189 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)){
1190 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1191 kvm_run
->debug
.arch
.pc
=
1192 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1193 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1200 static int bp_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1202 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1203 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1204 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1208 static int ud_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1212 er
= emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
1213 if (er
!= EMULATE_DONE
)
1214 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1218 static int nm_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1220 svm
->vmcb
->control
.intercept_exceptions
&= ~(1 << NM_VECTOR
);
1221 if (!(svm
->vcpu
.arch
.cr0
& X86_CR0_TS
))
1222 svm
->vmcb
->save
.cr0
&= ~X86_CR0_TS
;
1223 svm
->vcpu
.fpu_active
= 1;
1228 static int mc_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1231 * On an #MC intercept the MCE handler is not called automatically in
1232 * the host. So do it by hand here.
1236 /* not sure if we ever come back to this point */
1241 static int shutdown_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1244 * VMCB is undefined after a SHUTDOWN intercept
1245 * so reinitialize it.
1247 clear_page(svm
->vmcb
);
1250 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1254 static int io_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1256 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1257 int size
, in
, string
;
1260 ++svm
->vcpu
.stat
.io_exits
;
1262 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1264 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1267 if (emulate_instruction(&svm
->vcpu
,
1268 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
1273 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1274 port
= io_info
>> 16;
1275 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1277 skip_emulated_instruction(&svm
->vcpu
);
1278 return kvm_emulate_pio(&svm
->vcpu
, kvm_run
, in
, size
, port
);
1281 static int nmi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1286 static int intr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1288 ++svm
->vcpu
.stat
.irq_exits
;
1292 static int nop_on_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1297 static int halt_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1299 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1300 skip_emulated_instruction(&svm
->vcpu
);
1301 return kvm_emulate_halt(&svm
->vcpu
);
1304 static int vmmcall_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1306 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1307 skip_emulated_instruction(&svm
->vcpu
);
1308 kvm_emulate_hypercall(&svm
->vcpu
);
1312 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1314 if (!(svm
->vcpu
.arch
.shadow_efer
& EFER_SVME
)
1315 || !is_paging(&svm
->vcpu
)) {
1316 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1320 if (svm
->vmcb
->save
.cpl
) {
1321 kvm_inject_gp(&svm
->vcpu
, 0);
1328 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1329 bool has_error_code
, u32 error_code
)
1331 if (is_nested(svm
)) {
1332 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1333 svm
->vmcb
->control
.exit_code_hi
= 0;
1334 svm
->vmcb
->control
.exit_info_1
= error_code
;
1335 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1336 if (nested_svm_exit_handled(svm
, false)) {
1337 nsvm_printk("VMexit -> EXCP 0x%x\n", nr
);
1339 nested_svm_vmexit(svm
);
1347 static inline int nested_svm_intr(struct vcpu_svm
*svm
)
1349 if (is_nested(svm
)) {
1350 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1353 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1356 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1358 if (nested_svm_exit_handled(svm
, false)) {
1359 nsvm_printk("VMexit -> INTR\n");
1360 nested_svm_vmexit(svm
);
1368 static struct page
*nested_svm_get_page(struct vcpu_svm
*svm
, u64 gpa
)
1372 down_read(¤t
->mm
->mmap_sem
);
1373 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1374 up_read(¤t
->mm
->mmap_sem
);
1376 if (is_error_page(page
)) {
1377 printk(KERN_INFO
"%s: could not find page at 0x%llx\n",
1379 kvm_release_page_clean(page
);
1380 kvm_inject_gp(&svm
->vcpu
, 0);
1386 static int nested_svm_do(struct vcpu_svm
*svm
,
1387 u64 arg1_gpa
, u64 arg2_gpa
, void *opaque
,
1388 int (*handler
)(struct vcpu_svm
*svm
,
1393 struct page
*arg1_page
;
1394 struct page
*arg2_page
= NULL
;
1399 arg1_page
= nested_svm_get_page(svm
, arg1_gpa
);
1400 if(arg1_page
== NULL
)
1404 arg2_page
= nested_svm_get_page(svm
, arg2_gpa
);
1405 if(arg2_page
== NULL
) {
1406 kvm_release_page_clean(arg1_page
);
1411 arg1
= kmap_atomic(arg1_page
, KM_USER0
);
1413 arg2
= kmap_atomic(arg2_page
, KM_USER1
);
1415 retval
= handler(svm
, arg1
, arg2
, opaque
);
1417 kunmap_atomic(arg1
, KM_USER0
);
1419 kunmap_atomic(arg2
, KM_USER1
);
1421 kvm_release_page_dirty(arg1_page
);
1423 kvm_release_page_dirty(arg2_page
);
1428 static int nested_svm_exit_handled_real(struct vcpu_svm
*svm
,
1433 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1434 bool kvm_overrides
= *(bool *)opaque
;
1435 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1437 if (kvm_overrides
) {
1438 switch (exit_code
) {
1442 /* For now we are always handling NPFs when using them */
1447 /* When we're shadowing, trap PFs */
1448 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1457 switch (exit_code
) {
1458 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1459 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1460 if (nested_vmcb
->control
.intercept_cr_read
& cr_bits
)
1464 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1465 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1466 if (nested_vmcb
->control
.intercept_cr_write
& cr_bits
)
1470 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1471 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1472 if (nested_vmcb
->control
.intercept_dr_read
& dr_bits
)
1476 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1477 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1478 if (nested_vmcb
->control
.intercept_dr_write
& dr_bits
)
1482 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1483 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1484 if (nested_vmcb
->control
.intercept_exceptions
& excp_bits
)
1489 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1490 nsvm_printk("exit code: 0x%x\n", exit_code
);
1491 if (nested_vmcb
->control
.intercept
& exit_bits
)
1499 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
,
1500 void *arg1
, void *arg2
,
1503 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1504 u8
*msrpm
= (u8
*)arg2
;
1506 u32 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1507 u32 param
= svm
->vmcb
->control
.exit_info_1
& 1;
1509 if (!(nested_vmcb
->control
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1517 case 0xc0000000 ... 0xc0001fff:
1518 t0
= (8192 + msr
- 0xc0000000) * 2;
1522 case 0xc0010000 ... 0xc0011fff:
1523 t0
= (16384 + msr
- 0xc0010000) * 2;
1531 if (msrpm
[t1
] & ((1 << param
) << t0
))
1537 static int nested_svm_exit_handled(struct vcpu_svm
*svm
, bool kvm_override
)
1539 bool k
= kvm_override
;
1541 switch (svm
->vmcb
->control
.exit_code
) {
1543 return nested_svm_do(svm
, svm
->nested_vmcb
,
1544 svm
->nested_vmcb_msrpm
, NULL
,
1545 nested_svm_exit_handled_msr
);
1549 return nested_svm_do(svm
, svm
->nested_vmcb
, 0, &k
,
1550 nested_svm_exit_handled_real
);
1553 static int nested_svm_vmexit_real(struct vcpu_svm
*svm
, void *arg1
,
1554 void *arg2
, void *opaque
)
1556 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1557 struct vmcb
*hsave
= svm
->hsave
;
1558 u64 nested_save
[] = { nested_vmcb
->save
.cr0
,
1559 nested_vmcb
->save
.cr3
,
1560 nested_vmcb
->save
.cr4
,
1561 nested_vmcb
->save
.efer
,
1562 nested_vmcb
->control
.intercept_cr_read
,
1563 nested_vmcb
->control
.intercept_cr_write
,
1564 nested_vmcb
->control
.intercept_dr_read
,
1565 nested_vmcb
->control
.intercept_dr_write
,
1566 nested_vmcb
->control
.intercept_exceptions
,
1567 nested_vmcb
->control
.intercept
,
1568 nested_vmcb
->control
.msrpm_base_pa
,
1569 nested_vmcb
->control
.iopm_base_pa
,
1570 nested_vmcb
->control
.tsc_offset
};
1572 /* Give the current vmcb to the guest */
1573 memcpy(nested_vmcb
, svm
->vmcb
, sizeof(struct vmcb
));
1574 nested_vmcb
->save
.cr0
= nested_save
[0];
1576 nested_vmcb
->save
.cr3
= nested_save
[1];
1577 nested_vmcb
->save
.cr4
= nested_save
[2];
1578 nested_vmcb
->save
.efer
= nested_save
[3];
1579 nested_vmcb
->control
.intercept_cr_read
= nested_save
[4];
1580 nested_vmcb
->control
.intercept_cr_write
= nested_save
[5];
1581 nested_vmcb
->control
.intercept_dr_read
= nested_save
[6];
1582 nested_vmcb
->control
.intercept_dr_write
= nested_save
[7];
1583 nested_vmcb
->control
.intercept_exceptions
= nested_save
[8];
1584 nested_vmcb
->control
.intercept
= nested_save
[9];
1585 nested_vmcb
->control
.msrpm_base_pa
= nested_save
[10];
1586 nested_vmcb
->control
.iopm_base_pa
= nested_save
[11];
1587 nested_vmcb
->control
.tsc_offset
= nested_save
[12];
1589 /* We always set V_INTR_MASKING and remember the old value in hflags */
1590 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1591 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1593 if ((nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) &&
1594 (nested_vmcb
->control
.int_vector
)) {
1595 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1596 nested_vmcb
->control
.int_vector
);
1599 /* Restore the original control entries */
1600 svm
->vmcb
->control
= hsave
->control
;
1602 /* Kill any pending exceptions */
1603 if (svm
->vcpu
.arch
.exception
.pending
== true)
1604 nsvm_printk("WARNING: Pending Exception\n");
1605 kvm_clear_exception_queue(&svm
->vcpu
);
1606 kvm_clear_interrupt_queue(&svm
->vcpu
);
1608 /* Restore selected save entries */
1609 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1610 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1611 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1612 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1613 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1614 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1615 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1616 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1617 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1618 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1620 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1621 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1623 kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1625 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1626 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1627 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1628 svm
->vmcb
->save
.dr7
= 0;
1629 svm
->vmcb
->save
.cpl
= 0;
1630 svm
->vmcb
->control
.exit_int_info
= 0;
1632 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1633 /* Exit nested SVM mode */
1634 svm
->nested_vmcb
= 0;
1639 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1641 nsvm_printk("VMexit\n");
1642 if (nested_svm_do(svm
, svm
->nested_vmcb
, 0,
1643 NULL
, nested_svm_vmexit_real
))
1646 kvm_mmu_reset_context(&svm
->vcpu
);
1647 kvm_mmu_load(&svm
->vcpu
);
1652 static int nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
, void *arg1
,
1653 void *arg2
, void *opaque
)
1656 u32
*nested_msrpm
= (u32
*)arg1
;
1657 for (i
=0; i
< PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
) / 4; i
++)
1658 svm
->nested_msrpm
[i
] = svm
->msrpm
[i
] | nested_msrpm
[i
];
1659 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested_msrpm
);
1664 static int nested_svm_vmrun(struct vcpu_svm
*svm
, void *arg1
,
1665 void *arg2
, void *opaque
)
1667 struct vmcb
*nested_vmcb
= (struct vmcb
*)arg1
;
1668 struct vmcb
*hsave
= svm
->hsave
;
1670 /* nested_vmcb is our indicator if nested SVM is activated */
1671 svm
->nested_vmcb
= svm
->vmcb
->save
.rax
;
1673 /* Clear internal status */
1674 kvm_clear_exception_queue(&svm
->vcpu
);
1675 kvm_clear_interrupt_queue(&svm
->vcpu
);
1677 /* Save the old vmcb, so we don't need to pick what we save, but
1678 can restore everything when a VMEXIT occurs */
1679 memcpy(hsave
, svm
->vmcb
, sizeof(struct vmcb
));
1680 /* We need to remember the original CR3 in the SPT case */
1682 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1683 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1684 hsave
->save
.rip
= svm
->next_rip
;
1686 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
1687 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
1689 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
1691 /* Load the nested guest state */
1692 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
1693 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
1694 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
1695 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
1696 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
1697 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
1698 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
1699 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
1700 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
1701 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
1703 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
1704 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
1706 kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
1707 kvm_mmu_reset_context(&svm
->vcpu
);
1709 svm
->vmcb
->save
.cr2
= nested_vmcb
->save
.cr2
;
1710 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
1711 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
1712 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
1713 /* In case we don't even reach vcpu_run, the fields are not updated */
1714 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
1715 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
1716 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
1717 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
1718 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
1719 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
1721 /* We don't want a nested guest to be more powerful than the guest,
1722 so all intercepts are ORed */
1723 svm
->vmcb
->control
.intercept_cr_read
|=
1724 nested_vmcb
->control
.intercept_cr_read
;
1725 svm
->vmcb
->control
.intercept_cr_write
|=
1726 nested_vmcb
->control
.intercept_cr_write
;
1727 svm
->vmcb
->control
.intercept_dr_read
|=
1728 nested_vmcb
->control
.intercept_dr_read
;
1729 svm
->vmcb
->control
.intercept_dr_write
|=
1730 nested_vmcb
->control
.intercept_dr_write
;
1731 svm
->vmcb
->control
.intercept_exceptions
|=
1732 nested_vmcb
->control
.intercept_exceptions
;
1734 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
1736 svm
->nested_vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
;
1738 force_new_asid(&svm
->vcpu
);
1739 svm
->vmcb
->control
.exit_int_info
= nested_vmcb
->control
.exit_int_info
;
1740 svm
->vmcb
->control
.exit_int_info_err
= nested_vmcb
->control
.exit_int_info_err
;
1741 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
1742 if (nested_vmcb
->control
.int_ctl
& V_IRQ_MASK
) {
1743 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1744 nested_vmcb
->control
.int_ctl
);
1746 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
1747 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
1749 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
1751 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1752 nested_vmcb
->control
.exit_int_info
,
1753 nested_vmcb
->control
.int_state
);
1755 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
1756 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
1757 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
1758 if (nested_vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
)
1759 nsvm_printk("Injecting Event: 0x%x\n",
1760 nested_vmcb
->control
.event_inj
);
1761 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
1762 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
1764 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1769 static int nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
1771 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
1772 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
1773 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
1774 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
1775 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
1776 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
1777 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
1778 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
1779 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
1780 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
1781 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
1782 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
1787 static int nested_svm_vmload(struct vcpu_svm
*svm
, void *nested_vmcb
,
1788 void *arg2
, void *opaque
)
1790 return nested_svm_vmloadsave((struct vmcb
*)nested_vmcb
, svm
->vmcb
);
1793 static int nested_svm_vmsave(struct vcpu_svm
*svm
, void *nested_vmcb
,
1794 void *arg2
, void *opaque
)
1796 return nested_svm_vmloadsave(svm
->vmcb
, (struct vmcb
*)nested_vmcb
);
1799 static int vmload_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1801 if (nested_svm_check_permissions(svm
))
1804 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1805 skip_emulated_instruction(&svm
->vcpu
);
1807 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmload
);
1812 static int vmsave_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1814 if (nested_svm_check_permissions(svm
))
1817 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1818 skip_emulated_instruction(&svm
->vcpu
);
1820 nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0, NULL
, nested_svm_vmsave
);
1825 static int vmrun_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1827 nsvm_printk("VMrun\n");
1828 if (nested_svm_check_permissions(svm
))
1831 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1832 skip_emulated_instruction(&svm
->vcpu
);
1834 if (nested_svm_do(svm
, svm
->vmcb
->save
.rax
, 0,
1835 NULL
, nested_svm_vmrun
))
1838 if (nested_svm_do(svm
, svm
->nested_vmcb_msrpm
, 0,
1839 NULL
, nested_svm_vmrun_msrpm
))
1845 static int stgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1847 if (nested_svm_check_permissions(svm
))
1850 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1851 skip_emulated_instruction(&svm
->vcpu
);
1853 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
1858 static int clgi_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1860 if (nested_svm_check_permissions(svm
))
1863 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1864 skip_emulated_instruction(&svm
->vcpu
);
1866 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
1868 /* After a CLGI no interrupts should come */
1869 svm_clear_vintr(svm
);
1870 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
1875 static int invlpga_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1877 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1878 nsvm_printk("INVLPGA\n");
1880 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1881 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
1883 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1884 skip_emulated_instruction(&svm
->vcpu
);
1888 static int invalid_op_interception(struct vcpu_svm
*svm
,
1889 struct kvm_run
*kvm_run
)
1891 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1895 static int task_switch_interception(struct vcpu_svm
*svm
,
1896 struct kvm_run
*kvm_run
)
1900 int int_type
= svm
->vmcb
->control
.exit_int_info
&
1901 SVM_EXITINTINFO_TYPE_MASK
;
1902 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
1904 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
1906 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
1908 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
1910 if (svm
->vmcb
->control
.exit_info_2
&
1911 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
1912 reason
= TASK_SWITCH_IRET
;
1913 else if (svm
->vmcb
->control
.exit_info_2
&
1914 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
1915 reason
= TASK_SWITCH_JMP
;
1917 reason
= TASK_SWITCH_GATE
;
1919 reason
= TASK_SWITCH_CALL
;
1921 if (reason
== TASK_SWITCH_GATE
) {
1923 case SVM_EXITINTINFO_TYPE_NMI
:
1924 svm
->vcpu
.arch
.nmi_injected
= false;
1926 case SVM_EXITINTINFO_TYPE_EXEPT
:
1927 kvm_clear_exception_queue(&svm
->vcpu
);
1929 case SVM_EXITINTINFO_TYPE_INTR
:
1930 kvm_clear_interrupt_queue(&svm
->vcpu
);
1937 if (reason
!= TASK_SWITCH_GATE
||
1938 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
1939 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
1940 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
1941 skip_emulated_instruction(&svm
->vcpu
);
1943 return kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
);
1946 static int cpuid_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1948 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
1949 kvm_emulate_cpuid(&svm
->vcpu
);
1953 static int iret_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1955 ++svm
->vcpu
.stat
.nmi_window_exits
;
1956 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
1957 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
1961 static int invlpg_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1963 if (emulate_instruction(&svm
->vcpu
, kvm_run
, 0, 0, 0) != EMULATE_DONE
)
1964 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1968 static int emulate_on_interception(struct vcpu_svm
*svm
,
1969 struct kvm_run
*kvm_run
)
1971 if (emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0) != EMULATE_DONE
)
1972 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
1976 static int cr8_write_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
1978 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
1979 /* instruction emulation calls kvm_set_cr8() */
1980 emulate_instruction(&svm
->vcpu
, NULL
, 0, 0, 0);
1981 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
1982 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
1985 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
1987 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
1991 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
1993 struct vcpu_svm
*svm
= to_svm(vcpu
);
1996 case MSR_IA32_TSC
: {
2000 *data
= svm
->vmcb
->control
.tsc_offset
+ tsc
;
2004 *data
= svm
->vmcb
->save
.star
;
2006 #ifdef CONFIG_X86_64
2008 *data
= svm
->vmcb
->save
.lstar
;
2011 *data
= svm
->vmcb
->save
.cstar
;
2013 case MSR_KERNEL_GS_BASE
:
2014 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2016 case MSR_SYSCALL_MASK
:
2017 *data
= svm
->vmcb
->save
.sfmask
;
2020 case MSR_IA32_SYSENTER_CS
:
2021 *data
= svm
->vmcb
->save
.sysenter_cs
;
2023 case MSR_IA32_SYSENTER_EIP
:
2024 *data
= svm
->sysenter_eip
;
2026 case MSR_IA32_SYSENTER_ESP
:
2027 *data
= svm
->sysenter_esp
;
2029 /* Nobody will change the following 5 values in the VMCB so
2030 we can safely return them on rdmsr. They will always be 0
2031 until LBRV is implemented. */
2032 case MSR_IA32_DEBUGCTLMSR
:
2033 *data
= svm
->vmcb
->save
.dbgctl
;
2035 case MSR_IA32_LASTBRANCHFROMIP
:
2036 *data
= svm
->vmcb
->save
.br_from
;
2038 case MSR_IA32_LASTBRANCHTOIP
:
2039 *data
= svm
->vmcb
->save
.br_to
;
2041 case MSR_IA32_LASTINTFROMIP
:
2042 *data
= svm
->vmcb
->save
.last_excp_from
;
2044 case MSR_IA32_LASTINTTOIP
:
2045 *data
= svm
->vmcb
->save
.last_excp_to
;
2047 case MSR_VM_HSAVE_PA
:
2048 *data
= svm
->hsave_msr
;
2053 case MSR_IA32_UCODE_REV
:
2057 return kvm_get_msr_common(vcpu
, ecx
, data
);
2062 static int rdmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2064 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2067 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
))
2068 kvm_inject_gp(&svm
->vcpu
, 0);
2070 trace_kvm_msr_read(ecx
, data
);
2072 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2073 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2074 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2075 skip_emulated_instruction(&svm
->vcpu
);
2080 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2082 struct vcpu_svm
*svm
= to_svm(vcpu
);
2085 case MSR_IA32_TSC
: {
2089 svm
->vmcb
->control
.tsc_offset
= data
- tsc
;
2093 svm
->vmcb
->save
.star
= data
;
2095 #ifdef CONFIG_X86_64
2097 svm
->vmcb
->save
.lstar
= data
;
2100 svm
->vmcb
->save
.cstar
= data
;
2102 case MSR_KERNEL_GS_BASE
:
2103 svm
->vmcb
->save
.kernel_gs_base
= data
;
2105 case MSR_SYSCALL_MASK
:
2106 svm
->vmcb
->save
.sfmask
= data
;
2109 case MSR_IA32_SYSENTER_CS
:
2110 svm
->vmcb
->save
.sysenter_cs
= data
;
2112 case MSR_IA32_SYSENTER_EIP
:
2113 svm
->sysenter_eip
= data
;
2114 svm
->vmcb
->save
.sysenter_eip
= data
;
2116 case MSR_IA32_SYSENTER_ESP
:
2117 svm
->sysenter_esp
= data
;
2118 svm
->vmcb
->save
.sysenter_esp
= data
;
2120 case MSR_IA32_DEBUGCTLMSR
:
2121 if (!svm_has(SVM_FEATURE_LBRV
)) {
2122 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2126 if (data
& DEBUGCTL_RESERVED_BITS
)
2129 svm
->vmcb
->save
.dbgctl
= data
;
2130 if (data
& (1ULL<<0))
2131 svm_enable_lbrv(svm
);
2133 svm_disable_lbrv(svm
);
2135 case MSR_VM_HSAVE_PA
:
2136 svm
->hsave_msr
= data
;
2140 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2143 return kvm_set_msr_common(vcpu
, ecx
, data
);
2148 static int wrmsr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2150 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2151 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2152 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2154 trace_kvm_msr_write(ecx
, data
);
2156 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2157 if (svm_set_msr(&svm
->vcpu
, ecx
, data
))
2158 kvm_inject_gp(&svm
->vcpu
, 0);
2160 skip_emulated_instruction(&svm
->vcpu
);
2164 static int msr_interception(struct vcpu_svm
*svm
, struct kvm_run
*kvm_run
)
2166 if (svm
->vmcb
->control
.exit_info_1
)
2167 return wrmsr_interception(svm
, kvm_run
);
2169 return rdmsr_interception(svm
, kvm_run
);
2172 static int interrupt_window_interception(struct vcpu_svm
*svm
,
2173 struct kvm_run
*kvm_run
)
2175 svm_clear_vintr(svm
);
2176 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2178 * If the user space waits to inject interrupts, exit as soon as
2181 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2182 kvm_run
->request_interrupt_window
&&
2183 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2184 ++svm
->vcpu
.stat
.irq_window_exits
;
2185 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2192 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
,
2193 struct kvm_run
*kvm_run
) = {
2194 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2195 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2196 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2197 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2199 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2200 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2201 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2202 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2203 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2204 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2205 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2206 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2207 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2208 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2209 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2210 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2211 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2212 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2213 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2214 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2215 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2216 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2217 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2218 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2219 [SVM_EXIT_INTR
] = intr_interception
,
2220 [SVM_EXIT_NMI
] = nmi_interception
,
2221 [SVM_EXIT_SMI
] = nop_on_interception
,
2222 [SVM_EXIT_INIT
] = nop_on_interception
,
2223 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2224 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2225 [SVM_EXIT_CPUID
] = cpuid_interception
,
2226 [SVM_EXIT_IRET
] = iret_interception
,
2227 [SVM_EXIT_INVD
] = emulate_on_interception
,
2228 [SVM_EXIT_HLT
] = halt_interception
,
2229 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2230 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2231 [SVM_EXIT_IOIO
] = io_interception
,
2232 [SVM_EXIT_MSR
] = msr_interception
,
2233 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2234 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2235 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2236 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2237 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2238 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2239 [SVM_EXIT_STGI
] = stgi_interception
,
2240 [SVM_EXIT_CLGI
] = clgi_interception
,
2241 [SVM_EXIT_SKINIT
] = invalid_op_interception
,
2242 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2243 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2244 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2245 [SVM_EXIT_NPF
] = pf_interception
,
2248 static int handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
2250 struct vcpu_svm
*svm
= to_svm(vcpu
);
2251 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2253 trace_kvm_exit(exit_code
, svm
->vmcb
->save
.rip
);
2255 if (is_nested(svm
)) {
2256 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2257 exit_code
, svm
->vmcb
->control
.exit_info_1
,
2258 svm
->vmcb
->control
.exit_info_2
, svm
->vmcb
->save
.rip
);
2259 if (nested_svm_exit_handled(svm
, true)) {
2260 nested_svm_vmexit(svm
);
2261 nsvm_printk("-> #VMEXIT\n");
2268 if ((vcpu
->arch
.cr0
^ svm
->vmcb
->save
.cr0
) & X86_CR0_PG
) {
2269 svm_set_cr0(vcpu
, svm
->vmcb
->save
.cr0
);
2272 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2273 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2275 kvm_mmu_reset_context(vcpu
);
2281 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2282 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2283 kvm_run
->fail_entry
.hardware_entry_failure_reason
2284 = svm
->vmcb
->control
.exit_code
;
2288 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2289 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2290 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
)
2291 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2293 __func__
, svm
->vmcb
->control
.exit_int_info
,
2296 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2297 || !svm_exit_handlers
[exit_code
]) {
2298 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2299 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2303 return svm_exit_handlers
[exit_code
](svm
, kvm_run
);
2306 static void reload_tss(struct kvm_vcpu
*vcpu
)
2308 int cpu
= raw_smp_processor_id();
2310 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2311 svm_data
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2315 static void pre_svm_run(struct vcpu_svm
*svm
)
2317 int cpu
= raw_smp_processor_id();
2319 struct svm_cpu_data
*svm_data
= per_cpu(svm_data
, cpu
);
2321 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2322 /* FIXME: handle wraparound of asid_generation */
2323 if (svm
->asid_generation
!= svm_data
->asid_generation
)
2324 new_asid(svm
, svm_data
);
2327 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
2329 struct vcpu_svm
*svm
= to_svm(vcpu
);
2331 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
2332 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
2333 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2334 ++vcpu
->stat
.nmi_injections
;
2337 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2339 struct vmcb_control_area
*control
;
2341 trace_kvm_inj_virq(irq
);
2343 ++svm
->vcpu
.stat
.irq_injections
;
2344 control
= &svm
->vmcb
->control
;
2345 control
->int_vector
= irq
;
2346 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2347 control
->int_ctl
|= V_IRQ_MASK
|
2348 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2351 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
2353 struct vcpu_svm
*svm
= to_svm(vcpu
);
2355 BUG_ON(!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
));
2357 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
2358 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
2361 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
2363 struct vcpu_svm
*svm
= to_svm(vcpu
);
2369 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2372 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
2374 struct vcpu_svm
*svm
= to_svm(vcpu
);
2375 struct vmcb
*vmcb
= svm
->vmcb
;
2376 return !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2377 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2380 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2382 struct vcpu_svm
*svm
= to_svm(vcpu
);
2383 struct vmcb
*vmcb
= svm
->vmcb
;
2384 return (vmcb
->save
.rflags
& X86_EFLAGS_IF
) &&
2385 !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2386 (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
) &&
2390 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2392 struct vcpu_svm
*svm
= to_svm(vcpu
);
2393 nsvm_printk("Trying to open IRQ window\n");
2395 nested_svm_intr(svm
);
2397 /* In case GIF=0 we can't rely on the CPU to tell us when
2398 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2399 * The next time we get that intercept, this function will be
2400 * called again though and we'll get the vintr intercept. */
2401 if (svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
) {
2403 svm_inject_irq(svm
, 0x0);
2407 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2409 struct vcpu_svm
*svm
= to_svm(vcpu
);
2411 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
2413 return; /* IRET will cause a vm exit */
2415 /* Something prevents NMI from been injected. Single step over
2416 possible problem (IRET or exception injection or interrupt
2418 vcpu
->arch
.singlestep
= true;
2419 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2420 update_db_intercept(vcpu
);
2423 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2428 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
2430 force_new_asid(vcpu
);
2433 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
2437 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
2439 struct vcpu_svm
*svm
= to_svm(vcpu
);
2441 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
2442 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
2443 kvm_set_cr8(vcpu
, cr8
);
2447 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
2449 struct vcpu_svm
*svm
= to_svm(vcpu
);
2452 cr8
= kvm_get_cr8(vcpu
);
2453 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
2454 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
2457 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
2461 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
2463 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
2464 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
2466 svm
->vcpu
.arch
.nmi_injected
= false;
2467 kvm_clear_exception_queue(&svm
->vcpu
);
2468 kvm_clear_interrupt_queue(&svm
->vcpu
);
2470 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
2473 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
2474 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
2477 case SVM_EXITINTINFO_TYPE_NMI
:
2478 svm
->vcpu
.arch
.nmi_injected
= true;
2480 case SVM_EXITINTINFO_TYPE_EXEPT
:
2481 /* In case of software exception do not reinject an exception
2482 vector, but re-execute and instruction instead */
2485 if (kvm_exception_is_soft(vector
))
2487 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
2488 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
2489 kvm_queue_exception_e(&svm
->vcpu
, vector
, err
);
2492 kvm_queue_exception(&svm
->vcpu
, vector
);
2494 case SVM_EXITINTINFO_TYPE_INTR
:
2495 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
2502 #ifdef CONFIG_X86_64
2508 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2510 struct vcpu_svm
*svm
= to_svm(vcpu
);
2515 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
2516 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
2517 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
2521 sync_lapic_to_cr8(vcpu
);
2523 save_host_msrs(vcpu
);
2524 fs_selector
= kvm_read_fs();
2525 gs_selector
= kvm_read_gs();
2526 ldt_selector
= kvm_read_ldt();
2527 if (!is_nested(svm
))
2528 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
2529 /* required for live migration with NPT */
2531 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
2538 "push %%"R
"bp; \n\t"
2539 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
2540 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
2541 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
2542 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
2543 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
2544 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
2545 #ifdef CONFIG_X86_64
2546 "mov %c[r8](%[svm]), %%r8 \n\t"
2547 "mov %c[r9](%[svm]), %%r9 \n\t"
2548 "mov %c[r10](%[svm]), %%r10 \n\t"
2549 "mov %c[r11](%[svm]), %%r11 \n\t"
2550 "mov %c[r12](%[svm]), %%r12 \n\t"
2551 "mov %c[r13](%[svm]), %%r13 \n\t"
2552 "mov %c[r14](%[svm]), %%r14 \n\t"
2553 "mov %c[r15](%[svm]), %%r15 \n\t"
2556 /* Enter guest mode */
2558 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
2559 __ex(SVM_VMLOAD
) "\n\t"
2560 __ex(SVM_VMRUN
) "\n\t"
2561 __ex(SVM_VMSAVE
) "\n\t"
2564 /* Save guest registers, load host registers */
2565 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
2566 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
2567 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
2568 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
2569 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
2570 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
2571 #ifdef CONFIG_X86_64
2572 "mov %%r8, %c[r8](%[svm]) \n\t"
2573 "mov %%r9, %c[r9](%[svm]) \n\t"
2574 "mov %%r10, %c[r10](%[svm]) \n\t"
2575 "mov %%r11, %c[r11](%[svm]) \n\t"
2576 "mov %%r12, %c[r12](%[svm]) \n\t"
2577 "mov %%r13, %c[r13](%[svm]) \n\t"
2578 "mov %%r14, %c[r14](%[svm]) \n\t"
2579 "mov %%r15, %c[r15](%[svm]) \n\t"
2584 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
2585 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
2586 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
2587 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
2588 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
2589 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
2590 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
2591 #ifdef CONFIG_X86_64
2592 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
2593 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
2594 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
2595 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
2596 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
2597 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
2598 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
2599 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
2602 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
2603 #ifdef CONFIG_X86_64
2604 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2608 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
2609 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
2610 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
2611 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
2613 kvm_load_fs(fs_selector
);
2614 kvm_load_gs(gs_selector
);
2615 kvm_load_ldt(ldt_selector
);
2616 load_host_msrs(vcpu
);
2620 local_irq_disable();
2624 sync_cr8_to_lapic(vcpu
);
2629 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
2630 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
2633 svm_complete_interrupts(svm
);
2638 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
2640 struct vcpu_svm
*svm
= to_svm(vcpu
);
2643 svm
->vmcb
->control
.nested_cr3
= root
;
2644 force_new_asid(vcpu
);
2648 svm
->vmcb
->save
.cr3
= root
;
2649 force_new_asid(vcpu
);
2651 if (vcpu
->fpu_active
) {
2652 svm
->vmcb
->control
.intercept_exceptions
|= (1 << NM_VECTOR
);
2653 svm
->vmcb
->save
.cr0
|= X86_CR0_TS
;
2654 vcpu
->fpu_active
= 0;
2658 static int is_disabled(void)
2662 rdmsrl(MSR_VM_CR
, vm_cr
);
2663 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
2670 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2673 * Patch in the VMMCALL instruction:
2675 hypercall
[0] = 0x0f;
2676 hypercall
[1] = 0x01;
2677 hypercall
[2] = 0xd9;
2680 static void svm_check_processor_compat(void *rtn
)
2685 static bool svm_cpu_has_accelerated_tpr(void)
2690 static int get_npt_level(void)
2692 #ifdef CONFIG_X86_64
2693 return PT64_ROOT_LEVEL
;
2695 return PT32E_ROOT_LEVEL
;
2699 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
2704 static const struct trace_print_flags svm_exit_reasons_str
[] = {
2705 { SVM_EXIT_READ_CR0
, "read_cr0" },
2706 { SVM_EXIT_READ_CR3
, "read_cr3" },
2707 { SVM_EXIT_READ_CR4
, "read_cr4" },
2708 { SVM_EXIT_READ_CR8
, "read_cr8" },
2709 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
2710 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
2711 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
2712 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
2713 { SVM_EXIT_READ_DR0
, "read_dr0" },
2714 { SVM_EXIT_READ_DR1
, "read_dr1" },
2715 { SVM_EXIT_READ_DR2
, "read_dr2" },
2716 { SVM_EXIT_READ_DR3
, "read_dr3" },
2717 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
2718 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
2719 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
2720 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
2721 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
2722 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
2723 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
2724 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
2725 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
2726 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
2727 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
2728 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
2729 { SVM_EXIT_INTR
, "interrupt" },
2730 { SVM_EXIT_NMI
, "nmi" },
2731 { SVM_EXIT_SMI
, "smi" },
2732 { SVM_EXIT_INIT
, "init" },
2733 { SVM_EXIT_VINTR
, "vintr" },
2734 { SVM_EXIT_CPUID
, "cpuid" },
2735 { SVM_EXIT_INVD
, "invd" },
2736 { SVM_EXIT_HLT
, "hlt" },
2737 { SVM_EXIT_INVLPG
, "invlpg" },
2738 { SVM_EXIT_INVLPGA
, "invlpga" },
2739 { SVM_EXIT_IOIO
, "io" },
2740 { SVM_EXIT_MSR
, "msr" },
2741 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
2742 { SVM_EXIT_SHUTDOWN
, "shutdown" },
2743 { SVM_EXIT_VMRUN
, "vmrun" },
2744 { SVM_EXIT_VMMCALL
, "hypercall" },
2745 { SVM_EXIT_VMLOAD
, "vmload" },
2746 { SVM_EXIT_VMSAVE
, "vmsave" },
2747 { SVM_EXIT_STGI
, "stgi" },
2748 { SVM_EXIT_CLGI
, "clgi" },
2749 { SVM_EXIT_SKINIT
, "skinit" },
2750 { SVM_EXIT_WBINVD
, "wbinvd" },
2751 { SVM_EXIT_MONITOR
, "monitor" },
2752 { SVM_EXIT_MWAIT
, "mwait" },
2753 { SVM_EXIT_NPF
, "npf" },
2757 static struct kvm_x86_ops svm_x86_ops
= {
2758 .cpu_has_kvm_support
= has_svm
,
2759 .disabled_by_bios
= is_disabled
,
2760 .hardware_setup
= svm_hardware_setup
,
2761 .hardware_unsetup
= svm_hardware_unsetup
,
2762 .check_processor_compatibility
= svm_check_processor_compat
,
2763 .hardware_enable
= svm_hardware_enable
,
2764 .hardware_disable
= svm_hardware_disable
,
2765 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
2767 .vcpu_create
= svm_create_vcpu
,
2768 .vcpu_free
= svm_free_vcpu
,
2769 .vcpu_reset
= svm_vcpu_reset
,
2771 .prepare_guest_switch
= svm_prepare_guest_switch
,
2772 .vcpu_load
= svm_vcpu_load
,
2773 .vcpu_put
= svm_vcpu_put
,
2775 .set_guest_debug
= svm_guest_debug
,
2776 .get_msr
= svm_get_msr
,
2777 .set_msr
= svm_set_msr
,
2778 .get_segment_base
= svm_get_segment_base
,
2779 .get_segment
= svm_get_segment
,
2780 .set_segment
= svm_set_segment
,
2781 .get_cpl
= svm_get_cpl
,
2782 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
2783 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
2784 .set_cr0
= svm_set_cr0
,
2785 .set_cr3
= svm_set_cr3
,
2786 .set_cr4
= svm_set_cr4
,
2787 .set_efer
= svm_set_efer
,
2788 .get_idt
= svm_get_idt
,
2789 .set_idt
= svm_set_idt
,
2790 .get_gdt
= svm_get_gdt
,
2791 .set_gdt
= svm_set_gdt
,
2792 .get_dr
= svm_get_dr
,
2793 .set_dr
= svm_set_dr
,
2794 .cache_reg
= svm_cache_reg
,
2795 .get_rflags
= svm_get_rflags
,
2796 .set_rflags
= svm_set_rflags
,
2798 .tlb_flush
= svm_flush_tlb
,
2800 .run
= svm_vcpu_run
,
2801 .handle_exit
= handle_exit
,
2802 .skip_emulated_instruction
= skip_emulated_instruction
,
2803 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
2804 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
2805 .patch_hypercall
= svm_patch_hypercall
,
2806 .set_irq
= svm_set_irq
,
2807 .set_nmi
= svm_inject_nmi
,
2808 .queue_exception
= svm_queue_exception
,
2809 .interrupt_allowed
= svm_interrupt_allowed
,
2810 .nmi_allowed
= svm_nmi_allowed
,
2811 .enable_nmi_window
= enable_nmi_window
,
2812 .enable_irq_window
= enable_irq_window
,
2813 .update_cr8_intercept
= update_cr8_intercept
,
2815 .set_tss_addr
= svm_set_tss_addr
,
2816 .get_tdp_level
= get_npt_level
,
2817 .get_mt_mask
= svm_get_mt_mask
,
2819 .exit_reasons_str
= svm_exit_reasons_str
,
2822 static int __init
svm_init(void)
2824 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
2828 static void __exit
svm_exit(void)
2833 module_init(svm_init
)
2834 module_exit(svm_exit
)