2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/spec-ctrl.h>
54 #include <asm/virtext.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id svm_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
66 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
68 #define IOPM_ALLOC_ORDER 2
69 #define MSRPM_ALLOC_ORDER 1
71 #define SEG_TYPE_LDT 2
72 #define SEG_TYPE_BUSY_TSS16 3
74 #define SVM_FEATURE_NPT (1 << 0)
75 #define SVM_FEATURE_LBRV (1 << 1)
76 #define SVM_FEATURE_SVML (1 << 2)
77 #define SVM_FEATURE_NRIP (1 << 3)
78 #define SVM_FEATURE_TSC_RATE (1 << 4)
79 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
80 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
81 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
82 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
84 #define SVM_AVIC_DOORBELL 0xc001011b
86 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
87 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
88 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
90 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
92 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
93 #define TSC_RATIO_MIN 0x0000000000000001ULL
94 #define TSC_RATIO_MAX 0x000000ffffffffffULL
96 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
99 * 0xff is broadcast, so the max index allowed for physical APIC ID
100 * table is 0xfe. APIC IDs above 0xff are reserved.
102 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
104 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
105 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
106 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
108 /* AVIC GATAG is encoded using VM and VCPU IDs */
109 #define AVIC_VCPU_ID_BITS 8
110 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
112 #define AVIC_VM_ID_BITS 24
113 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
114 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
116 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
117 (y & AVIC_VCPU_ID_MASK))
118 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
119 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
121 static bool erratum_383_found __read_mostly
;
123 static const u32 host_save_user_msrs
[] = {
125 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
128 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
132 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
134 struct kvm_sev_info
{
135 bool active
; /* SEV enabled guest */
136 unsigned int asid
; /* ASID used for this guest */
137 unsigned int handle
; /* SEV firmware handle */
138 int fd
; /* SEV device fd */
139 unsigned long pages_locked
; /* Number of pages locked */
140 struct list_head regions_list
; /* List of registered regions */
146 /* Struct members for AVIC */
149 struct page
*avic_logical_id_table_page
;
150 struct page
*avic_physical_id_table_page
;
151 struct hlist_node hnode
;
153 struct kvm_sev_info sev_info
;
158 struct nested_state
{
164 /* These are the merged vectors */
167 /* gpa pointers to the real vectors */
171 /* A VMEXIT is required but not yet emulated */
174 /* cache for intercepts of the guest */
177 u32 intercept_exceptions
;
180 /* Nested Paging related state */
184 #define MSRPM_OFFSETS 16
185 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
188 * Set osvw_len to higher value when updated Revision Guides
189 * are published and we know what the new status bits are
191 static uint64_t osvw_len
= 4, osvw_status
;
194 struct kvm_vcpu vcpu
;
196 unsigned long vmcb_pa
;
197 struct svm_cpu_data
*svm_data
;
198 uint64_t asid_generation
;
199 uint64_t sysenter_esp
;
200 uint64_t sysenter_eip
;
207 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
217 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
218 * translated into the appropriate L2_CFG bits on the host to
219 * perform speculative control.
227 struct nested_state nested
;
230 u64 nmi_singlestep_guest_rflags
;
232 unsigned int3_injected
;
233 unsigned long int3_rip
;
235 /* cached guest cpuid flags for faster access */
236 bool nrips_enabled
: 1;
239 struct page
*avic_backing_page
;
240 u64
*avic_physical_id_cache
;
241 bool avic_is_running
;
244 * Per-vcpu list of struct amd_svm_iommu_ir:
245 * This is used mainly to store interrupt remapping information used
246 * when update the vcpu affinity. This avoids the need to scan for
247 * IRTE and try to match ga_tag in the IOMMU driver.
249 struct list_head ir_list
;
250 spinlock_t ir_list_lock
;
252 /* which host CPU was used for running this vcpu */
253 unsigned int last_cpu
;
257 * This is a wrapper of struct amd_iommu_ir_data.
259 struct amd_svm_iommu_ir
{
260 struct list_head node
; /* Used by SVM for per-vcpu ir_list */
261 void *data
; /* Storing pointer to struct amd_ir_data */
264 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
265 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
267 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
268 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
269 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
270 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
272 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
273 #define TSC_RATIO_DEFAULT 0x0100000000ULL
275 #define MSR_INVALID 0xffffffffU
277 static const struct svm_direct_access_msrs
{
278 u32 index
; /* Index of the MSR */
279 bool always
; /* True if intercept is always on */
280 } direct_access_msrs
[] = {
281 { .index
= MSR_STAR
, .always
= true },
282 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
284 { .index
= MSR_GS_BASE
, .always
= true },
285 { .index
= MSR_FS_BASE
, .always
= true },
286 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
287 { .index
= MSR_LSTAR
, .always
= true },
288 { .index
= MSR_CSTAR
, .always
= true },
289 { .index
= MSR_SYSCALL_MASK
, .always
= true },
291 { .index
= MSR_IA32_SPEC_CTRL
, .always
= false },
292 { .index
= MSR_IA32_PRED_CMD
, .always
= false },
293 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
294 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
295 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
296 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
297 { .index
= MSR_INVALID
, .always
= false },
300 /* enable NPT for AMD64 and X86 with PAE */
301 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
302 static bool npt_enabled
= true;
304 static bool npt_enabled
;
308 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
309 * pause_filter_count: On processors that support Pause filtering(indicated
310 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
311 * count value. On VMRUN this value is loaded into an internal counter.
312 * Each time a pause instruction is executed, this counter is decremented
313 * until it reaches zero at which time a #VMEXIT is generated if pause
314 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
315 * Intercept Filtering for more details.
316 * This also indicate if ple logic enabled.
318 * pause_filter_thresh: In addition, some processor families support advanced
319 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
320 * the amount of time a guest is allowed to execute in a pause loop.
321 * In this mode, a 16-bit pause filter threshold field is added in the
322 * VMCB. The threshold value is a cycle count that is used to reset the
323 * pause counter. As with simple pause filtering, VMRUN loads the pause
324 * count value from VMCB into an internal counter. Then, on each pause
325 * instruction the hardware checks the elapsed number of cycles since
326 * the most recent pause instruction against the pause filter threshold.
327 * If the elapsed cycle count is greater than the pause filter threshold,
328 * then the internal pause count is reloaded from the VMCB and execution
329 * continues. If the elapsed cycle count is less than the pause filter
330 * threshold, then the internal pause count is decremented. If the count
331 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
332 * triggered. If advanced pause filtering is supported and pause filter
333 * threshold field is set to zero, the filter will operate in the simpler,
337 static unsigned short pause_filter_thresh
= KVM_DEFAULT_PLE_GAP
;
338 module_param(pause_filter_thresh
, ushort
, 0444);
340 static unsigned short pause_filter_count
= KVM_SVM_DEFAULT_PLE_WINDOW
;
341 module_param(pause_filter_count
, ushort
, 0444);
343 /* Default doubles per-vcpu window every exit. */
344 static unsigned short pause_filter_count_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
345 module_param(pause_filter_count_grow
, ushort
, 0444);
347 /* Default resets per-vcpu window every exit to pause_filter_count. */
348 static unsigned short pause_filter_count_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
349 module_param(pause_filter_count_shrink
, ushort
, 0444);
351 /* Default is to compute the maximum so we can never overflow. */
352 static unsigned short pause_filter_count_max
= KVM_SVM_DEFAULT_PLE_WINDOW_MAX
;
353 module_param(pause_filter_count_max
, ushort
, 0444);
355 /* allow nested paging (virtualized MMU) for all guests */
356 static int npt
= true;
357 module_param(npt
, int, S_IRUGO
);
359 /* allow nested virtualization in KVM/SVM */
360 static int nested
= true;
361 module_param(nested
, int, S_IRUGO
);
363 /* enable / disable AVIC */
365 #ifdef CONFIG_X86_LOCAL_APIC
366 module_param(avic
, int, S_IRUGO
);
369 /* enable/disable Virtual VMLOAD VMSAVE */
370 static int vls
= true;
371 module_param(vls
, int, 0444);
373 /* enable/disable Virtual GIF */
374 static int vgif
= true;
375 module_param(vgif
, int, 0444);
377 /* enable/disable SEV support */
378 static int sev
= IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
);
379 module_param(sev
, int, 0444);
381 static u8 rsm_ins_bytes
[] = "\x0f\xaa";
383 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
384 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
);
385 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
387 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
388 static int nested_svm_intercept(struct vcpu_svm
*svm
);
389 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
390 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
391 bool has_error_code
, u32 error_code
);
394 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
395 pause filter count */
396 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
397 VMCB_ASID
, /* ASID */
398 VMCB_INTR
, /* int_ctl, int_vector */
399 VMCB_NPT
, /* npt_en, nCR3, gPAT */
400 VMCB_CR
, /* CR0, CR3, CR4, EFER */
401 VMCB_DR
, /* DR6, DR7 */
402 VMCB_DT
, /* GDT, IDT */
403 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
404 VMCB_CR2
, /* CR2 only */
405 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
406 VMCB_AVIC
, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
407 * AVIC PHYSICAL_TABLE pointer,
408 * AVIC LOGICAL_TABLE pointer
413 /* TPR and CR2 are always written before VMRUN */
414 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
416 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
418 static unsigned int max_sev_asid
;
419 static unsigned int min_sev_asid
;
420 static unsigned long *sev_asid_bitmap
;
421 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
424 struct list_head list
;
425 unsigned long npages
;
432 static inline struct kvm_svm
*to_kvm_svm(struct kvm
*kvm
)
434 return container_of(kvm
, struct kvm_svm
, kvm
);
437 static inline bool svm_sev_enabled(void)
442 static inline bool sev_guest(struct kvm
*kvm
)
444 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
449 static inline int sev_get_asid(struct kvm
*kvm
)
451 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
456 static inline void mark_all_dirty(struct vmcb
*vmcb
)
458 vmcb
->control
.clean
= 0;
461 static inline void mark_all_clean(struct vmcb
*vmcb
)
463 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
464 & ~VMCB_ALWAYS_DIRTY_MASK
;
467 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
469 vmcb
->control
.clean
&= ~(1 << bit
);
472 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
474 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
477 static inline void avic_update_vapic_bar(struct vcpu_svm
*svm
, u64 data
)
479 svm
->vmcb
->control
.avic_vapic_bar
= data
& VMCB_AVIC_APIC_BAR_MASK
;
480 mark_dirty(svm
->vmcb
, VMCB_AVIC
);
483 static inline bool avic_vcpu_is_running(struct kvm_vcpu
*vcpu
)
485 struct vcpu_svm
*svm
= to_svm(vcpu
);
486 u64
*entry
= svm
->avic_physical_id_cache
;
491 return (READ_ONCE(*entry
) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
494 static void recalc_intercepts(struct vcpu_svm
*svm
)
496 struct vmcb_control_area
*c
, *h
;
497 struct nested_state
*g
;
499 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
501 if (!is_guest_mode(&svm
->vcpu
))
504 c
= &svm
->vmcb
->control
;
505 h
= &svm
->nested
.hsave
->control
;
508 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
509 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
510 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
511 c
->intercept
= h
->intercept
| g
->intercept
;
514 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
516 if (is_guest_mode(&svm
->vcpu
))
517 return svm
->nested
.hsave
;
522 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
524 struct vmcb
*vmcb
= get_host_vmcb(svm
);
526 vmcb
->control
.intercept_cr
|= (1U << bit
);
528 recalc_intercepts(svm
);
531 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
533 struct vmcb
*vmcb
= get_host_vmcb(svm
);
535 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
537 recalc_intercepts(svm
);
540 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
542 struct vmcb
*vmcb
= get_host_vmcb(svm
);
544 return vmcb
->control
.intercept_cr
& (1U << bit
);
547 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
549 struct vmcb
*vmcb
= get_host_vmcb(svm
);
551 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
552 | (1 << INTERCEPT_DR1_READ
)
553 | (1 << INTERCEPT_DR2_READ
)
554 | (1 << INTERCEPT_DR3_READ
)
555 | (1 << INTERCEPT_DR4_READ
)
556 | (1 << INTERCEPT_DR5_READ
)
557 | (1 << INTERCEPT_DR6_READ
)
558 | (1 << INTERCEPT_DR7_READ
)
559 | (1 << INTERCEPT_DR0_WRITE
)
560 | (1 << INTERCEPT_DR1_WRITE
)
561 | (1 << INTERCEPT_DR2_WRITE
)
562 | (1 << INTERCEPT_DR3_WRITE
)
563 | (1 << INTERCEPT_DR4_WRITE
)
564 | (1 << INTERCEPT_DR5_WRITE
)
565 | (1 << INTERCEPT_DR6_WRITE
)
566 | (1 << INTERCEPT_DR7_WRITE
);
568 recalc_intercepts(svm
);
571 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
573 struct vmcb
*vmcb
= get_host_vmcb(svm
);
575 vmcb
->control
.intercept_dr
= 0;
577 recalc_intercepts(svm
);
580 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
582 struct vmcb
*vmcb
= get_host_vmcb(svm
);
584 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
586 recalc_intercepts(svm
);
589 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
591 struct vmcb
*vmcb
= get_host_vmcb(svm
);
593 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
595 recalc_intercepts(svm
);
598 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
600 struct vmcb
*vmcb
= get_host_vmcb(svm
);
602 vmcb
->control
.intercept
|= (1ULL << bit
);
604 recalc_intercepts(svm
);
607 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
609 struct vmcb
*vmcb
= get_host_vmcb(svm
);
611 vmcb
->control
.intercept
&= ~(1ULL << bit
);
613 recalc_intercepts(svm
);
616 static inline bool vgif_enabled(struct vcpu_svm
*svm
)
618 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_ENABLE_MASK
);
621 static inline void enable_gif(struct vcpu_svm
*svm
)
623 if (vgif_enabled(svm
))
624 svm
->vmcb
->control
.int_ctl
|= V_GIF_MASK
;
626 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
629 static inline void disable_gif(struct vcpu_svm
*svm
)
631 if (vgif_enabled(svm
))
632 svm
->vmcb
->control
.int_ctl
&= ~V_GIF_MASK
;
634 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
637 static inline bool gif_set(struct vcpu_svm
*svm
)
639 if (vgif_enabled(svm
))
640 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_MASK
);
642 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
645 static unsigned long iopm_base
;
647 struct kvm_ldttss_desc
{
650 unsigned base1
:8, type
:5, dpl
:2, p
:1;
651 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
654 } __attribute__((packed
));
656 struct svm_cpu_data
{
663 struct kvm_ldttss_desc
*tss_desc
;
665 struct page
*save_area
;
666 struct vmcb
*current_vmcb
;
668 /* index = sev_asid, value = vmcb pointer */
669 struct vmcb
**sev_vmcbs
;
672 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
674 struct svm_init_data
{
679 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
681 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
682 #define MSRS_RANGE_SIZE 2048
683 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
685 static u32
svm_msrpm_offset(u32 msr
)
690 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
691 if (msr
< msrpm_ranges
[i
] ||
692 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
695 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
696 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
698 /* Now we have the u8 offset - but need the u32 offset */
702 /* MSR not in any range */
706 #define MAX_INST_SIZE 15
708 static inline void clgi(void)
710 asm volatile (__ex(SVM_CLGI
));
713 static inline void stgi(void)
715 asm volatile (__ex(SVM_STGI
));
718 static inline void invlpga(unsigned long addr
, u32 asid
)
720 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
723 static int get_npt_level(struct kvm_vcpu
*vcpu
)
726 return PT64_ROOT_4LEVEL
;
728 return PT32E_ROOT_LEVEL
;
732 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
734 vcpu
->arch
.efer
= efer
;
735 if (!npt_enabled
&& !(efer
& EFER_LMA
))
738 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
739 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
742 static int is_external_interrupt(u32 info
)
744 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
745 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
748 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
750 struct vcpu_svm
*svm
= to_svm(vcpu
);
753 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
754 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
758 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
760 struct vcpu_svm
*svm
= to_svm(vcpu
);
763 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
765 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
769 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
771 struct vcpu_svm
*svm
= to_svm(vcpu
);
773 if (svm
->vmcb
->control
.next_rip
!= 0) {
774 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
775 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
778 if (!svm
->next_rip
) {
779 if (kvm_emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
781 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
784 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
785 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
786 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
788 kvm_rip_write(vcpu
, svm
->next_rip
);
789 svm_set_interrupt_shadow(vcpu
, 0);
792 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
794 struct vcpu_svm
*svm
= to_svm(vcpu
);
795 unsigned nr
= vcpu
->arch
.exception
.nr
;
796 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
797 bool reinject
= vcpu
->arch
.exception
.injected
;
798 u32 error_code
= vcpu
->arch
.exception
.error_code
;
801 * If we are within a nested VM we'd better #VMEXIT and let the guest
802 * handle the exception
805 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
808 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
809 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
812 * For guest debugging where we have to reinject #BP if some
813 * INT3 is guest-owned:
814 * Emulate nRIP by moving RIP forward. Will fail if injection
815 * raises a fault that is not intercepted. Still better than
816 * failing in all cases.
818 skip_emulated_instruction(&svm
->vcpu
);
819 rip
= kvm_rip_read(&svm
->vcpu
);
820 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
821 svm
->int3_injected
= rip
- old_rip
;
824 svm
->vmcb
->control
.event_inj
= nr
826 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
827 | SVM_EVTINJ_TYPE_EXEPT
;
828 svm
->vmcb
->control
.event_inj_err
= error_code
;
831 static void svm_init_erratum_383(void)
837 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
840 /* Use _safe variants to not break nested virtualization */
841 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
847 low
= lower_32_bits(val
);
848 high
= upper_32_bits(val
);
850 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
852 erratum_383_found
= true;
855 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
858 * Guests should see errata 400 and 415 as fixed (assuming that
859 * HLT and IO instructions are intercepted).
861 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
862 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
865 * By increasing VCPU's osvw.length to 3 we are telling the guest that
866 * all osvw.status bits inside that length, including bit 0 (which is
867 * reserved for erratum 298), are valid. However, if host processor's
868 * osvw_len is 0 then osvw_status[0] carries no information. We need to
869 * be conservative here and therefore we tell the guest that erratum 298
870 * is present (because we really don't know).
872 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
873 vcpu
->arch
.osvw
.status
|= 1;
876 static int has_svm(void)
880 if (!cpu_has_svm(&msg
)) {
881 printk(KERN_INFO
"has_svm: %s\n", msg
);
888 static void svm_hardware_disable(void)
890 /* Make sure we clean up behind us */
891 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
892 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
896 amd_pmu_disable_virt();
899 static int svm_hardware_enable(void)
902 struct svm_cpu_data
*sd
;
904 struct desc_struct
*gdt
;
905 int me
= raw_smp_processor_id();
907 rdmsrl(MSR_EFER
, efer
);
908 if (efer
& EFER_SVME
)
912 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
915 sd
= per_cpu(svm_data
, me
);
917 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
921 sd
->asid_generation
= 1;
922 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
923 sd
->next_asid
= sd
->max_asid
+ 1;
924 sd
->min_asid
= max_sev_asid
+ 1;
926 gdt
= get_current_gdt_rw();
927 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
929 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
931 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
933 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
934 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
935 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
942 * Note that it is possible to have a system with mixed processor
943 * revisions and therefore different OSVW bits. If bits are not the same
944 * on different processors then choose the worst case (i.e. if erratum
945 * is present on one processor and not on another then assume that the
946 * erratum is present everywhere).
948 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
949 uint64_t len
, status
= 0;
952 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
954 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
958 osvw_status
= osvw_len
= 0;
962 osvw_status
|= status
;
963 osvw_status
&= (1ULL << osvw_len
) - 1;
966 osvw_status
= osvw_len
= 0;
968 svm_init_erratum_383();
970 amd_pmu_enable_virt();
975 static void svm_cpu_uninit(int cpu
)
977 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
982 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
983 kfree(sd
->sev_vmcbs
);
984 __free_page(sd
->save_area
);
988 static int svm_cpu_init(int cpu
)
990 struct svm_cpu_data
*sd
;
993 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
998 sd
->save_area
= alloc_page(GFP_KERNEL
);
1002 if (svm_sev_enabled()) {
1004 sd
->sev_vmcbs
= kmalloc_array(max_sev_asid
+ 1,
1011 per_cpu(svm_data
, cpu
) = sd
;
1021 static bool valid_msr_intercept(u32 index
)
1025 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
1026 if (direct_access_msrs
[i
].index
== index
)
1032 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, unsigned msr
)
1039 msrpm
= is_guest_mode(vcpu
) ? to_svm(vcpu
)->nested
.msrpm
:
1040 to_svm(vcpu
)->msrpm
;
1042 offset
= svm_msrpm_offset(msr
);
1043 bit_write
= 2 * (msr
& 0x0f) + 1;
1044 tmp
= msrpm
[offset
];
1046 BUG_ON(offset
== MSR_INVALID
);
1048 return !!test_bit(bit_write
, &tmp
);
1051 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
1052 int read
, int write
)
1054 u8 bit_read
, bit_write
;
1059 * If this warning triggers extend the direct_access_msrs list at the
1060 * beginning of the file
1062 WARN_ON(!valid_msr_intercept(msr
));
1064 offset
= svm_msrpm_offset(msr
);
1065 bit_read
= 2 * (msr
& 0x0f);
1066 bit_write
= 2 * (msr
& 0x0f) + 1;
1067 tmp
= msrpm
[offset
];
1069 BUG_ON(offset
== MSR_INVALID
);
1071 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
1072 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
1074 msrpm
[offset
] = tmp
;
1077 static void svm_vcpu_init_msrpm(u32
*msrpm
)
1081 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
1083 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
1084 if (!direct_access_msrs
[i
].always
)
1087 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
1091 static void add_msr_offset(u32 offset
)
1095 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
1097 /* Offset already in list? */
1098 if (msrpm_offsets
[i
] == offset
)
1101 /* Slot used by another offset? */
1102 if (msrpm_offsets
[i
] != MSR_INVALID
)
1105 /* Add offset to list */
1106 msrpm_offsets
[i
] = offset
;
1112 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1113 * increase MSRPM_OFFSETS in this case.
1118 static void init_msrpm_offsets(void)
1122 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
1124 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
1127 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
1128 BUG_ON(offset
== MSR_INVALID
);
1130 add_msr_offset(offset
);
1134 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
1136 u32
*msrpm
= svm
->msrpm
;
1138 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
1139 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
1140 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
1141 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
1142 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
1145 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
1147 u32
*msrpm
= svm
->msrpm
;
1149 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
1150 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
1151 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
1152 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
1153 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
1156 static void disable_nmi_singlestep(struct vcpu_svm
*svm
)
1158 svm
->nmi_singlestep
= false;
1160 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
1161 /* Clear our flags if they were not set by the guest */
1162 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1163 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
1164 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1165 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
1170 * This hash table is used to map VM_ID to a struct kvm_svm,
1171 * when handling AMD IOMMU GALOG notification to schedule in
1172 * a particular vCPU.
1174 #define SVM_VM_DATA_HASH_BITS 8
1175 static DEFINE_HASHTABLE(svm_vm_data_hash
, SVM_VM_DATA_HASH_BITS
);
1176 static u32 next_vm_id
= 0;
1177 static bool next_vm_id_wrapped
= 0;
1178 static DEFINE_SPINLOCK(svm_vm_data_hash_lock
);
1181 * This function is called from IOMMU driver to notify
1182 * SVM to schedule in a particular vCPU of a particular VM.
1184 static int avic_ga_log_notifier(u32 ga_tag
)
1186 unsigned long flags
;
1187 struct kvm_svm
*kvm_svm
;
1188 struct kvm_vcpu
*vcpu
= NULL
;
1189 u32 vm_id
= AVIC_GATAG_TO_VMID(ga_tag
);
1190 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(ga_tag
);
1192 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__
, vm_id
, vcpu_id
);
1194 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1195 hash_for_each_possible(svm_vm_data_hash
, kvm_svm
, hnode
, vm_id
) {
1196 if (kvm_svm
->avic_vm_id
!= vm_id
)
1198 vcpu
= kvm_get_vcpu_by_id(&kvm_svm
->kvm
, vcpu_id
);
1201 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1204 * At this point, the IOMMU should have already set the pending
1205 * bit in the vAPIC backing page. So, we just need to schedule
1209 kvm_vcpu_wake_up(vcpu
);
1214 static __init
int sev_hardware_setup(void)
1216 struct sev_user_data_status
*status
;
1219 /* Maximum number of encrypted guests supported simultaneously */
1220 max_sev_asid
= cpuid_ecx(0x8000001F);
1225 /* Minimum ASID value that should be used for SEV guest */
1226 min_sev_asid
= cpuid_edx(0x8000001F);
1228 /* Initialize SEV ASID bitmap */
1229 sev_asid_bitmap
= bitmap_zalloc(max_sev_asid
, GFP_KERNEL
);
1230 if (!sev_asid_bitmap
)
1233 status
= kmalloc(sizeof(*status
), GFP_KERNEL
);
1238 * Check SEV platform status.
1240 * PLATFORM_STATUS can be called in any state, if we failed to query
1241 * the PLATFORM status then either PSP firmware does not support SEV
1242 * feature or SEV firmware is dead.
1244 rc
= sev_platform_status(status
, NULL
);
1248 pr_info("SEV supported\n");
1255 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
1257 struct vcpu_svm
*svm
= to_svm(vcpu
);
1258 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1259 int old
= control
->pause_filter_count
;
1261 control
->pause_filter_count
= __grow_ple_window(old
,
1263 pause_filter_count_grow
,
1264 pause_filter_count_max
);
1266 if (control
->pause_filter_count
!= old
)
1267 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1269 trace_kvm_ple_window_grow(vcpu
->vcpu_id
,
1270 control
->pause_filter_count
, old
);
1273 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
1275 struct vcpu_svm
*svm
= to_svm(vcpu
);
1276 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1277 int old
= control
->pause_filter_count
;
1279 control
->pause_filter_count
=
1280 __shrink_ple_window(old
,
1282 pause_filter_count_shrink
,
1283 pause_filter_count
);
1284 if (control
->pause_filter_count
!= old
)
1285 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1287 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
,
1288 control
->pause_filter_count
, old
);
1291 static __init
int svm_hardware_setup(void)
1294 struct page
*iopm_pages
;
1298 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
1303 iopm_va
= page_address(iopm_pages
);
1304 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
1305 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
1307 init_msrpm_offsets();
1309 if (boot_cpu_has(X86_FEATURE_NX
))
1310 kvm_enable_efer_bits(EFER_NX
);
1312 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
1313 kvm_enable_efer_bits(EFER_FFXSR
);
1315 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1316 kvm_has_tsc_control
= true;
1317 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
1318 kvm_tsc_scaling_ratio_frac_bits
= 32;
1321 /* Check for pause filtering support */
1322 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1323 pause_filter_count
= 0;
1324 pause_filter_thresh
= 0;
1325 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD
)) {
1326 pause_filter_thresh
= 0;
1330 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
1331 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
1335 if (boot_cpu_has(X86_FEATURE_SEV
) &&
1336 IS_ENABLED(CONFIG_KVM_AMD_SEV
)) {
1337 r
= sev_hardware_setup();
1345 for_each_possible_cpu(cpu
) {
1346 r
= svm_cpu_init(cpu
);
1351 if (!boot_cpu_has(X86_FEATURE_NPT
))
1352 npt_enabled
= false;
1354 if (npt_enabled
&& !npt
) {
1355 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
1356 npt_enabled
= false;
1360 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
1367 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1368 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1371 pr_info("AVIC enabled\n");
1373 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1379 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1380 !IS_ENABLED(CONFIG_X86_64
)) {
1383 pr_info("Virtual VMLOAD VMSAVE supported\n");
1388 if (!boot_cpu_has(X86_FEATURE_VGIF
))
1391 pr_info("Virtual GIF supported\n");
1397 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1402 static __exit
void svm_hardware_unsetup(void)
1406 if (svm_sev_enabled())
1407 bitmap_free(sev_asid_bitmap
);
1409 for_each_possible_cpu(cpu
)
1410 svm_cpu_uninit(cpu
);
1412 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1416 static void init_seg(struct vmcb_seg
*seg
)
1419 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1420 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1421 seg
->limit
= 0xffff;
1425 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1428 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1429 seg
->limit
= 0xffff;
1433 static u64
svm_read_l1_tsc_offset(struct kvm_vcpu
*vcpu
)
1435 struct vcpu_svm
*svm
= to_svm(vcpu
);
1437 if (is_guest_mode(vcpu
))
1438 return svm
->nested
.hsave
->control
.tsc_offset
;
1440 return vcpu
->arch
.tsc_offset
;
1443 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1445 struct vcpu_svm
*svm
= to_svm(vcpu
);
1446 u64 g_tsc_offset
= 0;
1448 if (is_guest_mode(vcpu
)) {
1449 /* Write L1's TSC offset. */
1450 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1451 svm
->nested
.hsave
->control
.tsc_offset
;
1452 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1454 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1455 svm
->vmcb
->control
.tsc_offset
,
1458 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1460 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1463 static void avic_init_vmcb(struct vcpu_svm
*svm
)
1465 struct vmcb
*vmcb
= svm
->vmcb
;
1466 struct kvm_svm
*kvm_svm
= to_kvm_svm(svm
->vcpu
.kvm
);
1467 phys_addr_t bpa
= __sme_set(page_to_phys(svm
->avic_backing_page
));
1468 phys_addr_t lpa
= __sme_set(page_to_phys(kvm_svm
->avic_logical_id_table_page
));
1469 phys_addr_t ppa
= __sme_set(page_to_phys(kvm_svm
->avic_physical_id_table_page
));
1471 vmcb
->control
.avic_backing_page
= bpa
& AVIC_HPA_MASK
;
1472 vmcb
->control
.avic_logical_id
= lpa
& AVIC_HPA_MASK
;
1473 vmcb
->control
.avic_physical_id
= ppa
& AVIC_HPA_MASK
;
1474 vmcb
->control
.avic_physical_id
|= AVIC_MAX_PHYSICAL_ID_COUNT
;
1475 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
1478 static void init_vmcb(struct vcpu_svm
*svm
)
1480 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1481 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1483 svm
->vcpu
.arch
.hflags
= 0;
1485 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1486 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1487 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1488 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1489 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1490 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1491 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1492 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1494 set_dr_intercepts(svm
);
1496 set_exception_intercept(svm
, PF_VECTOR
);
1497 set_exception_intercept(svm
, UD_VECTOR
);
1498 set_exception_intercept(svm
, MC_VECTOR
);
1499 set_exception_intercept(svm
, AC_VECTOR
);
1500 set_exception_intercept(svm
, DB_VECTOR
);
1502 * Guest access to VMware backdoor ports could legitimately
1503 * trigger #GP because of TSS I/O permission bitmap.
1504 * We intercept those #GP and allow access to them anyway
1507 if (enable_vmware_backdoor
)
1508 set_exception_intercept(svm
, GP_VECTOR
);
1510 set_intercept(svm
, INTERCEPT_INTR
);
1511 set_intercept(svm
, INTERCEPT_NMI
);
1512 set_intercept(svm
, INTERCEPT_SMI
);
1513 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1514 set_intercept(svm
, INTERCEPT_RDPMC
);
1515 set_intercept(svm
, INTERCEPT_CPUID
);
1516 set_intercept(svm
, INTERCEPT_INVD
);
1517 set_intercept(svm
, INTERCEPT_INVLPG
);
1518 set_intercept(svm
, INTERCEPT_INVLPGA
);
1519 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1520 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1521 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1522 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1523 set_intercept(svm
, INTERCEPT_VMRUN
);
1524 set_intercept(svm
, INTERCEPT_VMMCALL
);
1525 set_intercept(svm
, INTERCEPT_VMLOAD
);
1526 set_intercept(svm
, INTERCEPT_VMSAVE
);
1527 set_intercept(svm
, INTERCEPT_STGI
);
1528 set_intercept(svm
, INTERCEPT_CLGI
);
1529 set_intercept(svm
, INTERCEPT_SKINIT
);
1530 set_intercept(svm
, INTERCEPT_WBINVD
);
1531 set_intercept(svm
, INTERCEPT_XSETBV
);
1532 set_intercept(svm
, INTERCEPT_RSM
);
1534 if (!kvm_mwait_in_guest(svm
->vcpu
.kvm
)) {
1535 set_intercept(svm
, INTERCEPT_MONITOR
);
1536 set_intercept(svm
, INTERCEPT_MWAIT
);
1539 if (!kvm_hlt_in_guest(svm
->vcpu
.kvm
))
1540 set_intercept(svm
, INTERCEPT_HLT
);
1542 control
->iopm_base_pa
= __sme_set(iopm_base
);
1543 control
->msrpm_base_pa
= __sme_set(__pa(svm
->msrpm
));
1544 control
->int_ctl
= V_INTR_MASKING_MASK
;
1546 init_seg(&save
->es
);
1547 init_seg(&save
->ss
);
1548 init_seg(&save
->ds
);
1549 init_seg(&save
->fs
);
1550 init_seg(&save
->gs
);
1552 save
->cs
.selector
= 0xf000;
1553 save
->cs
.base
= 0xffff0000;
1554 /* Executable/Readable Code Segment */
1555 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1556 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1557 save
->cs
.limit
= 0xffff;
1559 save
->gdtr
.limit
= 0xffff;
1560 save
->idtr
.limit
= 0xffff;
1562 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1563 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1565 svm_set_efer(&svm
->vcpu
, 0);
1566 save
->dr6
= 0xffff0ff0;
1567 kvm_set_rflags(&svm
->vcpu
, 2);
1568 save
->rip
= 0x0000fff0;
1569 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1572 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1573 * It also updates the guest-visible cr0 value.
1575 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1576 kvm_mmu_reset_context(&svm
->vcpu
);
1578 save
->cr4
= X86_CR4_PAE
;
1582 /* Setup VMCB for Nested Paging */
1583 control
->nested_ctl
|= SVM_NESTED_CTL_NP_ENABLE
;
1584 clr_intercept(svm
, INTERCEPT_INVLPG
);
1585 clr_exception_intercept(svm
, PF_VECTOR
);
1586 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1587 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1588 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1592 svm
->asid_generation
= 0;
1594 svm
->nested
.vmcb
= 0;
1595 svm
->vcpu
.arch
.hflags
= 0;
1597 if (pause_filter_count
) {
1598 control
->pause_filter_count
= pause_filter_count
;
1599 if (pause_filter_thresh
)
1600 control
->pause_filter_thresh
= pause_filter_thresh
;
1601 set_intercept(svm
, INTERCEPT_PAUSE
);
1603 clr_intercept(svm
, INTERCEPT_PAUSE
);
1606 if (kvm_vcpu_apicv_active(&svm
->vcpu
))
1607 avic_init_vmcb(svm
);
1610 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1611 * in VMCB and clear intercepts to avoid #VMEXIT.
1614 clr_intercept(svm
, INTERCEPT_VMLOAD
);
1615 clr_intercept(svm
, INTERCEPT_VMSAVE
);
1616 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
1620 clr_intercept(svm
, INTERCEPT_STGI
);
1621 clr_intercept(svm
, INTERCEPT_CLGI
);
1622 svm
->vmcb
->control
.int_ctl
|= V_GIF_ENABLE_MASK
;
1625 if (sev_guest(svm
->vcpu
.kvm
)) {
1626 svm
->vmcb
->control
.nested_ctl
|= SVM_NESTED_CTL_SEV_ENABLE
;
1627 clr_exception_intercept(svm
, UD_VECTOR
);
1630 mark_all_dirty(svm
->vmcb
);
1636 static u64
*avic_get_physical_id_entry(struct kvm_vcpu
*vcpu
,
1639 u64
*avic_physical_id_table
;
1640 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
1642 if (index
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1645 avic_physical_id_table
= page_address(kvm_svm
->avic_physical_id_table_page
);
1647 return &avic_physical_id_table
[index
];
1652 * AVIC hardware walks the nested page table to check permissions,
1653 * but does not use the SPA address specified in the leaf page
1654 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1655 * field of the VMCB. Therefore, we set up the
1656 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1658 static int avic_init_access_page(struct kvm_vcpu
*vcpu
)
1660 struct kvm
*kvm
= vcpu
->kvm
;
1663 if (kvm
->arch
.apic_access_page_done
)
1666 ret
= x86_set_memory_region(kvm
,
1667 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
1668 APIC_DEFAULT_PHYS_BASE
,
1673 kvm
->arch
.apic_access_page_done
= true;
1677 static int avic_init_backing_page(struct kvm_vcpu
*vcpu
)
1680 u64
*entry
, new_entry
;
1681 int id
= vcpu
->vcpu_id
;
1682 struct vcpu_svm
*svm
= to_svm(vcpu
);
1684 ret
= avic_init_access_page(vcpu
);
1688 if (id
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1691 if (!svm
->vcpu
.arch
.apic
->regs
)
1694 svm
->avic_backing_page
= virt_to_page(svm
->vcpu
.arch
.apic
->regs
);
1696 /* Setting AVIC backing page address in the phy APIC ID table */
1697 entry
= avic_get_physical_id_entry(vcpu
, id
);
1701 new_entry
= READ_ONCE(*entry
);
1702 new_entry
= __sme_set((page_to_phys(svm
->avic_backing_page
) &
1703 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
) |
1704 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
);
1705 WRITE_ONCE(*entry
, new_entry
);
1707 svm
->avic_physical_id_cache
= entry
;
1712 static void __sev_asid_free(int asid
)
1714 struct svm_cpu_data
*sd
;
1718 clear_bit(pos
, sev_asid_bitmap
);
1720 for_each_possible_cpu(cpu
) {
1721 sd
= per_cpu(svm_data
, cpu
);
1722 sd
->sev_vmcbs
[pos
] = NULL
;
1726 static void sev_asid_free(struct kvm
*kvm
)
1728 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1730 __sev_asid_free(sev
->asid
);
1733 static void sev_unbind_asid(struct kvm
*kvm
, unsigned int handle
)
1735 struct sev_data_decommission
*decommission
;
1736 struct sev_data_deactivate
*data
;
1741 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
1745 /* deactivate handle */
1746 data
->handle
= handle
;
1747 sev_guest_deactivate(data
, NULL
);
1749 wbinvd_on_all_cpus();
1750 sev_guest_df_flush(NULL
);
1753 decommission
= kzalloc(sizeof(*decommission
), GFP_KERNEL
);
1757 /* decommission handle */
1758 decommission
->handle
= handle
;
1759 sev_guest_decommission(decommission
, NULL
);
1761 kfree(decommission
);
1764 static struct page
**sev_pin_memory(struct kvm
*kvm
, unsigned long uaddr
,
1765 unsigned long ulen
, unsigned long *n
,
1768 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1769 unsigned long npages
, npinned
, size
;
1770 unsigned long locked
, lock_limit
;
1771 struct page
**pages
;
1772 unsigned long first
, last
;
1774 if (ulen
== 0 || uaddr
+ ulen
< uaddr
)
1777 /* Calculate number of pages. */
1778 first
= (uaddr
& PAGE_MASK
) >> PAGE_SHIFT
;
1779 last
= ((uaddr
+ ulen
- 1) & PAGE_MASK
) >> PAGE_SHIFT
;
1780 npages
= (last
- first
+ 1);
1782 locked
= sev
->pages_locked
+ npages
;
1783 lock_limit
= rlimit(RLIMIT_MEMLOCK
) >> PAGE_SHIFT
;
1784 if (locked
> lock_limit
&& !capable(CAP_IPC_LOCK
)) {
1785 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked
, lock_limit
);
1789 /* Avoid using vmalloc for smaller buffers. */
1790 size
= npages
* sizeof(struct page
*);
1791 if (size
> PAGE_SIZE
)
1792 pages
= vmalloc(size
);
1794 pages
= kmalloc(size
, GFP_KERNEL
);
1799 /* Pin the user virtual address. */
1800 npinned
= get_user_pages_fast(uaddr
, npages
, write
? FOLL_WRITE
: 0, pages
);
1801 if (npinned
!= npages
) {
1802 pr_err("SEV: Failure locking %lu pages.\n", npages
);
1807 sev
->pages_locked
= locked
;
1813 release_pages(pages
, npinned
);
1819 static void sev_unpin_memory(struct kvm
*kvm
, struct page
**pages
,
1820 unsigned long npages
)
1822 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1824 release_pages(pages
, npages
);
1826 sev
->pages_locked
-= npages
;
1829 static void sev_clflush_pages(struct page
*pages
[], unsigned long npages
)
1831 uint8_t *page_virtual
;
1834 if (npages
== 0 || pages
== NULL
)
1837 for (i
= 0; i
< npages
; i
++) {
1838 page_virtual
= kmap_atomic(pages
[i
]);
1839 clflush_cache_range(page_virtual
, PAGE_SIZE
);
1840 kunmap_atomic(page_virtual
);
1844 static void __unregister_enc_region_locked(struct kvm
*kvm
,
1845 struct enc_region
*region
)
1848 * The guest may change the memory encryption attribute from C=0 -> C=1
1849 * or vice versa for this memory range. Lets make sure caches are
1850 * flushed to ensure that guest data gets written into memory with
1853 sev_clflush_pages(region
->pages
, region
->npages
);
1855 sev_unpin_memory(kvm
, region
->pages
, region
->npages
);
1856 list_del(®ion
->list
);
1860 static struct kvm
*svm_vm_alloc(void)
1862 struct kvm_svm
*kvm_svm
= vzalloc(sizeof(struct kvm_svm
));
1863 return &kvm_svm
->kvm
;
1866 static void svm_vm_free(struct kvm
*kvm
)
1868 vfree(to_kvm_svm(kvm
));
1871 static void sev_vm_destroy(struct kvm
*kvm
)
1873 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1874 struct list_head
*head
= &sev
->regions_list
;
1875 struct list_head
*pos
, *q
;
1877 if (!sev_guest(kvm
))
1880 mutex_lock(&kvm
->lock
);
1883 * if userspace was terminated before unregistering the memory regions
1884 * then lets unpin all the registered memory.
1886 if (!list_empty(head
)) {
1887 list_for_each_safe(pos
, q
, head
) {
1888 __unregister_enc_region_locked(kvm
,
1889 list_entry(pos
, struct enc_region
, list
));
1893 mutex_unlock(&kvm
->lock
);
1895 sev_unbind_asid(kvm
, sev
->handle
);
1899 static void avic_vm_destroy(struct kvm
*kvm
)
1901 unsigned long flags
;
1902 struct kvm_svm
*kvm_svm
= to_kvm_svm(kvm
);
1907 if (kvm_svm
->avic_logical_id_table_page
)
1908 __free_page(kvm_svm
->avic_logical_id_table_page
);
1909 if (kvm_svm
->avic_physical_id_table_page
)
1910 __free_page(kvm_svm
->avic_physical_id_table_page
);
1912 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1913 hash_del(&kvm_svm
->hnode
);
1914 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1917 static void svm_vm_destroy(struct kvm
*kvm
)
1919 avic_vm_destroy(kvm
);
1920 sev_vm_destroy(kvm
);
1923 static int avic_vm_init(struct kvm
*kvm
)
1925 unsigned long flags
;
1927 struct kvm_svm
*kvm_svm
= to_kvm_svm(kvm
);
1929 struct page
*p_page
;
1930 struct page
*l_page
;
1936 /* Allocating physical APIC ID table (4KB) */
1937 p_page
= alloc_page(GFP_KERNEL
);
1941 kvm_svm
->avic_physical_id_table_page
= p_page
;
1942 clear_page(page_address(p_page
));
1944 /* Allocating logical APIC ID table (4KB) */
1945 l_page
= alloc_page(GFP_KERNEL
);
1949 kvm_svm
->avic_logical_id_table_page
= l_page
;
1950 clear_page(page_address(l_page
));
1952 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1954 vm_id
= next_vm_id
= (next_vm_id
+ 1) & AVIC_VM_ID_MASK
;
1955 if (vm_id
== 0) { /* id is 1-based, zero is not okay */
1956 next_vm_id_wrapped
= 1;
1959 /* Is it still in use? Only possible if wrapped at least once */
1960 if (next_vm_id_wrapped
) {
1961 hash_for_each_possible(svm_vm_data_hash
, k2
, hnode
, vm_id
) {
1962 if (k2
->avic_vm_id
== vm_id
)
1966 kvm_svm
->avic_vm_id
= vm_id
;
1967 hash_add(svm_vm_data_hash
, &kvm_svm
->hnode
, kvm_svm
->avic_vm_id
);
1968 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1973 avic_vm_destroy(kvm
);
1978 avic_update_iommu_vcpu_affinity(struct kvm_vcpu
*vcpu
, int cpu
, bool r
)
1981 unsigned long flags
;
1982 struct amd_svm_iommu_ir
*ir
;
1983 struct vcpu_svm
*svm
= to_svm(vcpu
);
1985 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1989 * Here, we go through the per-vcpu ir_list to update all existing
1990 * interrupt remapping table entry targeting this vcpu.
1992 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
1994 if (list_empty(&svm
->ir_list
))
1997 list_for_each_entry(ir
, &svm
->ir_list
, node
) {
1998 ret
= amd_iommu_update_ga(cpu
, r
, ir
->data
);
2003 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
2007 static void avic_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2010 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
2011 int h_physical_id
= kvm_cpu_get_apicid(cpu
);
2012 struct vcpu_svm
*svm
= to_svm(vcpu
);
2014 if (!kvm_vcpu_apicv_active(vcpu
))
2017 if (WARN_ON(h_physical_id
>= AVIC_MAX_PHYSICAL_ID_COUNT
))
2020 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
2021 WARN_ON(entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
2023 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
;
2024 entry
|= (h_physical_id
& AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
);
2026 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2027 if (svm
->avic_is_running
)
2028 entry
|= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2030 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
2031 avic_update_iommu_vcpu_affinity(vcpu
, h_physical_id
,
2032 svm
->avic_is_running
);
2035 static void avic_vcpu_put(struct kvm_vcpu
*vcpu
)
2038 struct vcpu_svm
*svm
= to_svm(vcpu
);
2040 if (!kvm_vcpu_apicv_active(vcpu
))
2043 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
2044 if (entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
)
2045 avic_update_iommu_vcpu_affinity(vcpu
, -1, 0);
2047 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2048 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
2052 * This function is called during VCPU halt/unhalt.
2054 static void avic_set_running(struct kvm_vcpu
*vcpu
, bool is_run
)
2056 struct vcpu_svm
*svm
= to_svm(vcpu
);
2058 svm
->avic_is_running
= is_run
;
2060 avic_vcpu_load(vcpu
, vcpu
->cpu
);
2062 avic_vcpu_put(vcpu
);
2065 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
2067 struct vcpu_svm
*svm
= to_svm(vcpu
);
2071 vcpu
->arch
.microcode_version
= 0x01000065;
2073 svm
->virt_spec_ctrl
= 0;
2076 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
2077 MSR_IA32_APICBASE_ENABLE
;
2078 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
2079 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
2083 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
, true);
2084 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
2086 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
2087 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
2090 static int avic_init_vcpu(struct vcpu_svm
*svm
)
2094 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
2097 ret
= avic_init_backing_page(&svm
->vcpu
);
2101 INIT_LIST_HEAD(&svm
->ir_list
);
2102 spin_lock_init(&svm
->ir_list_lock
);
2107 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
2109 struct vcpu_svm
*svm
;
2111 struct page
*msrpm_pages
;
2112 struct page
*hsave_page
;
2113 struct page
*nested_msrpm_pages
;
2116 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
2122 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
2127 page
= alloc_page(GFP_KERNEL
);
2131 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
2135 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
2136 if (!nested_msrpm_pages
)
2139 hsave_page
= alloc_page(GFP_KERNEL
);
2143 err
= avic_init_vcpu(svm
);
2147 /* We initialize this flag to true to make sure that the is_running
2148 * bit would be set the first time the vcpu is loaded.
2150 svm
->avic_is_running
= true;
2152 svm
->nested
.hsave
= page_address(hsave_page
);
2154 svm
->msrpm
= page_address(msrpm_pages
);
2155 svm_vcpu_init_msrpm(svm
->msrpm
);
2157 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
2158 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
2160 svm
->vmcb
= page_address(page
);
2161 clear_page(svm
->vmcb
);
2162 svm
->vmcb_pa
= __sme_set(page_to_pfn(page
) << PAGE_SHIFT
);
2163 svm
->asid_generation
= 0;
2166 svm_init_osvw(&svm
->vcpu
);
2171 __free_page(hsave_page
);
2173 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
2175 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
2179 kvm_vcpu_uninit(&svm
->vcpu
);
2181 kmem_cache_free(kvm_vcpu_cache
, svm
);
2183 return ERR_PTR(err
);
2186 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
2188 struct vcpu_svm
*svm
= to_svm(vcpu
);
2190 __free_page(pfn_to_page(__sme_clr(svm
->vmcb_pa
) >> PAGE_SHIFT
));
2191 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
2192 __free_page(virt_to_page(svm
->nested
.hsave
));
2193 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
2194 kvm_vcpu_uninit(vcpu
);
2195 kmem_cache_free(kvm_vcpu_cache
, svm
);
2197 * The vmcb page can be recycled, causing a false negative in
2198 * svm_vcpu_load(). So do a full IBPB now.
2200 indirect_branch_prediction_barrier();
2203 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2205 struct vcpu_svm
*svm
= to_svm(vcpu
);
2206 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2209 if (unlikely(cpu
!= vcpu
->cpu
)) {
2210 svm
->asid_generation
= 0;
2211 mark_all_dirty(svm
->vmcb
);
2214 #ifdef CONFIG_X86_64
2215 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
2217 savesegment(fs
, svm
->host
.fs
);
2218 savesegment(gs
, svm
->host
.gs
);
2219 svm
->host
.ldt
= kvm_read_ldt();
2221 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
2222 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
2224 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
2225 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2226 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
2227 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
2228 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
2231 /* This assumes that the kernel never uses MSR_TSC_AUX */
2232 if (static_cpu_has(X86_FEATURE_RDTSCP
))
2233 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
2235 if (sd
->current_vmcb
!= svm
->vmcb
) {
2236 sd
->current_vmcb
= svm
->vmcb
;
2237 indirect_branch_prediction_barrier();
2239 avic_vcpu_load(vcpu
, cpu
);
2242 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
2244 struct vcpu_svm
*svm
= to_svm(vcpu
);
2247 avic_vcpu_put(vcpu
);
2249 ++vcpu
->stat
.host_state_reload
;
2250 kvm_load_ldt(svm
->host
.ldt
);
2251 #ifdef CONFIG_X86_64
2252 loadsegment(fs
, svm
->host
.fs
);
2253 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
2254 load_gs_index(svm
->host
.gs
);
2256 #ifdef CONFIG_X86_32_LAZY_GS
2257 loadsegment(gs
, svm
->host
.gs
);
2260 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
2261 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
2264 static void svm_vcpu_blocking(struct kvm_vcpu
*vcpu
)
2266 avic_set_running(vcpu
, false);
2269 static void svm_vcpu_unblocking(struct kvm_vcpu
*vcpu
)
2271 avic_set_running(vcpu
, true);
2274 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
2276 struct vcpu_svm
*svm
= to_svm(vcpu
);
2277 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
2279 if (svm
->nmi_singlestep
) {
2280 /* Hide our flags if they were not set by the guest */
2281 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
2282 rflags
&= ~X86_EFLAGS_TF
;
2283 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
2284 rflags
&= ~X86_EFLAGS_RF
;
2289 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2291 if (to_svm(vcpu
)->nmi_singlestep
)
2292 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2295 * Any change of EFLAGS.VM is accompanied by a reload of SS
2296 * (caused by either a task switch or an inter-privilege IRET),
2297 * so we do not need to update the CPL here.
2299 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
2302 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2305 case VCPU_EXREG_PDPTR
:
2306 BUG_ON(!npt_enabled
);
2307 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
2314 static void svm_set_vintr(struct vcpu_svm
*svm
)
2316 set_intercept(svm
, INTERCEPT_VINTR
);
2319 static void svm_clear_vintr(struct vcpu_svm
*svm
)
2321 clr_intercept(svm
, INTERCEPT_VINTR
);
2324 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
2326 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
2329 case VCPU_SREG_CS
: return &save
->cs
;
2330 case VCPU_SREG_DS
: return &save
->ds
;
2331 case VCPU_SREG_ES
: return &save
->es
;
2332 case VCPU_SREG_FS
: return &save
->fs
;
2333 case VCPU_SREG_GS
: return &save
->gs
;
2334 case VCPU_SREG_SS
: return &save
->ss
;
2335 case VCPU_SREG_TR
: return &save
->tr
;
2336 case VCPU_SREG_LDTR
: return &save
->ldtr
;
2342 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
2344 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2349 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
2350 struct kvm_segment
*var
, int seg
)
2352 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2354 var
->base
= s
->base
;
2355 var
->limit
= s
->limit
;
2356 var
->selector
= s
->selector
;
2357 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
2358 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
2359 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
2360 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
2361 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
2362 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
2363 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
2366 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2367 * However, the SVM spec states that the G bit is not observed by the
2368 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2369 * So let's synthesize a legal G bit for all segments, this helps
2370 * running KVM nested. It also helps cross-vendor migration, because
2371 * Intel's vmentry has a check on the 'G' bit.
2373 var
->g
= s
->limit
> 0xfffff;
2376 * AMD's VMCB does not have an explicit unusable field, so emulate it
2377 * for cross vendor migration purposes by "not present"
2379 var
->unusable
= !var
->present
;
2384 * Work around a bug where the busy flag in the tr selector
2394 * The accessed bit must always be set in the segment
2395 * descriptor cache, although it can be cleared in the
2396 * descriptor, the cached bit always remains at 1. Since
2397 * Intel has a check on this, set it here to support
2398 * cross-vendor migration.
2405 * On AMD CPUs sometimes the DB bit in the segment
2406 * descriptor is left as 1, although the whole segment has
2407 * been made unusable. Clear it here to pass an Intel VMX
2408 * entry check when cross vendor migrating.
2412 /* This is symmetric with svm_set_segment() */
2413 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
2418 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
2420 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
2425 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2427 struct vcpu_svm
*svm
= to_svm(vcpu
);
2429 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
2430 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
2433 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2435 struct vcpu_svm
*svm
= to_svm(vcpu
);
2437 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
2438 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
2439 mark_dirty(svm
->vmcb
, VMCB_DT
);
2442 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2444 struct vcpu_svm
*svm
= to_svm(vcpu
);
2446 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
2447 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
2450 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2452 struct vcpu_svm
*svm
= to_svm(vcpu
);
2454 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
2455 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
2456 mark_dirty(svm
->vmcb
, VMCB_DT
);
2459 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2463 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
2467 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2471 static void update_cr0_intercept(struct vcpu_svm
*svm
)
2473 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
2474 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
2476 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
2477 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
2479 mark_dirty(svm
->vmcb
, VMCB_CR
);
2481 if (gcr0
== *hcr0
) {
2482 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2483 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2485 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2486 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2490 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2492 struct vcpu_svm
*svm
= to_svm(vcpu
);
2494 #ifdef CONFIG_X86_64
2495 if (vcpu
->arch
.efer
& EFER_LME
) {
2496 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
2497 vcpu
->arch
.efer
|= EFER_LMA
;
2498 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
2501 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
2502 vcpu
->arch
.efer
&= ~EFER_LMA
;
2503 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
2507 vcpu
->arch
.cr0
= cr0
;
2510 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
2513 * re-enable caching here because the QEMU bios
2514 * does not do it - this results in some delay at
2517 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
2518 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
2519 svm
->vmcb
->save
.cr0
= cr0
;
2520 mark_dirty(svm
->vmcb
, VMCB_CR
);
2521 update_cr0_intercept(svm
);
2524 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2526 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
2527 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
2529 if (cr4
& X86_CR4_VMXE
)
2532 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
2533 svm_flush_tlb(vcpu
, true);
2535 vcpu
->arch
.cr4
= cr4
;
2538 cr4
|= host_cr4_mce
;
2539 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
2540 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
2544 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
2545 struct kvm_segment
*var
, int seg
)
2547 struct vcpu_svm
*svm
= to_svm(vcpu
);
2548 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2550 s
->base
= var
->base
;
2551 s
->limit
= var
->limit
;
2552 s
->selector
= var
->selector
;
2553 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
2554 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
2555 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
2556 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
2557 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
2558 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
2559 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
2560 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
2563 * This is always accurate, except if SYSRET returned to a segment
2564 * with SS.DPL != 3. Intel does not have this quirk, and always
2565 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2566 * would entail passing the CPL to userspace and back.
2568 if (seg
== VCPU_SREG_SS
)
2569 /* This is symmetric with svm_get_segment() */
2570 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
2572 mark_dirty(svm
->vmcb
, VMCB_SEG
);
2575 static void update_bp_intercept(struct kvm_vcpu
*vcpu
)
2577 struct vcpu_svm
*svm
= to_svm(vcpu
);
2579 clr_exception_intercept(svm
, BP_VECTOR
);
2581 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
2582 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2583 set_exception_intercept(svm
, BP_VECTOR
);
2585 vcpu
->guest_debug
= 0;
2588 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
2590 if (sd
->next_asid
> sd
->max_asid
) {
2591 ++sd
->asid_generation
;
2592 sd
->next_asid
= sd
->min_asid
;
2593 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
2596 svm
->asid_generation
= sd
->asid_generation
;
2597 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
2599 mark_dirty(svm
->vmcb
, VMCB_ASID
);
2602 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
2604 return to_svm(vcpu
)->vmcb
->save
.dr6
;
2607 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
2609 struct vcpu_svm
*svm
= to_svm(vcpu
);
2611 svm
->vmcb
->save
.dr6
= value
;
2612 mark_dirty(svm
->vmcb
, VMCB_DR
);
2615 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
2617 struct vcpu_svm
*svm
= to_svm(vcpu
);
2619 get_debugreg(vcpu
->arch
.db
[0], 0);
2620 get_debugreg(vcpu
->arch
.db
[1], 1);
2621 get_debugreg(vcpu
->arch
.db
[2], 2);
2622 get_debugreg(vcpu
->arch
.db
[3], 3);
2623 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
2624 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
2626 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
2627 set_dr_intercepts(svm
);
2630 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
2632 struct vcpu_svm
*svm
= to_svm(vcpu
);
2634 svm
->vmcb
->save
.dr7
= value
;
2635 mark_dirty(svm
->vmcb
, VMCB_DR
);
2638 static int pf_interception(struct vcpu_svm
*svm
)
2640 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
2641 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2643 return kvm_handle_page_fault(&svm
->vcpu
, error_code
, fault_address
,
2644 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2645 svm
->vmcb
->control
.insn_bytes
: NULL
,
2646 svm
->vmcb
->control
.insn_len
);
2649 static int npf_interception(struct vcpu_svm
*svm
)
2651 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
2652 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2654 trace_kvm_page_fault(fault_address
, error_code
);
2655 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
2656 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2657 svm
->vmcb
->control
.insn_bytes
: NULL
,
2658 svm
->vmcb
->control
.insn_len
);
2661 static int db_interception(struct vcpu_svm
*svm
)
2663 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2665 if (!(svm
->vcpu
.guest_debug
&
2666 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
2667 !svm
->nmi_singlestep
) {
2668 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
2672 if (svm
->nmi_singlestep
) {
2673 disable_nmi_singlestep(svm
);
2676 if (svm
->vcpu
.guest_debug
&
2677 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
2678 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2679 kvm_run
->debug
.arch
.pc
=
2680 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2681 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2688 static int bp_interception(struct vcpu_svm
*svm
)
2690 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2692 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2693 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2694 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
2698 static int ud_interception(struct vcpu_svm
*svm
)
2700 return handle_ud(&svm
->vcpu
);
2703 static int ac_interception(struct vcpu_svm
*svm
)
2705 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
2709 static int gp_interception(struct vcpu_svm
*svm
)
2711 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2712 u32 error_code
= svm
->vmcb
->control
.exit_info_1
;
2715 WARN_ON_ONCE(!enable_vmware_backdoor
);
2717 er
= kvm_emulate_instruction(vcpu
,
2718 EMULTYPE_VMWARE
| EMULTYPE_NO_UD_ON_FAIL
);
2719 if (er
== EMULATE_USER_EXIT
)
2721 else if (er
!= EMULATE_DONE
)
2722 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
2726 static bool is_erratum_383(void)
2731 if (!erratum_383_found
)
2734 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
2738 /* Bit 62 may or may not be set for this mce */
2739 value
&= ~(1ULL << 62);
2741 if (value
!= 0xb600000000010015ULL
)
2744 /* Clear MCi_STATUS registers */
2745 for (i
= 0; i
< 6; ++i
)
2746 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2748 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2752 value
&= ~(1ULL << 2);
2753 low
= lower_32_bits(value
);
2754 high
= upper_32_bits(value
);
2756 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2759 /* Flush tlb to evict multi-match entries */
2765 static void svm_handle_mce(struct vcpu_svm
*svm
)
2767 if (is_erratum_383()) {
2769 * Erratum 383 triggered. Guest state is corrupt so kill the
2772 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2774 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2780 * On an #MC intercept the MCE handler is not called automatically in
2781 * the host. So do it by hand here.
2785 /* not sure if we ever come back to this point */
2790 static int mc_interception(struct vcpu_svm
*svm
)
2795 static int shutdown_interception(struct vcpu_svm
*svm
)
2797 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2800 * VMCB is undefined after a SHUTDOWN intercept
2801 * so reinitialize it.
2803 clear_page(svm
->vmcb
);
2806 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2810 static int io_interception(struct vcpu_svm
*svm
)
2812 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2813 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2814 int size
, in
, string
;
2817 ++svm
->vcpu
.stat
.io_exits
;
2818 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2819 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2821 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2823 port
= io_info
>> 16;
2824 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2825 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2827 return kvm_fast_pio(&svm
->vcpu
, size
, port
, in
);
2830 static int nmi_interception(struct vcpu_svm
*svm
)
2835 static int intr_interception(struct vcpu_svm
*svm
)
2837 ++svm
->vcpu
.stat
.irq_exits
;
2841 static int nop_on_interception(struct vcpu_svm
*svm
)
2846 static int halt_interception(struct vcpu_svm
*svm
)
2848 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2849 return kvm_emulate_halt(&svm
->vcpu
);
2852 static int vmmcall_interception(struct vcpu_svm
*svm
)
2854 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2855 return kvm_emulate_hypercall(&svm
->vcpu
);
2858 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2860 struct vcpu_svm
*svm
= to_svm(vcpu
);
2862 return svm
->nested
.nested_cr3
;
2865 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2867 struct vcpu_svm
*svm
= to_svm(vcpu
);
2868 u64 cr3
= svm
->nested
.nested_cr3
;
2872 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(__sme_clr(cr3
)), &pdpte
,
2873 offset_in_page(cr3
) + index
* 8, 8);
2879 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2882 struct vcpu_svm
*svm
= to_svm(vcpu
);
2884 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
2885 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2888 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2889 struct x86_exception
*fault
)
2891 struct vcpu_svm
*svm
= to_svm(vcpu
);
2893 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2895 * TODO: track the cause of the nested page fault, and
2896 * correctly fill in the high bits of exit_info_1.
2898 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2899 svm
->vmcb
->control
.exit_code_hi
= 0;
2900 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2901 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2904 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2905 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2908 * The present bit is always zero for page structure faults on real
2911 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2912 svm
->vmcb
->control
.exit_info_1
&= ~1;
2914 nested_svm_vmexit(svm
);
2917 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2919 WARN_ON(mmu_is_nested(vcpu
));
2920 kvm_init_shadow_mmu(vcpu
);
2921 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
2922 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
2923 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
2924 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
2925 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level(vcpu
);
2926 reset_shadow_zero_bits_mask(vcpu
, &vcpu
->arch
.mmu
);
2927 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2930 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2932 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2935 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2937 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
) ||
2938 !is_paging(&svm
->vcpu
)) {
2939 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2943 if (svm
->vmcb
->save
.cpl
) {
2944 kvm_inject_gp(&svm
->vcpu
, 0);
2951 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2952 bool has_error_code
, u32 error_code
)
2956 if (!is_guest_mode(&svm
->vcpu
))
2959 vmexit
= nested_svm_intercept(svm
);
2960 if (vmexit
!= NESTED_EXIT_DONE
)
2963 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2964 svm
->vmcb
->control
.exit_code_hi
= 0;
2965 svm
->vmcb
->control
.exit_info_1
= error_code
;
2968 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2969 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2970 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2971 * written only when inject_pending_event runs (DR6 would written here
2972 * too). This should be conditional on a new capability---if the
2973 * capability is disabled, kvm_multiple_exception would write the
2974 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2976 if (svm
->vcpu
.arch
.exception
.nested_apf
)
2977 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.apf
.nested_apf_token
;
2979 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2981 svm
->nested
.exit_required
= true;
2985 /* This function returns true if it is save to enable the irq window */
2986 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2988 if (!is_guest_mode(&svm
->vcpu
))
2991 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2994 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2998 * if vmexit was already requested (by intercepted exception
2999 * for instance) do not overwrite it with "external interrupt"
3002 if (svm
->nested
.exit_required
)
3005 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
3006 svm
->vmcb
->control
.exit_info_1
= 0;
3007 svm
->vmcb
->control
.exit_info_2
= 0;
3009 if (svm
->nested
.intercept
& 1ULL) {
3011 * The #vmexit can't be emulated here directly because this
3012 * code path runs with irqs and preemption disabled. A
3013 * #vmexit emulation might sleep. Only signal request for
3016 svm
->nested
.exit_required
= true;
3017 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
3024 /* This function returns true if it is save to enable the nmi window */
3025 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
3027 if (!is_guest_mode(&svm
->vcpu
))
3030 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
3033 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
3034 svm
->nested
.exit_required
= true;
3039 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
3045 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
3046 if (is_error_page(page
))
3054 kvm_inject_gp(&svm
->vcpu
, 0);
3059 static void nested_svm_unmap(struct page
*page
)
3062 kvm_release_page_dirty(page
);
3065 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
3067 unsigned port
, size
, iopm_len
;
3072 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
3073 return NESTED_EXIT_HOST
;
3075 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
3076 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
3077 SVM_IOIO_SIZE_SHIFT
;
3078 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
3079 start_bit
= port
% 8;
3080 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
3081 mask
= (0xf >> (4 - size
)) << start_bit
;
3084 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
3085 return NESTED_EXIT_DONE
;
3087 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
3090 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
3092 u32 offset
, msr
, value
;
3095 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
3096 return NESTED_EXIT_HOST
;
3098 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3099 offset
= svm_msrpm_offset(msr
);
3100 write
= svm
->vmcb
->control
.exit_info_1
& 1;
3101 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
3103 if (offset
== MSR_INVALID
)
3104 return NESTED_EXIT_DONE
;
3106 /* Offset is in 32 bit units but need in 8 bit units */
3109 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
3110 return NESTED_EXIT_DONE
;
3112 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
3115 /* DB exceptions for our internal use must not cause vmexit */
3116 static int nested_svm_intercept_db(struct vcpu_svm
*svm
)
3120 /* if we're not singlestepping, it's not ours */
3121 if (!svm
->nmi_singlestep
)
3122 return NESTED_EXIT_DONE
;
3124 /* if it's not a singlestep exception, it's not ours */
3125 if (kvm_get_dr(&svm
->vcpu
, 6, &dr6
))
3126 return NESTED_EXIT_DONE
;
3127 if (!(dr6
& DR6_BS
))
3128 return NESTED_EXIT_DONE
;
3130 /* if the guest is singlestepping, it should get the vmexit */
3131 if (svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
) {
3132 disable_nmi_singlestep(svm
);
3133 return NESTED_EXIT_DONE
;
3136 /* it's ours, the nested hypervisor must not see this one */
3137 return NESTED_EXIT_HOST
;
3140 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
3142 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3144 switch (exit_code
) {
3147 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
3148 return NESTED_EXIT_HOST
;
3150 /* For now we are always handling NPFs when using them */
3152 return NESTED_EXIT_HOST
;
3154 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
3155 /* When we're shadowing, trap PFs, but not async PF */
3156 if (!npt_enabled
&& svm
->vcpu
.arch
.apf
.host_apf_reason
== 0)
3157 return NESTED_EXIT_HOST
;
3163 return NESTED_EXIT_CONTINUE
;
3167 * If this function returns true, this #vmexit was already handled
3169 static int nested_svm_intercept(struct vcpu_svm
*svm
)
3171 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3172 int vmexit
= NESTED_EXIT_HOST
;
3174 switch (exit_code
) {
3176 vmexit
= nested_svm_exit_handled_msr(svm
);
3179 vmexit
= nested_svm_intercept_ioio(svm
);
3181 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
3182 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
3183 if (svm
->nested
.intercept_cr
& bit
)
3184 vmexit
= NESTED_EXIT_DONE
;
3187 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
3188 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
3189 if (svm
->nested
.intercept_dr
& bit
)
3190 vmexit
= NESTED_EXIT_DONE
;
3193 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
3194 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
3195 if (svm
->nested
.intercept_exceptions
& excp_bits
) {
3196 if (exit_code
== SVM_EXIT_EXCP_BASE
+ DB_VECTOR
)
3197 vmexit
= nested_svm_intercept_db(svm
);
3199 vmexit
= NESTED_EXIT_DONE
;
3201 /* async page fault always cause vmexit */
3202 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
3203 svm
->vcpu
.arch
.exception
.nested_apf
!= 0)
3204 vmexit
= NESTED_EXIT_DONE
;
3207 case SVM_EXIT_ERR
: {
3208 vmexit
= NESTED_EXIT_DONE
;
3212 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
3213 if (svm
->nested
.intercept
& exit_bits
)
3214 vmexit
= NESTED_EXIT_DONE
;
3221 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
3225 vmexit
= nested_svm_intercept(svm
);
3227 if (vmexit
== NESTED_EXIT_DONE
)
3228 nested_svm_vmexit(svm
);
3233 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
3235 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
3236 struct vmcb_control_area
*from
= &from_vmcb
->control
;
3238 dst
->intercept_cr
= from
->intercept_cr
;
3239 dst
->intercept_dr
= from
->intercept_dr
;
3240 dst
->intercept_exceptions
= from
->intercept_exceptions
;
3241 dst
->intercept
= from
->intercept
;
3242 dst
->iopm_base_pa
= from
->iopm_base_pa
;
3243 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
3244 dst
->tsc_offset
= from
->tsc_offset
;
3245 dst
->asid
= from
->asid
;
3246 dst
->tlb_ctl
= from
->tlb_ctl
;
3247 dst
->int_ctl
= from
->int_ctl
;
3248 dst
->int_vector
= from
->int_vector
;
3249 dst
->int_state
= from
->int_state
;
3250 dst
->exit_code
= from
->exit_code
;
3251 dst
->exit_code_hi
= from
->exit_code_hi
;
3252 dst
->exit_info_1
= from
->exit_info_1
;
3253 dst
->exit_info_2
= from
->exit_info_2
;
3254 dst
->exit_int_info
= from
->exit_int_info
;
3255 dst
->exit_int_info_err
= from
->exit_int_info_err
;
3256 dst
->nested_ctl
= from
->nested_ctl
;
3257 dst
->event_inj
= from
->event_inj
;
3258 dst
->event_inj_err
= from
->event_inj_err
;
3259 dst
->nested_cr3
= from
->nested_cr3
;
3260 dst
->virt_ext
= from
->virt_ext
;
3263 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
3265 struct vmcb
*nested_vmcb
;
3266 struct vmcb
*hsave
= svm
->nested
.hsave
;
3267 struct vmcb
*vmcb
= svm
->vmcb
;
3270 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
3271 vmcb
->control
.exit_info_1
,
3272 vmcb
->control
.exit_info_2
,
3273 vmcb
->control
.exit_int_info
,
3274 vmcb
->control
.exit_int_info_err
,
3277 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
3281 /* Exit Guest-Mode */
3282 leave_guest_mode(&svm
->vcpu
);
3283 svm
->nested
.vmcb
= 0;
3285 /* Give the current vmcb to the guest */
3288 nested_vmcb
->save
.es
= vmcb
->save
.es
;
3289 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
3290 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
3291 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
3292 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
3293 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
3294 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
3295 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3296 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3297 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
3298 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3299 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3300 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
3301 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
3302 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
3303 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
3304 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
3305 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
3307 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
3308 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
3309 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
3310 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
3311 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
3312 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
3313 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
3314 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
3315 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
3317 if (svm
->nrips_enabled
)
3318 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
3321 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3322 * to make sure that we do not lose injected events. So check event_inj
3323 * here and copy it to exit_int_info if it is valid.
3324 * Exit_int_info and event_inj can't be both valid because the case
3325 * below only happens on a VMRUN instruction intercept which has
3326 * no valid exit_int_info set.
3328 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
3329 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
3331 nc
->exit_int_info
= vmcb
->control
.event_inj
;
3332 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
3335 nested_vmcb
->control
.tlb_ctl
= 0;
3336 nested_vmcb
->control
.event_inj
= 0;
3337 nested_vmcb
->control
.event_inj_err
= 0;
3339 /* We always set V_INTR_MASKING and remember the old value in hflags */
3340 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
3341 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
3343 /* Restore the original control entries */
3344 copy_vmcb_control_area(vmcb
, hsave
);
3346 svm
->vcpu
.arch
.tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
3347 kvm_clear_exception_queue(&svm
->vcpu
);
3348 kvm_clear_interrupt_queue(&svm
->vcpu
);
3350 svm
->nested
.nested_cr3
= 0;
3352 /* Restore selected save entries */
3353 svm
->vmcb
->save
.es
= hsave
->save
.es
;
3354 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
3355 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
3356 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
3357 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
3358 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
3359 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
3360 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
3361 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
3362 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
3364 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
3365 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
3367 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
3369 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
3370 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
3371 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
3372 svm
->vmcb
->save
.dr7
= 0;
3373 svm
->vmcb
->save
.cpl
= 0;
3374 svm
->vmcb
->control
.exit_int_info
= 0;
3376 mark_all_dirty(svm
->vmcb
);
3378 nested_svm_unmap(page
);
3380 nested_svm_uninit_mmu_context(&svm
->vcpu
);
3381 kvm_mmu_reset_context(&svm
->vcpu
);
3382 kvm_mmu_load(&svm
->vcpu
);
3387 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
3390 * This function merges the msr permission bitmaps of kvm and the
3391 * nested vmcb. It is optimized in that it only merges the parts where
3392 * the kvm msr permission bitmap may contain zero bits
3396 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
3399 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
3403 if (msrpm_offsets
[i
] == 0xffffffff)
3406 p
= msrpm_offsets
[i
];
3407 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
3409 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
3412 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
3415 svm
->vmcb
->control
.msrpm_base_pa
= __sme_set(__pa(svm
->nested
.msrpm
));
3420 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
3422 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
3425 if (vmcb
->control
.asid
== 0)
3428 if ((vmcb
->control
.nested_ctl
& SVM_NESTED_CTL_NP_ENABLE
) &&
3435 static void enter_svm_guest_mode(struct vcpu_svm
*svm
, u64 vmcb_gpa
,
3436 struct vmcb
*nested_vmcb
, struct page
*page
)
3438 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
3439 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
3441 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
3443 if (nested_vmcb
->control
.nested_ctl
& SVM_NESTED_CTL_NP_ENABLE
) {
3444 kvm_mmu_unload(&svm
->vcpu
);
3445 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
3446 nested_svm_init_mmu_context(&svm
->vcpu
);
3449 /* Load the nested guest state */
3450 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
3451 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
3452 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
3453 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
3454 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
3455 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
3456 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
3457 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
3458 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
3459 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
3461 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
3462 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
3464 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
3466 /* Guest paging mode is active - reset mmu */
3467 kvm_mmu_reset_context(&svm
->vcpu
);
3469 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
3470 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
3471 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
3472 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
3474 /* In case we don't even reach vcpu_run, the fields are not updated */
3475 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
3476 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
3477 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
3478 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
3479 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
3480 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
3482 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
3483 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
3485 /* cache intercepts */
3486 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
3487 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
3488 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
3489 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
3491 svm_flush_tlb(&svm
->vcpu
, true);
3492 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
3493 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
3494 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
3496 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
3498 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
3499 /* We only want the cr8 intercept bits of the guest */
3500 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
3501 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3504 /* We don't want to see VMMCALLs from a nested guest */
3505 clr_intercept(svm
, INTERCEPT_VMMCALL
);
3507 svm
->vcpu
.arch
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
3508 svm
->vmcb
->control
.tsc_offset
= svm
->vcpu
.arch
.tsc_offset
;
3510 svm
->vmcb
->control
.virt_ext
= nested_vmcb
->control
.virt_ext
;
3511 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
3512 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
3513 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
3514 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
3516 nested_svm_unmap(page
);
3518 /* Enter Guest-Mode */
3519 enter_guest_mode(&svm
->vcpu
);
3522 * Merge guest and host intercepts - must be called with vcpu in
3523 * guest-mode to take affect here
3525 recalc_intercepts(svm
);
3527 svm
->nested
.vmcb
= vmcb_gpa
;
3531 mark_all_dirty(svm
->vmcb
);
3534 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
3536 struct vmcb
*nested_vmcb
;
3537 struct vmcb
*hsave
= svm
->nested
.hsave
;
3538 struct vmcb
*vmcb
= svm
->vmcb
;
3542 vmcb_gpa
= svm
->vmcb
->save
.rax
;
3544 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3548 if (!nested_vmcb_checks(nested_vmcb
)) {
3549 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3550 nested_vmcb
->control
.exit_code_hi
= 0;
3551 nested_vmcb
->control
.exit_info_1
= 0;
3552 nested_vmcb
->control
.exit_info_2
= 0;
3554 nested_svm_unmap(page
);
3559 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
3560 nested_vmcb
->save
.rip
,
3561 nested_vmcb
->control
.int_ctl
,
3562 nested_vmcb
->control
.event_inj
,
3563 nested_vmcb
->control
.nested_ctl
);
3565 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
3566 nested_vmcb
->control
.intercept_cr
>> 16,
3567 nested_vmcb
->control
.intercept_exceptions
,
3568 nested_vmcb
->control
.intercept
);
3570 /* Clear internal status */
3571 kvm_clear_exception_queue(&svm
->vcpu
);
3572 kvm_clear_interrupt_queue(&svm
->vcpu
);
3575 * Save the old vmcb, so we don't need to pick what we save, but can
3576 * restore everything when a VMEXIT occurs
3578 hsave
->save
.es
= vmcb
->save
.es
;
3579 hsave
->save
.cs
= vmcb
->save
.cs
;
3580 hsave
->save
.ss
= vmcb
->save
.ss
;
3581 hsave
->save
.ds
= vmcb
->save
.ds
;
3582 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
3583 hsave
->save
.idtr
= vmcb
->save
.idtr
;
3584 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
3585 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3586 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3587 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3588 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
3589 hsave
->save
.rsp
= vmcb
->save
.rsp
;
3590 hsave
->save
.rax
= vmcb
->save
.rax
;
3592 hsave
->save
.cr3
= vmcb
->save
.cr3
;
3594 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3596 copy_vmcb_control_area(hsave
, vmcb
);
3598 enter_svm_guest_mode(svm
, vmcb_gpa
, nested_vmcb
, page
);
3603 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
3605 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
3606 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
3607 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
3608 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
3609 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
3610 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
3611 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
3612 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
3613 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
3614 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
3615 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
3616 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
3619 static int vmload_interception(struct vcpu_svm
*svm
)
3621 struct vmcb
*nested_vmcb
;
3625 if (nested_svm_check_permissions(svm
))
3628 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3632 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3633 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3635 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
3636 nested_svm_unmap(page
);
3641 static int vmsave_interception(struct vcpu_svm
*svm
)
3643 struct vmcb
*nested_vmcb
;
3647 if (nested_svm_check_permissions(svm
))
3650 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3654 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3655 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3657 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
3658 nested_svm_unmap(page
);
3663 static int vmrun_interception(struct vcpu_svm
*svm
)
3665 if (nested_svm_check_permissions(svm
))
3668 /* Save rip after vmrun instruction */
3669 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
3671 if (!nested_svm_vmrun(svm
))
3674 if (!nested_svm_vmrun_msrpm(svm
))
3681 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3682 svm
->vmcb
->control
.exit_code_hi
= 0;
3683 svm
->vmcb
->control
.exit_info_1
= 0;
3684 svm
->vmcb
->control
.exit_info_2
= 0;
3686 nested_svm_vmexit(svm
);
3691 static int stgi_interception(struct vcpu_svm
*svm
)
3695 if (nested_svm_check_permissions(svm
))
3699 * If VGIF is enabled, the STGI intercept is only added to
3700 * detect the opening of the SMI/NMI window; remove it now.
3702 if (vgif_enabled(svm
))
3703 clr_intercept(svm
, INTERCEPT_STGI
);
3705 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3706 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3707 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3714 static int clgi_interception(struct vcpu_svm
*svm
)
3718 if (nested_svm_check_permissions(svm
))
3721 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3722 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3726 /* After a CLGI no interrupts should come */
3727 if (!kvm_vcpu_apicv_active(&svm
->vcpu
)) {
3728 svm_clear_vintr(svm
);
3729 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3730 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3736 static int invlpga_interception(struct vcpu_svm
*svm
)
3738 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3740 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
3741 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3743 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3744 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3746 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3747 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3750 static int skinit_interception(struct vcpu_svm
*svm
)
3752 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3754 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3758 static int wbinvd_interception(struct vcpu_svm
*svm
)
3760 return kvm_emulate_wbinvd(&svm
->vcpu
);
3763 static int xsetbv_interception(struct vcpu_svm
*svm
)
3765 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
3766 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3768 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
3769 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3770 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3776 static int task_switch_interception(struct vcpu_svm
*svm
)
3780 int int_type
= svm
->vmcb
->control
.exit_int_info
&
3781 SVM_EXITINTINFO_TYPE_MASK
;
3782 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
3784 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
3786 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
3787 bool has_error_code
= false;
3790 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
3792 if (svm
->vmcb
->control
.exit_info_2
&
3793 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
3794 reason
= TASK_SWITCH_IRET
;
3795 else if (svm
->vmcb
->control
.exit_info_2
&
3796 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
3797 reason
= TASK_SWITCH_JMP
;
3799 reason
= TASK_SWITCH_GATE
;
3801 reason
= TASK_SWITCH_CALL
;
3803 if (reason
== TASK_SWITCH_GATE
) {
3805 case SVM_EXITINTINFO_TYPE_NMI
:
3806 svm
->vcpu
.arch
.nmi_injected
= false;
3808 case SVM_EXITINTINFO_TYPE_EXEPT
:
3809 if (svm
->vmcb
->control
.exit_info_2
&
3810 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
3811 has_error_code
= true;
3813 (u32
)svm
->vmcb
->control
.exit_info_2
;
3815 kvm_clear_exception_queue(&svm
->vcpu
);
3817 case SVM_EXITINTINFO_TYPE_INTR
:
3818 kvm_clear_interrupt_queue(&svm
->vcpu
);
3825 if (reason
!= TASK_SWITCH_GATE
||
3826 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
3827 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
3828 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
3829 skip_emulated_instruction(&svm
->vcpu
);
3831 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
3834 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
3835 has_error_code
, error_code
) == EMULATE_FAIL
) {
3836 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3837 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3838 svm
->vcpu
.run
->internal
.ndata
= 0;
3844 static int cpuid_interception(struct vcpu_svm
*svm
)
3846 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3847 return kvm_emulate_cpuid(&svm
->vcpu
);
3850 static int iret_interception(struct vcpu_svm
*svm
)
3852 ++svm
->vcpu
.stat
.nmi_window_exits
;
3853 clr_intercept(svm
, INTERCEPT_IRET
);
3854 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
3855 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
3856 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3860 static int invlpg_interception(struct vcpu_svm
*svm
)
3862 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3863 return kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3865 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
3866 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3869 static int emulate_on_interception(struct vcpu_svm
*svm
)
3871 return kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3874 static int rsm_interception(struct vcpu_svm
*svm
)
3876 return kvm_emulate_instruction_from_buffer(&svm
->vcpu
,
3877 rsm_ins_bytes
, 2) == EMULATE_DONE
;
3880 static int rdpmc_interception(struct vcpu_svm
*svm
)
3884 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3885 return emulate_on_interception(svm
);
3887 err
= kvm_rdpmc(&svm
->vcpu
);
3888 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3891 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3894 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3898 intercept
= svm
->nested
.intercept
;
3900 if (!is_guest_mode(&svm
->vcpu
) ||
3901 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3904 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3905 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3908 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3909 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3915 #define CR_VALID (1ULL << 63)
3917 static int cr_interception(struct vcpu_svm
*svm
)
3923 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3924 return emulate_on_interception(svm
);
3926 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3927 return emulate_on_interception(svm
);
3929 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3930 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3931 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3933 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3936 if (cr
>= 16) { /* mov to cr */
3938 val
= kvm_register_read(&svm
->vcpu
, reg
);
3941 if (!check_selective_cr0_intercepted(svm
, val
))
3942 err
= kvm_set_cr0(&svm
->vcpu
, val
);
3948 err
= kvm_set_cr3(&svm
->vcpu
, val
);
3951 err
= kvm_set_cr4(&svm
->vcpu
, val
);
3954 err
= kvm_set_cr8(&svm
->vcpu
, val
);
3957 WARN(1, "unhandled write to CR%d", cr
);
3958 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3961 } else { /* mov from cr */
3964 val
= kvm_read_cr0(&svm
->vcpu
);
3967 val
= svm
->vcpu
.arch
.cr2
;
3970 val
= kvm_read_cr3(&svm
->vcpu
);
3973 val
= kvm_read_cr4(&svm
->vcpu
);
3976 val
= kvm_get_cr8(&svm
->vcpu
);
3979 WARN(1, "unhandled read from CR%d", cr
);
3980 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3983 kvm_register_write(&svm
->vcpu
, reg
, val
);
3985 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3988 static int dr_interception(struct vcpu_svm
*svm
)
3993 if (svm
->vcpu
.guest_debug
== 0) {
3995 * No more DR vmexits; force a reload of the debug registers
3996 * and reenter on this instruction. The next vmexit will
3997 * retrieve the full state of the debug registers.
3999 clr_dr_intercepts(svm
);
4000 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
4004 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
4005 return emulate_on_interception(svm
);
4007 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
4008 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
4010 if (dr
>= 16) { /* mov to DRn */
4011 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
4013 val
= kvm_register_read(&svm
->vcpu
, reg
);
4014 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
4016 if (!kvm_require_dr(&svm
->vcpu
, dr
))
4018 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
4019 kvm_register_write(&svm
->vcpu
, reg
, val
);
4022 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4025 static int cr8_write_interception(struct vcpu_svm
*svm
)
4027 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
4030 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
4031 /* instruction emulation calls kvm_set_cr8() */
4032 r
= cr_interception(svm
);
4033 if (lapic_in_kernel(&svm
->vcpu
))
4035 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
4037 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
4041 static int svm_get_msr_feature(struct kvm_msr_entry
*msr
)
4045 switch (msr
->index
) {
4046 case MSR_F10H_DECFG
:
4047 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
))
4048 msr
->data
|= MSR_F10H_DECFG_LFENCE_SERIALIZE
;
4057 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
4059 struct vcpu_svm
*svm
= to_svm(vcpu
);
4061 switch (msr_info
->index
) {
4063 msr_info
->data
= svm
->vmcb
->save
.star
;
4065 #ifdef CONFIG_X86_64
4067 msr_info
->data
= svm
->vmcb
->save
.lstar
;
4070 msr_info
->data
= svm
->vmcb
->save
.cstar
;
4072 case MSR_KERNEL_GS_BASE
:
4073 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
4075 case MSR_SYSCALL_MASK
:
4076 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
4079 case MSR_IA32_SYSENTER_CS
:
4080 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
4082 case MSR_IA32_SYSENTER_EIP
:
4083 msr_info
->data
= svm
->sysenter_eip
;
4085 case MSR_IA32_SYSENTER_ESP
:
4086 msr_info
->data
= svm
->sysenter_esp
;
4089 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
4091 msr_info
->data
= svm
->tsc_aux
;
4094 * Nobody will change the following 5 values in the VMCB so we can
4095 * safely return them on rdmsr. They will always be 0 until LBRV is
4098 case MSR_IA32_DEBUGCTLMSR
:
4099 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
4101 case MSR_IA32_LASTBRANCHFROMIP
:
4102 msr_info
->data
= svm
->vmcb
->save
.br_from
;
4104 case MSR_IA32_LASTBRANCHTOIP
:
4105 msr_info
->data
= svm
->vmcb
->save
.br_to
;
4107 case MSR_IA32_LASTINTFROMIP
:
4108 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
4110 case MSR_IA32_LASTINTTOIP
:
4111 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
4113 case MSR_VM_HSAVE_PA
:
4114 msr_info
->data
= svm
->nested
.hsave_msr
;
4117 msr_info
->data
= svm
->nested
.vm_cr_msr
;
4119 case MSR_IA32_SPEC_CTRL
:
4120 if (!msr_info
->host_initiated
&&
4121 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBRS
) &&
4122 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_SSBD
))
4125 msr_info
->data
= svm
->spec_ctrl
;
4127 case MSR_AMD64_VIRT_SPEC_CTRL
:
4128 if (!msr_info
->host_initiated
&&
4129 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
4132 msr_info
->data
= svm
->virt_spec_ctrl
;
4134 case MSR_F15H_IC_CFG
: {
4138 family
= guest_cpuid_family(vcpu
);
4139 model
= guest_cpuid_model(vcpu
);
4141 if (family
< 0 || model
< 0)
4142 return kvm_get_msr_common(vcpu
, msr_info
);
4146 if (family
== 0x15 &&
4147 (model
>= 0x2 && model
< 0x20))
4148 msr_info
->data
= 0x1E;
4151 case MSR_F10H_DECFG
:
4152 msr_info
->data
= svm
->msr_decfg
;
4155 return kvm_get_msr_common(vcpu
, msr_info
);
4160 static int rdmsr_interception(struct vcpu_svm
*svm
)
4162 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
4163 struct msr_data msr_info
;
4165 msr_info
.index
= ecx
;
4166 msr_info
.host_initiated
= false;
4167 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
4168 trace_kvm_msr_read_ex(ecx
);
4169 kvm_inject_gp(&svm
->vcpu
, 0);
4172 trace_kvm_msr_read(ecx
, msr_info
.data
);
4174 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
4175 msr_info
.data
& 0xffffffff);
4176 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
4177 msr_info
.data
>> 32);
4178 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
4179 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4183 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
4185 struct vcpu_svm
*svm
= to_svm(vcpu
);
4186 int svm_dis
, chg_mask
;
4188 if (data
& ~SVM_VM_CR_VALID_MASK
)
4191 chg_mask
= SVM_VM_CR_VALID_MASK
;
4193 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
4194 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
4196 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
4197 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
4199 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
4201 /* check for svm_disable while efer.svme is set */
4202 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
4208 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
4210 struct vcpu_svm
*svm
= to_svm(vcpu
);
4212 u32 ecx
= msr
->index
;
4213 u64 data
= msr
->data
;
4215 case MSR_IA32_CR_PAT
:
4216 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
4218 vcpu
->arch
.pat
= data
;
4219 svm
->vmcb
->save
.g_pat
= data
;
4220 mark_dirty(svm
->vmcb
, VMCB_NPT
);
4222 case MSR_IA32_SPEC_CTRL
:
4223 if (!msr
->host_initiated
&&
4224 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBRS
) &&
4225 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_SSBD
))
4228 /* The STIBP bit doesn't fault even if it's not advertised */
4229 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
| SPEC_CTRL_SSBD
))
4232 svm
->spec_ctrl
= data
;
4239 * When it's written (to non-zero) for the first time, pass
4243 * The handling of the MSR bitmap for L2 guests is done in
4244 * nested_svm_vmrun_msrpm.
4245 * We update the L1 MSR bit as well since it will end up
4246 * touching the MSR anyway now.
4248 set_msr_interception(svm
->msrpm
, MSR_IA32_SPEC_CTRL
, 1, 1);
4250 case MSR_IA32_PRED_CMD
:
4251 if (!msr
->host_initiated
&&
4252 !guest_cpuid_has(vcpu
, X86_FEATURE_AMD_IBPB
))
4255 if (data
& ~PRED_CMD_IBPB
)
4261 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
4262 if (is_guest_mode(vcpu
))
4264 set_msr_interception(svm
->msrpm
, MSR_IA32_PRED_CMD
, 0, 1);
4266 case MSR_AMD64_VIRT_SPEC_CTRL
:
4267 if (!msr
->host_initiated
&&
4268 !guest_cpuid_has(vcpu
, X86_FEATURE_VIRT_SSBD
))
4271 if (data
& ~SPEC_CTRL_SSBD
)
4274 svm
->virt_spec_ctrl
= data
;
4277 svm
->vmcb
->save
.star
= data
;
4279 #ifdef CONFIG_X86_64
4281 svm
->vmcb
->save
.lstar
= data
;
4284 svm
->vmcb
->save
.cstar
= data
;
4286 case MSR_KERNEL_GS_BASE
:
4287 svm
->vmcb
->save
.kernel_gs_base
= data
;
4289 case MSR_SYSCALL_MASK
:
4290 svm
->vmcb
->save
.sfmask
= data
;
4293 case MSR_IA32_SYSENTER_CS
:
4294 svm
->vmcb
->save
.sysenter_cs
= data
;
4296 case MSR_IA32_SYSENTER_EIP
:
4297 svm
->sysenter_eip
= data
;
4298 svm
->vmcb
->save
.sysenter_eip
= data
;
4300 case MSR_IA32_SYSENTER_ESP
:
4301 svm
->sysenter_esp
= data
;
4302 svm
->vmcb
->save
.sysenter_esp
= data
;
4305 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
4309 * This is rare, so we update the MSR here instead of using
4310 * direct_access_msrs. Doing that would require a rdmsr in
4313 svm
->tsc_aux
= data
;
4314 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
4316 case MSR_IA32_DEBUGCTLMSR
:
4317 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
4318 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4322 if (data
& DEBUGCTL_RESERVED_BITS
)
4325 svm
->vmcb
->save
.dbgctl
= data
;
4326 mark_dirty(svm
->vmcb
, VMCB_LBR
);
4327 if (data
& (1ULL<<0))
4328 svm_enable_lbrv(svm
);
4330 svm_disable_lbrv(svm
);
4332 case MSR_VM_HSAVE_PA
:
4333 svm
->nested
.hsave_msr
= data
;
4336 return svm_set_vm_cr(vcpu
, data
);
4338 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
4340 case MSR_F10H_DECFG
: {
4341 struct kvm_msr_entry msr_entry
;
4343 msr_entry
.index
= msr
->index
;
4344 if (svm_get_msr_feature(&msr_entry
))
4347 /* Check the supported bits */
4348 if (data
& ~msr_entry
.data
)
4351 /* Don't allow the guest to change a bit, #GP */
4352 if (!msr
->host_initiated
&& (data
^ msr_entry
.data
))
4355 svm
->msr_decfg
= data
;
4358 case MSR_IA32_APICBASE
:
4359 if (kvm_vcpu_apicv_active(vcpu
))
4360 avic_update_vapic_bar(to_svm(vcpu
), data
);
4361 /* Follow through */
4363 return kvm_set_msr_common(vcpu
, msr
);
4368 static int wrmsr_interception(struct vcpu_svm
*svm
)
4370 struct msr_data msr
;
4371 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
4372 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
4376 msr
.host_initiated
= false;
4378 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
4379 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
4380 trace_kvm_msr_write_ex(ecx
, data
);
4381 kvm_inject_gp(&svm
->vcpu
, 0);
4384 trace_kvm_msr_write(ecx
, data
);
4385 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4389 static int msr_interception(struct vcpu_svm
*svm
)
4391 if (svm
->vmcb
->control
.exit_info_1
)
4392 return wrmsr_interception(svm
);
4394 return rdmsr_interception(svm
);
4397 static int interrupt_window_interception(struct vcpu_svm
*svm
)
4399 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4400 svm_clear_vintr(svm
);
4401 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
4402 mark_dirty(svm
->vmcb
, VMCB_INTR
);
4403 ++svm
->vcpu
.stat
.irq_window_exits
;
4407 static int pause_interception(struct vcpu_svm
*svm
)
4409 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
4410 bool in_kernel
= (svm_get_cpl(vcpu
) == 0);
4412 if (pause_filter_thresh
)
4413 grow_ple_window(vcpu
);
4415 kvm_vcpu_on_spin(vcpu
, in_kernel
);
4419 static int nop_interception(struct vcpu_svm
*svm
)
4421 return kvm_skip_emulated_instruction(&(svm
->vcpu
));
4424 static int monitor_interception(struct vcpu_svm
*svm
)
4426 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
4427 return nop_interception(svm
);
4430 static int mwait_interception(struct vcpu_svm
*svm
)
4432 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
4433 return nop_interception(svm
);
4436 enum avic_ipi_failure_cause
{
4437 AVIC_IPI_FAILURE_INVALID_INT_TYPE
,
4438 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
,
4439 AVIC_IPI_FAILURE_INVALID_TARGET
,
4440 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
,
4443 static int avic_incomplete_ipi_interception(struct vcpu_svm
*svm
)
4445 u32 icrh
= svm
->vmcb
->control
.exit_info_1
>> 32;
4446 u32 icrl
= svm
->vmcb
->control
.exit_info_1
;
4447 u32 id
= svm
->vmcb
->control
.exit_info_2
>> 32;
4448 u32 index
= svm
->vmcb
->control
.exit_info_2
& 0xFF;
4449 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4451 trace_kvm_avic_incomplete_ipi(svm
->vcpu
.vcpu_id
, icrh
, icrl
, id
, index
);
4454 case AVIC_IPI_FAILURE_INVALID_INT_TYPE
:
4456 * AVIC hardware handles the generation of
4457 * IPIs when the specified Message Type is Fixed
4458 * (also known as fixed delivery mode) and
4459 * the Trigger Mode is edge-triggered. The hardware
4460 * also supports self and broadcast delivery modes
4461 * specified via the Destination Shorthand(DSH)
4462 * field of the ICRL. Logical and physical APIC ID
4463 * formats are supported. All other IPI types cause
4464 * a #VMEXIT, which needs to emulated.
4466 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
4467 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
4469 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
: {
4471 struct kvm_vcpu
*vcpu
;
4472 struct kvm
*kvm
= svm
->vcpu
.kvm
;
4473 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4476 * At this point, we expect that the AVIC HW has already
4477 * set the appropriate IRR bits on the valid target
4478 * vcpus. So, we just need to kick the appropriate vcpu.
4480 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
4481 bool m
= kvm_apic_match_dest(vcpu
, apic
,
4482 icrl
& KVM_APIC_SHORT_MASK
,
4483 GET_APIC_DEST_FIELD(icrh
),
4484 icrl
& KVM_APIC_DEST_MASK
);
4486 if (m
&& !avic_vcpu_is_running(vcpu
))
4487 kvm_vcpu_wake_up(vcpu
);
4491 case AVIC_IPI_FAILURE_INVALID_TARGET
:
4493 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
:
4494 WARN_ONCE(1, "Invalid backing page\n");
4497 pr_err("Unknown IPI interception\n");
4503 static u32
*avic_get_logical_id_entry(struct kvm_vcpu
*vcpu
, u32 ldr
, bool flat
)
4505 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
4507 u32
*logical_apic_id_table
;
4508 int dlid
= GET_APIC_LOGICAL_ID(ldr
);
4513 if (flat
) { /* flat */
4514 index
= ffs(dlid
) - 1;
4517 } else { /* cluster */
4518 int cluster
= (dlid
& 0xf0) >> 4;
4519 int apic
= ffs(dlid
& 0x0f) - 1;
4521 if ((apic
< 0) || (apic
> 7) ||
4524 index
= (cluster
<< 2) + apic
;
4527 logical_apic_id_table
= (u32
*) page_address(kvm_svm
->avic_logical_id_table_page
);
4529 return &logical_apic_id_table
[index
];
4532 static int avic_ldr_write(struct kvm_vcpu
*vcpu
, u8 g_physical_id
, u32 ldr
,
4536 u32
*entry
, new_entry
;
4538 flat
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
) == APIC_DFR_FLAT
;
4539 entry
= avic_get_logical_id_entry(vcpu
, ldr
, flat
);
4543 new_entry
= READ_ONCE(*entry
);
4544 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
;
4545 new_entry
|= (g_physical_id
& AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
);
4547 new_entry
|= AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4549 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4550 WRITE_ONCE(*entry
, new_entry
);
4555 static int avic_handle_ldr_update(struct kvm_vcpu
*vcpu
)
4558 struct vcpu_svm
*svm
= to_svm(vcpu
);
4559 u32 ldr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LDR
);
4564 ret
= avic_ldr_write(vcpu
, vcpu
->vcpu_id
, ldr
, true);
4565 if (ret
&& svm
->ldr_reg
) {
4566 avic_ldr_write(vcpu
, 0, svm
->ldr_reg
, false);
4574 static int avic_handle_apic_id_update(struct kvm_vcpu
*vcpu
)
4577 struct vcpu_svm
*svm
= to_svm(vcpu
);
4578 u32 apic_id_reg
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_ID
);
4579 u32 id
= (apic_id_reg
>> 24) & 0xff;
4581 if (vcpu
->vcpu_id
== id
)
4584 old
= avic_get_physical_id_entry(vcpu
, vcpu
->vcpu_id
);
4585 new = avic_get_physical_id_entry(vcpu
, id
);
4589 /* We need to move physical_id_entry to new offset */
4592 to_svm(vcpu
)->avic_physical_id_cache
= new;
4595 * Also update the guest physical APIC ID in the logical
4596 * APIC ID table entry if already setup the LDR.
4599 avic_handle_ldr_update(vcpu
);
4604 static int avic_handle_dfr_update(struct kvm_vcpu
*vcpu
)
4606 struct vcpu_svm
*svm
= to_svm(vcpu
);
4607 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
4608 u32 dfr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
);
4609 u32 mod
= (dfr
>> 28) & 0xf;
4612 * We assume that all local APICs are using the same type.
4613 * If this changes, we need to flush the AVIC logical
4616 if (kvm_svm
->ldr_mode
== mod
)
4619 clear_page(page_address(kvm_svm
->avic_logical_id_table_page
));
4620 kvm_svm
->ldr_mode
= mod
;
4623 avic_handle_ldr_update(vcpu
);
4627 static int avic_unaccel_trap_write(struct vcpu_svm
*svm
)
4629 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4630 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4631 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4635 if (avic_handle_apic_id_update(&svm
->vcpu
))
4639 if (avic_handle_ldr_update(&svm
->vcpu
))
4643 avic_handle_dfr_update(&svm
->vcpu
);
4649 kvm_lapic_reg_write(apic
, offset
, kvm_lapic_get_reg(apic
, offset
));
4654 static bool is_avic_unaccelerated_access_trap(u32 offset
)
4683 static int avic_unaccelerated_access_interception(struct vcpu_svm
*svm
)
4686 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4687 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4688 u32 vector
= svm
->vmcb
->control
.exit_info_2
&
4689 AVIC_UNACCEL_ACCESS_VECTOR_MASK
;
4690 bool write
= (svm
->vmcb
->control
.exit_info_1
>> 32) &
4691 AVIC_UNACCEL_ACCESS_WRITE_MASK
;
4692 bool trap
= is_avic_unaccelerated_access_trap(offset
);
4694 trace_kvm_avic_unaccelerated_access(svm
->vcpu
.vcpu_id
, offset
,
4695 trap
, write
, vector
);
4698 WARN_ONCE(!write
, "svm: Handling trap read.\n");
4699 ret
= avic_unaccel_trap_write(svm
);
4701 /* Handling Fault */
4702 ret
= (kvm_emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
);
4708 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
4709 [SVM_EXIT_READ_CR0
] = cr_interception
,
4710 [SVM_EXIT_READ_CR3
] = cr_interception
,
4711 [SVM_EXIT_READ_CR4
] = cr_interception
,
4712 [SVM_EXIT_READ_CR8
] = cr_interception
,
4713 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
4714 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
4715 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
4716 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
4717 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
4718 [SVM_EXIT_READ_DR0
] = dr_interception
,
4719 [SVM_EXIT_READ_DR1
] = dr_interception
,
4720 [SVM_EXIT_READ_DR2
] = dr_interception
,
4721 [SVM_EXIT_READ_DR3
] = dr_interception
,
4722 [SVM_EXIT_READ_DR4
] = dr_interception
,
4723 [SVM_EXIT_READ_DR5
] = dr_interception
,
4724 [SVM_EXIT_READ_DR6
] = dr_interception
,
4725 [SVM_EXIT_READ_DR7
] = dr_interception
,
4726 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
4727 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
4728 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
4729 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
4730 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
4731 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
4732 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
4733 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
4734 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
4735 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
4736 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
4737 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
4738 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
4739 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
4740 [SVM_EXIT_EXCP_BASE
+ GP_VECTOR
] = gp_interception
,
4741 [SVM_EXIT_INTR
] = intr_interception
,
4742 [SVM_EXIT_NMI
] = nmi_interception
,
4743 [SVM_EXIT_SMI
] = nop_on_interception
,
4744 [SVM_EXIT_INIT
] = nop_on_interception
,
4745 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
4746 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
4747 [SVM_EXIT_CPUID
] = cpuid_interception
,
4748 [SVM_EXIT_IRET
] = iret_interception
,
4749 [SVM_EXIT_INVD
] = emulate_on_interception
,
4750 [SVM_EXIT_PAUSE
] = pause_interception
,
4751 [SVM_EXIT_HLT
] = halt_interception
,
4752 [SVM_EXIT_INVLPG
] = invlpg_interception
,
4753 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
4754 [SVM_EXIT_IOIO
] = io_interception
,
4755 [SVM_EXIT_MSR
] = msr_interception
,
4756 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
4757 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
4758 [SVM_EXIT_VMRUN
] = vmrun_interception
,
4759 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
4760 [SVM_EXIT_VMLOAD
] = vmload_interception
,
4761 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
4762 [SVM_EXIT_STGI
] = stgi_interception
,
4763 [SVM_EXIT_CLGI
] = clgi_interception
,
4764 [SVM_EXIT_SKINIT
] = skinit_interception
,
4765 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
4766 [SVM_EXIT_MONITOR
] = monitor_interception
,
4767 [SVM_EXIT_MWAIT
] = mwait_interception
,
4768 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
4769 [SVM_EXIT_NPF
] = npf_interception
,
4770 [SVM_EXIT_RSM
] = rsm_interception
,
4771 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
4772 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
4775 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
4777 struct vcpu_svm
*svm
= to_svm(vcpu
);
4778 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4779 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
4781 pr_err("VMCB Control Area:\n");
4782 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
4783 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
4784 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
4785 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
4786 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
4787 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
4788 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
4789 pr_err("%-20s%d\n", "pause filter threshold:",
4790 control
->pause_filter_thresh
);
4791 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
4792 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
4793 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
4794 pr_err("%-20s%d\n", "asid:", control
->asid
);
4795 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
4796 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
4797 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
4798 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
4799 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
4800 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
4801 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
4802 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
4803 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
4804 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
4805 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
4806 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
4807 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
4808 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
4809 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
4810 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
4811 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
4812 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
4813 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
4814 pr_err("VMCB State Save Area:\n");
4815 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4817 save
->es
.selector
, save
->es
.attrib
,
4818 save
->es
.limit
, save
->es
.base
);
4819 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4821 save
->cs
.selector
, save
->cs
.attrib
,
4822 save
->cs
.limit
, save
->cs
.base
);
4823 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4825 save
->ss
.selector
, save
->ss
.attrib
,
4826 save
->ss
.limit
, save
->ss
.base
);
4827 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4829 save
->ds
.selector
, save
->ds
.attrib
,
4830 save
->ds
.limit
, save
->ds
.base
);
4831 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4833 save
->fs
.selector
, save
->fs
.attrib
,
4834 save
->fs
.limit
, save
->fs
.base
);
4835 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4837 save
->gs
.selector
, save
->gs
.attrib
,
4838 save
->gs
.limit
, save
->gs
.base
);
4839 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4841 save
->gdtr
.selector
, save
->gdtr
.attrib
,
4842 save
->gdtr
.limit
, save
->gdtr
.base
);
4843 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4845 save
->ldtr
.selector
, save
->ldtr
.attrib
,
4846 save
->ldtr
.limit
, save
->ldtr
.base
);
4847 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4849 save
->idtr
.selector
, save
->idtr
.attrib
,
4850 save
->idtr
.limit
, save
->idtr
.base
);
4851 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4853 save
->tr
.selector
, save
->tr
.attrib
,
4854 save
->tr
.limit
, save
->tr
.base
);
4855 pr_err("cpl: %d efer: %016llx\n",
4856 save
->cpl
, save
->efer
);
4857 pr_err("%-15s %016llx %-13s %016llx\n",
4858 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
4859 pr_err("%-15s %016llx %-13s %016llx\n",
4860 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
4861 pr_err("%-15s %016llx %-13s %016llx\n",
4862 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
4863 pr_err("%-15s %016llx %-13s %016llx\n",
4864 "rip:", save
->rip
, "rflags:", save
->rflags
);
4865 pr_err("%-15s %016llx %-13s %016llx\n",
4866 "rsp:", save
->rsp
, "rax:", save
->rax
);
4867 pr_err("%-15s %016llx %-13s %016llx\n",
4868 "star:", save
->star
, "lstar:", save
->lstar
);
4869 pr_err("%-15s %016llx %-13s %016llx\n",
4870 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
4871 pr_err("%-15s %016llx %-13s %016llx\n",
4872 "kernel_gs_base:", save
->kernel_gs_base
,
4873 "sysenter_cs:", save
->sysenter_cs
);
4874 pr_err("%-15s %016llx %-13s %016llx\n",
4875 "sysenter_esp:", save
->sysenter_esp
,
4876 "sysenter_eip:", save
->sysenter_eip
);
4877 pr_err("%-15s %016llx %-13s %016llx\n",
4878 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
4879 pr_err("%-15s %016llx %-13s %016llx\n",
4880 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
4881 pr_err("%-15s %016llx %-13s %016llx\n",
4882 "excp_from:", save
->last_excp_from
,
4883 "excp_to:", save
->last_excp_to
);
4886 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4888 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
4890 *info1
= control
->exit_info_1
;
4891 *info2
= control
->exit_info_2
;
4894 static int handle_exit(struct kvm_vcpu
*vcpu
)
4896 struct vcpu_svm
*svm
= to_svm(vcpu
);
4897 struct kvm_run
*kvm_run
= vcpu
->run
;
4898 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
4900 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
4902 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
4903 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
4905 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
4907 if (unlikely(svm
->nested
.exit_required
)) {
4908 nested_svm_vmexit(svm
);
4909 svm
->nested
.exit_required
= false;
4914 if (is_guest_mode(vcpu
)) {
4917 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
4918 svm
->vmcb
->control
.exit_info_1
,
4919 svm
->vmcb
->control
.exit_info_2
,
4920 svm
->vmcb
->control
.exit_int_info
,
4921 svm
->vmcb
->control
.exit_int_info_err
,
4924 vmexit
= nested_svm_exit_special(svm
);
4926 if (vmexit
== NESTED_EXIT_CONTINUE
)
4927 vmexit
= nested_svm_exit_handled(svm
);
4929 if (vmexit
== NESTED_EXIT_DONE
)
4933 svm_complete_interrupts(svm
);
4935 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
4936 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4937 kvm_run
->fail_entry
.hardware_entry_failure_reason
4938 = svm
->vmcb
->control
.exit_code
;
4939 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4944 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
4945 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
4946 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
4947 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
4948 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
4950 __func__
, svm
->vmcb
->control
.exit_int_info
,
4953 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
4954 || !svm_exit_handlers
[exit_code
]) {
4955 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
4956 kvm_queue_exception(vcpu
, UD_VECTOR
);
4960 return svm_exit_handlers
[exit_code
](svm
);
4963 static void reload_tss(struct kvm_vcpu
*vcpu
)
4965 int cpu
= raw_smp_processor_id();
4967 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4968 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
4972 static void pre_sev_run(struct vcpu_svm
*svm
, int cpu
)
4974 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4975 int asid
= sev_get_asid(svm
->vcpu
.kvm
);
4977 /* Assign the asid allocated with this SEV guest */
4978 svm
->vmcb
->control
.asid
= asid
;
4983 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4984 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4986 if (sd
->sev_vmcbs
[asid
] == svm
->vmcb
&&
4987 svm
->last_cpu
== cpu
)
4990 svm
->last_cpu
= cpu
;
4991 sd
->sev_vmcbs
[asid
] = svm
->vmcb
;
4992 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
4993 mark_dirty(svm
->vmcb
, VMCB_ASID
);
4996 static void pre_svm_run(struct vcpu_svm
*svm
)
4998 int cpu
= raw_smp_processor_id();
5000 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
5002 if (sev_guest(svm
->vcpu
.kvm
))
5003 return pre_sev_run(svm
, cpu
);
5005 /* FIXME: handle wraparound of asid_generation */
5006 if (svm
->asid_generation
!= sd
->asid_generation
)
5010 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
5012 struct vcpu_svm
*svm
= to_svm(vcpu
);
5014 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
5015 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
5016 set_intercept(svm
, INTERCEPT_IRET
);
5017 ++vcpu
->stat
.nmi_injections
;
5020 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
5022 struct vmcb_control_area
*control
;
5024 /* The following fields are ignored when AVIC is enabled */
5025 control
= &svm
->vmcb
->control
;
5026 control
->int_vector
= irq
;
5027 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
5028 control
->int_ctl
|= V_IRQ_MASK
|
5029 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
5030 mark_dirty(svm
->vmcb
, VMCB_INTR
);
5033 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
5035 struct vcpu_svm
*svm
= to_svm(vcpu
);
5037 BUG_ON(!(gif_set(svm
)));
5039 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
5040 ++vcpu
->stat
.irq_injections
;
5042 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
5043 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
5046 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu
*vcpu
)
5048 return is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
);
5051 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
5053 struct vcpu_svm
*svm
= to_svm(vcpu
);
5055 if (svm_nested_virtualize_tpr(vcpu
) ||
5056 kvm_vcpu_apicv_active(vcpu
))
5059 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
5065 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
5068 static void svm_set_virtual_apic_mode(struct kvm_vcpu
*vcpu
)
5073 static bool svm_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5075 return avic
&& irqchip_split(vcpu
->kvm
);
5078 static void svm_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
5082 static void svm_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
5086 /* Note: Currently only used by Hyper-V. */
5087 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5089 struct vcpu_svm
*svm
= to_svm(vcpu
);
5090 struct vmcb
*vmcb
= svm
->vmcb
;
5092 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
5095 vmcb
->control
.int_ctl
&= ~AVIC_ENABLE_MASK
;
5096 mark_dirty(vmcb
, VMCB_INTR
);
5099 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
5104 static void svm_deliver_avic_intr(struct kvm_vcpu
*vcpu
, int vec
)
5106 kvm_lapic_set_irr(vec
, vcpu
->arch
.apic
);
5107 smp_mb__after_atomic();
5109 if (avic_vcpu_is_running(vcpu
))
5110 wrmsrl(SVM_AVIC_DOORBELL
,
5111 kvm_cpu_get_apicid(vcpu
->cpu
));
5113 kvm_vcpu_wake_up(vcpu
);
5116 static void svm_ir_list_del(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
5118 unsigned long flags
;
5119 struct amd_svm_iommu_ir
*cur
;
5121 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
5122 list_for_each_entry(cur
, &svm
->ir_list
, node
) {
5123 if (cur
->data
!= pi
->ir_data
)
5125 list_del(&cur
->node
);
5129 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
5132 static int svm_ir_list_add(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
5135 unsigned long flags
;
5136 struct amd_svm_iommu_ir
*ir
;
5139 * In some cases, the existing irte is updaed and re-set,
5140 * so we need to check here if it's already been * added
5143 if (pi
->ir_data
&& (pi
->prev_ga_tag
!= 0)) {
5144 struct kvm
*kvm
= svm
->vcpu
.kvm
;
5145 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(pi
->prev_ga_tag
);
5146 struct kvm_vcpu
*prev_vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
5147 struct vcpu_svm
*prev_svm
;
5154 prev_svm
= to_svm(prev_vcpu
);
5155 svm_ir_list_del(prev_svm
, pi
);
5159 * Allocating new amd_iommu_pi_data, which will get
5160 * add to the per-vcpu ir_list.
5162 ir
= kzalloc(sizeof(struct amd_svm_iommu_ir
), GFP_KERNEL
);
5167 ir
->data
= pi
->ir_data
;
5169 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
5170 list_add(&ir
->node
, &svm
->ir_list
);
5171 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
5178 * The HW cannot support posting multicast/broadcast
5179 * interrupts to a vCPU. So, we still use legacy interrupt
5180 * remapping for these kind of interrupts.
5182 * For lowest-priority interrupts, we only support
5183 * those with single CPU as the destination, e.g. user
5184 * configures the interrupts via /proc/irq or uses
5185 * irqbalance to make the interrupts single-CPU.
5188 get_pi_vcpu_info(struct kvm
*kvm
, struct kvm_kernel_irq_routing_entry
*e
,
5189 struct vcpu_data
*vcpu_info
, struct vcpu_svm
**svm
)
5191 struct kvm_lapic_irq irq
;
5192 struct kvm_vcpu
*vcpu
= NULL
;
5194 kvm_set_msi_irq(kvm
, e
, &irq
);
5196 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
5197 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5198 __func__
, irq
.vector
);
5202 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__
,
5204 *svm
= to_svm(vcpu
);
5205 vcpu_info
->pi_desc_addr
= __sme_set(page_to_phys((*svm
)->avic_backing_page
));
5206 vcpu_info
->vector
= irq
.vector
;
5212 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5215 * @host_irq: host irq of the interrupt
5216 * @guest_irq: gsi of the interrupt
5217 * @set: set or unset PI
5218 * returns 0 on success, < 0 on failure
5220 static int svm_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
5221 uint32_t guest_irq
, bool set
)
5223 struct kvm_kernel_irq_routing_entry
*e
;
5224 struct kvm_irq_routing_table
*irq_rt
;
5225 int idx
, ret
= -EINVAL
;
5227 if (!kvm_arch_has_assigned_device(kvm
) ||
5228 !irq_remapping_cap(IRQ_POSTING_CAP
))
5231 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5232 __func__
, host_irq
, guest_irq
, set
);
5234 idx
= srcu_read_lock(&kvm
->irq_srcu
);
5235 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
5236 WARN_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
5238 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
5239 struct vcpu_data vcpu_info
;
5240 struct vcpu_svm
*svm
= NULL
;
5242 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
5246 * Here, we setup with legacy mode in the following cases:
5247 * 1. When cannot target interrupt to a specific vcpu.
5248 * 2. Unsetting posted interrupt.
5249 * 3. APIC virtialization is disabled for the vcpu.
5251 if (!get_pi_vcpu_info(kvm
, e
, &vcpu_info
, &svm
) && set
&&
5252 kvm_vcpu_apicv_active(&svm
->vcpu
)) {
5253 struct amd_iommu_pi_data pi
;
5255 /* Try to enable guest_mode in IRTE */
5256 pi
.base
= __sme_set(page_to_phys(svm
->avic_backing_page
) &
5258 pi
.ga_tag
= AVIC_GATAG(to_kvm_svm(kvm
)->avic_vm_id
,
5260 pi
.is_guest_mode
= true;
5261 pi
.vcpu_data
= &vcpu_info
;
5262 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
5265 * Here, we successfully setting up vcpu affinity in
5266 * IOMMU guest mode. Now, we need to store the posted
5267 * interrupt information in a per-vcpu ir_list so that
5268 * we can reference to them directly when we update vcpu
5269 * scheduling information in IOMMU irte.
5271 if (!ret
&& pi
.is_guest_mode
)
5272 svm_ir_list_add(svm
, &pi
);
5274 /* Use legacy mode in IRTE */
5275 struct amd_iommu_pi_data pi
;
5278 * Here, pi is used to:
5279 * - Tell IOMMU to use legacy mode for this interrupt.
5280 * - Retrieve ga_tag of prior interrupt remapping data.
5282 pi
.is_guest_mode
= false;
5283 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
5286 * Check if the posted interrupt was previously
5287 * setup with the guest_mode by checking if the ga_tag
5288 * was cached. If so, we need to clean up the per-vcpu
5291 if (!ret
&& pi
.prev_ga_tag
) {
5292 int id
= AVIC_GATAG_TO_VCPUID(pi
.prev_ga_tag
);
5293 struct kvm_vcpu
*vcpu
;
5295 vcpu
= kvm_get_vcpu_by_id(kvm
, id
);
5297 svm_ir_list_del(to_svm(vcpu
), &pi
);
5302 trace_kvm_pi_irte_update(host_irq
, svm
->vcpu
.vcpu_id
,
5303 e
->gsi
, vcpu_info
.vector
,
5304 vcpu_info
.pi_desc_addr
, set
);
5308 pr_err("%s: failed to update PI IRTE\n", __func__
);
5315 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
5319 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
5321 struct vcpu_svm
*svm
= to_svm(vcpu
);
5322 struct vmcb
*vmcb
= svm
->vmcb
;
5324 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
5325 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
5326 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
5331 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5333 struct vcpu_svm
*svm
= to_svm(vcpu
);
5335 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
5338 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5340 struct vcpu_svm
*svm
= to_svm(vcpu
);
5343 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
5344 set_intercept(svm
, INTERCEPT_IRET
);
5346 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
5347 clr_intercept(svm
, INTERCEPT_IRET
);
5351 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5353 struct vcpu_svm
*svm
= to_svm(vcpu
);
5354 struct vmcb
*vmcb
= svm
->vmcb
;
5357 if (!gif_set(svm
) ||
5358 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
5361 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
5363 if (is_guest_mode(vcpu
))
5364 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
5369 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5371 struct vcpu_svm
*svm
= to_svm(vcpu
);
5373 if (kvm_vcpu_apicv_active(vcpu
))
5377 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5378 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5379 * get that intercept, this function will be called again though and
5380 * we'll get the vintr intercept. However, if the vGIF feature is
5381 * enabled, the STGI interception will not occur. Enable the irq
5382 * window under the assumption that the hardware will set the GIF.
5384 if ((vgif_enabled(svm
) || gif_set(svm
)) && nested_svm_intr(svm
)) {
5386 svm_inject_irq(svm
, 0x0);
5390 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5392 struct vcpu_svm
*svm
= to_svm(vcpu
);
5394 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
5396 return; /* IRET will cause a vm exit */
5398 if (!gif_set(svm
)) {
5399 if (vgif_enabled(svm
))
5400 set_intercept(svm
, INTERCEPT_STGI
);
5401 return; /* STGI will cause a vm exit */
5404 if (svm
->nested
.exit_required
)
5405 return; /* we're not going to run the guest yet */
5408 * Something prevents NMI from been injected. Single step over possible
5409 * problem (IRET or exception injection or interrupt shadow)
5411 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
5412 svm
->nmi_singlestep
= true;
5413 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
5416 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5421 static int svm_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
5426 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
)
5428 struct vcpu_svm
*svm
= to_svm(vcpu
);
5430 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
5431 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
5433 svm
->asid_generation
--;
5436 static void svm_flush_tlb_gva(struct kvm_vcpu
*vcpu
, gva_t gva
)
5438 struct vcpu_svm
*svm
= to_svm(vcpu
);
5440 invlpga(gva
, svm
->vmcb
->control
.asid
);
5443 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
5447 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
5449 struct vcpu_svm
*svm
= to_svm(vcpu
);
5451 if (svm_nested_virtualize_tpr(vcpu
))
5454 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
5455 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
5456 kvm_set_cr8(vcpu
, cr8
);
5460 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
5462 struct vcpu_svm
*svm
= to_svm(vcpu
);
5465 if (svm_nested_virtualize_tpr(vcpu
) ||
5466 kvm_vcpu_apicv_active(vcpu
))
5469 cr8
= kvm_get_cr8(vcpu
);
5470 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
5471 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
5474 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
5478 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
5479 unsigned int3_injected
= svm
->int3_injected
;
5481 svm
->int3_injected
= 0;
5484 * If we've made progress since setting HF_IRET_MASK, we've
5485 * executed an IRET and can allow NMI injection.
5487 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
5488 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
5489 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
5490 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
5493 svm
->vcpu
.arch
.nmi_injected
= false;
5494 kvm_clear_exception_queue(&svm
->vcpu
);
5495 kvm_clear_interrupt_queue(&svm
->vcpu
);
5497 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
5500 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
5502 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
5503 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
5506 case SVM_EXITINTINFO_TYPE_NMI
:
5507 svm
->vcpu
.arch
.nmi_injected
= true;
5509 case SVM_EXITINTINFO_TYPE_EXEPT
:
5511 * In case of software exceptions, do not reinject the vector,
5512 * but re-execute the instruction instead. Rewind RIP first
5513 * if we emulated INT3 before.
5515 if (kvm_exception_is_soft(vector
)) {
5516 if (vector
== BP_VECTOR
&& int3_injected
&&
5517 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
5518 kvm_rip_write(&svm
->vcpu
,
5519 kvm_rip_read(&svm
->vcpu
) -
5523 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
5524 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
5525 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
5528 kvm_requeue_exception(&svm
->vcpu
, vector
);
5530 case SVM_EXITINTINFO_TYPE_INTR
:
5531 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
5538 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
5540 struct vcpu_svm
*svm
= to_svm(vcpu
);
5541 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
5543 control
->exit_int_info
= control
->event_inj
;
5544 control
->exit_int_info_err
= control
->event_inj_err
;
5545 control
->event_inj
= 0;
5546 svm_complete_interrupts(svm
);
5549 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
5551 struct vcpu_svm
*svm
= to_svm(vcpu
);
5553 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
5554 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
5555 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
5558 * A vmexit emulation is required before the vcpu can be executed
5561 if (unlikely(svm
->nested
.exit_required
))
5565 * Disable singlestep if we're injecting an interrupt/exception.
5566 * We don't want our modified rflags to be pushed on the stack where
5567 * we might not be able to easily reset them if we disabled NMI
5570 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
5572 * Event injection happens before external interrupts cause a
5573 * vmexit and interrupts are disabled here, so smp_send_reschedule
5574 * is enough to force an immediate vmexit.
5576 disable_nmi_singlestep(svm
);
5577 smp_send_reschedule(vcpu
->cpu
);
5582 sync_lapic_to_cr8(vcpu
);
5584 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
5589 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5590 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5591 * is no need to worry about the conditional branch over the wrmsr
5592 * being speculatively taken.
5594 x86_spec_ctrl_set_guest(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
5599 "push %%" _ASM_BP
"; \n\t"
5600 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
5601 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
5602 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
5603 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
5604 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
5605 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
5606 #ifdef CONFIG_X86_64
5607 "mov %c[r8](%[svm]), %%r8 \n\t"
5608 "mov %c[r9](%[svm]), %%r9 \n\t"
5609 "mov %c[r10](%[svm]), %%r10 \n\t"
5610 "mov %c[r11](%[svm]), %%r11 \n\t"
5611 "mov %c[r12](%[svm]), %%r12 \n\t"
5612 "mov %c[r13](%[svm]), %%r13 \n\t"
5613 "mov %c[r14](%[svm]), %%r14 \n\t"
5614 "mov %c[r15](%[svm]), %%r15 \n\t"
5617 /* Enter guest mode */
5618 "push %%" _ASM_AX
" \n\t"
5619 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
5620 __ex(SVM_VMLOAD
) "\n\t"
5621 __ex(SVM_VMRUN
) "\n\t"
5622 __ex(SVM_VMSAVE
) "\n\t"
5623 "pop %%" _ASM_AX
" \n\t"
5625 /* Save guest registers, load host registers */
5626 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
5627 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
5628 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
5629 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
5630 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
5631 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
5632 #ifdef CONFIG_X86_64
5633 "mov %%r8, %c[r8](%[svm]) \n\t"
5634 "mov %%r9, %c[r9](%[svm]) \n\t"
5635 "mov %%r10, %c[r10](%[svm]) \n\t"
5636 "mov %%r11, %c[r11](%[svm]) \n\t"
5637 "mov %%r12, %c[r12](%[svm]) \n\t"
5638 "mov %%r13, %c[r13](%[svm]) \n\t"
5639 "mov %%r14, %c[r14](%[svm]) \n\t"
5640 "mov %%r15, %c[r15](%[svm]) \n\t"
5643 * Clear host registers marked as clobbered to prevent
5646 "xor %%" _ASM_BX
", %%" _ASM_BX
" \n\t"
5647 "xor %%" _ASM_CX
", %%" _ASM_CX
" \n\t"
5648 "xor %%" _ASM_DX
", %%" _ASM_DX
" \n\t"
5649 "xor %%" _ASM_SI
", %%" _ASM_SI
" \n\t"
5650 "xor %%" _ASM_DI
", %%" _ASM_DI
" \n\t"
5651 #ifdef CONFIG_X86_64
5652 "xor %%r8, %%r8 \n\t"
5653 "xor %%r9, %%r9 \n\t"
5654 "xor %%r10, %%r10 \n\t"
5655 "xor %%r11, %%r11 \n\t"
5656 "xor %%r12, %%r12 \n\t"
5657 "xor %%r13, %%r13 \n\t"
5658 "xor %%r14, %%r14 \n\t"
5659 "xor %%r15, %%r15 \n\t"
5664 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
5665 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
5666 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
5667 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
5668 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
5669 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
5670 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
5671 #ifdef CONFIG_X86_64
5672 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
5673 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
5674 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
5675 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
5676 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
5677 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
5678 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
5679 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
5682 #ifdef CONFIG_X86_64
5683 , "rbx", "rcx", "rdx", "rsi", "rdi"
5684 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5686 , "ebx", "ecx", "edx", "esi", "edi"
5690 /* Eliminate branch target predictions from guest mode */
5693 #ifdef CONFIG_X86_64
5694 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
5696 loadsegment(fs
, svm
->host
.fs
);
5697 #ifndef CONFIG_X86_32_LAZY_GS
5698 loadsegment(gs
, svm
->host
.gs
);
5703 * We do not use IBRS in the kernel. If this vCPU has used the
5704 * SPEC_CTRL MSR it may have left it on; save the value and
5705 * turn it off. This is much more efficient than blindly adding
5706 * it to the atomic save/restore list. Especially as the former
5707 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5709 * For non-nested case:
5710 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5714 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5717 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
5718 svm
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
5722 local_irq_disable();
5724 x86_spec_ctrl_restore_host(svm
->spec_ctrl
, svm
->virt_spec_ctrl
);
5726 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
5727 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
5728 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
5729 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
5731 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5732 kvm_before_interrupt(&svm
->vcpu
);
5736 /* Any pending NMI will happen here */
5738 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5739 kvm_after_interrupt(&svm
->vcpu
);
5741 sync_cr8_to_lapic(vcpu
);
5745 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
5747 /* if exit due to PF check for async PF */
5748 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
5749 svm
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
5752 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
5753 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
5757 * We need to handle MC intercepts here before the vcpu has a chance to
5758 * change the physical cpu
5760 if (unlikely(svm
->vmcb
->control
.exit_code
==
5761 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
5762 svm_handle_mce(svm
);
5764 mark_all_clean(svm
->vmcb
);
5766 STACK_FRAME_NON_STANDARD(svm_vcpu_run
);
5768 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5770 struct vcpu_svm
*svm
= to_svm(vcpu
);
5772 svm
->vmcb
->save
.cr3
= __sme_set(root
);
5773 mark_dirty(svm
->vmcb
, VMCB_CR
);
5776 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5778 struct vcpu_svm
*svm
= to_svm(vcpu
);
5780 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
5781 mark_dirty(svm
->vmcb
, VMCB_NPT
);
5783 /* Also sync guest cr3 here in case we live migrate */
5784 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
5785 mark_dirty(svm
->vmcb
, VMCB_CR
);
5788 static int is_disabled(void)
5792 rdmsrl(MSR_VM_CR
, vm_cr
);
5793 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
5800 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5803 * Patch in the VMMCALL instruction:
5805 hypercall
[0] = 0x0f;
5806 hypercall
[1] = 0x01;
5807 hypercall
[2] = 0xd9;
5810 static void svm_check_processor_compat(void *rtn
)
5815 static bool svm_cpu_has_accelerated_tpr(void)
5820 static bool svm_has_emulated_msr(int index
)
5825 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5830 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
5832 struct vcpu_svm
*svm
= to_svm(vcpu
);
5834 /* Update nrips enabled cache */
5835 svm
->nrips_enabled
= !!guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_NRIPS
);
5837 if (!kvm_vcpu_apicv_active(vcpu
))
5840 guest_cpuid_clear(vcpu
, X86_FEATURE_X2APIC
);
5843 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5848 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5852 entry
->ecx
|= (1 << 2); /* Set SVM bit */
5855 entry
->eax
= 1; /* SVM revision 1 */
5856 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
5857 ASID emulation to nested SVM */
5858 entry
->ecx
= 0; /* Reserved */
5859 entry
->edx
= 0; /* Per default do not support any
5860 additional features */
5862 /* Support next_rip if host supports it */
5863 if (boot_cpu_has(X86_FEATURE_NRIPS
))
5864 entry
->edx
|= SVM_FEATURE_NRIP
;
5866 /* Support NPT for the guest if enabled */
5868 entry
->edx
|= SVM_FEATURE_NPT
;
5872 /* Support memory encryption cpuid if host supports it */
5873 if (boot_cpu_has(X86_FEATURE_SEV
))
5874 cpuid(0x8000001f, &entry
->eax
, &entry
->ebx
,
5875 &entry
->ecx
, &entry
->edx
);
5880 static int svm_get_lpage_level(void)
5882 return PT_PDPE_LEVEL
;
5885 static bool svm_rdtscp_supported(void)
5887 return boot_cpu_has(X86_FEATURE_RDTSCP
);
5890 static bool svm_invpcid_supported(void)
5895 static bool svm_mpx_supported(void)
5900 static bool svm_xsaves_supported(void)
5905 static bool svm_umip_emulated(void)
5910 static bool svm_has_wbinvd_exit(void)
5915 #define PRE_EX(exit) { .exit_code = (exit), \
5916 .stage = X86_ICPT_PRE_EXCEPT, }
5917 #define POST_EX(exit) { .exit_code = (exit), \
5918 .stage = X86_ICPT_POST_EXCEPT, }
5919 #define POST_MEM(exit) { .exit_code = (exit), \
5920 .stage = X86_ICPT_POST_MEMACCESS, }
5922 static const struct __x86_intercept
{
5924 enum x86_intercept_stage stage
;
5925 } x86_intercept_map
[] = {
5926 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
5927 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5928 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5929 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5930 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
5931 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
5932 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
5933 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
5934 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
5935 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
5936 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
5937 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
5938 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
5939 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
5940 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
5941 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
5942 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
5943 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
5944 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
5945 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
5946 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
5947 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
5948 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
5949 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
5950 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
5951 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
5952 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
5953 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
5954 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
5955 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
5956 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
5957 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
5958 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
5959 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
5960 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
5961 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
5962 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
5963 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
5964 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
5965 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
5966 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
5967 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
5968 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
5969 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
5970 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
5971 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
5978 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
5979 struct x86_instruction_info
*info
,
5980 enum x86_intercept_stage stage
)
5982 struct vcpu_svm
*svm
= to_svm(vcpu
);
5983 int vmexit
, ret
= X86EMUL_CONTINUE
;
5984 struct __x86_intercept icpt_info
;
5985 struct vmcb
*vmcb
= svm
->vmcb
;
5987 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
5990 icpt_info
= x86_intercept_map
[info
->intercept
];
5992 if (stage
!= icpt_info
.stage
)
5995 switch (icpt_info
.exit_code
) {
5996 case SVM_EXIT_READ_CR0
:
5997 if (info
->intercept
== x86_intercept_cr_read
)
5998 icpt_info
.exit_code
+= info
->modrm_reg
;
6000 case SVM_EXIT_WRITE_CR0
: {
6001 unsigned long cr0
, val
;
6004 if (info
->intercept
== x86_intercept_cr_write
)
6005 icpt_info
.exit_code
+= info
->modrm_reg
;
6007 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
6008 info
->intercept
== x86_intercept_clts
)
6011 intercept
= svm
->nested
.intercept
;
6013 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
6016 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
6017 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
6019 if (info
->intercept
== x86_intercept_lmsw
) {
6022 /* lmsw can't clear PE - catch this here */
6023 if (cr0
& X86_CR0_PE
)
6028 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
6032 case SVM_EXIT_READ_DR0
:
6033 case SVM_EXIT_WRITE_DR0
:
6034 icpt_info
.exit_code
+= info
->modrm_reg
;
6037 if (info
->intercept
== x86_intercept_wrmsr
)
6038 vmcb
->control
.exit_info_1
= 1;
6040 vmcb
->control
.exit_info_1
= 0;
6042 case SVM_EXIT_PAUSE
:
6044 * We get this for NOP only, but pause
6045 * is rep not, check this here
6047 if (info
->rep_prefix
!= REPE_PREFIX
)
6050 case SVM_EXIT_IOIO
: {
6054 if (info
->intercept
== x86_intercept_in
||
6055 info
->intercept
== x86_intercept_ins
) {
6056 exit_info
= ((info
->src_val
& 0xffff) << 16) |
6058 bytes
= info
->dst_bytes
;
6060 exit_info
= (info
->dst_val
& 0xffff) << 16;
6061 bytes
= info
->src_bytes
;
6064 if (info
->intercept
== x86_intercept_outs
||
6065 info
->intercept
== x86_intercept_ins
)
6066 exit_info
|= SVM_IOIO_STR_MASK
;
6068 if (info
->rep_prefix
)
6069 exit_info
|= SVM_IOIO_REP_MASK
;
6071 bytes
= min(bytes
, 4u);
6073 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
6075 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
6077 vmcb
->control
.exit_info_1
= exit_info
;
6078 vmcb
->control
.exit_info_2
= info
->next_rip
;
6086 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6087 if (static_cpu_has(X86_FEATURE_NRIPS
))
6088 vmcb
->control
.next_rip
= info
->next_rip
;
6089 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
6090 vmexit
= nested_svm_exit_handled(svm
);
6092 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
6099 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
6103 * We must have an instruction with interrupts enabled, so
6104 * the timer interrupt isn't delayed by the interrupt shadow.
6107 local_irq_disable();
6110 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
6112 if (pause_filter_thresh
)
6113 shrink_ple_window(vcpu
);
6116 static inline void avic_post_state_restore(struct kvm_vcpu
*vcpu
)
6118 if (avic_handle_apic_id_update(vcpu
) != 0)
6120 if (avic_handle_dfr_update(vcpu
) != 0)
6122 avic_handle_ldr_update(vcpu
);
6125 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
6127 /* [63:9] are reserved. */
6128 vcpu
->arch
.mcg_cap
&= 0x1ff;
6131 static int svm_smi_allowed(struct kvm_vcpu
*vcpu
)
6133 struct vcpu_svm
*svm
= to_svm(vcpu
);
6135 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6139 if (is_guest_mode(&svm
->vcpu
) &&
6140 svm
->nested
.intercept
& (1ULL << INTERCEPT_SMI
)) {
6141 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6142 svm
->vmcb
->control
.exit_code
= SVM_EXIT_SMI
;
6143 svm
->nested
.exit_required
= true;
6150 static int svm_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
6152 struct vcpu_svm
*svm
= to_svm(vcpu
);
6155 if (is_guest_mode(vcpu
)) {
6156 /* FED8h - SVM Guest */
6157 put_smstate(u64
, smstate
, 0x7ed8, 1);
6158 /* FEE0h - SVM Guest VMCB Physical Address */
6159 put_smstate(u64
, smstate
, 0x7ee0, svm
->nested
.vmcb
);
6161 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
6162 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
6163 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
6165 ret
= nested_svm_vmexit(svm
);
6172 static int svm_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
6174 struct vcpu_svm
*svm
= to_svm(vcpu
);
6175 struct vmcb
*nested_vmcb
;
6183 ret
= kvm_vcpu_read_guest(vcpu
, smbase
+ 0xfed8, &svm_state_save
,
6184 sizeof(svm_state_save
));
6188 if (svm_state_save
.guest
) {
6189 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
6190 nested_vmcb
= nested_svm_map(svm
, svm_state_save
.vmcb
, &page
);
6192 enter_svm_guest_mode(svm
, svm_state_save
.vmcb
, nested_vmcb
, page
);
6195 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
6200 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
6202 struct vcpu_svm
*svm
= to_svm(vcpu
);
6204 if (!gif_set(svm
)) {
6205 if (vgif_enabled(svm
))
6206 set_intercept(svm
, INTERCEPT_STGI
);
6207 /* STGI will cause a vm exit */
6213 static int sev_asid_new(void)
6218 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6220 pos
= find_next_zero_bit(sev_asid_bitmap
, max_sev_asid
, min_sev_asid
- 1);
6221 if (pos
>= max_sev_asid
)
6224 set_bit(pos
, sev_asid_bitmap
);
6228 static int sev_guest_init(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6230 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6234 asid
= sev_asid_new();
6238 ret
= sev_platform_init(&argp
->error
);
6244 INIT_LIST_HEAD(&sev
->regions_list
);
6249 __sev_asid_free(asid
);
6253 static int sev_bind_asid(struct kvm
*kvm
, unsigned int handle
, int *error
)
6255 struct sev_data_activate
*data
;
6256 int asid
= sev_get_asid(kvm
);
6259 wbinvd_on_all_cpus();
6261 ret
= sev_guest_df_flush(error
);
6265 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6269 /* activate ASID on the given handle */
6270 data
->handle
= handle
;
6272 ret
= sev_guest_activate(data
, error
);
6278 static int __sev_issue_cmd(int fd
, int id
, void *data
, int *error
)
6287 ret
= sev_issue_cmd_external_user(f
.file
, id
, data
, error
);
6293 static int sev_issue_cmd(struct kvm
*kvm
, int id
, void *data
, int *error
)
6295 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6297 return __sev_issue_cmd(sev
->fd
, id
, data
, error
);
6300 static int sev_launch_start(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6302 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6303 struct sev_data_launch_start
*start
;
6304 struct kvm_sev_launch_start params
;
6305 void *dh_blob
, *session_blob
;
6306 int *error
= &argp
->error
;
6309 if (!sev_guest(kvm
))
6312 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6315 start
= kzalloc(sizeof(*start
), GFP_KERNEL
);
6320 if (params
.dh_uaddr
) {
6321 dh_blob
= psp_copy_user_blob(params
.dh_uaddr
, params
.dh_len
);
6322 if (IS_ERR(dh_blob
)) {
6323 ret
= PTR_ERR(dh_blob
);
6327 start
->dh_cert_address
= __sme_set(__pa(dh_blob
));
6328 start
->dh_cert_len
= params
.dh_len
;
6331 session_blob
= NULL
;
6332 if (params
.session_uaddr
) {
6333 session_blob
= psp_copy_user_blob(params
.session_uaddr
, params
.session_len
);
6334 if (IS_ERR(session_blob
)) {
6335 ret
= PTR_ERR(session_blob
);
6339 start
->session_address
= __sme_set(__pa(session_blob
));
6340 start
->session_len
= params
.session_len
;
6343 start
->handle
= params
.handle
;
6344 start
->policy
= params
.policy
;
6346 /* create memory encryption context */
6347 ret
= __sev_issue_cmd(argp
->sev_fd
, SEV_CMD_LAUNCH_START
, start
, error
);
6349 goto e_free_session
;
6351 /* Bind ASID to this guest */
6352 ret
= sev_bind_asid(kvm
, start
->handle
, error
);
6354 goto e_free_session
;
6356 /* return handle to userspace */
6357 params
.handle
= start
->handle
;
6358 if (copy_to_user((void __user
*)(uintptr_t)argp
->data
, ¶ms
, sizeof(params
))) {
6359 sev_unbind_asid(kvm
, start
->handle
);
6361 goto e_free_session
;
6364 sev
->handle
= start
->handle
;
6365 sev
->fd
= argp
->sev_fd
;
6368 kfree(session_blob
);
6376 static int get_num_contig_pages(int idx
, struct page
**inpages
,
6377 unsigned long npages
)
6379 unsigned long paddr
, next_paddr
;
6380 int i
= idx
+ 1, pages
= 1;
6382 /* find the number of contiguous pages starting from idx */
6383 paddr
= __sme_page_pa(inpages
[idx
]);
6384 while (i
< npages
) {
6385 next_paddr
= __sme_page_pa(inpages
[i
++]);
6386 if ((paddr
+ PAGE_SIZE
) == next_paddr
) {
6397 static int sev_launch_update_data(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6399 unsigned long vaddr
, vaddr_end
, next_vaddr
, npages
, size
;
6400 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6401 struct kvm_sev_launch_update_data params
;
6402 struct sev_data_launch_update_data
*data
;
6403 struct page
**inpages
;
6406 if (!sev_guest(kvm
))
6409 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6412 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6416 vaddr
= params
.uaddr
;
6418 vaddr_end
= vaddr
+ size
;
6420 /* Lock the user memory. */
6421 inpages
= sev_pin_memory(kvm
, vaddr
, size
, &npages
, 1);
6428 * The LAUNCH_UPDATE command will perform in-place encryption of the
6429 * memory content (i.e it will write the same memory region with C=1).
6430 * It's possible that the cache may contain the data with C=0, i.e.,
6431 * unencrypted so invalidate it first.
6433 sev_clflush_pages(inpages
, npages
);
6435 for (i
= 0; vaddr
< vaddr_end
; vaddr
= next_vaddr
, i
+= pages
) {
6439 * If the user buffer is not page-aligned, calculate the offset
6442 offset
= vaddr
& (PAGE_SIZE
- 1);
6444 /* Calculate the number of pages that can be encrypted in one go. */
6445 pages
= get_num_contig_pages(i
, inpages
, npages
);
6447 len
= min_t(size_t, ((pages
* PAGE_SIZE
) - offset
), size
);
6449 data
->handle
= sev
->handle
;
6451 data
->address
= __sme_page_pa(inpages
[i
]) + offset
;
6452 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_UPDATE_DATA
, data
, &argp
->error
);
6457 next_vaddr
= vaddr
+ len
;
6461 /* content of memory is updated, mark pages dirty */
6462 for (i
= 0; i
< npages
; i
++) {
6463 set_page_dirty_lock(inpages
[i
]);
6464 mark_page_accessed(inpages
[i
]);
6466 /* unlock the user pages */
6467 sev_unpin_memory(kvm
, inpages
, npages
);
6473 static int sev_launch_measure(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6475 void __user
*measure
= (void __user
*)(uintptr_t)argp
->data
;
6476 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6477 struct sev_data_launch_measure
*data
;
6478 struct kvm_sev_launch_measure params
;
6479 void __user
*p
= NULL
;
6483 if (!sev_guest(kvm
))
6486 if (copy_from_user(¶ms
, measure
, sizeof(params
)))
6489 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6493 /* User wants to query the blob length */
6497 p
= (void __user
*)(uintptr_t)params
.uaddr
;
6499 if (params
.len
> SEV_FW_BLOB_MAX_SIZE
) {
6505 blob
= kmalloc(params
.len
, GFP_KERNEL
);
6509 data
->address
= __psp_pa(blob
);
6510 data
->len
= params
.len
;
6514 data
->handle
= sev
->handle
;
6515 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_MEASURE
, data
, &argp
->error
);
6518 * If we query the session length, FW responded with expected data.
6527 if (copy_to_user(p
, blob
, params
.len
))
6532 params
.len
= data
->len
;
6533 if (copy_to_user(measure
, ¶ms
, sizeof(params
)))
6542 static int sev_launch_finish(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6544 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6545 struct sev_data_launch_finish
*data
;
6548 if (!sev_guest(kvm
))
6551 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6555 data
->handle
= sev
->handle
;
6556 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_FINISH
, data
, &argp
->error
);
6562 static int sev_guest_status(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6564 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6565 struct kvm_sev_guest_status params
;
6566 struct sev_data_guest_status
*data
;
6569 if (!sev_guest(kvm
))
6572 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6576 data
->handle
= sev
->handle
;
6577 ret
= sev_issue_cmd(kvm
, SEV_CMD_GUEST_STATUS
, data
, &argp
->error
);
6581 params
.policy
= data
->policy
;
6582 params
.state
= data
->state
;
6583 params
.handle
= data
->handle
;
6585 if (copy_to_user((void __user
*)(uintptr_t)argp
->data
, ¶ms
, sizeof(params
)))
6592 static int __sev_issue_dbg_cmd(struct kvm
*kvm
, unsigned long src
,
6593 unsigned long dst
, int size
,
6594 int *error
, bool enc
)
6596 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6597 struct sev_data_dbg
*data
;
6600 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6604 data
->handle
= sev
->handle
;
6605 data
->dst_addr
= dst
;
6606 data
->src_addr
= src
;
6609 ret
= sev_issue_cmd(kvm
,
6610 enc
? SEV_CMD_DBG_ENCRYPT
: SEV_CMD_DBG_DECRYPT
,
6616 static int __sev_dbg_decrypt(struct kvm
*kvm
, unsigned long src_paddr
,
6617 unsigned long dst_paddr
, int sz
, int *err
)
6622 * Its safe to read more than we are asked, caller should ensure that
6623 * destination has enough space.
6625 src_paddr
= round_down(src_paddr
, 16);
6626 offset
= src_paddr
& 15;
6627 sz
= round_up(sz
+ offset
, 16);
6629 return __sev_issue_dbg_cmd(kvm
, src_paddr
, dst_paddr
, sz
, err
, false);
6632 static int __sev_dbg_decrypt_user(struct kvm
*kvm
, unsigned long paddr
,
6633 unsigned long __user dst_uaddr
,
6634 unsigned long dst_paddr
,
6637 struct page
*tpage
= NULL
;
6640 /* if inputs are not 16-byte then use intermediate buffer */
6641 if (!IS_ALIGNED(dst_paddr
, 16) ||
6642 !IS_ALIGNED(paddr
, 16) ||
6643 !IS_ALIGNED(size
, 16)) {
6644 tpage
= (void *)alloc_page(GFP_KERNEL
);
6648 dst_paddr
= __sme_page_pa(tpage
);
6651 ret
= __sev_dbg_decrypt(kvm
, paddr
, dst_paddr
, size
, err
);
6656 offset
= paddr
& 15;
6657 if (copy_to_user((void __user
*)(uintptr_t)dst_uaddr
,
6658 page_address(tpage
) + offset
, size
))
6669 static int __sev_dbg_encrypt_user(struct kvm
*kvm
, unsigned long paddr
,
6670 unsigned long __user vaddr
,
6671 unsigned long dst_paddr
,
6672 unsigned long __user dst_vaddr
,
6673 int size
, int *error
)
6675 struct page
*src_tpage
= NULL
;
6676 struct page
*dst_tpage
= NULL
;
6677 int ret
, len
= size
;
6679 /* If source buffer is not aligned then use an intermediate buffer */
6680 if (!IS_ALIGNED(vaddr
, 16)) {
6681 src_tpage
= alloc_page(GFP_KERNEL
);
6685 if (copy_from_user(page_address(src_tpage
),
6686 (void __user
*)(uintptr_t)vaddr
, size
)) {
6687 __free_page(src_tpage
);
6691 paddr
= __sme_page_pa(src_tpage
);
6695 * If destination buffer or length is not aligned then do read-modify-write:
6696 * - decrypt destination in an intermediate buffer
6697 * - copy the source buffer in an intermediate buffer
6698 * - use the intermediate buffer as source buffer
6700 if (!IS_ALIGNED(dst_vaddr
, 16) || !IS_ALIGNED(size
, 16)) {
6703 dst_tpage
= alloc_page(GFP_KERNEL
);
6709 ret
= __sev_dbg_decrypt(kvm
, dst_paddr
,
6710 __sme_page_pa(dst_tpage
), size
, error
);
6715 * If source is kernel buffer then use memcpy() otherwise
6718 dst_offset
= dst_paddr
& 15;
6721 memcpy(page_address(dst_tpage
) + dst_offset
,
6722 page_address(src_tpage
), size
);
6724 if (copy_from_user(page_address(dst_tpage
) + dst_offset
,
6725 (void __user
*)(uintptr_t)vaddr
, size
)) {
6731 paddr
= __sme_page_pa(dst_tpage
);
6732 dst_paddr
= round_down(dst_paddr
, 16);
6733 len
= round_up(size
, 16);
6736 ret
= __sev_issue_dbg_cmd(kvm
, paddr
, dst_paddr
, len
, error
, true);
6740 __free_page(src_tpage
);
6742 __free_page(dst_tpage
);
6746 static int sev_dbg_crypt(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
, bool dec
)
6748 unsigned long vaddr
, vaddr_end
, next_vaddr
;
6749 unsigned long dst_vaddr
;
6750 struct page
**src_p
, **dst_p
;
6751 struct kvm_sev_dbg debug
;
6755 if (!sev_guest(kvm
))
6758 if (copy_from_user(&debug
, (void __user
*)(uintptr_t)argp
->data
, sizeof(debug
)))
6761 vaddr
= debug
.src_uaddr
;
6763 vaddr_end
= vaddr
+ size
;
6764 dst_vaddr
= debug
.dst_uaddr
;
6766 for (; vaddr
< vaddr_end
; vaddr
= next_vaddr
) {
6767 int len
, s_off
, d_off
;
6769 /* lock userspace source and destination page */
6770 src_p
= sev_pin_memory(kvm
, vaddr
& PAGE_MASK
, PAGE_SIZE
, &n
, 0);
6774 dst_p
= sev_pin_memory(kvm
, dst_vaddr
& PAGE_MASK
, PAGE_SIZE
, &n
, 1);
6776 sev_unpin_memory(kvm
, src_p
, n
);
6781 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6782 * memory content (i.e it will write the same memory region with C=1).
6783 * It's possible that the cache may contain the data with C=0, i.e.,
6784 * unencrypted so invalidate it first.
6786 sev_clflush_pages(src_p
, 1);
6787 sev_clflush_pages(dst_p
, 1);
6790 * Since user buffer may not be page aligned, calculate the
6791 * offset within the page.
6793 s_off
= vaddr
& ~PAGE_MASK
;
6794 d_off
= dst_vaddr
& ~PAGE_MASK
;
6795 len
= min_t(size_t, (PAGE_SIZE
- s_off
), size
);
6798 ret
= __sev_dbg_decrypt_user(kvm
,
6799 __sme_page_pa(src_p
[0]) + s_off
,
6801 __sme_page_pa(dst_p
[0]) + d_off
,
6804 ret
= __sev_dbg_encrypt_user(kvm
,
6805 __sme_page_pa(src_p
[0]) + s_off
,
6807 __sme_page_pa(dst_p
[0]) + d_off
,
6811 sev_unpin_memory(kvm
, src_p
, 1);
6812 sev_unpin_memory(kvm
, dst_p
, 1);
6817 next_vaddr
= vaddr
+ len
;
6818 dst_vaddr
= dst_vaddr
+ len
;
6825 static int sev_launch_secret(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6827 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6828 struct sev_data_launch_secret
*data
;
6829 struct kvm_sev_launch_secret params
;
6830 struct page
**pages
;
6835 if (!sev_guest(kvm
))
6838 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6841 pages
= sev_pin_memory(kvm
, params
.guest_uaddr
, params
.guest_len
, &n
, 1);
6846 * The secret must be copied into contiguous memory region, lets verify
6847 * that userspace memory pages are contiguous before we issue command.
6849 if (get_num_contig_pages(0, pages
, n
) != n
) {
6851 goto e_unpin_memory
;
6855 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6857 goto e_unpin_memory
;
6859 offset
= params
.guest_uaddr
& (PAGE_SIZE
- 1);
6860 data
->guest_address
= __sme_page_pa(pages
[0]) + offset
;
6861 data
->guest_len
= params
.guest_len
;
6863 blob
= psp_copy_user_blob(params
.trans_uaddr
, params
.trans_len
);
6865 ret
= PTR_ERR(blob
);
6869 data
->trans_address
= __psp_pa(blob
);
6870 data
->trans_len
= params
.trans_len
;
6872 hdr
= psp_copy_user_blob(params
.hdr_uaddr
, params
.hdr_len
);
6877 data
->hdr_address
= __psp_pa(hdr
);
6878 data
->hdr_len
= params
.hdr_len
;
6880 data
->handle
= sev
->handle
;
6881 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_UPDATE_SECRET
, data
, &argp
->error
);
6890 sev_unpin_memory(kvm
, pages
, n
);
6894 static int svm_mem_enc_op(struct kvm
*kvm
, void __user
*argp
)
6896 struct kvm_sev_cmd sev_cmd
;
6899 if (!svm_sev_enabled())
6902 if (copy_from_user(&sev_cmd
, argp
, sizeof(struct kvm_sev_cmd
)))
6905 mutex_lock(&kvm
->lock
);
6907 switch (sev_cmd
.id
) {
6909 r
= sev_guest_init(kvm
, &sev_cmd
);
6911 case KVM_SEV_LAUNCH_START
:
6912 r
= sev_launch_start(kvm
, &sev_cmd
);
6914 case KVM_SEV_LAUNCH_UPDATE_DATA
:
6915 r
= sev_launch_update_data(kvm
, &sev_cmd
);
6917 case KVM_SEV_LAUNCH_MEASURE
:
6918 r
= sev_launch_measure(kvm
, &sev_cmd
);
6920 case KVM_SEV_LAUNCH_FINISH
:
6921 r
= sev_launch_finish(kvm
, &sev_cmd
);
6923 case KVM_SEV_GUEST_STATUS
:
6924 r
= sev_guest_status(kvm
, &sev_cmd
);
6926 case KVM_SEV_DBG_DECRYPT
:
6927 r
= sev_dbg_crypt(kvm
, &sev_cmd
, true);
6929 case KVM_SEV_DBG_ENCRYPT
:
6930 r
= sev_dbg_crypt(kvm
, &sev_cmd
, false);
6932 case KVM_SEV_LAUNCH_SECRET
:
6933 r
= sev_launch_secret(kvm
, &sev_cmd
);
6940 if (copy_to_user(argp
, &sev_cmd
, sizeof(struct kvm_sev_cmd
)))
6944 mutex_unlock(&kvm
->lock
);
6948 static int svm_register_enc_region(struct kvm
*kvm
,
6949 struct kvm_enc_region
*range
)
6951 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6952 struct enc_region
*region
;
6955 if (!sev_guest(kvm
))
6958 if (range
->addr
> ULONG_MAX
|| range
->size
> ULONG_MAX
)
6961 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
6965 region
->pages
= sev_pin_memory(kvm
, range
->addr
, range
->size
, ®ion
->npages
, 1);
6966 if (!region
->pages
) {
6972 * The guest may change the memory encryption attribute from C=0 -> C=1
6973 * or vice versa for this memory range. Lets make sure caches are
6974 * flushed to ensure that guest data gets written into memory with
6977 sev_clflush_pages(region
->pages
, region
->npages
);
6979 region
->uaddr
= range
->addr
;
6980 region
->size
= range
->size
;
6982 mutex_lock(&kvm
->lock
);
6983 list_add_tail(®ion
->list
, &sev
->regions_list
);
6984 mutex_unlock(&kvm
->lock
);
6993 static struct enc_region
*
6994 find_enc_region(struct kvm
*kvm
, struct kvm_enc_region
*range
)
6996 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6997 struct list_head
*head
= &sev
->regions_list
;
6998 struct enc_region
*i
;
7000 list_for_each_entry(i
, head
, list
) {
7001 if (i
->uaddr
== range
->addr
&&
7002 i
->size
== range
->size
)
7010 static int svm_unregister_enc_region(struct kvm
*kvm
,
7011 struct kvm_enc_region
*range
)
7013 struct enc_region
*region
;
7016 mutex_lock(&kvm
->lock
);
7018 if (!sev_guest(kvm
)) {
7023 region
= find_enc_region(kvm
, range
);
7029 __unregister_enc_region_locked(kvm
, region
);
7031 mutex_unlock(&kvm
->lock
);
7035 mutex_unlock(&kvm
->lock
);
7039 static struct kvm_x86_ops svm_x86_ops __ro_after_init
= {
7040 .cpu_has_kvm_support
= has_svm
,
7041 .disabled_by_bios
= is_disabled
,
7042 .hardware_setup
= svm_hardware_setup
,
7043 .hardware_unsetup
= svm_hardware_unsetup
,
7044 .check_processor_compatibility
= svm_check_processor_compat
,
7045 .hardware_enable
= svm_hardware_enable
,
7046 .hardware_disable
= svm_hardware_disable
,
7047 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
7048 .has_emulated_msr
= svm_has_emulated_msr
,
7050 .vcpu_create
= svm_create_vcpu
,
7051 .vcpu_free
= svm_free_vcpu
,
7052 .vcpu_reset
= svm_vcpu_reset
,
7054 .vm_alloc
= svm_vm_alloc
,
7055 .vm_free
= svm_vm_free
,
7056 .vm_init
= avic_vm_init
,
7057 .vm_destroy
= svm_vm_destroy
,
7059 .prepare_guest_switch
= svm_prepare_guest_switch
,
7060 .vcpu_load
= svm_vcpu_load
,
7061 .vcpu_put
= svm_vcpu_put
,
7062 .vcpu_blocking
= svm_vcpu_blocking
,
7063 .vcpu_unblocking
= svm_vcpu_unblocking
,
7065 .update_bp_intercept
= update_bp_intercept
,
7066 .get_msr_feature
= svm_get_msr_feature
,
7067 .get_msr
= svm_get_msr
,
7068 .set_msr
= svm_set_msr
,
7069 .get_segment_base
= svm_get_segment_base
,
7070 .get_segment
= svm_get_segment
,
7071 .set_segment
= svm_set_segment
,
7072 .get_cpl
= svm_get_cpl
,
7073 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
7074 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
7075 .decache_cr3
= svm_decache_cr3
,
7076 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
7077 .set_cr0
= svm_set_cr0
,
7078 .set_cr3
= svm_set_cr3
,
7079 .set_cr4
= svm_set_cr4
,
7080 .set_efer
= svm_set_efer
,
7081 .get_idt
= svm_get_idt
,
7082 .set_idt
= svm_set_idt
,
7083 .get_gdt
= svm_get_gdt
,
7084 .set_gdt
= svm_set_gdt
,
7085 .get_dr6
= svm_get_dr6
,
7086 .set_dr6
= svm_set_dr6
,
7087 .set_dr7
= svm_set_dr7
,
7088 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
7089 .cache_reg
= svm_cache_reg
,
7090 .get_rflags
= svm_get_rflags
,
7091 .set_rflags
= svm_set_rflags
,
7093 .tlb_flush
= svm_flush_tlb
,
7094 .tlb_flush_gva
= svm_flush_tlb_gva
,
7096 .run
= svm_vcpu_run
,
7097 .handle_exit
= handle_exit
,
7098 .skip_emulated_instruction
= skip_emulated_instruction
,
7099 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
7100 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
7101 .patch_hypercall
= svm_patch_hypercall
,
7102 .set_irq
= svm_set_irq
,
7103 .set_nmi
= svm_inject_nmi
,
7104 .queue_exception
= svm_queue_exception
,
7105 .cancel_injection
= svm_cancel_injection
,
7106 .interrupt_allowed
= svm_interrupt_allowed
,
7107 .nmi_allowed
= svm_nmi_allowed
,
7108 .get_nmi_mask
= svm_get_nmi_mask
,
7109 .set_nmi_mask
= svm_set_nmi_mask
,
7110 .enable_nmi_window
= enable_nmi_window
,
7111 .enable_irq_window
= enable_irq_window
,
7112 .update_cr8_intercept
= update_cr8_intercept
,
7113 .set_virtual_apic_mode
= svm_set_virtual_apic_mode
,
7114 .get_enable_apicv
= svm_get_enable_apicv
,
7115 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
7116 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
7117 .hwapic_irr_update
= svm_hwapic_irr_update
,
7118 .hwapic_isr_update
= svm_hwapic_isr_update
,
7119 .sync_pir_to_irr
= kvm_lapic_find_highest_irr
,
7120 .apicv_post_state_restore
= avic_post_state_restore
,
7122 .set_tss_addr
= svm_set_tss_addr
,
7123 .set_identity_map_addr
= svm_set_identity_map_addr
,
7124 .get_tdp_level
= get_npt_level
,
7125 .get_mt_mask
= svm_get_mt_mask
,
7127 .get_exit_info
= svm_get_exit_info
,
7129 .get_lpage_level
= svm_get_lpage_level
,
7131 .cpuid_update
= svm_cpuid_update
,
7133 .rdtscp_supported
= svm_rdtscp_supported
,
7134 .invpcid_supported
= svm_invpcid_supported
,
7135 .mpx_supported
= svm_mpx_supported
,
7136 .xsaves_supported
= svm_xsaves_supported
,
7137 .umip_emulated
= svm_umip_emulated
,
7139 .set_supported_cpuid
= svm_set_supported_cpuid
,
7141 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
7143 .read_l1_tsc_offset
= svm_read_l1_tsc_offset
,
7144 .write_tsc_offset
= svm_write_tsc_offset
,
7146 .set_tdp_cr3
= set_tdp_cr3
,
7148 .check_intercept
= svm_check_intercept
,
7149 .handle_external_intr
= svm_handle_external_intr
,
7151 .request_immediate_exit
= __kvm_request_immediate_exit
,
7153 .sched_in
= svm_sched_in
,
7155 .pmu_ops
= &amd_pmu_ops
,
7156 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
7157 .update_pi_irte
= svm_update_pi_irte
,
7158 .setup_mce
= svm_setup_mce
,
7160 .smi_allowed
= svm_smi_allowed
,
7161 .pre_enter_smm
= svm_pre_enter_smm
,
7162 .pre_leave_smm
= svm_pre_leave_smm
,
7163 .enable_smi_window
= enable_smi_window
,
7165 .mem_enc_op
= svm_mem_enc_op
,
7166 .mem_enc_reg_region
= svm_register_enc_region
,
7167 .mem_enc_unreg_region
= svm_unregister_enc_region
,
7170 static int __init
svm_init(void)
7172 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
7173 __alignof__(struct vcpu_svm
), THIS_MODULE
);
7176 static void __exit
svm_exit(void)
7181 module_init(svm_init
)
7182 module_exit(svm_exit
)