2 * Driver core for Samsung SoC onboard UARTs.
4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 /* Hote on 2410 error handling
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
27 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/delay.h>
43 #include <linux/clk.h>
44 #include <linux/cpufreq.h>
49 #include <mach/hardware.h>
52 #include <plat/regs-serial.h>
53 #include <plat/clock.h>
57 /* UART name and device definitions */
59 #define S3C24XX_SERIAL_NAME "ttySAC"
60 #define S3C24XX_SERIAL_MAJOR 204
61 #define S3C24XX_SERIAL_MINOR 64
63 /* macros to change one thing to another */
65 #define tx_enabled(port) ((port)->unused[0])
66 #define rx_enabled(port) ((port)->unused[1])
68 /* flag to ignore all characters coming in */
69 #define RXSTAT_DUMMY_READ (0x10000000)
71 static inline struct s3c24xx_uart_port
*to_ourport(struct uart_port
*port
)
73 return container_of(port
, struct s3c24xx_uart_port
, port
);
76 /* translate a port to the device name */
78 static inline const char *s3c24xx_serial_portname(struct uart_port
*port
)
80 return to_platform_device(port
->dev
)->name
;
83 static int s3c24xx_serial_txempty_nofifo(struct uart_port
*port
)
85 return rd_regl(port
, S3C2410_UTRSTAT
) & S3C2410_UTRSTAT_TXE
;
89 * s3c64xx and later SoC's include the interrupt mask and status registers in
90 * the controller itself, unlike the s3c24xx SoC's which have these registers
91 * in the interrupt controller. Check if the port type is s3c64xx or higher.
93 static int s3c24xx_serial_has_interrupt_mask(struct uart_port
*port
)
95 return to_ourport(port
)->info
->type
== PORT_S3C6400
;
98 static void s3c24xx_serial_rx_enable(struct uart_port
*port
)
101 unsigned int ucon
, ufcon
;
104 spin_lock_irqsave(&port
->lock
, flags
);
106 while (--count
&& !s3c24xx_serial_txempty_nofifo(port
))
109 ufcon
= rd_regl(port
, S3C2410_UFCON
);
110 ufcon
|= S3C2410_UFCON_RESETRX
;
111 wr_regl(port
, S3C2410_UFCON
, ufcon
);
113 ucon
= rd_regl(port
, S3C2410_UCON
);
114 ucon
|= S3C2410_UCON_RXIRQMODE
;
115 wr_regl(port
, S3C2410_UCON
, ucon
);
117 rx_enabled(port
) = 1;
118 spin_unlock_irqrestore(&port
->lock
, flags
);
121 static void s3c24xx_serial_rx_disable(struct uart_port
*port
)
126 spin_lock_irqsave(&port
->lock
, flags
);
128 ucon
= rd_regl(port
, S3C2410_UCON
);
129 ucon
&= ~S3C2410_UCON_RXIRQMODE
;
130 wr_regl(port
, S3C2410_UCON
, ucon
);
132 rx_enabled(port
) = 0;
133 spin_unlock_irqrestore(&port
->lock
, flags
);
136 static void s3c24xx_serial_stop_tx(struct uart_port
*port
)
138 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
140 if (tx_enabled(port
)) {
141 if (s3c24xx_serial_has_interrupt_mask(port
))
142 __set_bit(S3C64XX_UINTM_TXD
,
143 portaddrl(port
, S3C64XX_UINTM
));
145 disable_irq_nosync(ourport
->tx_irq
);
146 tx_enabled(port
) = 0;
147 if (port
->flags
& UPF_CONS_FLOW
)
148 s3c24xx_serial_rx_enable(port
);
152 static void s3c24xx_serial_start_tx(struct uart_port
*port
)
154 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
156 if (!tx_enabled(port
)) {
157 if (port
->flags
& UPF_CONS_FLOW
)
158 s3c24xx_serial_rx_disable(port
);
160 if (s3c24xx_serial_has_interrupt_mask(port
))
161 __clear_bit(S3C64XX_UINTM_TXD
,
162 portaddrl(port
, S3C64XX_UINTM
));
164 enable_irq(ourport
->tx_irq
);
165 tx_enabled(port
) = 1;
169 static void s3c24xx_serial_stop_rx(struct uart_port
*port
)
171 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
173 if (rx_enabled(port
)) {
174 dbg("s3c24xx_serial_stop_rx: port=%p\n", port
);
175 if (s3c24xx_serial_has_interrupt_mask(port
))
176 __set_bit(S3C64XX_UINTM_RXD
,
177 portaddrl(port
, S3C64XX_UINTM
));
179 disable_irq_nosync(ourport
->rx_irq
);
180 rx_enabled(port
) = 0;
184 static void s3c24xx_serial_enable_ms(struct uart_port
*port
)
188 static inline struct s3c24xx_uart_info
*s3c24xx_port_to_info(struct uart_port
*port
)
190 return to_ourport(port
)->info
;
193 static inline struct s3c2410_uartcfg
*s3c24xx_port_to_cfg(struct uart_port
*port
)
195 struct s3c24xx_uart_port
*ourport
;
197 if (port
->dev
== NULL
)
200 ourport
= container_of(port
, struct s3c24xx_uart_port
, port
);
204 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port
*ourport
,
205 unsigned long ufstat
)
207 struct s3c24xx_uart_info
*info
= ourport
->info
;
209 if (ufstat
& info
->rx_fifofull
)
210 return ourport
->port
.fifosize
;
212 return (ufstat
& info
->rx_fifomask
) >> info
->rx_fifoshift
;
216 /* ? - where has parity gone?? */
217 #define S3C2410_UERSTAT_PARITY (0x1000)
220 s3c24xx_serial_rx_chars(int irq
, void *dev_id
)
222 struct s3c24xx_uart_port
*ourport
= dev_id
;
223 struct uart_port
*port
= &ourport
->port
;
224 struct tty_struct
*tty
= port
->state
->port
.tty
;
225 unsigned int ufcon
, ch
, flag
, ufstat
, uerstat
;
229 spin_lock_irqsave(&port
->lock
, flags
);
231 while (max_count
-- > 0) {
232 ufcon
= rd_regl(port
, S3C2410_UFCON
);
233 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
235 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
238 uerstat
= rd_regl(port
, S3C2410_UERSTAT
);
239 ch
= rd_regb(port
, S3C2410_URXH
);
241 if (port
->flags
& UPF_CONS_FLOW
) {
242 int txe
= s3c24xx_serial_txempty_nofifo(port
);
244 if (rx_enabled(port
)) {
246 rx_enabled(port
) = 0;
251 ufcon
|= S3C2410_UFCON_RESETRX
;
252 wr_regl(port
, S3C2410_UFCON
, ufcon
);
253 rx_enabled(port
) = 1;
260 /* insert the character into the buffer */
265 if (unlikely(uerstat
& S3C2410_UERSTAT_ANY
)) {
266 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
269 /* check for break */
270 if (uerstat
& S3C2410_UERSTAT_BREAK
) {
273 if (uart_handle_break(port
))
277 if (uerstat
& S3C2410_UERSTAT_FRAME
)
278 port
->icount
.frame
++;
279 if (uerstat
& S3C2410_UERSTAT_OVERRUN
)
280 port
->icount
.overrun
++;
282 uerstat
&= port
->read_status_mask
;
284 if (uerstat
& S3C2410_UERSTAT_BREAK
)
286 else if (uerstat
& S3C2410_UERSTAT_PARITY
)
288 else if (uerstat
& (S3C2410_UERSTAT_FRAME
|
289 S3C2410_UERSTAT_OVERRUN
))
293 if (uart_handle_sysrq_char(port
, ch
))
296 uart_insert_char(port
, uerstat
, S3C2410_UERSTAT_OVERRUN
,
302 tty_flip_buffer_push(tty
);
305 spin_unlock_irqrestore(&port
->lock
, flags
);
309 static irqreturn_t
s3c24xx_serial_tx_chars(int irq
, void *id
)
311 struct s3c24xx_uart_port
*ourport
= id
;
312 struct uart_port
*port
= &ourport
->port
;
313 struct circ_buf
*xmit
= &port
->state
->xmit
;
317 spin_lock_irqsave(&port
->lock
, flags
);
320 wr_regb(port
, S3C2410_UTXH
, port
->x_char
);
326 /* if there isn't anything more to transmit, or the uart is now
327 * stopped, disable the uart and exit
330 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
)) {
331 s3c24xx_serial_stop_tx(port
);
335 /* try and drain the buffer... */
337 while (!uart_circ_empty(xmit
) && count
-- > 0) {
338 if (rd_regl(port
, S3C2410_UFSTAT
) & ourport
->info
->tx_fifofull
)
341 wr_regb(port
, S3C2410_UTXH
, xmit
->buf
[xmit
->tail
]);
342 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
346 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
) {
347 spin_unlock(&port
->lock
);
348 uart_write_wakeup(port
);
349 spin_lock(&port
->lock
);
352 if (uart_circ_empty(xmit
))
353 s3c24xx_serial_stop_tx(port
);
356 spin_unlock_irqrestore(&port
->lock
, flags
);
360 /* interrupt handler for s3c64xx and later SoC's.*/
361 static irqreturn_t
s3c64xx_serial_handle_irq(int irq
, void *id
)
363 struct s3c24xx_uart_port
*ourport
= id
;
364 struct uart_port
*port
= &ourport
->port
;
365 unsigned int pend
= rd_regl(port
, S3C64XX_UINTP
);
366 irqreturn_t ret
= IRQ_HANDLED
;
368 if (pend
& S3C64XX_UINTM_RXD_MSK
) {
369 ret
= s3c24xx_serial_rx_chars(irq
, id
);
370 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_RXD_MSK
);
372 if (pend
& S3C64XX_UINTM_TXD_MSK
) {
373 ret
= s3c24xx_serial_tx_chars(irq
, id
);
374 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_TXD_MSK
);
379 static unsigned int s3c24xx_serial_tx_empty(struct uart_port
*port
)
381 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
382 unsigned long ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
383 unsigned long ufcon
= rd_regl(port
, S3C2410_UFCON
);
385 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
386 if ((ufstat
& info
->tx_fifomask
) != 0 ||
387 (ufstat
& info
->tx_fifofull
))
393 return s3c24xx_serial_txempty_nofifo(port
);
396 /* no modem control lines */
397 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port
*port
)
399 unsigned int umstat
= rd_regb(port
, S3C2410_UMSTAT
);
401 if (umstat
& S3C2410_UMSTAT_CTS
)
402 return TIOCM_CAR
| TIOCM_DSR
| TIOCM_CTS
;
404 return TIOCM_CAR
| TIOCM_DSR
;
407 static void s3c24xx_serial_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
409 /* todo - possibly remove AFC and do manual CTS */
412 static void s3c24xx_serial_break_ctl(struct uart_port
*port
, int break_state
)
417 spin_lock_irqsave(&port
->lock
, flags
);
419 ucon
= rd_regl(port
, S3C2410_UCON
);
422 ucon
|= S3C2410_UCON_SBREAK
;
424 ucon
&= ~S3C2410_UCON_SBREAK
;
426 wr_regl(port
, S3C2410_UCON
, ucon
);
428 spin_unlock_irqrestore(&port
->lock
, flags
);
431 static void s3c24xx_serial_shutdown(struct uart_port
*port
)
433 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
435 if (ourport
->tx_claimed
) {
436 if (!s3c24xx_serial_has_interrupt_mask(port
))
437 free_irq(ourport
->tx_irq
, ourport
);
438 tx_enabled(port
) = 0;
439 ourport
->tx_claimed
= 0;
442 if (ourport
->rx_claimed
) {
443 if (!s3c24xx_serial_has_interrupt_mask(port
))
444 free_irq(ourport
->rx_irq
, ourport
);
445 ourport
->rx_claimed
= 0;
446 rx_enabled(port
) = 0;
449 /* Clear pending interrupts and mask all interrupts */
450 if (s3c24xx_serial_has_interrupt_mask(port
)) {
451 wr_regl(port
, S3C64XX_UINTP
, 0xf);
452 wr_regl(port
, S3C64XX_UINTM
, 0xf);
456 static int s3c24xx_serial_startup(struct uart_port
*port
)
458 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
461 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
462 port
->mapbase
, port
->membase
);
464 rx_enabled(port
) = 1;
466 ret
= request_irq(ourport
->rx_irq
, s3c24xx_serial_rx_chars
, 0,
467 s3c24xx_serial_portname(port
), ourport
);
470 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->rx_irq
);
474 ourport
->rx_claimed
= 1;
476 dbg("requesting tx irq...\n");
478 tx_enabled(port
) = 1;
480 ret
= request_irq(ourport
->tx_irq
, s3c24xx_serial_tx_chars
, 0,
481 s3c24xx_serial_portname(port
), ourport
);
484 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->tx_irq
);
488 ourport
->tx_claimed
= 1;
490 dbg("s3c24xx_serial_startup ok\n");
492 /* the port reset code should have done the correct
493 * register setup for the port controls */
498 s3c24xx_serial_shutdown(port
);
502 static int s3c64xx_serial_startup(struct uart_port
*port
)
504 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
507 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
508 port
->mapbase
, port
->membase
);
510 ret
= request_irq(port
->irq
, s3c64xx_serial_handle_irq
, IRQF_SHARED
,
511 s3c24xx_serial_portname(port
), ourport
);
513 dev_err(port
->dev
, "cannot get irq %d\n", port
->irq
);
517 /* For compatibility with s3c24xx Soc's */
518 rx_enabled(port
) = 1;
519 ourport
->rx_claimed
= 1;
520 tx_enabled(port
) = 0;
521 ourport
->tx_claimed
= 1;
523 /* Enable Rx Interrupt */
524 __clear_bit(S3C64XX_UINTM_RXD
, portaddrl(port
, S3C64XX_UINTM
));
525 dbg("s3c64xx_serial_startup ok\n");
529 /* power power management control */
531 static void s3c24xx_serial_pm(struct uart_port
*port
, unsigned int level
,
534 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
536 ourport
->pm_level
= level
;
540 if (!IS_ERR(ourport
->baudclk
))
541 clk_disable_unprepare(ourport
->baudclk
);
543 clk_disable_unprepare(ourport
->clk
);
547 clk_prepare_enable(ourport
->clk
);
549 if (!IS_ERR(ourport
->baudclk
))
550 clk_prepare_enable(ourport
->baudclk
);
554 dev_err(port
->dev
, "s3c24xx_serial: unknown pm %d\n", level
);
558 /* baud rate calculation
560 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
561 * of different sources, including the peripheral clock ("pclk") and an
562 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
563 * with a programmable extra divisor.
565 * The following code goes through the clock sources, and calculates the
566 * baud clocks (and the resultant actual baud rates) and then tries to
567 * pick the closest one and select that.
571 #define MAX_CLK_NAME_LENGTH 15
573 static inline int s3c24xx_serial_getsource(struct uart_port
*port
)
575 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
578 if (info
->num_clks
== 1)
581 ucon
= rd_regl(port
, S3C2410_UCON
);
582 ucon
&= info
->clksel_mask
;
583 return ucon
>> info
->clksel_shift
;
586 static void s3c24xx_serial_setsource(struct uart_port
*port
,
587 unsigned int clk_sel
)
589 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
592 if (info
->num_clks
== 1)
595 ucon
= rd_regl(port
, S3C2410_UCON
);
596 if ((ucon
& info
->clksel_mask
) >> info
->clksel_shift
== clk_sel
)
599 ucon
&= ~info
->clksel_mask
;
600 ucon
|= clk_sel
<< info
->clksel_shift
;
601 wr_regl(port
, S3C2410_UCON
, ucon
);
604 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port
*ourport
,
605 unsigned int req_baud
, struct clk
**best_clk
,
606 unsigned int *clk_num
)
608 struct s3c24xx_uart_info
*info
= ourport
->info
;
611 unsigned int cnt
, baud
, quot
, clk_sel
, best_quot
= 0;
612 char clkname
[MAX_CLK_NAME_LENGTH
];
613 int calc_deviation
, deviation
= (1 << 30) - 1;
615 clk_sel
= (ourport
->cfg
->clk_sel
) ? ourport
->cfg
->clk_sel
:
616 ourport
->info
->def_clk_sel
;
617 for (cnt
= 0; cnt
< info
->num_clks
; cnt
++) {
618 if (!(clk_sel
& (1 << cnt
)))
621 sprintf(clkname
, "clk_uart_baud%d", cnt
);
622 clk
= clk_get(ourport
->port
.dev
, clkname
);
626 rate
= clk_get_rate(clk
);
630 if (ourport
->info
->has_divslot
) {
631 unsigned long div
= rate
/ req_baud
;
633 /* The UDIVSLOT register on the newer UARTs allows us to
634 * get a divisor adjustment of 1/16th on the baud clock.
636 * We don't keep the UDIVSLOT value (the 16ths we
637 * calculated by not multiplying the baud by 16) as it
638 * is easy enough to recalculate.
644 quot
= (rate
+ (8 * req_baud
)) / (16 * req_baud
);
645 baud
= rate
/ (quot
* 16);
649 calc_deviation
= req_baud
- baud
;
650 if (calc_deviation
< 0)
651 calc_deviation
= -calc_deviation
;
653 if (calc_deviation
< deviation
) {
657 deviation
= calc_deviation
;
666 * This table takes the fractional value of the baud divisor and gives
667 * the recommended setting for the UDIVSLOT register.
669 static u16 udivslot_table
[16] = {
688 static void s3c24xx_serial_set_termios(struct uart_port
*port
,
689 struct ktermios
*termios
,
690 struct ktermios
*old
)
692 struct s3c2410_uartcfg
*cfg
= s3c24xx_port_to_cfg(port
);
693 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
694 struct clk
*clk
= ERR_PTR(-EINVAL
);
696 unsigned int baud
, quot
, clk_sel
= 0;
699 unsigned int udivslot
= 0;
702 * We don't support modem control lines.
704 termios
->c_cflag
&= ~(HUPCL
| CMSPAR
);
705 termios
->c_cflag
|= CLOCAL
;
708 * Ask the core to calculate the divisor for us.
711 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 115200*8);
712 quot
= s3c24xx_serial_getclk(ourport
, baud
, &clk
, &clk_sel
);
713 if (baud
== 38400 && (port
->flags
& UPF_SPD_MASK
) == UPF_SPD_CUST
)
714 quot
= port
->custom_divisor
;
718 /* check to see if we need to change clock source */
720 if (ourport
->baudclk
!= clk
) {
721 s3c24xx_serial_setsource(port
, clk_sel
);
723 if (!IS_ERR(ourport
->baudclk
)) {
724 clk_disable_unprepare(ourport
->baudclk
);
725 ourport
->baudclk
= ERR_PTR(-EINVAL
);
728 clk_prepare_enable(clk
);
730 ourport
->baudclk
= clk
;
731 ourport
->baudclk_rate
= clk
? clk_get_rate(clk
) : 0;
734 if (ourport
->info
->has_divslot
) {
735 unsigned int div
= ourport
->baudclk_rate
/ baud
;
737 if (cfg
->has_fracval
) {
738 udivslot
= (div
& 15);
739 dbg("fracval = %04x\n", udivslot
);
741 udivslot
= udivslot_table
[div
& 15];
742 dbg("udivslot = %04x (div %d)\n", udivslot
, div
& 15);
746 switch (termios
->c_cflag
& CSIZE
) {
748 dbg("config: 5bits/char\n");
749 ulcon
= S3C2410_LCON_CS5
;
752 dbg("config: 6bits/char\n");
753 ulcon
= S3C2410_LCON_CS6
;
756 dbg("config: 7bits/char\n");
757 ulcon
= S3C2410_LCON_CS7
;
761 dbg("config: 8bits/char\n");
762 ulcon
= S3C2410_LCON_CS8
;
766 /* preserve original lcon IR settings */
767 ulcon
|= (cfg
->ulcon
& S3C2410_LCON_IRM
);
769 if (termios
->c_cflag
& CSTOPB
)
770 ulcon
|= S3C2410_LCON_STOPB
;
772 umcon
= (termios
->c_cflag
& CRTSCTS
) ? S3C2410_UMCOM_AFC
: 0;
774 if (termios
->c_cflag
& PARENB
) {
775 if (termios
->c_cflag
& PARODD
)
776 ulcon
|= S3C2410_LCON_PODD
;
778 ulcon
|= S3C2410_LCON_PEVEN
;
780 ulcon
|= S3C2410_LCON_PNONE
;
783 spin_lock_irqsave(&port
->lock
, flags
);
785 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
786 ulcon
, quot
, udivslot
);
788 wr_regl(port
, S3C2410_ULCON
, ulcon
);
789 wr_regl(port
, S3C2410_UBRDIV
, quot
);
790 wr_regl(port
, S3C2410_UMCON
, umcon
);
792 if (ourport
->info
->has_divslot
)
793 wr_regl(port
, S3C2443_DIVSLOT
, udivslot
);
795 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
796 rd_regl(port
, S3C2410_ULCON
),
797 rd_regl(port
, S3C2410_UCON
),
798 rd_regl(port
, S3C2410_UFCON
));
801 * Update the per-port timeout.
803 uart_update_timeout(port
, termios
->c_cflag
, baud
);
806 * Which character status flags are we interested in?
808 port
->read_status_mask
= S3C2410_UERSTAT_OVERRUN
;
809 if (termios
->c_iflag
& INPCK
)
810 port
->read_status_mask
|= S3C2410_UERSTAT_FRAME
| S3C2410_UERSTAT_PARITY
;
813 * Which character status flags should we ignore?
815 port
->ignore_status_mask
= 0;
816 if (termios
->c_iflag
& IGNPAR
)
817 port
->ignore_status_mask
|= S3C2410_UERSTAT_OVERRUN
;
818 if (termios
->c_iflag
& IGNBRK
&& termios
->c_iflag
& IGNPAR
)
819 port
->ignore_status_mask
|= S3C2410_UERSTAT_FRAME
;
822 * Ignore all characters if CREAD is not set.
824 if ((termios
->c_cflag
& CREAD
) == 0)
825 port
->ignore_status_mask
|= RXSTAT_DUMMY_READ
;
827 spin_unlock_irqrestore(&port
->lock
, flags
);
830 static const char *s3c24xx_serial_type(struct uart_port
*port
)
832 switch (port
->type
) {
846 #define MAP_SIZE (0x100)
848 static void s3c24xx_serial_release_port(struct uart_port
*port
)
850 release_mem_region(port
->mapbase
, MAP_SIZE
);
853 static int s3c24xx_serial_request_port(struct uart_port
*port
)
855 const char *name
= s3c24xx_serial_portname(port
);
856 return request_mem_region(port
->mapbase
, MAP_SIZE
, name
) ? 0 : -EBUSY
;
859 static void s3c24xx_serial_config_port(struct uart_port
*port
, int flags
)
861 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
863 if (flags
& UART_CONFIG_TYPE
&&
864 s3c24xx_serial_request_port(port
) == 0)
865 port
->type
= info
->type
;
869 * verify the new serial_struct (for TIOCSSERIAL).
872 s3c24xx_serial_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
874 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
876 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= info
->type
)
883 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
885 static struct console s3c24xx_serial_console
;
887 static int __init
s3c24xx_serial_console_init(void)
889 register_console(&s3c24xx_serial_console
);
892 console_initcall(s3c24xx_serial_console_init
);
894 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
896 #define S3C24XX_SERIAL_CONSOLE NULL
899 #ifdef CONFIG_CONSOLE_POLL
900 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
);
901 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
905 static struct uart_ops s3c24xx_serial_ops
= {
906 .pm
= s3c24xx_serial_pm
,
907 .tx_empty
= s3c24xx_serial_tx_empty
,
908 .get_mctrl
= s3c24xx_serial_get_mctrl
,
909 .set_mctrl
= s3c24xx_serial_set_mctrl
,
910 .stop_tx
= s3c24xx_serial_stop_tx
,
911 .start_tx
= s3c24xx_serial_start_tx
,
912 .stop_rx
= s3c24xx_serial_stop_rx
,
913 .enable_ms
= s3c24xx_serial_enable_ms
,
914 .break_ctl
= s3c24xx_serial_break_ctl
,
915 .startup
= s3c24xx_serial_startup
,
916 .shutdown
= s3c24xx_serial_shutdown
,
917 .set_termios
= s3c24xx_serial_set_termios
,
918 .type
= s3c24xx_serial_type
,
919 .release_port
= s3c24xx_serial_release_port
,
920 .request_port
= s3c24xx_serial_request_port
,
921 .config_port
= s3c24xx_serial_config_port
,
922 .verify_port
= s3c24xx_serial_verify_port
,
923 #ifdef CONFIG_CONSOLE_POLL
924 .poll_get_char
= s3c24xx_serial_get_poll_char
,
925 .poll_put_char
= s3c24xx_serial_put_poll_char
,
929 static struct uart_driver s3c24xx_uart_drv
= {
930 .owner
= THIS_MODULE
,
931 .driver_name
= "s3c2410_serial",
932 .nr
= CONFIG_SERIAL_SAMSUNG_UARTS
,
933 .cons
= S3C24XX_SERIAL_CONSOLE
,
934 .dev_name
= S3C24XX_SERIAL_NAME
,
935 .major
= S3C24XX_SERIAL_MAJOR
,
936 .minor
= S3C24XX_SERIAL_MINOR
,
939 static struct s3c24xx_uart_port s3c24xx_serial_ports
[CONFIG_SERIAL_SAMSUNG_UARTS
] = {
942 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[0].port
.lock
),
946 .ops
= &s3c24xx_serial_ops
,
947 .flags
= UPF_BOOT_AUTOCONF
,
953 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[1].port
.lock
),
957 .ops
= &s3c24xx_serial_ops
,
958 .flags
= UPF_BOOT_AUTOCONF
,
962 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
966 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[2].port
.lock
),
970 .ops
= &s3c24xx_serial_ops
,
971 .flags
= UPF_BOOT_AUTOCONF
,
976 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
979 .lock
= __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports
[3].port
.lock
),
983 .ops
= &s3c24xx_serial_ops
,
984 .flags
= UPF_BOOT_AUTOCONF
,
991 /* s3c24xx_serial_resetport
993 * reset the fifos and other the settings.
996 static void s3c24xx_serial_resetport(struct uart_port
*port
,
997 struct s3c2410_uartcfg
*cfg
)
999 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1000 unsigned long ucon
= rd_regl(port
, S3C2410_UCON
);
1001 unsigned int ucon_mask
;
1003 ucon_mask
= info
->clksel_mask
;
1004 if (info
->type
== PORT_S3C2440
)
1005 ucon_mask
|= S3C2440_UCON0_DIVMASK
;
1008 wr_regl(port
, S3C2410_UCON
, ucon
| cfg
->ucon
);
1010 /* reset both fifos */
1011 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
| S3C2410_UFCON_RESETBOTH
);
1012 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
);
1014 /* some delay is required after fifo reset */
1019 #ifdef CONFIG_CPU_FREQ
1021 static int s3c24xx_serial_cpufreq_transition(struct notifier_block
*nb
,
1022 unsigned long val
, void *data
)
1024 struct s3c24xx_uart_port
*port
;
1025 struct uart_port
*uport
;
1027 port
= container_of(nb
, struct s3c24xx_uart_port
, freq_transition
);
1028 uport
= &port
->port
;
1030 /* check to see if port is enabled */
1032 if (port
->pm_level
!= 0)
1035 /* try and work out if the baudrate is changing, we can detect
1036 * a change in rate, but we do not have support for detecting
1037 * a disturbance in the clock-rate over the change.
1040 if (IS_ERR(port
->baudclk
))
1043 if (port
->baudclk_rate
== clk_get_rate(port
->baudclk
))
1046 if (val
== CPUFREQ_PRECHANGE
) {
1047 /* we should really shut the port down whilst the
1048 * frequency change is in progress. */
1050 } else if (val
== CPUFREQ_POSTCHANGE
) {
1051 struct ktermios
*termios
;
1052 struct tty_struct
*tty
;
1054 if (uport
->state
== NULL
)
1057 tty
= uport
->state
->port
.tty
;
1062 termios
= &tty
->termios
;
1064 if (termios
== NULL
) {
1065 dev_warn(uport
->dev
, "%s: no termios?\n", __func__
);
1069 s3c24xx_serial_set_termios(uport
, termios
, NULL
);
1076 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1078 port
->freq_transition
.notifier_call
= s3c24xx_serial_cpufreq_transition
;
1080 return cpufreq_register_notifier(&port
->freq_transition
,
1081 CPUFREQ_TRANSITION_NOTIFIER
);
1084 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1086 cpufreq_unregister_notifier(&port
->freq_transition
,
1087 CPUFREQ_TRANSITION_NOTIFIER
);
1091 static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1096 static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1101 /* s3c24xx_serial_init_port
1103 * initialise a single serial port from the platform device given
1106 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port
*ourport
,
1107 struct platform_device
*platdev
)
1109 struct uart_port
*port
= &ourport
->port
;
1110 struct s3c2410_uartcfg
*cfg
= ourport
->cfg
;
1111 struct resource
*res
;
1114 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port
, platdev
);
1116 if (platdev
== NULL
)
1119 if (port
->mapbase
!= 0)
1122 /* setup info for port */
1123 port
->dev
= &platdev
->dev
;
1125 /* Startup sequence is different for s3c64xx and higher SoC's */
1126 if (s3c24xx_serial_has_interrupt_mask(port
))
1127 s3c24xx_serial_ops
.startup
= s3c64xx_serial_startup
;
1131 if (cfg
->uart_flags
& UPF_CONS_FLOW
) {
1132 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1133 port
->flags
|= UPF_CONS_FLOW
;
1136 /* sort our the physical and virtual addresses for each UART */
1138 res
= platform_get_resource(platdev
, IORESOURCE_MEM
, 0);
1140 dev_err(port
->dev
, "failed to find memory resource for uart\n");
1144 dbg("resource %p (%lx..%lx)\n", res
, res
->start
, res
->end
);
1146 port
->mapbase
= res
->start
;
1147 port
->membase
= S3C_VA_UART
+ (res
->start
& 0xfffff);
1148 ret
= platform_get_irq(platdev
, 0);
1153 ourport
->rx_irq
= ret
;
1154 ourport
->tx_irq
= ret
+ 1;
1157 ret
= platform_get_irq(platdev
, 1);
1159 ourport
->tx_irq
= ret
;
1161 ourport
->clk
= clk_get(&platdev
->dev
, "uart");
1163 /* Keep all interrupts masked and cleared */
1164 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1165 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1166 wr_regl(port
, S3C64XX_UINTP
, 0xf);
1167 wr_regl(port
, S3C64XX_UINTSP
, 0xf);
1170 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1171 port
->mapbase
, port
->membase
, port
->irq
,
1172 ourport
->rx_irq
, ourport
->tx_irq
, port
->uartclk
);
1174 /* reset the fifos (and setup the uart) */
1175 s3c24xx_serial_resetport(port
, cfg
);
1179 static ssize_t
s3c24xx_serial_show_clksrc(struct device
*dev
,
1180 struct device_attribute
*attr
,
1183 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1184 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1186 if (IS_ERR(ourport
->baudclk
))
1189 return snprintf(buf
, PAGE_SIZE
, "* %s\n",
1190 ourport
->baudclk
->name
?: "(null)");
1193 static DEVICE_ATTR(clock_source
, S_IRUGO
, s3c24xx_serial_show_clksrc
, NULL
);
1196 /* Device driver serial port probe */
1198 static const struct of_device_id s3c24xx_uart_dt_match
[];
1199 static int probe_index
;
1201 static inline struct s3c24xx_serial_drv_data
*s3c24xx_get_driver_data(
1202 struct platform_device
*pdev
)
1205 if (pdev
->dev
.of_node
) {
1206 const struct of_device_id
*match
;
1207 match
= of_match_node(s3c24xx_uart_dt_match
, pdev
->dev
.of_node
);
1208 return (struct s3c24xx_serial_drv_data
*)match
->data
;
1211 return (struct s3c24xx_serial_drv_data
*)
1212 platform_get_device_id(pdev
)->driver_data
;
1215 static int s3c24xx_serial_probe(struct platform_device
*pdev
)
1217 struct s3c24xx_uart_port
*ourport
;
1220 dbg("s3c24xx_serial_probe(%p) %d\n", pdev
, probe_index
);
1222 ourport
= &s3c24xx_serial_ports
[probe_index
];
1224 ourport
->drv_data
= s3c24xx_get_driver_data(pdev
);
1225 if (!ourport
->drv_data
) {
1226 dev_err(&pdev
->dev
, "could not find driver data\n");
1230 ourport
->baudclk
= ERR_PTR(-EINVAL
);
1231 ourport
->info
= ourport
->drv_data
->info
;
1232 ourport
->cfg
= (pdev
->dev
.platform_data
) ?
1233 (struct s3c2410_uartcfg
*)pdev
->dev
.platform_data
:
1234 ourport
->drv_data
->def_cfg
;
1236 ourport
->port
.fifosize
= (ourport
->info
->fifosize
) ?
1237 ourport
->info
->fifosize
:
1238 ourport
->drv_data
->fifosize
[probe_index
];
1242 dbg("%s: initialising port %p...\n", __func__
, ourport
);
1244 ret
= s3c24xx_serial_init_port(ourport
, pdev
);
1248 dbg("%s: adding port\n", __func__
);
1249 uart_add_one_port(&s3c24xx_uart_drv
, &ourport
->port
);
1250 platform_set_drvdata(pdev
, &ourport
->port
);
1252 ret
= device_create_file(&pdev
->dev
, &dev_attr_clock_source
);
1254 dev_err(&pdev
->dev
, "failed to add clock source attr.\n");
1256 ret
= s3c24xx_serial_cpufreq_register(ourport
);
1258 dev_err(&pdev
->dev
, "failed to add cpufreq notifier\n");
1266 static int s3c24xx_serial_remove(struct platform_device
*dev
)
1268 struct uart_port
*port
= s3c24xx_dev_to_port(&dev
->dev
);
1271 s3c24xx_serial_cpufreq_deregister(to_ourport(port
));
1272 device_remove_file(&dev
->dev
, &dev_attr_clock_source
);
1273 uart_remove_one_port(&s3c24xx_uart_drv
, port
);
1279 /* UART power management code */
1280 #ifdef CONFIG_PM_SLEEP
1281 static int s3c24xx_serial_suspend(struct device
*dev
)
1283 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1286 uart_suspend_port(&s3c24xx_uart_drv
, port
);
1291 static int s3c24xx_serial_resume(struct device
*dev
)
1293 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1294 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1297 clk_prepare_enable(ourport
->clk
);
1298 s3c24xx_serial_resetport(port
, s3c24xx_port_to_cfg(port
));
1299 clk_disable_unprepare(ourport
->clk
);
1301 uart_resume_port(&s3c24xx_uart_drv
, port
);
1307 static const struct dev_pm_ops s3c24xx_serial_pm_ops
= {
1308 .suspend
= s3c24xx_serial_suspend
,
1309 .resume
= s3c24xx_serial_resume
,
1311 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1313 #else /* !CONFIG_PM_SLEEP */
1315 #define SERIAL_SAMSUNG_PM_OPS NULL
1316 #endif /* CONFIG_PM_SLEEP */
1320 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1322 static struct uart_port
*cons_uart
;
1325 s3c24xx_serial_console_txrdy(struct uart_port
*port
, unsigned int ufcon
)
1327 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1328 unsigned long ufstat
, utrstat
;
1330 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
1331 /* fifo mode - check amount of data in fifo registers... */
1333 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
1334 return (ufstat
& info
->tx_fifofull
) ? 0 : 1;
1337 /* in non-fifo mode, we go and use the tx buffer empty */
1339 utrstat
= rd_regl(port
, S3C2410_UTRSTAT
);
1340 return (utrstat
& S3C2410_UTRSTAT_TXE
) ? 1 : 0;
1343 #ifdef CONFIG_CONSOLE_POLL
1345 * Console polling routines for writing and reading from the uart while
1346 * in an interrupt or debug context.
1349 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
)
1351 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1352 unsigned int ufstat
;
1354 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
1355 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
1356 return NO_POLL_CHAR
;
1358 return rd_regb(port
, S3C2410_URXH
);
1361 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
1364 unsigned int ufcon
= rd_regl(cons_uart
, S3C2410_UFCON
);
1366 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
1368 wr_regb(cons_uart
, S3C2410_UTXH
, c
);
1371 #endif /* CONFIG_CONSOLE_POLL */
1374 s3c24xx_serial_console_putchar(struct uart_port
*port
, int ch
)
1376 unsigned int ufcon
= rd_regl(cons_uart
, S3C2410_UFCON
);
1377 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
1379 wr_regb(cons_uart
, S3C2410_UTXH
, ch
);
1383 s3c24xx_serial_console_write(struct console
*co
, const char *s
,
1386 uart_console_write(cons_uart
, s
, count
, s3c24xx_serial_console_putchar
);
1390 s3c24xx_serial_get_options(struct uart_port
*port
, int *baud
,
1391 int *parity
, int *bits
)
1396 unsigned int ubrdiv
;
1398 unsigned int clk_sel
;
1399 char clk_name
[MAX_CLK_NAME_LENGTH
];
1401 ulcon
= rd_regl(port
, S3C2410_ULCON
);
1402 ucon
= rd_regl(port
, S3C2410_UCON
);
1403 ubrdiv
= rd_regl(port
, S3C2410_UBRDIV
);
1405 dbg("s3c24xx_serial_get_options: port=%p\n"
1406 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1407 port
, ulcon
, ucon
, ubrdiv
);
1409 if ((ucon
& 0xf) != 0) {
1410 /* consider the serial port configured if the tx/rx mode set */
1412 switch (ulcon
& S3C2410_LCON_CSMASK
) {
1413 case S3C2410_LCON_CS5
:
1416 case S3C2410_LCON_CS6
:
1419 case S3C2410_LCON_CS7
:
1423 case S3C2410_LCON_CS8
:
1428 switch (ulcon
& S3C2410_LCON_PMASK
) {
1429 case S3C2410_LCON_PEVEN
:
1433 case S3C2410_LCON_PODD
:
1437 case S3C2410_LCON_PNONE
:
1442 /* now calculate the baud rate */
1444 clk_sel
= s3c24xx_serial_getsource(port
);
1445 sprintf(clk_name
, "clk_uart_baud%d", clk_sel
);
1447 clk
= clk_get(port
->dev
, clk_name
);
1449 rate
= clk_get_rate(clk
);
1453 *baud
= rate
/ (16 * (ubrdiv
+ 1));
1454 dbg("calculated baud %d\n", *baud
);
1460 s3c24xx_serial_console_setup(struct console
*co
, char *options
)
1462 struct uart_port
*port
;
1468 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1469 co
, co
->index
, options
);
1471 /* is this a valid port */
1473 if (co
->index
== -1 || co
->index
>= CONFIG_SERIAL_SAMSUNG_UARTS
)
1476 port
= &s3c24xx_serial_ports
[co
->index
].port
;
1478 /* is the port configured? */
1480 if (port
->mapbase
== 0x0)
1485 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port
, co
->index
);
1488 * Check whether an invalid uart number has been specified, and
1489 * if so, search for the first available port that does have
1493 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1495 s3c24xx_serial_get_options(port
, &baud
, &parity
, &bits
);
1497 dbg("s3c24xx_serial_console_setup: baud %d\n", baud
);
1499 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
1502 static struct console s3c24xx_serial_console
= {
1503 .name
= S3C24XX_SERIAL_NAME
,
1504 .device
= uart_console_device
,
1505 .flags
= CON_PRINTBUFFER
,
1507 .write
= s3c24xx_serial_console_write
,
1508 .setup
= s3c24xx_serial_console_setup
,
1509 .data
= &s3c24xx_uart_drv
,
1511 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1513 #ifdef CONFIG_CPU_S3C2410
1514 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data
= {
1515 .info
= &(struct s3c24xx_uart_info
) {
1516 .name
= "Samsung S3C2410 UART",
1517 .type
= PORT_S3C2410
,
1519 .rx_fifomask
= S3C2410_UFSTAT_RXMASK
,
1520 .rx_fifoshift
= S3C2410_UFSTAT_RXSHIFT
,
1521 .rx_fifofull
= S3C2410_UFSTAT_RXFULL
,
1522 .tx_fifofull
= S3C2410_UFSTAT_TXFULL
,
1523 .tx_fifomask
= S3C2410_UFSTAT_TXMASK
,
1524 .tx_fifoshift
= S3C2410_UFSTAT_TXSHIFT
,
1525 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1527 .clksel_mask
= S3C2410_UCON_CLKMASK
,
1528 .clksel_shift
= S3C2410_UCON_CLKSHIFT
,
1530 .def_cfg
= &(struct s3c2410_uartcfg
) {
1531 .ucon
= S3C2410_UCON_DEFAULT
,
1532 .ufcon
= S3C2410_UFCON_DEFAULT
,
1535 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1537 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1540 #ifdef CONFIG_CPU_S3C2412
1541 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data
= {
1542 .info
= &(struct s3c24xx_uart_info
) {
1543 .name
= "Samsung S3C2412 UART",
1544 .type
= PORT_S3C2412
,
1547 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1548 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1549 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1550 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1551 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1552 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1553 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1555 .clksel_mask
= S3C2412_UCON_CLKMASK
,
1556 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
1558 .def_cfg
= &(struct s3c2410_uartcfg
) {
1559 .ucon
= S3C2410_UCON_DEFAULT
,
1560 .ufcon
= S3C2410_UFCON_DEFAULT
,
1563 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1565 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1568 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1569 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
1570 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data
= {
1571 .info
= &(struct s3c24xx_uart_info
) {
1572 .name
= "Samsung S3C2440 UART",
1573 .type
= PORT_S3C2440
,
1576 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1577 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1578 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1579 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1580 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1581 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1582 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1584 .clksel_mask
= S3C2412_UCON_CLKMASK
,
1585 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
1587 .def_cfg
= &(struct s3c2410_uartcfg
) {
1588 .ucon
= S3C2410_UCON_DEFAULT
,
1589 .ufcon
= S3C2410_UFCON_DEFAULT
,
1592 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1594 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1597 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1598 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1599 defined(CONFIG_CPU_S5PC100)
1600 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data
= {
1601 .info
= &(struct s3c24xx_uart_info
) {
1602 .name
= "Samsung S3C6400 UART",
1603 .type
= PORT_S3C6400
,
1606 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
1607 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
1608 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
1609 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
1610 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
1611 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
1612 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
1614 .clksel_mask
= S3C6400_UCON_CLKMASK
,
1615 .clksel_shift
= S3C6400_UCON_CLKSHIFT
,
1617 .def_cfg
= &(struct s3c2410_uartcfg
) {
1618 .ucon
= S3C2410_UCON_DEFAULT
,
1619 .ufcon
= S3C2410_UFCON_DEFAULT
,
1622 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1624 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1627 #ifdef CONFIG_CPU_S5PV210
1628 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data
= {
1629 .info
= &(struct s3c24xx_uart_info
) {
1630 .name
= "Samsung S5PV210 UART",
1631 .type
= PORT_S3C6400
,
1633 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
1634 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
1635 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
1636 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
1637 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
1638 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
1639 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1641 .clksel_mask
= S5PV210_UCON_CLKMASK
,
1642 .clksel_shift
= S5PV210_UCON_CLKSHIFT
,
1644 .def_cfg
= &(struct s3c2410_uartcfg
) {
1645 .ucon
= S5PV210_UCON_DEFAULT
,
1646 .ufcon
= S5PV210_UFCON_DEFAULT
,
1648 .fifosize
= { 256, 64, 16, 16 },
1650 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1652 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1655 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
1656 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1657 defined(CONFIG_SOC_EXYNOS5440)
1658 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data
= {
1659 .info
= &(struct s3c24xx_uart_info
) {
1660 .name
= "Samsung Exynos4 UART",
1661 .type
= PORT_S3C6400
,
1663 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
1664 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
1665 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
1666 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
1667 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
1668 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
1669 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
1674 .def_cfg
= &(struct s3c2410_uartcfg
) {
1675 .ucon
= S5PV210_UCON_DEFAULT
,
1676 .ufcon
= S5PV210_UFCON_DEFAULT
,
1679 .fifosize
= { 256, 64, 16, 16 },
1681 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1683 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1686 static struct platform_device_id s3c24xx_serial_driver_ids
[] = {
1688 .name
= "s3c2410-uart",
1689 .driver_data
= S3C2410_SERIAL_DRV_DATA
,
1691 .name
= "s3c2412-uart",
1692 .driver_data
= S3C2412_SERIAL_DRV_DATA
,
1694 .name
= "s3c2440-uart",
1695 .driver_data
= S3C2440_SERIAL_DRV_DATA
,
1697 .name
= "s3c6400-uart",
1698 .driver_data
= S3C6400_SERIAL_DRV_DATA
,
1700 .name
= "s5pv210-uart",
1701 .driver_data
= S5PV210_SERIAL_DRV_DATA
,
1703 .name
= "exynos4210-uart",
1704 .driver_data
= EXYNOS4210_SERIAL_DRV_DATA
,
1708 MODULE_DEVICE_TABLE(platform
, s3c24xx_serial_driver_ids
);
1711 static const struct of_device_id s3c24xx_uart_dt_match
[] = {
1712 { .compatible
= "samsung,s3c2410-uart",
1713 .data
= (void *)S3C2410_SERIAL_DRV_DATA
},
1714 { .compatible
= "samsung,s3c2412-uart",
1715 .data
= (void *)S3C2412_SERIAL_DRV_DATA
},
1716 { .compatible
= "samsung,s3c2440-uart",
1717 .data
= (void *)S3C2440_SERIAL_DRV_DATA
},
1718 { .compatible
= "samsung,s3c6400-uart",
1719 .data
= (void *)S3C6400_SERIAL_DRV_DATA
},
1720 { .compatible
= "samsung,s5pv210-uart",
1721 .data
= (void *)S5PV210_SERIAL_DRV_DATA
},
1722 { .compatible
= "samsung,exynos4210-uart",
1723 .data
= (void *)EXYNOS4210_SERIAL_DRV_DATA
},
1726 MODULE_DEVICE_TABLE(of
, s3c24xx_uart_dt_match
);
1728 #define s3c24xx_uart_dt_match NULL
1731 static struct platform_driver samsung_serial_driver
= {
1732 .probe
= s3c24xx_serial_probe
,
1733 .remove
= s3c24xx_serial_remove
,
1734 .id_table
= s3c24xx_serial_driver_ids
,
1736 .name
= "samsung-uart",
1737 .owner
= THIS_MODULE
,
1738 .pm
= SERIAL_SAMSUNG_PM_OPS
,
1739 .of_match_table
= s3c24xx_uart_dt_match
,
1743 /* module initialisation code */
1745 static int __init
s3c24xx_serial_modinit(void)
1749 ret
= uart_register_driver(&s3c24xx_uart_drv
);
1751 pr_err("Failed to register Samsung UART driver\n");
1755 return platform_driver_register(&samsung_serial_driver
);
1758 static void __exit
s3c24xx_serial_modexit(void)
1760 uart_unregister_driver(&s3c24xx_uart_drv
);
1763 module_init(s3c24xx_serial_modinit
);
1764 module_exit(s3c24xx_serial_modexit
);
1766 MODULE_ALIAS("platform:samsung-uart");
1767 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1768 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1769 MODULE_LICENSE("GPL v2");