1 // SPDX-License-Identifier: GPL-2.0
3 * Driver core for Samsung SoC onboard UARTs.
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
9 /* Hote on 2410 error handling
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
24 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/module.h>
32 #include <linux/ioport.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
52 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
55 extern void printascii(const char *);
58 static void dbg(const char *fmt
, ...)
64 vscnprintf(buff
, sizeof(buff
), fmt
, va
);
71 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
74 /* UART name and device definitions */
76 #define S3C24XX_SERIAL_NAME "ttySAC"
77 #define S3C24XX_SERIAL_MAJOR 204
78 #define S3C24XX_SERIAL_MINOR 64
80 #define S3C24XX_TX_PIO 1
81 #define S3C24XX_TX_DMA 2
82 #define S3C24XX_RX_PIO 1
83 #define S3C24XX_RX_DMA 2
84 /* macros to change one thing to another */
86 #define tx_enabled(port) ((port)->unused[0])
87 #define rx_enabled(port) ((port)->unused[1])
89 /* flag to ignore all characters coming in */
90 #define RXSTAT_DUMMY_READ (0x10000000)
92 static inline struct s3c24xx_uart_port
*to_ourport(struct uart_port
*port
)
94 return container_of(port
, struct s3c24xx_uart_port
, port
);
97 /* translate a port to the device name */
99 static inline const char *s3c24xx_serial_portname(struct uart_port
*port
)
101 return to_platform_device(port
->dev
)->name
;
104 static int s3c24xx_serial_txempty_nofifo(struct uart_port
*port
)
106 return rd_regl(port
, S3C2410_UTRSTAT
) & S3C2410_UTRSTAT_TXE
;
110 * s3c64xx and later SoC's include the interrupt mask and status registers in
111 * the controller itself, unlike the s3c24xx SoC's which have these registers
112 * in the interrupt controller. Check if the port type is s3c64xx or higher.
114 static int s3c24xx_serial_has_interrupt_mask(struct uart_port
*port
)
116 return to_ourport(port
)->info
->type
== PORT_S3C6400
;
119 static void s3c24xx_serial_rx_enable(struct uart_port
*port
)
122 unsigned int ucon
, ufcon
;
125 spin_lock_irqsave(&port
->lock
, flags
);
127 while (--count
&& !s3c24xx_serial_txempty_nofifo(port
))
130 ufcon
= rd_regl(port
, S3C2410_UFCON
);
131 ufcon
|= S3C2410_UFCON_RESETRX
;
132 wr_regl(port
, S3C2410_UFCON
, ufcon
);
134 ucon
= rd_regl(port
, S3C2410_UCON
);
135 ucon
|= S3C2410_UCON_RXIRQMODE
;
136 wr_regl(port
, S3C2410_UCON
, ucon
);
138 rx_enabled(port
) = 1;
139 spin_unlock_irqrestore(&port
->lock
, flags
);
142 static void s3c24xx_serial_rx_disable(struct uart_port
*port
)
147 spin_lock_irqsave(&port
->lock
, flags
);
149 ucon
= rd_regl(port
, S3C2410_UCON
);
150 ucon
&= ~S3C2410_UCON_RXIRQMODE
;
151 wr_regl(port
, S3C2410_UCON
, ucon
);
153 rx_enabled(port
) = 0;
154 spin_unlock_irqrestore(&port
->lock
, flags
);
157 static void s3c24xx_serial_stop_tx(struct uart_port
*port
)
159 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
160 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
161 struct circ_buf
*xmit
= &port
->state
->xmit
;
162 struct dma_tx_state state
;
165 if (!tx_enabled(port
))
168 if (s3c24xx_serial_has_interrupt_mask(port
))
169 s3c24xx_set_bit(port
, S3C64XX_UINTM_TXD
, S3C64XX_UINTM
);
171 disable_irq_nosync(ourport
->tx_irq
);
173 if (dma
&& dma
->tx_chan
&& ourport
->tx_in_progress
== S3C24XX_TX_DMA
) {
174 dmaengine_pause(dma
->tx_chan
);
175 dmaengine_tx_status(dma
->tx_chan
, dma
->tx_cookie
, &state
);
176 dmaengine_terminate_all(dma
->tx_chan
);
177 dma_sync_single_for_cpu(ourport
->port
.dev
,
178 dma
->tx_transfer_addr
, dma
->tx_size
, DMA_TO_DEVICE
);
179 async_tx_ack(dma
->tx_desc
);
180 count
= dma
->tx_bytes_requested
- state
.residue
;
181 xmit
->tail
= (xmit
->tail
+ count
) & (UART_XMIT_SIZE
- 1);
182 port
->icount
.tx
+= count
;
185 tx_enabled(port
) = 0;
186 ourport
->tx_in_progress
= 0;
188 if (port
->flags
& UPF_CONS_FLOW
)
189 s3c24xx_serial_rx_enable(port
);
191 ourport
->tx_mode
= 0;
194 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port
*ourport
);
196 static void s3c24xx_serial_tx_dma_complete(void *args
)
198 struct s3c24xx_uart_port
*ourport
= args
;
199 struct uart_port
*port
= &ourport
->port
;
200 struct circ_buf
*xmit
= &port
->state
->xmit
;
201 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
202 struct dma_tx_state state
;
207 dmaengine_tx_status(dma
->tx_chan
, dma
->tx_cookie
, &state
);
208 count
= dma
->tx_bytes_requested
- state
.residue
;
209 async_tx_ack(dma
->tx_desc
);
211 dma_sync_single_for_cpu(ourport
->port
.dev
, dma
->tx_transfer_addr
,
212 dma
->tx_size
, DMA_TO_DEVICE
);
214 spin_lock_irqsave(&port
->lock
, flags
);
216 xmit
->tail
= (xmit
->tail
+ count
) & (UART_XMIT_SIZE
- 1);
217 port
->icount
.tx
+= count
;
218 ourport
->tx_in_progress
= 0;
220 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
221 uart_write_wakeup(port
);
223 s3c24xx_serial_start_next_tx(ourport
);
224 spin_unlock_irqrestore(&port
->lock
, flags
);
227 static void enable_tx_dma(struct s3c24xx_uart_port
*ourport
)
229 struct uart_port
*port
= &ourport
->port
;
232 /* Mask Tx interrupt */
233 if (s3c24xx_serial_has_interrupt_mask(port
))
234 s3c24xx_set_bit(port
, S3C64XX_UINTM_TXD
, S3C64XX_UINTM
);
236 disable_irq_nosync(ourport
->tx_irq
);
238 /* Enable tx dma mode */
239 ucon
= rd_regl(port
, S3C2410_UCON
);
240 ucon
&= ~(S3C64XX_UCON_TXBURST_MASK
| S3C64XX_UCON_TXMODE_MASK
);
241 ucon
|= (dma_get_cache_alignment() >= 16) ?
242 S3C64XX_UCON_TXBURST_16
: S3C64XX_UCON_TXBURST_1
;
243 ucon
|= S3C64XX_UCON_TXMODE_DMA
;
244 wr_regl(port
, S3C2410_UCON
, ucon
);
246 ourport
->tx_mode
= S3C24XX_TX_DMA
;
249 static void enable_tx_pio(struct s3c24xx_uart_port
*ourport
)
251 struct uart_port
*port
= &ourport
->port
;
254 /* Set ufcon txtrig */
255 ourport
->tx_in_progress
= S3C24XX_TX_PIO
;
256 ufcon
= rd_regl(port
, S3C2410_UFCON
);
257 wr_regl(port
, S3C2410_UFCON
, ufcon
);
259 /* Enable tx pio mode */
260 ucon
= rd_regl(port
, S3C2410_UCON
);
261 ucon
&= ~(S3C64XX_UCON_TXMODE_MASK
);
262 ucon
|= S3C64XX_UCON_TXMODE_CPU
;
263 wr_regl(port
, S3C2410_UCON
, ucon
);
265 /* Unmask Tx interrupt */
266 if (s3c24xx_serial_has_interrupt_mask(port
))
267 s3c24xx_clear_bit(port
, S3C64XX_UINTM_TXD
,
270 enable_irq(ourport
->tx_irq
);
272 ourport
->tx_mode
= S3C24XX_TX_PIO
;
275 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port
*ourport
)
277 if (ourport
->tx_mode
!= S3C24XX_TX_PIO
)
278 enable_tx_pio(ourport
);
281 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port
*ourport
,
284 struct uart_port
*port
= &ourport
->port
;
285 struct circ_buf
*xmit
= &port
->state
->xmit
;
286 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
289 if (ourport
->tx_mode
!= S3C24XX_TX_DMA
)
290 enable_tx_dma(ourport
);
292 dma
->tx_size
= count
& ~(dma_get_cache_alignment() - 1);
293 dma
->tx_transfer_addr
= dma
->tx_addr
+ xmit
->tail
;
295 dma_sync_single_for_device(ourport
->port
.dev
, dma
->tx_transfer_addr
,
296 dma
->tx_size
, DMA_TO_DEVICE
);
298 dma
->tx_desc
= dmaengine_prep_slave_single(dma
->tx_chan
,
299 dma
->tx_transfer_addr
, dma
->tx_size
,
300 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
302 dev_err(ourport
->port
.dev
, "Unable to get desc for Tx\n");
306 dma
->tx_desc
->callback
= s3c24xx_serial_tx_dma_complete
;
307 dma
->tx_desc
->callback_param
= ourport
;
308 dma
->tx_bytes_requested
= dma
->tx_size
;
310 ourport
->tx_in_progress
= S3C24XX_TX_DMA
;
311 dma
->tx_cookie
= dmaengine_submit(dma
->tx_desc
);
312 dma_async_issue_pending(dma
->tx_chan
);
316 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port
*ourport
)
318 struct uart_port
*port
= &ourport
->port
;
319 struct circ_buf
*xmit
= &port
->state
->xmit
;
322 /* Get data size up to the end of buffer */
323 count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
326 s3c24xx_serial_stop_tx(port
);
330 if (!ourport
->dma
|| !ourport
->dma
->tx_chan
||
331 count
< ourport
->min_dma_size
||
332 xmit
->tail
& (dma_get_cache_alignment() - 1))
333 s3c24xx_serial_start_tx_pio(ourport
);
335 s3c24xx_serial_start_tx_dma(ourport
, count
);
338 static void s3c24xx_serial_start_tx(struct uart_port
*port
)
340 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
341 struct circ_buf
*xmit
= &port
->state
->xmit
;
343 if (!tx_enabled(port
)) {
344 if (port
->flags
& UPF_CONS_FLOW
)
345 s3c24xx_serial_rx_disable(port
);
347 tx_enabled(port
) = 1;
348 if (!ourport
->dma
|| !ourport
->dma
->tx_chan
)
349 s3c24xx_serial_start_tx_pio(ourport
);
352 if (ourport
->dma
&& ourport
->dma
->tx_chan
) {
353 if (!uart_circ_empty(xmit
) && !ourport
->tx_in_progress
)
354 s3c24xx_serial_start_next_tx(ourport
);
358 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port
*ourport
,
359 struct tty_port
*tty
, int count
)
361 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
367 dma_sync_single_for_cpu(ourport
->port
.dev
, dma
->rx_addr
,
368 dma
->rx_size
, DMA_FROM_DEVICE
);
370 ourport
->port
.icount
.rx
+= count
;
372 dev_err(ourport
->port
.dev
, "No tty port\n");
375 copied
= tty_insert_flip_string(tty
,
376 ((unsigned char *)(ourport
->dma
->rx_buf
)), count
);
377 if (copied
!= count
) {
379 dev_err(ourport
->port
.dev
, "RxData copy to tty layer failed\n");
383 static void s3c24xx_serial_stop_rx(struct uart_port
*port
)
385 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
386 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
387 struct tty_port
*t
= &port
->state
->port
;
388 struct dma_tx_state state
;
389 enum dma_status dma_status
;
390 unsigned int received
;
392 if (rx_enabled(port
)) {
393 dbg("s3c24xx_serial_stop_rx: port=%p\n", port
);
394 if (s3c24xx_serial_has_interrupt_mask(port
))
395 s3c24xx_set_bit(port
, S3C64XX_UINTM_RXD
,
398 disable_irq_nosync(ourport
->rx_irq
);
399 rx_enabled(port
) = 0;
401 if (dma
&& dma
->rx_chan
) {
402 dmaengine_pause(dma
->tx_chan
);
403 dma_status
= dmaengine_tx_status(dma
->rx_chan
,
404 dma
->rx_cookie
, &state
);
405 if (dma_status
== DMA_IN_PROGRESS
||
406 dma_status
== DMA_PAUSED
) {
407 received
= dma
->rx_bytes_requested
- state
.residue
;
408 dmaengine_terminate_all(dma
->rx_chan
);
409 s3c24xx_uart_copy_rx_to_tty(ourport
, t
, received
);
414 static inline struct s3c24xx_uart_info
415 *s3c24xx_port_to_info(struct uart_port
*port
)
417 return to_ourport(port
)->info
;
420 static inline struct s3c2410_uartcfg
421 *s3c24xx_port_to_cfg(struct uart_port
*port
)
423 struct s3c24xx_uart_port
*ourport
;
425 if (port
->dev
== NULL
)
428 ourport
= container_of(port
, struct s3c24xx_uart_port
, port
);
432 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port
*ourport
,
433 unsigned long ufstat
)
435 struct s3c24xx_uart_info
*info
= ourport
->info
;
437 if (ufstat
& info
->rx_fifofull
)
438 return ourport
->port
.fifosize
;
440 return (ufstat
& info
->rx_fifomask
) >> info
->rx_fifoshift
;
443 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port
*ourport
);
444 static void s3c24xx_serial_rx_dma_complete(void *args
)
446 struct s3c24xx_uart_port
*ourport
= args
;
447 struct uart_port
*port
= &ourport
->port
;
449 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
450 struct tty_port
*t
= &port
->state
->port
;
451 struct tty_struct
*tty
= tty_port_tty_get(&ourport
->port
.state
->port
);
453 struct dma_tx_state state
;
457 dmaengine_tx_status(dma
->rx_chan
, dma
->rx_cookie
, &state
);
458 received
= dma
->rx_bytes_requested
- state
.residue
;
459 async_tx_ack(dma
->rx_desc
);
461 spin_lock_irqsave(&port
->lock
, flags
);
464 s3c24xx_uart_copy_rx_to_tty(ourport
, t
, received
);
467 tty_flip_buffer_push(t
);
471 s3c64xx_start_rx_dma(ourport
);
473 spin_unlock_irqrestore(&port
->lock
, flags
);
476 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port
*ourport
)
478 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
480 dma_sync_single_for_device(ourport
->port
.dev
, dma
->rx_addr
,
481 dma
->rx_size
, DMA_FROM_DEVICE
);
483 dma
->rx_desc
= dmaengine_prep_slave_single(dma
->rx_chan
,
484 dma
->rx_addr
, dma
->rx_size
, DMA_DEV_TO_MEM
,
487 dev_err(ourport
->port
.dev
, "Unable to get desc for Rx\n");
491 dma
->rx_desc
->callback
= s3c24xx_serial_rx_dma_complete
;
492 dma
->rx_desc
->callback_param
= ourport
;
493 dma
->rx_bytes_requested
= dma
->rx_size
;
495 dma
->rx_cookie
= dmaengine_submit(dma
->rx_desc
);
496 dma_async_issue_pending(dma
->rx_chan
);
499 /* ? - where has parity gone?? */
500 #define S3C2410_UERSTAT_PARITY (0x1000)
502 static void enable_rx_dma(struct s3c24xx_uart_port
*ourport
)
504 struct uart_port
*port
= &ourport
->port
;
507 /* set Rx mode to DMA mode */
508 ucon
= rd_regl(port
, S3C2410_UCON
);
509 ucon
&= ~(S3C64XX_UCON_RXBURST_MASK
|
510 S3C64XX_UCON_TIMEOUT_MASK
|
511 S3C64XX_UCON_EMPTYINT_EN
|
512 S3C64XX_UCON_DMASUS_EN
|
513 S3C64XX_UCON_TIMEOUT_EN
|
514 S3C64XX_UCON_RXMODE_MASK
);
515 ucon
|= S3C64XX_UCON_RXBURST_16
|
516 0xf << S3C64XX_UCON_TIMEOUT_SHIFT
|
517 S3C64XX_UCON_EMPTYINT_EN
|
518 S3C64XX_UCON_TIMEOUT_EN
|
519 S3C64XX_UCON_RXMODE_DMA
;
520 wr_regl(port
, S3C2410_UCON
, ucon
);
522 ourport
->rx_mode
= S3C24XX_RX_DMA
;
525 static void enable_rx_pio(struct s3c24xx_uart_port
*ourport
)
527 struct uart_port
*port
= &ourport
->port
;
530 /* set Rx mode to DMA mode */
531 ucon
= rd_regl(port
, S3C2410_UCON
);
532 ucon
&= ~(S3C64XX_UCON_TIMEOUT_MASK
|
533 S3C64XX_UCON_EMPTYINT_EN
|
534 S3C64XX_UCON_DMASUS_EN
|
535 S3C64XX_UCON_TIMEOUT_EN
|
536 S3C64XX_UCON_RXMODE_MASK
);
537 ucon
|= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT
|
538 S3C64XX_UCON_TIMEOUT_EN
|
539 S3C64XX_UCON_RXMODE_CPU
;
540 wr_regl(port
, S3C2410_UCON
, ucon
);
542 ourport
->rx_mode
= S3C24XX_RX_PIO
;
545 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port
*ourport
);
547 static irqreturn_t
s3c24xx_serial_rx_chars_dma(void *dev_id
)
549 unsigned int utrstat
, ufstat
, received
;
550 struct s3c24xx_uart_port
*ourport
= dev_id
;
551 struct uart_port
*port
= &ourport
->port
;
552 struct s3c24xx_uart_dma
*dma
= ourport
->dma
;
553 struct tty_struct
*tty
= tty_port_tty_get(&ourport
->port
.state
->port
);
554 struct tty_port
*t
= &port
->state
->port
;
556 struct dma_tx_state state
;
558 utrstat
= rd_regl(port
, S3C2410_UTRSTAT
);
559 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
561 spin_lock_irqsave(&port
->lock
, flags
);
563 if (!(utrstat
& S3C2410_UTRSTAT_TIMEOUT
)) {
564 s3c64xx_start_rx_dma(ourport
);
565 if (ourport
->rx_mode
== S3C24XX_RX_PIO
)
566 enable_rx_dma(ourport
);
570 if (ourport
->rx_mode
== S3C24XX_RX_DMA
) {
571 dmaengine_pause(dma
->rx_chan
);
572 dmaengine_tx_status(dma
->rx_chan
, dma
->rx_cookie
, &state
);
573 dmaengine_terminate_all(dma
->rx_chan
);
574 received
= dma
->rx_bytes_requested
- state
.residue
;
575 s3c24xx_uart_copy_rx_to_tty(ourport
, t
, received
);
577 enable_rx_pio(ourport
);
580 s3c24xx_serial_rx_drain_fifo(ourport
);
583 tty_flip_buffer_push(t
);
587 wr_regl(port
, S3C2410_UTRSTAT
, S3C2410_UTRSTAT_TIMEOUT
);
590 spin_unlock_irqrestore(&port
->lock
, flags
);
595 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port
*ourport
)
597 struct uart_port
*port
= &ourport
->port
;
598 unsigned int ufcon
, ch
, flag
, ufstat
, uerstat
;
599 unsigned int fifocnt
= 0;
600 int max_count
= port
->fifosize
;
602 while (max_count
-- > 0) {
604 * Receive all characters known to be in FIFO
605 * before reading FIFO level again
608 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
609 fifocnt
= s3c24xx_serial_rx_fifocnt(ourport
, ufstat
);
615 uerstat
= rd_regl(port
, S3C2410_UERSTAT
);
616 ch
= rd_regb(port
, S3C2410_URXH
);
618 if (port
->flags
& UPF_CONS_FLOW
) {
619 int txe
= s3c24xx_serial_txempty_nofifo(port
);
621 if (rx_enabled(port
)) {
623 rx_enabled(port
) = 0;
628 ufcon
= rd_regl(port
, S3C2410_UFCON
);
629 ufcon
|= S3C2410_UFCON_RESETRX
;
630 wr_regl(port
, S3C2410_UFCON
, ufcon
);
631 rx_enabled(port
) = 1;
638 /* insert the character into the buffer */
643 if (unlikely(uerstat
& S3C2410_UERSTAT_ANY
)) {
644 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
647 /* check for break */
648 if (uerstat
& S3C2410_UERSTAT_BREAK
) {
651 if (uart_handle_break(port
))
652 continue; /* Ignore character */
655 if (uerstat
& S3C2410_UERSTAT_FRAME
)
656 port
->icount
.frame
++;
657 if (uerstat
& S3C2410_UERSTAT_OVERRUN
)
658 port
->icount
.overrun
++;
660 uerstat
&= port
->read_status_mask
;
662 if (uerstat
& S3C2410_UERSTAT_BREAK
)
664 else if (uerstat
& S3C2410_UERSTAT_PARITY
)
666 else if (uerstat
& (S3C2410_UERSTAT_FRAME
|
667 S3C2410_UERSTAT_OVERRUN
))
671 if (uart_handle_sysrq_char(port
, ch
))
672 continue; /* Ignore character */
674 uart_insert_char(port
, uerstat
, S3C2410_UERSTAT_OVERRUN
,
678 tty_flip_buffer_push(&port
->state
->port
);
681 static irqreturn_t
s3c24xx_serial_rx_chars_pio(void *dev_id
)
683 struct s3c24xx_uart_port
*ourport
= dev_id
;
684 struct uart_port
*port
= &ourport
->port
;
687 spin_lock_irqsave(&port
->lock
, flags
);
688 s3c24xx_serial_rx_drain_fifo(ourport
);
689 spin_unlock_irqrestore(&port
->lock
, flags
);
695 static irqreturn_t
s3c24xx_serial_rx_chars(int irq
, void *dev_id
)
697 struct s3c24xx_uart_port
*ourport
= dev_id
;
699 if (ourport
->dma
&& ourport
->dma
->rx_chan
)
700 return s3c24xx_serial_rx_chars_dma(dev_id
);
701 return s3c24xx_serial_rx_chars_pio(dev_id
);
704 static irqreturn_t
s3c24xx_serial_tx_chars(int irq
, void *id
)
706 struct s3c24xx_uart_port
*ourport
= id
;
707 struct uart_port
*port
= &ourport
->port
;
708 struct circ_buf
*xmit
= &port
->state
->xmit
;
710 int count
, dma_count
= 0;
712 spin_lock_irqsave(&port
->lock
, flags
);
714 count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
716 if (ourport
->dma
&& ourport
->dma
->tx_chan
&&
717 count
>= ourport
->min_dma_size
) {
718 int align
= dma_get_cache_alignment() -
719 (xmit
->tail
& (dma_get_cache_alignment() - 1));
720 if (count
-align
>= ourport
->min_dma_size
) {
721 dma_count
= count
-align
;
727 wr_regb(port
, S3C2410_UTXH
, port
->x_char
);
733 /* if there isn't anything more to transmit, or the uart is now
734 * stopped, disable the uart and exit
737 if (uart_circ_empty(xmit
) || uart_tx_stopped(port
)) {
738 s3c24xx_serial_stop_tx(port
);
742 /* try and drain the buffer... */
744 if (count
> port
->fifosize
) {
745 count
= port
->fifosize
;
749 while (!uart_circ_empty(xmit
) && count
> 0) {
750 if (rd_regl(port
, S3C2410_UFSTAT
) & ourport
->info
->tx_fifofull
)
753 wr_regb(port
, S3C2410_UTXH
, xmit
->buf
[xmit
->tail
]);
754 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
759 if (!count
&& dma_count
) {
760 s3c24xx_serial_start_tx_dma(ourport
, dma_count
);
764 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
) {
765 spin_unlock(&port
->lock
);
766 uart_write_wakeup(port
);
767 spin_lock(&port
->lock
);
770 if (uart_circ_empty(xmit
))
771 s3c24xx_serial_stop_tx(port
);
774 spin_unlock_irqrestore(&port
->lock
, flags
);
778 /* interrupt handler for s3c64xx and later SoC's.*/
779 static irqreturn_t
s3c64xx_serial_handle_irq(int irq
, void *id
)
781 struct s3c24xx_uart_port
*ourport
= id
;
782 struct uart_port
*port
= &ourport
->port
;
783 unsigned int pend
= rd_regl(port
, S3C64XX_UINTP
);
784 irqreturn_t ret
= IRQ_HANDLED
;
786 if (pend
& S3C64XX_UINTM_RXD_MSK
) {
787 ret
= s3c24xx_serial_rx_chars(irq
, id
);
788 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_RXD_MSK
);
790 if (pend
& S3C64XX_UINTM_TXD_MSK
) {
791 ret
= s3c24xx_serial_tx_chars(irq
, id
);
792 wr_regl(port
, S3C64XX_UINTP
, S3C64XX_UINTM_TXD_MSK
);
797 static unsigned int s3c24xx_serial_tx_empty(struct uart_port
*port
)
799 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
800 unsigned long ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
801 unsigned long ufcon
= rd_regl(port
, S3C2410_UFCON
);
803 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
804 if ((ufstat
& info
->tx_fifomask
) != 0 ||
805 (ufstat
& info
->tx_fifofull
))
811 return s3c24xx_serial_txempty_nofifo(port
);
814 /* no modem control lines */
815 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port
*port
)
817 unsigned int umstat
= rd_regb(port
, S3C2410_UMSTAT
);
819 if (umstat
& S3C2410_UMSTAT_CTS
)
820 return TIOCM_CAR
| TIOCM_DSR
| TIOCM_CTS
;
822 return TIOCM_CAR
| TIOCM_DSR
;
825 static void s3c24xx_serial_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
827 unsigned int umcon
= rd_regl(port
, S3C2410_UMCON
);
829 if (mctrl
& TIOCM_RTS
)
830 umcon
|= S3C2410_UMCOM_RTS_LOW
;
832 umcon
&= ~S3C2410_UMCOM_RTS_LOW
;
834 wr_regl(port
, S3C2410_UMCON
, umcon
);
837 static void s3c24xx_serial_break_ctl(struct uart_port
*port
, int break_state
)
842 spin_lock_irqsave(&port
->lock
, flags
);
844 ucon
= rd_regl(port
, S3C2410_UCON
);
847 ucon
|= S3C2410_UCON_SBREAK
;
849 ucon
&= ~S3C2410_UCON_SBREAK
;
851 wr_regl(port
, S3C2410_UCON
, ucon
);
853 spin_unlock_irqrestore(&port
->lock
, flags
);
856 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port
*p
)
858 struct s3c24xx_uart_dma
*dma
= p
->dma
;
859 struct dma_slave_caps dma_caps
;
860 const char *reason
= NULL
;
863 /* Default slave configuration parameters */
864 dma
->rx_conf
.direction
= DMA_DEV_TO_MEM
;
865 dma
->rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
866 dma
->rx_conf
.src_addr
= p
->port
.mapbase
+ S3C2410_URXH
;
867 dma
->rx_conf
.src_maxburst
= 1;
869 dma
->tx_conf
.direction
= DMA_MEM_TO_DEV
;
870 dma
->tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
871 dma
->tx_conf
.dst_addr
= p
->port
.mapbase
+ S3C2410_UTXH
;
872 dma
->tx_conf
.dst_maxburst
= 1;
874 dma
->rx_chan
= dma_request_chan(p
->port
.dev
, "rx");
876 if (IS_ERR(dma
->rx_chan
)) {
877 reason
= "DMA RX channel request failed";
878 ret
= PTR_ERR(dma
->rx_chan
);
882 ret
= dma_get_slave_caps(dma
->rx_chan
, &dma_caps
);
884 dma_caps
.residue_granularity
< DMA_RESIDUE_GRANULARITY_BURST
) {
885 reason
= "insufficient DMA RX engine capabilities";
890 dmaengine_slave_config(dma
->rx_chan
, &dma
->rx_conf
);
892 dma
->tx_chan
= dma_request_chan(p
->port
.dev
, "tx");
893 if (IS_ERR(dma
->tx_chan
)) {
894 reason
= "DMA TX channel request failed";
895 ret
= PTR_ERR(dma
->tx_chan
);
899 ret
= dma_get_slave_caps(dma
->tx_chan
, &dma_caps
);
901 dma_caps
.residue_granularity
< DMA_RESIDUE_GRANULARITY_BURST
) {
902 reason
= "insufficient DMA TX engine capabilities";
907 dmaengine_slave_config(dma
->tx_chan
, &dma
->tx_conf
);
910 dma
->rx_size
= PAGE_SIZE
;
912 dma
->rx_buf
= kmalloc(dma
->rx_size
, GFP_KERNEL
);
918 dma
->rx_addr
= dma_map_single(p
->port
.dev
, dma
->rx_buf
,
919 dma
->rx_size
, DMA_FROM_DEVICE
);
920 if (dma_mapping_error(p
->port
.dev
, dma
->rx_addr
)) {
921 reason
= "DMA mapping error for RX buffer";
927 dma
->tx_addr
= dma_map_single(p
->port
.dev
, p
->port
.state
->xmit
.buf
,
928 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
929 if (dma_mapping_error(p
->port
.dev
, dma
->tx_addr
)) {
930 reason
= "DMA mapping error for TX buffer";
938 dma_unmap_single(p
->port
.dev
, dma
->rx_addr
, dma
->rx_size
,
943 dma_release_channel(dma
->tx_chan
);
945 dma_release_channel(dma
->rx_chan
);
948 dev_warn(p
->port
.dev
, "%s, DMA will not be used\n", reason
);
952 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port
*p
)
954 struct s3c24xx_uart_dma
*dma
= p
->dma
;
957 dmaengine_terminate_all(dma
->rx_chan
);
958 dma_unmap_single(p
->port
.dev
, dma
->rx_addr
,
959 dma
->rx_size
, DMA_FROM_DEVICE
);
961 dma_release_channel(dma
->rx_chan
);
966 dmaengine_terminate_all(dma
->tx_chan
);
967 dma_unmap_single(p
->port
.dev
, dma
->tx_addr
,
968 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
969 dma_release_channel(dma
->tx_chan
);
974 static void s3c24xx_serial_shutdown(struct uart_port
*port
)
976 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
978 if (ourport
->tx_claimed
) {
979 if (!s3c24xx_serial_has_interrupt_mask(port
))
980 free_irq(ourport
->tx_irq
, ourport
);
981 tx_enabled(port
) = 0;
982 ourport
->tx_claimed
= 0;
983 ourport
->tx_mode
= 0;
986 if (ourport
->rx_claimed
) {
987 if (!s3c24xx_serial_has_interrupt_mask(port
))
988 free_irq(ourport
->rx_irq
, ourport
);
989 ourport
->rx_claimed
= 0;
990 rx_enabled(port
) = 0;
993 /* Clear pending interrupts and mask all interrupts */
994 if (s3c24xx_serial_has_interrupt_mask(port
)) {
995 free_irq(port
->irq
, ourport
);
997 wr_regl(port
, S3C64XX_UINTP
, 0xf);
998 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1002 s3c24xx_serial_release_dma(ourport
);
1004 ourport
->tx_in_progress
= 0;
1007 static int s3c24xx_serial_startup(struct uart_port
*port
)
1009 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1012 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1013 port
, (unsigned long long)port
->mapbase
, port
->membase
);
1015 rx_enabled(port
) = 1;
1017 ret
= request_irq(ourport
->rx_irq
, s3c24xx_serial_rx_chars
, 0,
1018 s3c24xx_serial_portname(port
), ourport
);
1021 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->rx_irq
);
1025 ourport
->rx_claimed
= 1;
1027 dbg("requesting tx irq...\n");
1029 tx_enabled(port
) = 1;
1031 ret
= request_irq(ourport
->tx_irq
, s3c24xx_serial_tx_chars
, 0,
1032 s3c24xx_serial_portname(port
), ourport
);
1035 dev_err(port
->dev
, "cannot get irq %d\n", ourport
->tx_irq
);
1039 ourport
->tx_claimed
= 1;
1041 dbg("s3c24xx_serial_startup ok\n");
1043 /* the port reset code should have done the correct
1044 * register setup for the port controls */
1049 s3c24xx_serial_shutdown(port
);
1053 static int s3c64xx_serial_startup(struct uart_port
*port
)
1055 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1056 unsigned long flags
;
1060 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1061 port
, (unsigned long long)port
->mapbase
, port
->membase
);
1063 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1065 ret
= s3c24xx_serial_request_dma(ourport
);
1067 devm_kfree(port
->dev
, ourport
->dma
);
1068 ourport
->dma
= NULL
;
1072 ret
= request_irq(port
->irq
, s3c64xx_serial_handle_irq
, IRQF_SHARED
,
1073 s3c24xx_serial_portname(port
), ourport
);
1075 dev_err(port
->dev
, "cannot get irq %d\n", port
->irq
);
1079 /* For compatibility with s3c24xx Soc's */
1080 rx_enabled(port
) = 1;
1081 ourport
->rx_claimed
= 1;
1082 tx_enabled(port
) = 0;
1083 ourport
->tx_claimed
= 1;
1085 spin_lock_irqsave(&port
->lock
, flags
);
1087 ufcon
= rd_regl(port
, S3C2410_UFCON
);
1088 ufcon
|= S3C2410_UFCON_RESETRX
| S5PV210_UFCON_RXTRIG8
;
1089 if (!uart_console(port
))
1090 ufcon
|= S3C2410_UFCON_RESETTX
;
1091 wr_regl(port
, S3C2410_UFCON
, ufcon
);
1093 enable_rx_pio(ourport
);
1095 spin_unlock_irqrestore(&port
->lock
, flags
);
1097 /* Enable Rx Interrupt */
1098 s3c24xx_clear_bit(port
, S3C64XX_UINTM_RXD
, S3C64XX_UINTM
);
1100 dbg("s3c64xx_serial_startup ok\n");
1104 /* power power management control */
1106 static void s3c24xx_serial_pm(struct uart_port
*port
, unsigned int level
,
1109 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1110 int timeout
= 10000;
1112 ourport
->pm_level
= level
;
1116 while (--timeout
&& !s3c24xx_serial_txempty_nofifo(port
))
1119 if (!IS_ERR(ourport
->baudclk
))
1120 clk_disable_unprepare(ourport
->baudclk
);
1122 clk_disable_unprepare(ourport
->clk
);
1126 clk_prepare_enable(ourport
->clk
);
1128 if (!IS_ERR(ourport
->baudclk
))
1129 clk_prepare_enable(ourport
->baudclk
);
1133 dev_err(port
->dev
, "s3c24xx_serial: unknown pm %d\n", level
);
1137 /* baud rate calculation
1139 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1140 * of different sources, including the peripheral clock ("pclk") and an
1141 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1142 * with a programmable extra divisor.
1144 * The following code goes through the clock sources, and calculates the
1145 * baud clocks (and the resultant actual baud rates) and then tries to
1146 * pick the closest one and select that.
1150 #define MAX_CLK_NAME_LENGTH 15
1152 static inline int s3c24xx_serial_getsource(struct uart_port
*port
)
1154 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1157 if (info
->num_clks
== 1)
1160 ucon
= rd_regl(port
, S3C2410_UCON
);
1161 ucon
&= info
->clksel_mask
;
1162 return ucon
>> info
->clksel_shift
;
1165 static void s3c24xx_serial_setsource(struct uart_port
*port
,
1166 unsigned int clk_sel
)
1168 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1171 if (info
->num_clks
== 1)
1174 ucon
= rd_regl(port
, S3C2410_UCON
);
1175 if ((ucon
& info
->clksel_mask
) >> info
->clksel_shift
== clk_sel
)
1178 ucon
&= ~info
->clksel_mask
;
1179 ucon
|= clk_sel
<< info
->clksel_shift
;
1180 wr_regl(port
, S3C2410_UCON
, ucon
);
1183 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port
*ourport
,
1184 unsigned int req_baud
, struct clk
**best_clk
,
1185 unsigned int *clk_num
)
1187 struct s3c24xx_uart_info
*info
= ourport
->info
;
1190 unsigned int cnt
, baud
, quot
, clk_sel
, best_quot
= 0;
1191 char clkname
[MAX_CLK_NAME_LENGTH
];
1192 int calc_deviation
, deviation
= (1 << 30) - 1;
1194 clk_sel
= (ourport
->cfg
->clk_sel
) ? ourport
->cfg
->clk_sel
:
1195 ourport
->info
->def_clk_sel
;
1196 for (cnt
= 0; cnt
< info
->num_clks
; cnt
++) {
1197 if (!(clk_sel
& (1 << cnt
)))
1200 sprintf(clkname
, "clk_uart_baud%d", cnt
);
1201 clk
= clk_get(ourport
->port
.dev
, clkname
);
1205 rate
= clk_get_rate(clk
);
1209 if (ourport
->info
->has_divslot
) {
1210 unsigned long div
= rate
/ req_baud
;
1212 /* The UDIVSLOT register on the newer UARTs allows us to
1213 * get a divisor adjustment of 1/16th on the baud clock.
1215 * We don't keep the UDIVSLOT value (the 16ths we
1216 * calculated by not multiplying the baud by 16) as it
1217 * is easy enough to recalculate.
1223 quot
= (rate
+ (8 * req_baud
)) / (16 * req_baud
);
1224 baud
= rate
/ (quot
* 16);
1228 calc_deviation
= req_baud
- baud
;
1229 if (calc_deviation
< 0)
1230 calc_deviation
= -calc_deviation
;
1232 if (calc_deviation
< deviation
) {
1236 deviation
= calc_deviation
;
1245 * This table takes the fractional value of the baud divisor and gives
1246 * the recommended setting for the UDIVSLOT register.
1248 static u16 udivslot_table
[16] = {
1267 static void s3c24xx_serial_set_termios(struct uart_port
*port
,
1268 struct ktermios
*termios
,
1269 struct ktermios
*old
)
1271 struct s3c2410_uartcfg
*cfg
= s3c24xx_port_to_cfg(port
);
1272 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1273 struct clk
*clk
= ERR_PTR(-EINVAL
);
1274 unsigned long flags
;
1275 unsigned int baud
, quot
, clk_sel
= 0;
1278 unsigned int udivslot
= 0;
1281 * We don't support modem control lines.
1283 termios
->c_cflag
&= ~(HUPCL
| CMSPAR
);
1284 termios
->c_cflag
|= CLOCAL
;
1287 * Ask the core to calculate the divisor for us.
1290 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 115200*8);
1291 quot
= s3c24xx_serial_getclk(ourport
, baud
, &clk
, &clk_sel
);
1292 if (baud
== 38400 && (port
->flags
& UPF_SPD_MASK
) == UPF_SPD_CUST
)
1293 quot
= port
->custom_divisor
;
1297 /* check to see if we need to change clock source */
1299 if (ourport
->baudclk
!= clk
) {
1300 clk_prepare_enable(clk
);
1302 s3c24xx_serial_setsource(port
, clk_sel
);
1304 if (!IS_ERR(ourport
->baudclk
)) {
1305 clk_disable_unprepare(ourport
->baudclk
);
1306 ourport
->baudclk
= ERR_PTR(-EINVAL
);
1309 ourport
->baudclk
= clk
;
1310 ourport
->baudclk_rate
= clk
? clk_get_rate(clk
) : 0;
1313 if (ourport
->info
->has_divslot
) {
1314 unsigned int div
= ourport
->baudclk_rate
/ baud
;
1316 if (cfg
->has_fracval
) {
1317 udivslot
= (div
& 15);
1318 dbg("fracval = %04x\n", udivslot
);
1320 udivslot
= udivslot_table
[div
& 15];
1321 dbg("udivslot = %04x (div %d)\n", udivslot
, div
& 15);
1325 switch (termios
->c_cflag
& CSIZE
) {
1327 dbg("config: 5bits/char\n");
1328 ulcon
= S3C2410_LCON_CS5
;
1331 dbg("config: 6bits/char\n");
1332 ulcon
= S3C2410_LCON_CS6
;
1335 dbg("config: 7bits/char\n");
1336 ulcon
= S3C2410_LCON_CS7
;
1340 dbg("config: 8bits/char\n");
1341 ulcon
= S3C2410_LCON_CS8
;
1345 /* preserve original lcon IR settings */
1346 ulcon
|= (cfg
->ulcon
& S3C2410_LCON_IRM
);
1348 if (termios
->c_cflag
& CSTOPB
)
1349 ulcon
|= S3C2410_LCON_STOPB
;
1351 if (termios
->c_cflag
& PARENB
) {
1352 if (termios
->c_cflag
& PARODD
)
1353 ulcon
|= S3C2410_LCON_PODD
;
1355 ulcon
|= S3C2410_LCON_PEVEN
;
1357 ulcon
|= S3C2410_LCON_PNONE
;
1360 spin_lock_irqsave(&port
->lock
, flags
);
1362 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1363 ulcon
, quot
, udivslot
);
1365 wr_regl(port
, S3C2410_ULCON
, ulcon
);
1366 wr_regl(port
, S3C2410_UBRDIV
, quot
);
1368 umcon
= rd_regl(port
, S3C2410_UMCON
);
1369 if (termios
->c_cflag
& CRTSCTS
) {
1370 umcon
|= S3C2410_UMCOM_AFC
;
1371 /* Disable RTS when RX FIFO contains 63 bytes */
1372 umcon
&= ~S3C2412_UMCON_AFC_8
;
1374 umcon
&= ~S3C2410_UMCOM_AFC
;
1376 wr_regl(port
, S3C2410_UMCON
, umcon
);
1378 if (ourport
->info
->has_divslot
)
1379 wr_regl(port
, S3C2443_DIVSLOT
, udivslot
);
1381 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1382 rd_regl(port
, S3C2410_ULCON
),
1383 rd_regl(port
, S3C2410_UCON
),
1384 rd_regl(port
, S3C2410_UFCON
));
1387 * Update the per-port timeout.
1389 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1392 * Which character status flags are we interested in?
1394 port
->read_status_mask
= S3C2410_UERSTAT_OVERRUN
;
1395 if (termios
->c_iflag
& INPCK
)
1396 port
->read_status_mask
|= S3C2410_UERSTAT_FRAME
|
1397 S3C2410_UERSTAT_PARITY
;
1399 * Which character status flags should we ignore?
1401 port
->ignore_status_mask
= 0;
1402 if (termios
->c_iflag
& IGNPAR
)
1403 port
->ignore_status_mask
|= S3C2410_UERSTAT_OVERRUN
;
1404 if (termios
->c_iflag
& IGNBRK
&& termios
->c_iflag
& IGNPAR
)
1405 port
->ignore_status_mask
|= S3C2410_UERSTAT_FRAME
;
1408 * Ignore all characters if CREAD is not set.
1410 if ((termios
->c_cflag
& CREAD
) == 0)
1411 port
->ignore_status_mask
|= RXSTAT_DUMMY_READ
;
1413 spin_unlock_irqrestore(&port
->lock
, flags
);
1416 static const char *s3c24xx_serial_type(struct uart_port
*port
)
1418 switch (port
->type
) {
1426 return "S3C6400/10";
1432 #define MAP_SIZE (0x100)
1434 static void s3c24xx_serial_release_port(struct uart_port
*port
)
1436 release_mem_region(port
->mapbase
, MAP_SIZE
);
1439 static int s3c24xx_serial_request_port(struct uart_port
*port
)
1441 const char *name
= s3c24xx_serial_portname(port
);
1442 return request_mem_region(port
->mapbase
, MAP_SIZE
, name
) ? 0 : -EBUSY
;
1445 static void s3c24xx_serial_config_port(struct uart_port
*port
, int flags
)
1447 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1449 if (flags
& UART_CONFIG_TYPE
&&
1450 s3c24xx_serial_request_port(port
) == 0)
1451 port
->type
= info
->type
;
1455 * verify the new serial_struct (for TIOCSSERIAL).
1458 s3c24xx_serial_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1460 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1462 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= info
->type
)
1469 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1471 static struct console s3c24xx_serial_console
;
1473 static int __init
s3c24xx_serial_console_init(void)
1475 register_console(&s3c24xx_serial_console
);
1478 console_initcall(s3c24xx_serial_console_init
);
1480 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1482 #define S3C24XX_SERIAL_CONSOLE NULL
1485 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1486 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
);
1487 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
1491 static struct uart_ops s3c24xx_serial_ops
= {
1492 .pm
= s3c24xx_serial_pm
,
1493 .tx_empty
= s3c24xx_serial_tx_empty
,
1494 .get_mctrl
= s3c24xx_serial_get_mctrl
,
1495 .set_mctrl
= s3c24xx_serial_set_mctrl
,
1496 .stop_tx
= s3c24xx_serial_stop_tx
,
1497 .start_tx
= s3c24xx_serial_start_tx
,
1498 .stop_rx
= s3c24xx_serial_stop_rx
,
1499 .break_ctl
= s3c24xx_serial_break_ctl
,
1500 .startup
= s3c24xx_serial_startup
,
1501 .shutdown
= s3c24xx_serial_shutdown
,
1502 .set_termios
= s3c24xx_serial_set_termios
,
1503 .type
= s3c24xx_serial_type
,
1504 .release_port
= s3c24xx_serial_release_port
,
1505 .request_port
= s3c24xx_serial_request_port
,
1506 .config_port
= s3c24xx_serial_config_port
,
1507 .verify_port
= s3c24xx_serial_verify_port
,
1508 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1509 .poll_get_char
= s3c24xx_serial_get_poll_char
,
1510 .poll_put_char
= s3c24xx_serial_put_poll_char
,
1514 static struct uart_driver s3c24xx_uart_drv
= {
1515 .owner
= THIS_MODULE
,
1516 .driver_name
= "s3c2410_serial",
1517 .nr
= CONFIG_SERIAL_SAMSUNG_UARTS
,
1518 .cons
= S3C24XX_SERIAL_CONSOLE
,
1519 .dev_name
= S3C24XX_SERIAL_NAME
,
1520 .major
= S3C24XX_SERIAL_MAJOR
,
1521 .minor
= S3C24XX_SERIAL_MINOR
,
1524 #define __PORT_LOCK_UNLOCKED(i) \
1525 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1526 static struct s3c24xx_uart_port
1527 s3c24xx_serial_ports
[CONFIG_SERIAL_SAMSUNG_UARTS
] = {
1530 .lock
= __PORT_LOCK_UNLOCKED(0),
1534 .ops
= &s3c24xx_serial_ops
,
1535 .flags
= UPF_BOOT_AUTOCONF
,
1541 .lock
= __PORT_LOCK_UNLOCKED(1),
1545 .ops
= &s3c24xx_serial_ops
,
1546 .flags
= UPF_BOOT_AUTOCONF
,
1550 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1554 .lock
= __PORT_LOCK_UNLOCKED(2),
1558 .ops
= &s3c24xx_serial_ops
,
1559 .flags
= UPF_BOOT_AUTOCONF
,
1564 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1567 .lock
= __PORT_LOCK_UNLOCKED(3),
1571 .ops
= &s3c24xx_serial_ops
,
1572 .flags
= UPF_BOOT_AUTOCONF
,
1578 #undef __PORT_LOCK_UNLOCKED
1580 /* s3c24xx_serial_resetport
1582 * reset the fifos and other the settings.
1585 static void s3c24xx_serial_resetport(struct uart_port
*port
,
1586 struct s3c2410_uartcfg
*cfg
)
1588 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1589 unsigned long ucon
= rd_regl(port
, S3C2410_UCON
);
1590 unsigned int ucon_mask
;
1592 ucon_mask
= info
->clksel_mask
;
1593 if (info
->type
== PORT_S3C2440
)
1594 ucon_mask
|= S3C2440_UCON0_DIVMASK
;
1597 wr_regl(port
, S3C2410_UCON
, ucon
| cfg
->ucon
);
1599 /* reset both fifos */
1600 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
| S3C2410_UFCON_RESETBOTH
);
1601 wr_regl(port
, S3C2410_UFCON
, cfg
->ufcon
);
1603 /* some delay is required after fifo reset */
1608 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1610 static int s3c24xx_serial_cpufreq_transition(struct notifier_block
*nb
,
1611 unsigned long val
, void *data
)
1613 struct s3c24xx_uart_port
*port
;
1614 struct uart_port
*uport
;
1616 port
= container_of(nb
, struct s3c24xx_uart_port
, freq_transition
);
1617 uport
= &port
->port
;
1619 /* check to see if port is enabled */
1621 if (port
->pm_level
!= 0)
1624 /* try and work out if the baudrate is changing, we can detect
1625 * a change in rate, but we do not have support for detecting
1626 * a disturbance in the clock-rate over the change.
1629 if (IS_ERR(port
->baudclk
))
1632 if (port
->baudclk_rate
== clk_get_rate(port
->baudclk
))
1635 if (val
== CPUFREQ_PRECHANGE
) {
1636 /* we should really shut the port down whilst the
1637 * frequency change is in progress. */
1639 } else if (val
== CPUFREQ_POSTCHANGE
) {
1640 struct ktermios
*termios
;
1641 struct tty_struct
*tty
;
1643 if (uport
->state
== NULL
)
1646 tty
= uport
->state
->port
.tty
;
1651 termios
= &tty
->termios
;
1653 if (termios
== NULL
) {
1654 dev_warn(uport
->dev
, "%s: no termios?\n", __func__
);
1658 s3c24xx_serial_set_termios(uport
, termios
, NULL
);
1666 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1668 port
->freq_transition
.notifier_call
= s3c24xx_serial_cpufreq_transition
;
1670 return cpufreq_register_notifier(&port
->freq_transition
,
1671 CPUFREQ_TRANSITION_NOTIFIER
);
1675 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1677 cpufreq_unregister_notifier(&port
->freq_transition
,
1678 CPUFREQ_TRANSITION_NOTIFIER
);
1683 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port
*port
)
1689 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port
*port
)
1694 /* s3c24xx_serial_init_port
1696 * initialise a single serial port from the platform device given
1699 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port
*ourport
,
1700 struct platform_device
*platdev
)
1702 struct uart_port
*port
= &ourport
->port
;
1703 struct s3c2410_uartcfg
*cfg
= ourport
->cfg
;
1704 struct resource
*res
;
1707 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port
, platdev
);
1709 if (platdev
== NULL
)
1712 if (port
->mapbase
!= 0)
1715 /* setup info for port */
1716 port
->dev
= &platdev
->dev
;
1718 /* Startup sequence is different for s3c64xx and higher SoC's */
1719 if (s3c24xx_serial_has_interrupt_mask(port
))
1720 s3c24xx_serial_ops
.startup
= s3c64xx_serial_startup
;
1724 if (cfg
->uart_flags
& UPF_CONS_FLOW
) {
1725 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1726 port
->flags
|= UPF_CONS_FLOW
;
1729 /* sort our the physical and virtual addresses for each UART */
1731 res
= platform_get_resource(platdev
, IORESOURCE_MEM
, 0);
1733 dev_err(port
->dev
, "failed to find memory resource for uart\n");
1737 dbg("resource %pR)\n", res
);
1739 port
->membase
= devm_ioremap(port
->dev
, res
->start
, resource_size(res
));
1740 if (!port
->membase
) {
1741 dev_err(port
->dev
, "failed to remap controller address\n");
1745 port
->mapbase
= res
->start
;
1746 ret
= platform_get_irq(platdev
, 0);
1751 ourport
->rx_irq
= ret
;
1752 ourport
->tx_irq
= ret
+ 1;
1755 ret
= platform_get_irq(platdev
, 1);
1757 ourport
->tx_irq
= ret
;
1759 * DMA is currently supported only on DT platforms, if DMA properties
1762 if (platdev
->dev
.of_node
&& of_find_property(platdev
->dev
.of_node
,
1764 ourport
->dma
= devm_kzalloc(port
->dev
,
1765 sizeof(*ourport
->dma
),
1767 if (!ourport
->dma
) {
1773 ourport
->clk
= clk_get(&platdev
->dev
, "uart");
1774 if (IS_ERR(ourport
->clk
)) {
1775 pr_err("%s: Controller clock not found\n",
1776 dev_name(&platdev
->dev
));
1777 ret
= PTR_ERR(ourport
->clk
);
1781 ret
= clk_prepare_enable(ourport
->clk
);
1783 pr_err("uart: clock failed to prepare+enable: %d\n", ret
);
1784 clk_put(ourport
->clk
);
1788 /* Keep all interrupts masked and cleared */
1789 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1790 wr_regl(port
, S3C64XX_UINTM
, 0xf);
1791 wr_regl(port
, S3C64XX_UINTP
, 0xf);
1792 wr_regl(port
, S3C64XX_UINTSP
, 0xf);
1795 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1796 &port
->mapbase
, port
->membase
, port
->irq
,
1797 ourport
->rx_irq
, ourport
->tx_irq
, port
->uartclk
);
1799 /* reset the fifos (and setup the uart) */
1800 s3c24xx_serial_resetport(port
, cfg
);
1809 /* Device driver serial port probe */
1811 static const struct of_device_id s3c24xx_uart_dt_match
[];
1812 static int probe_index
;
1814 static inline struct s3c24xx_serial_drv_data
*s3c24xx_get_driver_data(
1815 struct platform_device
*pdev
)
1818 if (pdev
->dev
.of_node
) {
1819 const struct of_device_id
*match
;
1820 match
= of_match_node(s3c24xx_uart_dt_match
, pdev
->dev
.of_node
);
1821 return (struct s3c24xx_serial_drv_data
*)match
->data
;
1824 return (struct s3c24xx_serial_drv_data
*)
1825 platform_get_device_id(pdev
)->driver_data
;
1828 static int s3c24xx_serial_probe(struct platform_device
*pdev
)
1830 struct device_node
*np
= pdev
->dev
.of_node
;
1831 struct s3c24xx_uart_port
*ourport
;
1832 int index
= probe_index
;
1836 ret
= of_alias_get_id(np
, "serial");
1841 dbg("s3c24xx_serial_probe(%p) %d\n", pdev
, index
);
1843 if (index
>= ARRAY_SIZE(s3c24xx_serial_ports
)) {
1844 dev_err(&pdev
->dev
, "serial%d out of range\n", index
);
1847 ourport
= &s3c24xx_serial_ports
[index
];
1849 ourport
->drv_data
= s3c24xx_get_driver_data(pdev
);
1850 if (!ourport
->drv_data
) {
1851 dev_err(&pdev
->dev
, "could not find driver data\n");
1855 ourport
->baudclk
= ERR_PTR(-EINVAL
);
1856 ourport
->info
= ourport
->drv_data
->info
;
1857 ourport
->cfg
= (dev_get_platdata(&pdev
->dev
)) ?
1858 dev_get_platdata(&pdev
->dev
) :
1859 ourport
->drv_data
->def_cfg
;
1862 of_property_read_u32(np
,
1863 "samsung,uart-fifosize", &ourport
->port
.fifosize
);
1865 if (ourport
->drv_data
->fifosize
[index
])
1866 ourport
->port
.fifosize
= ourport
->drv_data
->fifosize
[index
];
1867 else if (ourport
->info
->fifosize
)
1868 ourport
->port
.fifosize
= ourport
->info
->fifosize
;
1871 * DMA transfers must be aligned at least to cache line size,
1872 * so find minimal transfer size suitable for DMA mode
1874 ourport
->min_dma_size
= max_t(int, ourport
->port
.fifosize
,
1875 dma_get_cache_alignment());
1877 dbg("%s: initialising port %p...\n", __func__
, ourport
);
1879 ret
= s3c24xx_serial_init_port(ourport
, pdev
);
1883 if (!s3c24xx_uart_drv
.state
) {
1884 ret
= uart_register_driver(&s3c24xx_uart_drv
);
1886 pr_err("Failed to register Samsung UART driver\n");
1891 dbg("%s: adding port\n", __func__
);
1892 uart_add_one_port(&s3c24xx_uart_drv
, &ourport
->port
);
1893 platform_set_drvdata(pdev
, &ourport
->port
);
1896 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1897 * so that a potential re-enablement through the pm-callback overlaps
1898 * and keeps the clock enabled in this case.
1900 clk_disable_unprepare(ourport
->clk
);
1902 ret
= s3c24xx_serial_cpufreq_register(ourport
);
1904 dev_err(&pdev
->dev
, "failed to add cpufreq notifier\n");
1911 static int s3c24xx_serial_remove(struct platform_device
*dev
)
1913 struct uart_port
*port
= s3c24xx_dev_to_port(&dev
->dev
);
1916 s3c24xx_serial_cpufreq_deregister(to_ourport(port
));
1917 uart_remove_one_port(&s3c24xx_uart_drv
, port
);
1920 uart_unregister_driver(&s3c24xx_uart_drv
);
1925 /* UART power management code */
1926 #ifdef CONFIG_PM_SLEEP
1927 static int s3c24xx_serial_suspend(struct device
*dev
)
1929 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1932 uart_suspend_port(&s3c24xx_uart_drv
, port
);
1937 static int s3c24xx_serial_resume(struct device
*dev
)
1939 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1940 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1943 clk_prepare_enable(ourport
->clk
);
1944 s3c24xx_serial_resetport(port
, s3c24xx_port_to_cfg(port
));
1945 clk_disable_unprepare(ourport
->clk
);
1947 uart_resume_port(&s3c24xx_uart_drv
, port
);
1953 static int s3c24xx_serial_resume_noirq(struct device
*dev
)
1955 struct uart_port
*port
= s3c24xx_dev_to_port(dev
);
1956 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
1959 /* restore IRQ mask */
1960 if (s3c24xx_serial_has_interrupt_mask(port
)) {
1961 unsigned int uintm
= 0xf;
1962 if (tx_enabled(port
))
1963 uintm
&= ~S3C64XX_UINTM_TXD_MSK
;
1964 if (rx_enabled(port
))
1965 uintm
&= ~S3C64XX_UINTM_RXD_MSK
;
1966 clk_prepare_enable(ourport
->clk
);
1967 wr_regl(port
, S3C64XX_UINTM
, uintm
);
1968 clk_disable_unprepare(ourport
->clk
);
1975 static const struct dev_pm_ops s3c24xx_serial_pm_ops
= {
1976 .suspend
= s3c24xx_serial_suspend
,
1977 .resume
= s3c24xx_serial_resume
,
1978 .resume_noirq
= s3c24xx_serial_resume_noirq
,
1980 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1982 #else /* !CONFIG_PM_SLEEP */
1984 #define SERIAL_SAMSUNG_PM_OPS NULL
1985 #endif /* CONFIG_PM_SLEEP */
1989 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1991 static struct uart_port
*cons_uart
;
1994 s3c24xx_serial_console_txrdy(struct uart_port
*port
, unsigned int ufcon
)
1996 struct s3c24xx_uart_info
*info
= s3c24xx_port_to_info(port
);
1997 unsigned long ufstat
, utrstat
;
1999 if (ufcon
& S3C2410_UFCON_FIFOMODE
) {
2000 /* fifo mode - check amount of data in fifo registers... */
2002 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
2003 return (ufstat
& info
->tx_fifofull
) ? 0 : 1;
2006 /* in non-fifo mode, we go and use the tx buffer empty */
2008 utrstat
= rd_regl(port
, S3C2410_UTRSTAT
);
2009 return (utrstat
& S3C2410_UTRSTAT_TXE
) ? 1 : 0;
2013 s3c24xx_port_configured(unsigned int ucon
)
2015 /* consider the serial port configured if the tx/rx mode set */
2016 return (ucon
& 0xf) != 0;
2019 #ifdef CONFIG_CONSOLE_POLL
2021 * Console polling routines for writing and reading from the uart while
2022 * in an interrupt or debug context.
2025 static int s3c24xx_serial_get_poll_char(struct uart_port
*port
)
2027 struct s3c24xx_uart_port
*ourport
= to_ourport(port
);
2028 unsigned int ufstat
;
2030 ufstat
= rd_regl(port
, S3C2410_UFSTAT
);
2031 if (s3c24xx_serial_rx_fifocnt(ourport
, ufstat
) == 0)
2032 return NO_POLL_CHAR
;
2034 return rd_regb(port
, S3C2410_URXH
);
2037 static void s3c24xx_serial_put_poll_char(struct uart_port
*port
,
2040 unsigned int ufcon
= rd_regl(port
, S3C2410_UFCON
);
2041 unsigned int ucon
= rd_regl(port
, S3C2410_UCON
);
2043 /* not possible to xmit on unconfigured port */
2044 if (!s3c24xx_port_configured(ucon
))
2047 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
2049 wr_regb(port
, S3C2410_UTXH
, c
);
2052 #endif /* CONFIG_CONSOLE_POLL */
2055 s3c24xx_serial_console_putchar(struct uart_port
*port
, int ch
)
2057 unsigned int ufcon
= rd_regl(port
, S3C2410_UFCON
);
2059 while (!s3c24xx_serial_console_txrdy(port
, ufcon
))
2061 wr_regb(port
, S3C2410_UTXH
, ch
);
2065 s3c24xx_serial_console_write(struct console
*co
, const char *s
,
2068 unsigned int ucon
= rd_regl(cons_uart
, S3C2410_UCON
);
2070 /* not possible to xmit on unconfigured port */
2071 if (!s3c24xx_port_configured(ucon
))
2074 uart_console_write(cons_uart
, s
, count
, s3c24xx_serial_console_putchar
);
2078 s3c24xx_serial_get_options(struct uart_port
*port
, int *baud
,
2079 int *parity
, int *bits
)
2084 unsigned int ubrdiv
;
2086 unsigned int clk_sel
;
2087 char clk_name
[MAX_CLK_NAME_LENGTH
];
2089 ulcon
= rd_regl(port
, S3C2410_ULCON
);
2090 ucon
= rd_regl(port
, S3C2410_UCON
);
2091 ubrdiv
= rd_regl(port
, S3C2410_UBRDIV
);
2093 dbg("s3c24xx_serial_get_options: port=%p\n"
2094 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2095 port
, ulcon
, ucon
, ubrdiv
);
2097 if (s3c24xx_port_configured(ucon
)) {
2098 switch (ulcon
& S3C2410_LCON_CSMASK
) {
2099 case S3C2410_LCON_CS5
:
2102 case S3C2410_LCON_CS6
:
2105 case S3C2410_LCON_CS7
:
2108 case S3C2410_LCON_CS8
:
2114 switch (ulcon
& S3C2410_LCON_PMASK
) {
2115 case S3C2410_LCON_PEVEN
:
2119 case S3C2410_LCON_PODD
:
2123 case S3C2410_LCON_PNONE
:
2128 /* now calculate the baud rate */
2130 clk_sel
= s3c24xx_serial_getsource(port
);
2131 sprintf(clk_name
, "clk_uart_baud%d", clk_sel
);
2133 clk
= clk_get(port
->dev
, clk_name
);
2135 rate
= clk_get_rate(clk
);
2139 *baud
= rate
/ (16 * (ubrdiv
+ 1));
2140 dbg("calculated baud %d\n", *baud
);
2146 s3c24xx_serial_console_setup(struct console
*co
, char *options
)
2148 struct uart_port
*port
;
2154 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2155 co
, co
->index
, options
);
2157 /* is this a valid port */
2159 if (co
->index
== -1 || co
->index
>= CONFIG_SERIAL_SAMSUNG_UARTS
)
2162 port
= &s3c24xx_serial_ports
[co
->index
].port
;
2164 /* is the port configured? */
2166 if (port
->mapbase
== 0x0)
2171 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port
, co
->index
);
2174 * Check whether an invalid uart number has been specified, and
2175 * if so, search for the first available port that does have
2179 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
2181 s3c24xx_serial_get_options(port
, &baud
, &parity
, &bits
);
2183 dbg("s3c24xx_serial_console_setup: baud %d\n", baud
);
2185 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
2188 static struct console s3c24xx_serial_console
= {
2189 .name
= S3C24XX_SERIAL_NAME
,
2190 .device
= uart_console_device
,
2191 .flags
= CON_PRINTBUFFER
,
2193 .write
= s3c24xx_serial_console_write
,
2194 .setup
= s3c24xx_serial_console_setup
,
2195 .data
= &s3c24xx_uart_drv
,
2197 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2199 #ifdef CONFIG_CPU_S3C2410
2200 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data
= {
2201 .info
= &(struct s3c24xx_uart_info
) {
2202 .name
= "Samsung S3C2410 UART",
2203 .type
= PORT_S3C2410
,
2205 .rx_fifomask
= S3C2410_UFSTAT_RXMASK
,
2206 .rx_fifoshift
= S3C2410_UFSTAT_RXSHIFT
,
2207 .rx_fifofull
= S3C2410_UFSTAT_RXFULL
,
2208 .tx_fifofull
= S3C2410_UFSTAT_TXFULL
,
2209 .tx_fifomask
= S3C2410_UFSTAT_TXMASK
,
2210 .tx_fifoshift
= S3C2410_UFSTAT_TXSHIFT
,
2211 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
2213 .clksel_mask
= S3C2410_UCON_CLKMASK
,
2214 .clksel_shift
= S3C2410_UCON_CLKSHIFT
,
2216 .def_cfg
= &(struct s3c2410_uartcfg
) {
2217 .ucon
= S3C2410_UCON_DEFAULT
,
2218 .ufcon
= S3C2410_UFCON_DEFAULT
,
2221 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2223 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2226 #ifdef CONFIG_CPU_S3C2412
2227 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data
= {
2228 .info
= &(struct s3c24xx_uart_info
) {
2229 .name
= "Samsung S3C2412 UART",
2230 .type
= PORT_S3C2412
,
2233 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
2234 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
2235 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
2236 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
2237 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
2238 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
2239 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
2241 .clksel_mask
= S3C2412_UCON_CLKMASK
,
2242 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
2244 .def_cfg
= &(struct s3c2410_uartcfg
) {
2245 .ucon
= S3C2410_UCON_DEFAULT
,
2246 .ufcon
= S3C2410_UFCON_DEFAULT
,
2249 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2251 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2254 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2255 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2256 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data
= {
2257 .info
= &(struct s3c24xx_uart_info
) {
2258 .name
= "Samsung S3C2440 UART",
2259 .type
= PORT_S3C2440
,
2262 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
2263 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
2264 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
2265 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
2266 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
2267 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
2268 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
2270 .clksel_mask
= S3C2412_UCON_CLKMASK
,
2271 .clksel_shift
= S3C2412_UCON_CLKSHIFT
,
2273 .def_cfg
= &(struct s3c2410_uartcfg
) {
2274 .ucon
= S3C2410_UCON_DEFAULT
,
2275 .ufcon
= S3C2410_UFCON_DEFAULT
,
2278 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2280 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2283 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2284 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data
= {
2285 .info
= &(struct s3c24xx_uart_info
) {
2286 .name
= "Samsung S3C6400 UART",
2287 .type
= PORT_S3C6400
,
2290 .rx_fifomask
= S3C2440_UFSTAT_RXMASK
,
2291 .rx_fifoshift
= S3C2440_UFSTAT_RXSHIFT
,
2292 .rx_fifofull
= S3C2440_UFSTAT_RXFULL
,
2293 .tx_fifofull
= S3C2440_UFSTAT_TXFULL
,
2294 .tx_fifomask
= S3C2440_UFSTAT_TXMASK
,
2295 .tx_fifoshift
= S3C2440_UFSTAT_TXSHIFT
,
2296 .def_clk_sel
= S3C2410_UCON_CLKSEL2
,
2298 .clksel_mask
= S3C6400_UCON_CLKMASK
,
2299 .clksel_shift
= S3C6400_UCON_CLKSHIFT
,
2301 .def_cfg
= &(struct s3c2410_uartcfg
) {
2302 .ucon
= S3C2410_UCON_DEFAULT
,
2303 .ufcon
= S3C2410_UFCON_DEFAULT
,
2306 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2308 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2311 #ifdef CONFIG_CPU_S5PV210
2312 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data
= {
2313 .info
= &(struct s3c24xx_uart_info
) {
2314 .name
= "Samsung S5PV210 UART",
2315 .type
= PORT_S3C6400
,
2317 .rx_fifomask
= S5PV210_UFSTAT_RXMASK
,
2318 .rx_fifoshift
= S5PV210_UFSTAT_RXSHIFT
,
2319 .rx_fifofull
= S5PV210_UFSTAT_RXFULL
,
2320 .tx_fifofull
= S5PV210_UFSTAT_TXFULL
,
2321 .tx_fifomask
= S5PV210_UFSTAT_TXMASK
,
2322 .tx_fifoshift
= S5PV210_UFSTAT_TXSHIFT
,
2323 .def_clk_sel
= S3C2410_UCON_CLKSEL0
,
2325 .clksel_mask
= S5PV210_UCON_CLKMASK
,
2326 .clksel_shift
= S5PV210_UCON_CLKSHIFT
,
2328 .def_cfg
= &(struct s3c2410_uartcfg
) {
2329 .ucon
= S5PV210_UCON_DEFAULT
,
2330 .ufcon
= S5PV210_UFCON_DEFAULT
,
2332 .fifosize
= { 256, 64, 16, 16 },
2334 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2336 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2339 #if defined(CONFIG_ARCH_EXYNOS)
2340 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2341 .info = &(struct s3c24xx_uart_info) { \
2342 .name = "Samsung Exynos UART", \
2343 .type = PORT_S3C6400, \
2345 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2346 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2347 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2348 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2349 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2350 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2351 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2354 .clksel_shift = 0, \
2356 .def_cfg = &(struct s3c2410_uartcfg) { \
2357 .ucon = S5PV210_UCON_DEFAULT, \
2358 .ufcon = S5PV210_UFCON_DEFAULT, \
2362 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2363 EXYNOS_COMMON_SERIAL_DRV_DATA
,
2364 .fifosize
= { 256, 64, 16, 16 },
2367 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data
= {
2368 EXYNOS_COMMON_SERIAL_DRV_DATA
,
2369 .fifosize
= { 64, 256, 16, 256 },
2372 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2373 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2375 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2376 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2379 static const struct platform_device_id s3c24xx_serial_driver_ids
[] = {
2381 .name
= "s3c2410-uart",
2382 .driver_data
= S3C2410_SERIAL_DRV_DATA
,
2384 .name
= "s3c2412-uart",
2385 .driver_data
= S3C2412_SERIAL_DRV_DATA
,
2387 .name
= "s3c2440-uart",
2388 .driver_data
= S3C2440_SERIAL_DRV_DATA
,
2390 .name
= "s3c6400-uart",
2391 .driver_data
= S3C6400_SERIAL_DRV_DATA
,
2393 .name
= "s5pv210-uart",
2394 .driver_data
= S5PV210_SERIAL_DRV_DATA
,
2396 .name
= "exynos4210-uart",
2397 .driver_data
= EXYNOS4210_SERIAL_DRV_DATA
,
2399 .name
= "exynos5433-uart",
2400 .driver_data
= EXYNOS5433_SERIAL_DRV_DATA
,
2404 MODULE_DEVICE_TABLE(platform
, s3c24xx_serial_driver_ids
);
2407 static const struct of_device_id s3c24xx_uart_dt_match
[] = {
2408 { .compatible
= "samsung,s3c2410-uart",
2409 .data
= (void *)S3C2410_SERIAL_DRV_DATA
},
2410 { .compatible
= "samsung,s3c2412-uart",
2411 .data
= (void *)S3C2412_SERIAL_DRV_DATA
},
2412 { .compatible
= "samsung,s3c2440-uart",
2413 .data
= (void *)S3C2440_SERIAL_DRV_DATA
},
2414 { .compatible
= "samsung,s3c6400-uart",
2415 .data
= (void *)S3C6400_SERIAL_DRV_DATA
},
2416 { .compatible
= "samsung,s5pv210-uart",
2417 .data
= (void *)S5PV210_SERIAL_DRV_DATA
},
2418 { .compatible
= "samsung,exynos4210-uart",
2419 .data
= (void *)EXYNOS4210_SERIAL_DRV_DATA
},
2420 { .compatible
= "samsung,exynos5433-uart",
2421 .data
= (void *)EXYNOS5433_SERIAL_DRV_DATA
},
2424 MODULE_DEVICE_TABLE(of
, s3c24xx_uart_dt_match
);
2427 static struct platform_driver samsung_serial_driver
= {
2428 .probe
= s3c24xx_serial_probe
,
2429 .remove
= s3c24xx_serial_remove
,
2430 .id_table
= s3c24xx_serial_driver_ids
,
2432 .name
= "samsung-uart",
2433 .pm
= SERIAL_SAMSUNG_PM_OPS
,
2434 .of_match_table
= of_match_ptr(s3c24xx_uart_dt_match
),
2438 module_platform_driver(samsung_serial_driver
);
2440 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2445 struct samsung_early_console_data
{
2449 static void samsung_early_busyuart(struct uart_port
*port
)
2451 while (!(readl(port
->membase
+ S3C2410_UTRSTAT
) & S3C2410_UTRSTAT_TXFE
))
2455 static void samsung_early_busyuart_fifo(struct uart_port
*port
)
2457 struct samsung_early_console_data
*data
= port
->private_data
;
2459 while (readl(port
->membase
+ S3C2410_UFSTAT
) & data
->txfull_mask
)
2463 static void samsung_early_putc(struct uart_port
*port
, int c
)
2465 if (readl(port
->membase
+ S3C2410_UFCON
) & S3C2410_UFCON_FIFOMODE
)
2466 samsung_early_busyuart_fifo(port
);
2468 samsung_early_busyuart(port
);
2470 writeb(c
, port
->membase
+ S3C2410_UTXH
);
2473 static void samsung_early_write(struct console
*con
, const char *s
, unsigned n
)
2475 struct earlycon_device
*dev
= con
->data
;
2477 uart_console_write(&dev
->port
, s
, n
, samsung_early_putc
);
2480 static int __init
samsung_early_console_setup(struct earlycon_device
*device
,
2483 if (!device
->port
.membase
)
2486 device
->con
->write
= samsung_early_write
;
2491 static struct samsung_early_console_data s3c2410_early_console_data
= {
2492 .txfull_mask
= S3C2410_UFSTAT_TXFULL
,
2495 static int __init
s3c2410_early_console_setup(struct earlycon_device
*device
,
2498 device
->port
.private_data
= &s3c2410_early_console_data
;
2499 return samsung_early_console_setup(device
, opt
);
2501 OF_EARLYCON_DECLARE(s3c2410
, "samsung,s3c2410-uart",
2502 s3c2410_early_console_setup
);
2504 /* S3C2412, S3C2440, S3C64xx */
2505 static struct samsung_early_console_data s3c2440_early_console_data
= {
2506 .txfull_mask
= S3C2440_UFSTAT_TXFULL
,
2509 static int __init
s3c2440_early_console_setup(struct earlycon_device
*device
,
2512 device
->port
.private_data
= &s3c2440_early_console_data
;
2513 return samsung_early_console_setup(device
, opt
);
2515 OF_EARLYCON_DECLARE(s3c2412
, "samsung,s3c2412-uart",
2516 s3c2440_early_console_setup
);
2517 OF_EARLYCON_DECLARE(s3c2440
, "samsung,s3c2440-uart",
2518 s3c2440_early_console_setup
);
2519 OF_EARLYCON_DECLARE(s3c6400
, "samsung,s3c6400-uart",
2520 s3c2440_early_console_setup
);
2522 /* S5PV210, EXYNOS */
2523 static struct samsung_early_console_data s5pv210_early_console_data
= {
2524 .txfull_mask
= S5PV210_UFSTAT_TXFULL
,
2527 static int __init
s5pv210_early_console_setup(struct earlycon_device
*device
,
2530 device
->port
.private_data
= &s5pv210_early_console_data
;
2531 return samsung_early_console_setup(device
, opt
);
2533 OF_EARLYCON_DECLARE(s5pv210
, "samsung,s5pv210-uart",
2534 s5pv210_early_console_setup
);
2535 OF_EARLYCON_DECLARE(exynos4210
, "samsung,exynos4210-uart",
2536 s5pv210_early_console_setup
);
2539 MODULE_ALIAS("platform:samsung-uart");
2540 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2541 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2542 MODULE_LICENSE("GPL v2");